Topics

Here is a list of all topics with brief descriptions:

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▼CMSIS Core Instruction Interface
▼CMSIS Core Register Access Functions
CMSIS SIMD Intrinsics
CMSIS Global Defines
▼Defines and Type Definitions	Type definitions and defines for Cortex-M processor based devices
▼Status and Control Registers	Core Register type definitions
▼Nested Vectored Interrupt Controller (NVIC)	Type definitions for the NVIC Registers
▼System Control Block (SCB)	Type definitions for the System Control Block Registers
▼System Controls not in SCB (SCnSCB)	Type definitions for the System Control and ID Register not in the SCB
▼System Tick Timer (SysTick)	Type definitions for the System Timer Registers
▼Instrumentation Trace Macrocell (ITM)	Type definitions for the Instrumentation Trace Macrocell (ITM)
▼Data Watchpoint and Trace (DWT)	Type definitions for the Data Watchpoint and Trace (DWT)
▼Trace Port Interface (TPI)	Type definitions for the Trace Port Interface (TPI)
▼Floating Point Unit (FPU)	Type definitions for the Floating Point Unit (FPU)
▼Core Debug Registers (CoreDebug)	Type definitions for the Core Debug Registers
▼Debug Control Block	Type definitions for the Debug Control Block Registers
▼Debug Identification Block	Type definitions for the Debug Identification Block Registers
▼Core register bit field macros	Macros for use with bit field definitions (xxx_Pos, xxx_Msk)
▼Core Definitions	Definitions for base addresses, unions, and structures
▼Backwards Compatibility Aliases	Register alias definitions for backwards compatibility
▼Functions and Instructions Reference
Cache Functions	Functions that configure Instruction and Data cache
▼CMSIS Core Register Access Functions
CMSIS SIMD Intrinsics
▼NVIC Functions	Functions that manage interrupts and exceptions via the NVIC
►FPU Functions	Function that provides FPU type
►MVE Functions	Function that provides MVE type
►SAU Functions	Functions that configure the SAU
PAC Key functions	Functions that access the PAC keys
▼NVIC Functions	Functions that manage interrupts and exceptions via the NVIC
▼FPU Functions	Function that provides FPU type
►MVE Functions	Function that provides MVE type
►SAU Functions	Functions that configure the SAU
►Debug Control Functions	Functions that access the Debug Control Block
▼Memory System Control Registers (IMPLEMENTATION DEFINED)	Type definitions for the Memory System Control Registers (MEMSYSCTL)
▼Power Mode Control Registers	Type definitions for the Power Mode Control Registers (PWRMODCTL)
▼External Wakeup Interrupt Controller Registers	Type definitions for the External Wakeup Interrupt Controller Registers (EWIC)
▼External Wakeup Interrupt Controller (EWIC) interrupt status access registers	Type definitions for the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA)
▼Error Banking Registers (IMPLEMENTATION DEFINED)	Type definitions for the Error Banking Registers (ERRBNK)
▼Processor Configuration Information Registers (IMPLEMENTATION DEFINED)	Type definitions for the Processor Configuration Information Registerss (PRCCFGINF)
▼Software Test Library Observation Registers	Type definitions for the Software Test Library Observation Registerss (STL)
▼Trace Port Interface (TPI)	Type definitions for the Trace Port Interface (TPI)
▼Floating Point Unit (FPU)	Type definitions for the Floating Point Unit (FPU)
▼Core Debug Registers (CoreDebug)	Type definitions for the Core Debug Registers
►Debug Control Block	Type definitions for the Debug Control Block Registers
►Debug Identification Block	Type definitions for the Debug Identification Block Registers
►Core register bit field macros	Macros for use with bit field definitions (xxx_Pos, xxx_Msk)
▼Implementation Control Block register (ICB)	Type definitions for the Implementation Control Block Register
▼System Tick Timer (SysTick)	Type definitions for the System Timer Registers
▼Instrumentation Trace Macrocell (ITM)	Type definitions for the Instrumentation Trace Macrocell (ITM)
▼Data Watchpoint and Trace (DWT)	Type definitions for the Data Watchpoint and Trace (DWT)
▼Trace Port Interface (TPI)	Type definitions for the Trace Port Interface (TPI)
▼Floating Point Unit (FPU)	Type definitions for the Floating Point Unit (FPU)
▼Core Debug Registers (CoreDebug)	Type definitions for the Core Debug Registers
▼Debug Control Block	Type definitions for the Debug Control Block Registers
▼Debug Identification Block	Type definitions for the Debug Identification Block Registers
▼Core register bit field macros	Macros for use with bit field definitions (xxx_Pos, xxx_Msk)
▼Core Definitions	Definitions for base addresses, unions, and structures
▼Backwards Compatibility Aliases	Register alias definitions for backwards compatibility
▼Functions and Instructions Reference
Cache Functions	Functions that configure Instruction and Data cache
▼CMSIS Core Register Access Functions
CMSIS SIMD Intrinsics
▼NVIC Functions	Functions that manage interrupts and exceptions via the NVIC
►FPU Functions	Function that provides FPU type
►MVE Functions	Function that provides MVE type
►SAU Functions	Functions that configure the SAU
PAC Key functions	Functions that access the PAC keys
▼NVIC Functions	Functions that manage interrupts and exceptions via the NVIC
▼FPU Functions	Function that provides FPU type
►MVE Functions	Function that provides MVE type
►SAU Functions	Functions that configure the SAU
►Debug Control Functions	Functions that access the Debug Control Block
▼Memory System Control Registers (IMPLEMENTATION DEFINED)	Type definitions for the Memory System Control Registers (MEMSYSCTL)
▼Power Mode Control Registers	Type definitions for the Power Mode Control Registers (PWRMODCTL)
▼External Wakeup Interrupt Controller Registers	Type definitions for the External Wakeup Interrupt Controller Registers (EWIC)
▼External Wakeup Interrupt Controller (EWIC) interrupt status access registers	Type definitions for the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA)
▼Error Banking Registers (IMPLEMENTATION DEFINED)	Type definitions for the Error Banking Registers (ERRBNK)
▼Processor Configuration Information Registers (IMPLEMENTATION DEFINED)	Type definitions for the Processor Configuration Information Registerss (PRCCFGINF)
▼Software Test Library Observation Registers	Type definitions for the Software Test Library Observation Registerss (STL)
▼Trace Port Interface (TPI)	Type definitions for the Trace Port Interface (TPI)
▼Floating Point Unit (FPU)	Type definitions for the Floating Point Unit (FPU)
▼Core Debug Registers (CoreDebug)	Type definitions for the Core Debug Registers
►Debug Control Block	Type definitions for the Debug Control Block Registers
►Debug Identification Block	Type definitions for the Debug Identification Block Registers
►Core register bit field macros	Macros for use with bit field definitions (xxx_Pos, xxx_Msk)
boot_uf2
pico_bootrom
▼MSP432P401R Definitions
▼Device CMSIS Definitions
▼MSP432P401R Memory Mapping
▼MSP432P401R Peripherals
▼MSP432P401R (ADC14)
▼MSP432P401R (AES256)
▼MSP432P401R (CAPTIO)
▼MSP432P401R (COMP_E)
▼MSP432P401R (CRC32)
▼MSP432P401R (CS)
▼MSP432P401R (DIO)
▼MSP432P401R (DMA)
▼MSP432P401R (EUSCI_A)
▼MSP432P401R (EUSCI_A_SPI)
▼MSP432P401R (EUSCI_B)
▼MSP432P401R (EUSCI_B_SPI)
▼MSP432P401R (FLCTL)
▼MSP432P401R (FL_BOOTOVER_MAILBOX)
►MSP432P401R (FL_BOOTOVER_MAILBOX)
►MSP432P401R (FL_BOOTOVER_MAILBOX)
►MSP432P401R (PCM)