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Yet Another Hardware Abstraction Library
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Debug Control Block
Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » Implementation Control Block register (ICB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » Implementation Control Block register (ICB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Memory System Control Registers (IMPLEMENTATION DEFINED) » Power Mode Control Registers » External Wakeup Interrupt Controller Registers » External Wakeup Interrupt Controller (EWIC) interrupt status access registers » Error Banking Registers (IMPLEMENTATION DEFINED) » Processor Configuration Information Registers (IMPLEMENTATION DEFINED) » Software Test Library Observation Registers » Trace Port Interface (TPI) » Floating Point Unit (FPU) » Core Debug Registers (CoreDebug)

Type definitions for the Debug Control Block Registers. More...

Topics

 Debug Identification Block
 Type definitions for the Debug Identification Block Registers.
 

Classes

struct  DCB_Type
 Structure type to access the Debug Control Block Registers (DCB). More...
 
#define DCB_DHCSR_DBGKEY_Pos   16U
 
#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
 
#define DCB_DHCSR_S_RESTART_ST_Pos   26U
 
#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
 
#define DCB_DHCSR_S_RESET_ST_Pos   25U
 
#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
 
#define DCB_DHCSR_S_RETIRE_ST_Pos   24U
 
#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
 
#define DCB_DHCSR_S_SDE_Pos   20U
 
#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)
 
#define DCB_DHCSR_S_LOCKUP_Pos   19U
 
#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
 
#define DCB_DHCSR_S_SLEEP_Pos   18U
 
#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
 
#define DCB_DHCSR_S_HALT_Pos   17U
 
#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)
 
#define DCB_DHCSR_S_REGRDY_Pos   16U
 
#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
 
#define DCB_DHCSR_C_SNAPSTALL_Pos   5U
 
#define DCB_DHCSR_C_SNAPSTALL_Msk   (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
 
#define DCB_DHCSR_C_MASKINTS_Pos   3U
 
#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
 
#define DCB_DHCSR_C_STEP_Pos   2U
 
#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)
 
#define DCB_DHCSR_C_HALT_Pos   1U
 
#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)
 
#define DCB_DHCSR_C_DEBUGEN_Pos   0U
 
#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)
 
#define DCB_DCRSR_REGWnR_Pos   16U
 
#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)
 
#define DCB_DCRSR_REGSEL_Pos   0U
 
#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)
 
#define DCB_DCRDR_DBGTMP_Pos   0U
 
#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)
 
#define DCB_DEMCR_TRCENA_Pos   24U
 
#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)
 
#define DCB_DEMCR_MONPRKEY_Pos   23U
 
#define DCB_DEMCR_MONPRKEY_Msk   (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
 
#define DCB_DEMCR_UMON_EN_Pos   21U
 
#define DCB_DEMCR_UMON_EN_Msk   (0x1UL << DCB_DEMCR_UMON_EN_Pos)
 
#define DCB_DEMCR_SDME_Pos   20U
 
#define DCB_DEMCR_SDME_Msk   (0x1UL << DCB_DEMCR_SDME_Pos)
 
#define DCB_DEMCR_MON_REQ_Pos   19U
 
#define DCB_DEMCR_MON_REQ_Msk   (0x1UL << DCB_DEMCR_MON_REQ_Pos)
 
#define DCB_DEMCR_MON_STEP_Pos   18U
 
#define DCB_DEMCR_MON_STEP_Msk   (0x1UL << DCB_DEMCR_MON_STEP_Pos)
 
#define DCB_DEMCR_MON_PEND_Pos   17U
 
#define DCB_DEMCR_MON_PEND_Msk   (0x1UL << DCB_DEMCR_MON_PEND_Pos)
 
#define DCB_DEMCR_MON_EN_Pos   16U
 
#define DCB_DEMCR_MON_EN_Msk   (0x1UL << DCB_DEMCR_MON_EN_Pos)
 
#define DCB_DEMCR_VC_SFERR_Pos   11U
 
#define DCB_DEMCR_VC_SFERR_Msk   (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
 
#define DCB_DEMCR_VC_HARDERR_Pos   10U
 
#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
 
#define DCB_DEMCR_VC_INTERR_Pos   9U
 
#define DCB_DEMCR_VC_INTERR_Msk   (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
 
#define DCB_DEMCR_VC_BUSERR_Pos   8U
 
#define DCB_DEMCR_VC_BUSERR_Msk   (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
 
#define DCB_DEMCR_VC_STATERR_Pos   7U
 
#define DCB_DEMCR_VC_STATERR_Msk   (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
 
#define DCB_DEMCR_VC_CHKERR_Pos   6U
 
#define DCB_DEMCR_VC_CHKERR_Msk   (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
 
#define DCB_DEMCR_VC_NOCPERR_Pos   5U
 
#define DCB_DEMCR_VC_NOCPERR_Msk   (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
 
#define DCB_DEMCR_VC_MMERR_Pos   4U
 
#define DCB_DEMCR_VC_MMERR_Msk   (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
 
#define DCB_DEMCR_VC_CORERESET_Pos   0U
 
#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define DCB_DSCSR_CDSKEY_Pos   17U
 
#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)
 
#define DCB_DSCSR_CDS_Pos   16U
 
#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)
 
#define DCB_DSCSR_SBRSEL_Pos   1U
 
#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)
 
#define DCB_DSCSR_SBRSELEN_Pos   0U
 
#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)
 
#define DCB_DHCSR_DBGKEY_Pos   16U
 
#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
 
#define DCB_DHCSR_S_RESTART_ST_Pos   26U
 
#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
 
#define DCB_DHCSR_S_RESET_ST_Pos   25U
 
#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
 
#define DCB_DHCSR_S_RETIRE_ST_Pos   24U
 
#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
 
#define DCB_DHCSR_S_SDE_Pos   20U
 
#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)
 
#define DCB_DHCSR_S_LOCKUP_Pos   19U
 
#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
 
#define DCB_DHCSR_S_SLEEP_Pos   18U
 
#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
 
#define DCB_DHCSR_S_HALT_Pos   17U
 
#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)
 
#define DCB_DHCSR_S_REGRDY_Pos   16U
 
#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
 
#define DCB_DHCSR_C_MASKINTS_Pos   3U
 
#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
 
#define DCB_DHCSR_C_STEP_Pos   2U
 
#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)
 
#define DCB_DHCSR_C_HALT_Pos   1U
 
#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)
 
#define DCB_DHCSR_C_DEBUGEN_Pos   0U
 
#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)
 
#define DCB_DCRSR_REGWnR_Pos   16U
 
#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)
 
#define DCB_DCRSR_REGSEL_Pos   0U
 
#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)
 
#define DCB_DCRDR_DBGTMP_Pos   0U
 
#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)
 
#define DCB_DEMCR_TRCENA_Pos   24U
 
#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)
 
#define DCB_DEMCR_VC_HARDERR_Pos   10U
 
#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
 
#define DCB_DEMCR_VC_CORERESET_Pos   0U
 
#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define DCB_DSCSR_CDSKEY_Pos   17U
 
#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)
 
#define DCB_DSCSR_CDS_Pos   16U
 
#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)
 
#define DCB_DSCSR_SBRSEL_Pos   1U
 
#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)
 
#define DCB_DSCSR_SBRSELEN_Pos   0U
 
#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)
 
#define DCB_DHCSR_DBGKEY_Pos   16U
 
#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
 
#define DCB_DHCSR_S_RESTART_ST_Pos   26U
 
#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
 
#define DCB_DHCSR_S_RESET_ST_Pos   25U
 
#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
 
#define DCB_DHCSR_S_RETIRE_ST_Pos   24U
 
#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
 
#define DCB_DHCSR_S_SDE_Pos   20U
 
#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)
 
#define DCB_DHCSR_S_LOCKUP_Pos   19U
 
#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
 
#define DCB_DHCSR_S_SLEEP_Pos   18U
 
#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
 
#define DCB_DHCSR_S_HALT_Pos   17U
 
#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)
 
#define DCB_DHCSR_S_REGRDY_Pos   16U
 
#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
 
#define DCB_DHCSR_C_SNAPSTALL_Pos   5U
 
#define DCB_DHCSR_C_SNAPSTALL_Msk   (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
 
#define DCB_DHCSR_C_MASKINTS_Pos   3U
 
#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
 
#define DCB_DHCSR_C_STEP_Pos   2U
 
#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)
 
#define DCB_DHCSR_C_HALT_Pos   1U
 
#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)
 
#define DCB_DHCSR_C_DEBUGEN_Pos   0U
 
#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)
 
#define DCB_DCRSR_REGWnR_Pos   16U
 
#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)
 
#define DCB_DCRSR_REGSEL_Pos   0U
 
#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)
 
#define DCB_DCRDR_DBGTMP_Pos   0U
 
#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)
 
#define DCB_DEMCR_TRCENA_Pos   24U
 
#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)
 
#define DCB_DEMCR_MONPRKEY_Pos   23U
 
#define DCB_DEMCR_MONPRKEY_Msk   (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
 
#define DCB_DEMCR_UMON_EN_Pos   21U
 
#define DCB_DEMCR_UMON_EN_Msk   (0x1UL << DCB_DEMCR_UMON_EN_Pos)
 
#define DCB_DEMCR_SDME_Pos   20U
 
#define DCB_DEMCR_SDME_Msk   (0x1UL << DCB_DEMCR_SDME_Pos)
 
#define DCB_DEMCR_MON_REQ_Pos   19U
 
#define DCB_DEMCR_MON_REQ_Msk   (0x1UL << DCB_DEMCR_MON_REQ_Pos)
 
#define DCB_DEMCR_MON_STEP_Pos   18U
 
#define DCB_DEMCR_MON_STEP_Msk   (0x1UL << DCB_DEMCR_MON_STEP_Pos)
 
#define DCB_DEMCR_MON_PEND_Pos   17U
 
#define DCB_DEMCR_MON_PEND_Msk   (0x1UL << DCB_DEMCR_MON_PEND_Pos)
 
#define DCB_DEMCR_MON_EN_Pos   16U
 
#define DCB_DEMCR_MON_EN_Msk   (0x1UL << DCB_DEMCR_MON_EN_Pos)
 
#define DCB_DEMCR_VC_SFERR_Pos   11U
 
#define DCB_DEMCR_VC_SFERR_Msk   (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
 
#define DCB_DEMCR_VC_HARDERR_Pos   10U
 
#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
 
#define DCB_DEMCR_VC_INTERR_Pos   9U
 
#define DCB_DEMCR_VC_INTERR_Msk   (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
 
#define DCB_DEMCR_VC_BUSERR_Pos   8U
 
#define DCB_DEMCR_VC_BUSERR_Msk   (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
 
#define DCB_DEMCR_VC_STATERR_Pos   7U
 
#define DCB_DEMCR_VC_STATERR_Msk   (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
 
#define DCB_DEMCR_VC_CHKERR_Pos   6U
 
#define DCB_DEMCR_VC_CHKERR_Msk   (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
 
#define DCB_DEMCR_VC_NOCPERR_Pos   5U
 
#define DCB_DEMCR_VC_NOCPERR_Msk   (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
 
#define DCB_DEMCR_VC_MMERR_Pos   4U
 
#define DCB_DEMCR_VC_MMERR_Msk   (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
 
#define DCB_DEMCR_VC_CORERESET_Pos   0U
 
#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define DCB_DSCSR_CDSKEY_Pos   17U
 
#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)
 
#define DCB_DSCSR_CDS_Pos   16U
 
#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)
 
#define DCB_DSCSR_SBRSEL_Pos   1U
 
#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)
 
#define DCB_DSCSR_SBRSELEN_Pos   0U
 
#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)
 
#define DCB_DHCSR_DBGKEY_Pos   16U
 
#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
 
#define DCB_DHCSR_S_RESTART_ST_Pos   26U
 
#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
 
#define DCB_DHCSR_S_RESET_ST_Pos   25U
 
#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
 
#define DCB_DHCSR_S_RETIRE_ST_Pos   24U
 
#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
 
#define DCB_DHCSR_S_SDE_Pos   20U
 
#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)
 
#define DCB_DHCSR_S_LOCKUP_Pos   19U
 
#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
 
#define DCB_DHCSR_S_SLEEP_Pos   18U
 
#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
 
#define DCB_DHCSR_S_HALT_Pos   17U
 
#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)
 
#define DCB_DHCSR_S_REGRDY_Pos   16U
 
#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
 
#define DCB_DHCSR_C_MASKINTS_Pos   3U
 
#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
 
#define DCB_DHCSR_C_STEP_Pos   2U
 
#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)
 
#define DCB_DHCSR_C_HALT_Pos   1U
 
#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)
 
#define DCB_DHCSR_C_DEBUGEN_Pos   0U
 
#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)
 
#define DCB_DCRSR_REGWnR_Pos   16U
 
#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)
 
#define DCB_DCRSR_REGSEL_Pos   0U
 
#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)
 
#define DCB_DCRDR_DBGTMP_Pos   0U
 
#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)
 
#define DCB_DEMCR_TRCENA_Pos   24U
 
#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)
 
#define DCB_DEMCR_VC_HARDERR_Pos   10U
 
#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
 
#define DCB_DEMCR_VC_CORERESET_Pos   0U
 
#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define DCB_DSCSR_CDSKEY_Pos   17U
 
#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)
 
#define DCB_DSCSR_CDS_Pos   16U
 
#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)
 
#define DCB_DSCSR_SBRSEL_Pos   1U
 
#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)
 
#define DCB_DSCSR_SBRSELEN_Pos   0U
 
#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)
 
#define DCB_DHCSR_DBGKEY_Pos   16U
 
#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
 
#define DCB_DHCSR_S_RESTART_ST_Pos   26U
 
#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
 
#define DCB_DHCSR_S_RESET_ST_Pos   25U
 
#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
 
#define DCB_DHCSR_S_RETIRE_ST_Pos   24U
 
#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
 
#define DCB_DHCSR_S_SDE_Pos   20U
 
#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)
 
#define DCB_DHCSR_S_LOCKUP_Pos   19U
 
#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
 
#define DCB_DHCSR_S_SLEEP_Pos   18U
 
#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
 
#define DCB_DHCSR_S_HALT_Pos   17U
 
#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)
 
#define DCB_DHCSR_S_REGRDY_Pos   16U
 
#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
 
#define DCB_DHCSR_C_SNAPSTALL_Pos   5U
 
#define DCB_DHCSR_C_SNAPSTALL_Msk   (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
 
#define DCB_DHCSR_C_MASKINTS_Pos   3U
 
#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
 
#define DCB_DHCSR_C_STEP_Pos   2U
 
#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)
 
#define DCB_DHCSR_C_HALT_Pos   1U
 
#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)
 
#define DCB_DHCSR_C_DEBUGEN_Pos   0U
 
#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)
 
#define DCB_DCRSR_REGWnR_Pos   16U
 
#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)
 
#define DCB_DCRSR_REGSEL_Pos   0U
 
#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)
 
#define DCB_DCRDR_DBGTMP_Pos   0U
 
#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)
 
#define DCB_DEMCR_TRCENA_Pos   24U
 
#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)
 
#define DCB_DEMCR_MONPRKEY_Pos   23U
 
#define DCB_DEMCR_MONPRKEY_Msk   (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
 
#define DCB_DEMCR_UMON_EN_Pos   21U
 
#define DCB_DEMCR_UMON_EN_Msk   (0x1UL << DCB_DEMCR_UMON_EN_Pos)
 
#define DCB_DEMCR_SDME_Pos   20U
 
#define DCB_DEMCR_SDME_Msk   (0x1UL << DCB_DEMCR_SDME_Pos)
 
#define DCB_DEMCR_MON_REQ_Pos   19U
 
#define DCB_DEMCR_MON_REQ_Msk   (0x1UL << DCB_DEMCR_MON_REQ_Pos)
 
#define DCB_DEMCR_MON_STEP_Pos   18U
 
#define DCB_DEMCR_MON_STEP_Msk   (0x1UL << DCB_DEMCR_MON_STEP_Pos)
 
#define DCB_DEMCR_MON_PEND_Pos   17U
 
#define DCB_DEMCR_MON_PEND_Msk   (0x1UL << DCB_DEMCR_MON_PEND_Pos)
 
#define DCB_DEMCR_MON_EN_Pos   16U
 
#define DCB_DEMCR_MON_EN_Msk   (0x1UL << DCB_DEMCR_MON_EN_Pos)
 
#define DCB_DEMCR_VC_SFERR_Pos   11U
 
#define DCB_DEMCR_VC_SFERR_Msk   (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
 
#define DCB_DEMCR_VC_HARDERR_Pos   10U
 
#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
 
#define DCB_DEMCR_VC_INTERR_Pos   9U
 
#define DCB_DEMCR_VC_INTERR_Msk   (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
 
#define DCB_DEMCR_VC_BUSERR_Pos   8U
 
#define DCB_DEMCR_VC_BUSERR_Msk   (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
 
#define DCB_DEMCR_VC_STATERR_Pos   7U
 
#define DCB_DEMCR_VC_STATERR_Msk   (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
 
#define DCB_DEMCR_VC_CHKERR_Pos   6U
 
#define DCB_DEMCR_VC_CHKERR_Msk   (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
 
#define DCB_DEMCR_VC_NOCPERR_Pos   5U
 
#define DCB_DEMCR_VC_NOCPERR_Msk   (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
 
#define DCB_DEMCR_VC_MMERR_Pos   4U
 
#define DCB_DEMCR_VC_MMERR_Msk   (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
 
#define DCB_DEMCR_VC_CORERESET_Pos   0U
 
#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define DCB_DSCSR_CDSKEY_Pos   17U
 
#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)
 
#define DCB_DSCSR_CDS_Pos   16U
 
#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)
 
#define DCB_DSCSR_SBRSEL_Pos   1U
 
#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)
 
#define DCB_DSCSR_SBRSELEN_Pos   0U
 
#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)
 
#define DCB_DHCSR_DBGKEY_Pos   16U
 
#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
 
#define DCB_DHCSR_S_RESTART_ST_Pos   26U
 
#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
 
#define DCB_DHCSR_S_RESET_ST_Pos   25U
 
#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
 
#define DCB_DHCSR_S_RETIRE_ST_Pos   24U
 
#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
 
#define DCB_DHCSR_S_SDE_Pos   20U
 
#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)
 
#define DCB_DHCSR_S_LOCKUP_Pos   19U
 
#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
 
#define DCB_DHCSR_S_SLEEP_Pos   18U
 
#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
 
#define DCB_DHCSR_S_HALT_Pos   17U
 
#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)
 
#define DCB_DHCSR_S_REGRDY_Pos   16U
 
#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
 
#define DCB_DHCSR_C_SNAPSTALL_Pos   5U
 
#define DCB_DHCSR_C_SNAPSTALL_Msk   (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
 
#define DCB_DHCSR_C_MASKINTS_Pos   3U
 
#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
 
#define DCB_DHCSR_C_STEP_Pos   2U
 
#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)
 
#define DCB_DHCSR_C_HALT_Pos   1U
 
#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)
 
#define DCB_DHCSR_C_DEBUGEN_Pos   0U
 
#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)
 
#define DCB_DCRSR_REGWnR_Pos   16U
 
#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)
 
#define DCB_DCRSR_REGSEL_Pos   0U
 
#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)
 
#define DCB_DCRDR_DBGTMP_Pos   0U
 
#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)
 
#define DCB_DEMCR_TRCENA_Pos   24U
 
#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)
 
#define DCB_DEMCR_MONPRKEY_Pos   23U
 
#define DCB_DEMCR_MONPRKEY_Msk   (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
 
#define DCB_DEMCR_UMON_EN_Pos   21U
 
#define DCB_DEMCR_UMON_EN_Msk   (0x1UL << DCB_DEMCR_UMON_EN_Pos)
 
#define DCB_DEMCR_SDME_Pos   20U
 
#define DCB_DEMCR_SDME_Msk   (0x1UL << DCB_DEMCR_SDME_Pos)
 
#define DCB_DEMCR_MON_REQ_Pos   19U
 
#define DCB_DEMCR_MON_REQ_Msk   (0x1UL << DCB_DEMCR_MON_REQ_Pos)
 
#define DCB_DEMCR_MON_STEP_Pos   18U
 
#define DCB_DEMCR_MON_STEP_Msk   (0x1UL << DCB_DEMCR_MON_STEP_Pos)
 
#define DCB_DEMCR_MON_PEND_Pos   17U
 
#define DCB_DEMCR_MON_PEND_Msk   (0x1UL << DCB_DEMCR_MON_PEND_Pos)
 
#define DCB_DEMCR_MON_EN_Pos   16U
 
#define DCB_DEMCR_MON_EN_Msk   (0x1UL << DCB_DEMCR_MON_EN_Pos)
 
#define DCB_DEMCR_VC_SFERR_Pos   11U
 
#define DCB_DEMCR_VC_SFERR_Msk   (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
 
#define DCB_DEMCR_VC_HARDERR_Pos   10U
 
#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
 
#define DCB_DEMCR_VC_INTERR_Pos   9U
 
#define DCB_DEMCR_VC_INTERR_Msk   (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
 
#define DCB_DEMCR_VC_BUSERR_Pos   8U
 
#define DCB_DEMCR_VC_BUSERR_Msk   (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
 
#define DCB_DEMCR_VC_STATERR_Pos   7U
 
#define DCB_DEMCR_VC_STATERR_Msk   (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
 
#define DCB_DEMCR_VC_CHKERR_Pos   6U
 
#define DCB_DEMCR_VC_CHKERR_Msk   (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
 
#define DCB_DEMCR_VC_NOCPERR_Pos   5U
 
#define DCB_DEMCR_VC_NOCPERR_Msk   (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
 
#define DCB_DEMCR_VC_MMERR_Pos   4U
 
#define DCB_DEMCR_VC_MMERR_Msk   (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
 
#define DCB_DEMCR_VC_CORERESET_Pos   0U
 
#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define DCB_DSCSR_CDSKEY_Pos   17U
 
#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)
 
#define DCB_DSCSR_CDS_Pos   16U
 
#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)
 
#define DCB_DSCSR_SBRSEL_Pos   1U
 
#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)
 
#define DCB_DSCSR_SBRSELEN_Pos   0U
 
#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)
 
#define DCB_DHCSR_DBGKEY_Pos   16U
 
#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
 
#define DCB_DHCSR_S_RESTART_ST_Pos   26U
 
#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
 
#define DCB_DHCSR_S_RESET_ST_Pos   25U
 
#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
 
#define DCB_DHCSR_S_RETIRE_ST_Pos   24U
 
#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
 
#define DCB_DHCSR_S_SDE_Pos   20U
 
#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)
 
#define DCB_DHCSR_S_LOCKUP_Pos   19U
 
#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
 
#define DCB_DHCSR_S_SLEEP_Pos   18U
 
#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
 
#define DCB_DHCSR_S_HALT_Pos   17U
 
#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)
 
#define DCB_DHCSR_S_REGRDY_Pos   16U
 
#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
 
#define DCB_DHCSR_C_SNAPSTALL_Pos   5U
 
#define DCB_DHCSR_C_SNAPSTALL_Msk   (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
 
#define DCB_DHCSR_C_MASKINTS_Pos   3U
 
#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
 
#define DCB_DHCSR_C_STEP_Pos   2U
 
#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)
 
#define DCB_DHCSR_C_HALT_Pos   1U
 
#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)
 
#define DCB_DHCSR_C_DEBUGEN_Pos   0U
 
#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)
 
#define DCB_DCRSR_REGWnR_Pos   16U
 
#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)
 
#define DCB_DCRSR_REGSEL_Pos   0U
 
#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)
 
#define DCB_DCRDR_DBGTMP_Pos   0U
 
#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)
 
#define DCB_DEMCR_TRCENA_Pos   24U
 
#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)
 
#define DCB_DEMCR_MONPRKEY_Pos   23U
 
#define DCB_DEMCR_MONPRKEY_Msk   (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
 
#define DCB_DEMCR_UMON_EN_Pos   21U
 
#define DCB_DEMCR_UMON_EN_Msk   (0x1UL << DCB_DEMCR_UMON_EN_Pos)
 
#define DCB_DEMCR_SDME_Pos   20U
 
#define DCB_DEMCR_SDME_Msk   (0x1UL << DCB_DEMCR_SDME_Pos)
 
#define DCB_DEMCR_MON_REQ_Pos   19U
 
#define DCB_DEMCR_MON_REQ_Msk   (0x1UL << DCB_DEMCR_MON_REQ_Pos)
 
#define DCB_DEMCR_MON_STEP_Pos   18U
 
#define DCB_DEMCR_MON_STEP_Msk   (0x1UL << DCB_DEMCR_MON_STEP_Pos)
 
#define DCB_DEMCR_MON_PEND_Pos   17U
 
#define DCB_DEMCR_MON_PEND_Msk   (0x1UL << DCB_DEMCR_MON_PEND_Pos)
 
#define DCB_DEMCR_MON_EN_Pos   16U
 
#define DCB_DEMCR_MON_EN_Msk   (0x1UL << DCB_DEMCR_MON_EN_Pos)
 
#define DCB_DEMCR_VC_SFERR_Pos   11U
 
#define DCB_DEMCR_VC_SFERR_Msk   (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
 
#define DCB_DEMCR_VC_HARDERR_Pos   10U
 
#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
 
#define DCB_DEMCR_VC_INTERR_Pos   9U
 
#define DCB_DEMCR_VC_INTERR_Msk   (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
 
#define DCB_DEMCR_VC_BUSERR_Pos   8U
 
#define DCB_DEMCR_VC_BUSERR_Msk   (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
 
#define DCB_DEMCR_VC_STATERR_Pos   7U
 
#define DCB_DEMCR_VC_STATERR_Msk   (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
 
#define DCB_DEMCR_VC_CHKERR_Pos   6U
 
#define DCB_DEMCR_VC_CHKERR_Msk   (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
 
#define DCB_DEMCR_VC_NOCPERR_Pos   5U
 
#define DCB_DEMCR_VC_NOCPERR_Msk   (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
 
#define DCB_DEMCR_VC_MMERR_Pos   4U
 
#define DCB_DEMCR_VC_MMERR_Msk   (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
 
#define DCB_DEMCR_VC_CORERESET_Pos   0U
 
#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define DCB_DSCSR_CDSKEY_Pos   17U
 
#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)
 
#define DCB_DSCSR_CDS_Pos   16U
 
#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)
 
#define DCB_DSCSR_SBRSEL_Pos   1U
 
#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)
 
#define DCB_DSCSR_SBRSELEN_Pos   0U
 
#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)
 
#define DCB_DHCSR_DBGKEY_Pos   16U
 
#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
 
#define DCB_DHCSR_S_RESTART_ST_Pos   26U
 
#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
 
#define DCB_DHCSR_S_RESET_ST_Pos   25U
 
#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
 
#define DCB_DHCSR_S_RETIRE_ST_Pos   24U
 
#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
 
#define DCB_DHCSR_S_SDE_Pos   20U
 
#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)
 
#define DCB_DHCSR_S_LOCKUP_Pos   19U
 
#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
 
#define DCB_DHCSR_S_SLEEP_Pos   18U
 
#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
 
#define DCB_DHCSR_S_HALT_Pos   17U
 
#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)
 
#define DCB_DHCSR_S_REGRDY_Pos   16U
 
#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
 
#define DCB_DHCSR_C_SNAPSTALL_Pos   5U
 
#define DCB_DHCSR_C_SNAPSTALL_Msk   (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
 
#define DCB_DHCSR_C_MASKINTS_Pos   3U
 
#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
 
#define DCB_DHCSR_C_STEP_Pos   2U
 
#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)
 
#define DCB_DHCSR_C_HALT_Pos   1U
 
#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)
 
#define DCB_DHCSR_C_DEBUGEN_Pos   0U
 
#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)
 
#define DCB_DCRSR_REGWnR_Pos   16U
 
#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)
 
#define DCB_DCRSR_REGSEL_Pos   0U
 
#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)
 
#define DCB_DCRDR_DBGTMP_Pos   0U
 
#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)
 
#define DCB_DEMCR_TRCENA_Pos   24U
 
#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)
 
#define DCB_DEMCR_MONPRKEY_Pos   23U
 
#define DCB_DEMCR_MONPRKEY_Msk   (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
 
#define DCB_DEMCR_UMON_EN_Pos   21U
 
#define DCB_DEMCR_UMON_EN_Msk   (0x1UL << DCB_DEMCR_UMON_EN_Pos)
 
#define DCB_DEMCR_SDME_Pos   20U
 
#define DCB_DEMCR_SDME_Msk   (0x1UL << DCB_DEMCR_SDME_Pos)
 
#define DCB_DEMCR_MON_REQ_Pos   19U
 
#define DCB_DEMCR_MON_REQ_Msk   (0x1UL << DCB_DEMCR_MON_REQ_Pos)
 
#define DCB_DEMCR_MON_STEP_Pos   18U
 
#define DCB_DEMCR_MON_STEP_Msk   (0x1UL << DCB_DEMCR_MON_STEP_Pos)
 
#define DCB_DEMCR_MON_PEND_Pos   17U
 
#define DCB_DEMCR_MON_PEND_Msk   (0x1UL << DCB_DEMCR_MON_PEND_Pos)
 
#define DCB_DEMCR_MON_EN_Pos   16U
 
#define DCB_DEMCR_MON_EN_Msk   (0x1UL << DCB_DEMCR_MON_EN_Pos)
 
#define DCB_DEMCR_VC_SFERR_Pos   11U
 
#define DCB_DEMCR_VC_SFERR_Msk   (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
 
#define DCB_DEMCR_VC_HARDERR_Pos   10U
 
#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
 
#define DCB_DEMCR_VC_INTERR_Pos   9U
 
#define DCB_DEMCR_VC_INTERR_Msk   (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
 
#define DCB_DEMCR_VC_BUSERR_Pos   8U
 
#define DCB_DEMCR_VC_BUSERR_Msk   (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
 
#define DCB_DEMCR_VC_STATERR_Pos   7U
 
#define DCB_DEMCR_VC_STATERR_Msk   (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
 
#define DCB_DEMCR_VC_CHKERR_Pos   6U
 
#define DCB_DEMCR_VC_CHKERR_Msk   (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
 
#define DCB_DEMCR_VC_NOCPERR_Pos   5U
 
#define DCB_DEMCR_VC_NOCPERR_Msk   (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
 
#define DCB_DEMCR_VC_MMERR_Pos   4U
 
#define DCB_DEMCR_VC_MMERR_Msk   (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
 
#define DCB_DEMCR_VC_CORERESET_Pos   0U
 
#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define DCB_DSCSR_CDSKEY_Pos   17U
 
#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)
 
#define DCB_DSCSR_CDS_Pos   16U
 
#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)
 
#define DCB_DSCSR_SBRSEL_Pos   1U
 
#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)
 
#define DCB_DSCSR_SBRSELEN_Pos   0U
 
#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)
 
#define DCB_DHCSR_DBGKEY_Pos   16U
 
#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
 
#define DCB_DHCSR_S_RESTART_ST_Pos   26U
 
#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
 
#define DCB_DHCSR_S_RESET_ST_Pos   25U
 
#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
 
#define DCB_DHCSR_S_RETIRE_ST_Pos   24U
 
#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
 
#define DCB_DHCSR_S_SDE_Pos   20U
 
#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)
 
#define DCB_DHCSR_S_LOCKUP_Pos   19U
 
#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
 
#define DCB_DHCSR_S_SLEEP_Pos   18U
 
#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
 
#define DCB_DHCSR_S_HALT_Pos   17U
 
#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)
 
#define DCB_DHCSR_S_REGRDY_Pos   16U
 
#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
 
#define DCB_DHCSR_C_SNAPSTALL_Pos   5U
 
#define DCB_DHCSR_C_SNAPSTALL_Msk   (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
 
#define DCB_DHCSR_C_MASKINTS_Pos   3U
 
#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
 
#define DCB_DHCSR_C_STEP_Pos   2U
 
#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)
 
#define DCB_DHCSR_C_HALT_Pos   1U
 
#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)
 
#define DCB_DHCSR_C_DEBUGEN_Pos   0U
 
#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)
 
#define DCB_DCRSR_REGWnR_Pos   16U
 
#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)
 
#define DCB_DCRSR_REGSEL_Pos   0U
 
#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)
 
#define DCB_DCRDR_DBGTMP_Pos   0U
 
#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)
 
#define DCB_DEMCR_TRCENA_Pos   24U
 
#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)
 
#define DCB_DEMCR_MONPRKEY_Pos   23U
 
#define DCB_DEMCR_MONPRKEY_Msk   (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
 
#define DCB_DEMCR_UMON_EN_Pos   21U
 
#define DCB_DEMCR_UMON_EN_Msk   (0x1UL << DCB_DEMCR_UMON_EN_Pos)
 
#define DCB_DEMCR_SDME_Pos   20U
 
#define DCB_DEMCR_SDME_Msk   (0x1UL << DCB_DEMCR_SDME_Pos)
 
#define DCB_DEMCR_MON_REQ_Pos   19U
 
#define DCB_DEMCR_MON_REQ_Msk   (0x1UL << DCB_DEMCR_MON_REQ_Pos)
 
#define DCB_DEMCR_MON_STEP_Pos   18U
 
#define DCB_DEMCR_MON_STEP_Msk   (0x1UL << DCB_DEMCR_MON_STEP_Pos)
 
#define DCB_DEMCR_MON_PEND_Pos   17U
 
#define DCB_DEMCR_MON_PEND_Msk   (0x1UL << DCB_DEMCR_MON_PEND_Pos)
 
#define DCB_DEMCR_MON_EN_Pos   16U
 
#define DCB_DEMCR_MON_EN_Msk   (0x1UL << DCB_DEMCR_MON_EN_Pos)
 
#define DCB_DEMCR_VC_SFERR_Pos   11U
 
#define DCB_DEMCR_VC_SFERR_Msk   (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
 
#define DCB_DEMCR_VC_HARDERR_Pos   10U
 
#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
 
#define DCB_DEMCR_VC_INTERR_Pos   9U
 
#define DCB_DEMCR_VC_INTERR_Msk   (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
 
#define DCB_DEMCR_VC_BUSERR_Pos   8U
 
#define DCB_DEMCR_VC_BUSERR_Msk   (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
 
#define DCB_DEMCR_VC_STATERR_Pos   7U
 
#define DCB_DEMCR_VC_STATERR_Msk   (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
 
#define DCB_DEMCR_VC_CHKERR_Pos   6U
 
#define DCB_DEMCR_VC_CHKERR_Msk   (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
 
#define DCB_DEMCR_VC_NOCPERR_Pos   5U
 
#define DCB_DEMCR_VC_NOCPERR_Msk   (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
 
#define DCB_DEMCR_VC_MMERR_Pos   4U
 
#define DCB_DEMCR_VC_MMERR_Msk   (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
 
#define DCB_DEMCR_VC_CORERESET_Pos   0U
 
#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define DCB_DSCSR_CDSKEY_Pos   17U
 
#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)
 
#define DCB_DSCSR_CDS_Pos   16U
 
#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)
 
#define DCB_DSCSR_SBRSEL_Pos   1U
 
#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)
 
#define DCB_DSCSR_SBRSELEN_Pos   0U
 
#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)
 
#define DCB_DHCSR_DBGKEY_Pos   16U
 
#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
 
#define DCB_DHCSR_S_RESTART_ST_Pos   26U
 
#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
 
#define DCB_DHCSR_S_RESET_ST_Pos   25U
 
#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
 
#define DCB_DHCSR_S_RETIRE_ST_Pos   24U
 
#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
 
#define DCB_DHCSR_S_SDE_Pos   20U
 
#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)
 
#define DCB_DHCSR_S_LOCKUP_Pos   19U
 
#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
 
#define DCB_DHCSR_S_SLEEP_Pos   18U
 
#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
 
#define DCB_DHCSR_S_HALT_Pos   17U
 
#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)
 
#define DCB_DHCSR_S_REGRDY_Pos   16U
 
#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
 
#define DCB_DHCSR_C_SNAPSTALL_Pos   5U
 
#define DCB_DHCSR_C_SNAPSTALL_Msk   (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
 
#define DCB_DHCSR_C_MASKINTS_Pos   3U
 
#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
 
#define DCB_DHCSR_C_STEP_Pos   2U
 
#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)
 
#define DCB_DHCSR_C_HALT_Pos   1U
 
#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)
 
#define DCB_DHCSR_C_DEBUGEN_Pos   0U
 
#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)
 
#define DCB_DCRSR_REGWnR_Pos   16U
 
#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)
 
#define DCB_DCRSR_REGSEL_Pos   0U
 
#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)
 
#define DCB_DCRDR_DBGTMP_Pos   0U
 
#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)
 
#define DCB_DEMCR_TRCENA_Pos   24U
 
#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)
 
#define DCB_DEMCR_MONPRKEY_Pos   23U
 
#define DCB_DEMCR_MONPRKEY_Msk   (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
 
#define DCB_DEMCR_UMON_EN_Pos   21U
 
#define DCB_DEMCR_UMON_EN_Msk   (0x1UL << DCB_DEMCR_UMON_EN_Pos)
 
#define DCB_DEMCR_SDME_Pos   20U
 
#define DCB_DEMCR_SDME_Msk   (0x1UL << DCB_DEMCR_SDME_Pos)
 
#define DCB_DEMCR_MON_REQ_Pos   19U
 
#define DCB_DEMCR_MON_REQ_Msk   (0x1UL << DCB_DEMCR_MON_REQ_Pos)
 
#define DCB_DEMCR_MON_STEP_Pos   18U
 
#define DCB_DEMCR_MON_STEP_Msk   (0x1UL << DCB_DEMCR_MON_STEP_Pos)
 
#define DCB_DEMCR_MON_PEND_Pos   17U
 
#define DCB_DEMCR_MON_PEND_Msk   (0x1UL << DCB_DEMCR_MON_PEND_Pos)
 
#define DCB_DEMCR_MON_EN_Pos   16U
 
#define DCB_DEMCR_MON_EN_Msk   (0x1UL << DCB_DEMCR_MON_EN_Pos)
 
#define DCB_DEMCR_VC_SFERR_Pos   11U
 
#define DCB_DEMCR_VC_SFERR_Msk   (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
 
#define DCB_DEMCR_VC_HARDERR_Pos   10U
 
#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
 
#define DCB_DEMCR_VC_INTERR_Pos   9U
 
#define DCB_DEMCR_VC_INTERR_Msk   (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
 
#define DCB_DEMCR_VC_BUSERR_Pos   8U
 
#define DCB_DEMCR_VC_BUSERR_Msk   (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
 
#define DCB_DEMCR_VC_STATERR_Pos   7U
 
#define DCB_DEMCR_VC_STATERR_Msk   (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
 
#define DCB_DEMCR_VC_CHKERR_Pos   6U
 
#define DCB_DEMCR_VC_CHKERR_Msk   (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
 
#define DCB_DEMCR_VC_NOCPERR_Pos   5U
 
#define DCB_DEMCR_VC_NOCPERR_Msk   (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
 
#define DCB_DEMCR_VC_MMERR_Pos   4U
 
#define DCB_DEMCR_VC_MMERR_Msk   (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
 
#define DCB_DEMCR_VC_CORERESET_Pos   0U
 
#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define DCB_DSCSR_CDSKEY_Pos   17U
 
#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)
 
#define DCB_DSCSR_CDS_Pos   16U
 
#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)
 
#define DCB_DSCSR_SBRSEL_Pos   1U
 
#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)
 
#define DCB_DSCSR_SBRSELEN_Pos   0U
 
#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)
 
#define DCB_DHCSR_DBGKEY_Pos   16U
 
#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
 
#define DCB_DHCSR_S_RESTART_ST_Pos   26U
 
#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
 
#define DCB_DHCSR_S_RESET_ST_Pos   25U
 
#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
 
#define DCB_DHCSR_S_RETIRE_ST_Pos   24U
 
#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
 
#define DCB_DHCSR_S_SDE_Pos   20U
 
#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)
 
#define DCB_DHCSR_S_LOCKUP_Pos   19U
 
#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
 
#define DCB_DHCSR_S_SLEEP_Pos   18U
 
#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
 
#define DCB_DHCSR_S_HALT_Pos   17U
 
#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)
 
#define DCB_DHCSR_S_REGRDY_Pos   16U
 
#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
 
#define DCB_DHCSR_C_MASKINTS_Pos   3U
 
#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
 
#define DCB_DHCSR_C_STEP_Pos   2U
 
#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)
 
#define DCB_DHCSR_C_HALT_Pos   1U
 
#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)
 
#define DCB_DHCSR_C_DEBUGEN_Pos   0U
 
#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)
 
#define DCB_DCRSR_REGWnR_Pos   16U
 
#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)
 
#define DCB_DCRSR_REGSEL_Pos   0U
 
#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)
 
#define DCB_DCRDR_DBGTMP_Pos   0U
 
#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)
 
#define DCB_DEMCR_TRCENA_Pos   24U
 
#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)
 
#define DCB_DEMCR_VC_HARDERR_Pos   10U
 
#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
 
#define DCB_DEMCR_VC_CORERESET_Pos   0U
 
#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define DCB_DSCSR_CDSKEY_Pos   17U
 
#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)
 
#define DCB_DSCSR_CDS_Pos   16U
 
#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)
 
#define DCB_DSCSR_SBRSEL_Pos   1U
 
#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)
 
#define DCB_DSCSR_SBRSELEN_Pos   0U
 
#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)
 
#define DCB_DHCSR_DBGKEY_Pos   16U
 
#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
 
#define DCB_DHCSR_S_RESTART_ST_Pos   26U
 
#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
 
#define DCB_DHCSR_S_RESET_ST_Pos   25U
 
#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
 
#define DCB_DHCSR_S_RETIRE_ST_Pos   24U
 
#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
 
#define DCB_DHCSR_S_SDE_Pos   20U
 
#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)
 
#define DCB_DHCSR_S_LOCKUP_Pos   19U
 
#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
 
#define DCB_DHCSR_S_SLEEP_Pos   18U
 
#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
 
#define DCB_DHCSR_S_HALT_Pos   17U
 
#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)
 
#define DCB_DHCSR_S_REGRDY_Pos   16U
 
#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
 
#define DCB_DHCSR_C_SNAPSTALL_Pos   5U
 
#define DCB_DHCSR_C_SNAPSTALL_Msk   (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
 
#define DCB_DHCSR_C_MASKINTS_Pos   3U
 
#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
 
#define DCB_DHCSR_C_STEP_Pos   2U
 
#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)
 
#define DCB_DHCSR_C_HALT_Pos   1U
 
#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)
 
#define DCB_DHCSR_C_DEBUGEN_Pos   0U
 
#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)
 
#define DCB_DCRSR_REGWnR_Pos   16U
 
#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)
 
#define DCB_DCRSR_REGSEL_Pos   0U
 
#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)
 
#define DCB_DCRDR_DBGTMP_Pos   0U
 
#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)
 
#define DCB_DEMCR_TRCENA_Pos   24U
 
#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)
 
#define DCB_DEMCR_MONPRKEY_Pos   23U
 
#define DCB_DEMCR_MONPRKEY_Msk   (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
 
#define DCB_DEMCR_UMON_EN_Pos   21U
 
#define DCB_DEMCR_UMON_EN_Msk   (0x1UL << DCB_DEMCR_UMON_EN_Pos)
 
#define DCB_DEMCR_SDME_Pos   20U
 
#define DCB_DEMCR_SDME_Msk   (0x1UL << DCB_DEMCR_SDME_Pos)
 
#define DCB_DEMCR_MON_REQ_Pos   19U
 
#define DCB_DEMCR_MON_REQ_Msk   (0x1UL << DCB_DEMCR_MON_REQ_Pos)
 
#define DCB_DEMCR_MON_STEP_Pos   18U
 
#define DCB_DEMCR_MON_STEP_Msk   (0x1UL << DCB_DEMCR_MON_STEP_Pos)
 
#define DCB_DEMCR_MON_PEND_Pos   17U
 
#define DCB_DEMCR_MON_PEND_Msk   (0x1UL << DCB_DEMCR_MON_PEND_Pos)
 
#define DCB_DEMCR_MON_EN_Pos   16U
 
#define DCB_DEMCR_MON_EN_Msk   (0x1UL << DCB_DEMCR_MON_EN_Pos)
 
#define DCB_DEMCR_VC_SFERR_Pos   11U
 
#define DCB_DEMCR_VC_SFERR_Msk   (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
 
#define DCB_DEMCR_VC_HARDERR_Pos   10U
 
#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
 
#define DCB_DEMCR_VC_INTERR_Pos   9U
 
#define DCB_DEMCR_VC_INTERR_Msk   (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
 
#define DCB_DEMCR_VC_BUSERR_Pos   8U
 
#define DCB_DEMCR_VC_BUSERR_Msk   (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
 
#define DCB_DEMCR_VC_STATERR_Pos   7U
 
#define DCB_DEMCR_VC_STATERR_Msk   (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
 
#define DCB_DEMCR_VC_CHKERR_Pos   6U
 
#define DCB_DEMCR_VC_CHKERR_Msk   (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
 
#define DCB_DEMCR_VC_NOCPERR_Pos   5U
 
#define DCB_DEMCR_VC_NOCPERR_Msk   (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
 
#define DCB_DEMCR_VC_MMERR_Pos   4U
 
#define DCB_DEMCR_VC_MMERR_Msk   (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
 
#define DCB_DEMCR_VC_CORERESET_Pos   0U
 
#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define DCB_DSCSR_CDSKEY_Pos   17U
 
#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)
 
#define DCB_DSCSR_CDS_Pos   16U
 
#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)
 
#define DCB_DSCSR_SBRSEL_Pos   1U
 
#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)
 
#define DCB_DSCSR_SBRSELEN_Pos   0U
 
#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)
 
#define DCB_DHCSR_DBGKEY_Pos   16U
 
#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
 
#define DCB_DHCSR_S_RESTART_ST_Pos   26U
 
#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
 
#define DCB_DHCSR_S_RESET_ST_Pos   25U
 
#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
 
#define DCB_DHCSR_S_RETIRE_ST_Pos   24U
 
#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
 
#define DCB_DHCSR_S_SDE_Pos   20U
 
#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)
 
#define DCB_DHCSR_S_LOCKUP_Pos   19U
 
#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
 
#define DCB_DHCSR_S_SLEEP_Pos   18U
 
#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
 
#define DCB_DHCSR_S_HALT_Pos   17U
 
#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)
 
#define DCB_DHCSR_S_REGRDY_Pos   16U
 
#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
 
#define DCB_DHCSR_C_SNAPSTALL_Pos   5U
 
#define DCB_DHCSR_C_SNAPSTALL_Msk   (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
 
#define DCB_DHCSR_C_MASKINTS_Pos   3U
 
#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
 
#define DCB_DHCSR_C_STEP_Pos   2U
 
#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)
 
#define DCB_DHCSR_C_HALT_Pos   1U
 
#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)
 
#define DCB_DHCSR_C_DEBUGEN_Pos   0U
 
#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)
 
#define DCB_DCRSR_REGWnR_Pos   16U
 
#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)
 
#define DCB_DCRSR_REGSEL_Pos   0U
 
#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)
 
#define DCB_DCRDR_DBGTMP_Pos   0U
 
#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)
 
#define DCB_DEMCR_TRCENA_Pos   24U
 
#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)
 
#define DCB_DEMCR_MONPRKEY_Pos   23U
 
#define DCB_DEMCR_MONPRKEY_Msk   (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
 
#define DCB_DEMCR_UMON_EN_Pos   21U
 
#define DCB_DEMCR_UMON_EN_Msk   (0x1UL << DCB_DEMCR_UMON_EN_Pos)
 
#define DCB_DEMCR_SDME_Pos   20U
 
#define DCB_DEMCR_SDME_Msk   (0x1UL << DCB_DEMCR_SDME_Pos)
 
#define DCB_DEMCR_MON_REQ_Pos   19U
 
#define DCB_DEMCR_MON_REQ_Msk   (0x1UL << DCB_DEMCR_MON_REQ_Pos)
 
#define DCB_DEMCR_MON_STEP_Pos   18U
 
#define DCB_DEMCR_MON_STEP_Msk   (0x1UL << DCB_DEMCR_MON_STEP_Pos)
 
#define DCB_DEMCR_MON_PEND_Pos   17U
 
#define DCB_DEMCR_MON_PEND_Msk   (0x1UL << DCB_DEMCR_MON_PEND_Pos)
 
#define DCB_DEMCR_MON_EN_Pos   16U
 
#define DCB_DEMCR_MON_EN_Msk   (0x1UL << DCB_DEMCR_MON_EN_Pos)
 
#define DCB_DEMCR_VC_SFERR_Pos   11U
 
#define DCB_DEMCR_VC_SFERR_Msk   (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
 
#define DCB_DEMCR_VC_HARDERR_Pos   10U
 
#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
 
#define DCB_DEMCR_VC_INTERR_Pos   9U
 
#define DCB_DEMCR_VC_INTERR_Msk   (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
 
#define DCB_DEMCR_VC_BUSERR_Pos   8U
 
#define DCB_DEMCR_VC_BUSERR_Msk   (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
 
#define DCB_DEMCR_VC_STATERR_Pos   7U
 
#define DCB_DEMCR_VC_STATERR_Msk   (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
 
#define DCB_DEMCR_VC_CHKERR_Pos   6U
 
#define DCB_DEMCR_VC_CHKERR_Msk   (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
 
#define DCB_DEMCR_VC_NOCPERR_Pos   5U
 
#define DCB_DEMCR_VC_NOCPERR_Msk   (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
 
#define DCB_DEMCR_VC_MMERR_Pos   4U
 
#define DCB_DEMCR_VC_MMERR_Msk   (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
 
#define DCB_DEMCR_VC_CORERESET_Pos   0U
 
#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
 
#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define DCB_DSCSR_CDSKEY_Pos   17U
 
#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)
 
#define DCB_DSCSR_CDS_Pos   16U
 
#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)
 
#define DCB_DSCSR_SBRSEL_Pos   1U
 
#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)
 
#define DCB_DSCSR_SBRSELEN_Pos   0U
 
#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)
 
#define DCB_DHCSR_S_FPD_Pos   23U
 
#define DCB_DHCSR_S_FPD_Msk   (0x1UL << DCB_DHCSR_S_FPD_Pos)
 
#define DCB_DHCSR_S_SUIDE_Pos   22U
 
#define DCB_DHCSR_S_SUIDE_Msk   (0x1UL << DCB_DHCSR_S_SUIDE_Pos)
 
#define DCB_DHCSR_S_NSUIDE_Pos   21U
 
#define DCB_DHCSR_S_NSUIDE_Msk   (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)
 
#define DCB_DHCSR_C_PMOV_Pos   6U
 
#define DCB_DHCSR_C_PMOV_Msk   (0x1UL << DCB_DHCSR_C_PMOV_Pos)
 
#define DCB_DSCEMCR_CLR_MON_REQ_Pos   19U
 
#define DCB_DSCEMCR_CLR_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)
 
#define DCB_DSCEMCR_CLR_MON_PEND_Pos   17U
 
#define DCB_DSCEMCR_CLR_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)
 
#define DCB_DSCEMCR_SET_MON_REQ_Pos   3U
 
#define DCB_DSCEMCR_SET_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)
 
#define DCB_DSCEMCR_SET_MON_PEND_Pos   1U
 
#define DCB_DSCEMCR_SET_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)
 
#define DCB_DAUTHCTRL_UIDEN_Pos   10U
 
#define DCB_DAUTHCTRL_UIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)
 
#define DCB_DAUTHCTRL_UIDAPEN_Pos   9U
 
#define DCB_DAUTHCTRL_UIDAPEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)
 
#define DCB_DAUTHCTRL_FSDMA_Pos   8U
 
#define DCB_DAUTHCTRL_FSDMA_Msk   (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)
 
#define DCB_DHCSR_S_FPD_Pos   23U
 
#define DCB_DHCSR_S_FPD_Msk   (0x1UL << DCB_DHCSR_S_FPD_Pos)
 
#define DCB_DHCSR_S_SUIDE_Pos   22U
 
#define DCB_DHCSR_S_SUIDE_Msk   (0x1UL << DCB_DHCSR_S_SUIDE_Pos)
 
#define DCB_DHCSR_S_NSUIDE_Pos   21U
 
#define DCB_DHCSR_S_NSUIDE_Msk   (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)
 
#define DCB_DHCSR_C_PMOV_Pos   6U
 
#define DCB_DHCSR_C_PMOV_Msk   (0x1UL << DCB_DHCSR_C_PMOV_Pos)
 
#define DCB_DSCEMCR_CLR_MON_REQ_Pos   19U
 
#define DCB_DSCEMCR_CLR_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)
 
#define DCB_DSCEMCR_CLR_MON_PEND_Pos   17U
 
#define DCB_DSCEMCR_CLR_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)
 
#define DCB_DSCEMCR_SET_MON_REQ_Pos   3U
 
#define DCB_DSCEMCR_SET_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)
 
#define DCB_DSCEMCR_SET_MON_PEND_Pos   1U
 
#define DCB_DSCEMCR_SET_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)
 
#define DCB_DAUTHCTRL_UIDEN_Pos   10U
 
#define DCB_DAUTHCTRL_UIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)
 
#define DCB_DAUTHCTRL_UIDAPEN_Pos   9U
 
#define DCB_DAUTHCTRL_UIDAPEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)
 
#define DCB_DAUTHCTRL_FSDMA_Pos   8U
 
#define DCB_DAUTHCTRL_FSDMA_Msk   (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)
 
#define DCB_DHCSR_S_FPD_Pos   23U
 
#define DCB_DHCSR_S_FPD_Msk   (0x1UL << DCB_DHCSR_S_FPD_Pos)
 
#define DCB_DHCSR_S_SUIDE_Pos   22U
 
#define DCB_DHCSR_S_SUIDE_Msk   (0x1UL << DCB_DHCSR_S_SUIDE_Pos)
 
#define DCB_DHCSR_S_NSUIDE_Pos   21U
 
#define DCB_DHCSR_S_NSUIDE_Msk   (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)
 
#define DCB_DHCSR_C_PMOV_Pos   6U
 
#define DCB_DHCSR_C_PMOV_Msk   (0x1UL << DCB_DHCSR_C_PMOV_Pos)
 
#define DCB_DSCEMCR_CLR_MON_REQ_Pos   19U
 
#define DCB_DSCEMCR_CLR_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)
 
#define DCB_DSCEMCR_CLR_MON_PEND_Pos   17U
 
#define DCB_DSCEMCR_CLR_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)
 
#define DCB_DSCEMCR_SET_MON_REQ_Pos   3U
 
#define DCB_DSCEMCR_SET_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)
 
#define DCB_DSCEMCR_SET_MON_PEND_Pos   1U
 
#define DCB_DSCEMCR_SET_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)
 
#define DCB_DAUTHCTRL_UIDEN_Pos   10U
 
#define DCB_DAUTHCTRL_UIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)
 
#define DCB_DAUTHCTRL_UIDAPEN_Pos   9U
 
#define DCB_DAUTHCTRL_UIDAPEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)
 
#define DCB_DAUTHCTRL_FSDMA_Pos   8U
 
#define DCB_DAUTHCTRL_FSDMA_Msk   (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)
 
#define DCB_DHCSR_S_FPD_Pos   23U
 
#define DCB_DHCSR_S_FPD_Msk   (0x1UL << DCB_DHCSR_S_FPD_Pos)
 
#define DCB_DHCSR_S_SUIDE_Pos   22U
 
#define DCB_DHCSR_S_SUIDE_Msk   (0x1UL << DCB_DHCSR_S_SUIDE_Pos)
 
#define DCB_DHCSR_S_NSUIDE_Pos   21U
 
#define DCB_DHCSR_S_NSUIDE_Msk   (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)
 
#define DCB_DHCSR_C_PMOV_Pos   6U
 
#define DCB_DHCSR_C_PMOV_Msk   (0x1UL << DCB_DHCSR_C_PMOV_Pos)
 
#define DCB_DSCEMCR_CLR_MON_REQ_Pos   19U
 
#define DCB_DSCEMCR_CLR_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)
 
#define DCB_DSCEMCR_CLR_MON_PEND_Pos   17U
 
#define DCB_DSCEMCR_CLR_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)
 
#define DCB_DSCEMCR_SET_MON_REQ_Pos   3U
 
#define DCB_DSCEMCR_SET_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)
 
#define DCB_DSCEMCR_SET_MON_PEND_Pos   1U
 
#define DCB_DSCEMCR_SET_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)
 
#define DCB_DAUTHCTRL_UIDEN_Pos   10U
 
#define DCB_DAUTHCTRL_UIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)
 
#define DCB_DAUTHCTRL_UIDAPEN_Pos   9U
 
#define DCB_DAUTHCTRL_UIDAPEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)
 
#define DCB_DAUTHCTRL_FSDMA_Pos   8U
 
#define DCB_DAUTHCTRL_FSDMA_Msk   (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)
 

Detailed Description

Type definitions for the Debug Control Block Registers.

Macro Definition Documentation

◆ DCB_DAUTHCTRL_FSDMA_Msk [1/4]

#define DCB_DAUTHCTRL_FSDMA_Msk   (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask

Definition at line 2967 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_FSDMA_Msk [2/4]

#define DCB_DAUTHCTRL_FSDMA_Msk   (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask

Definition at line 3521 of file core_cm55.h.

◆ DCB_DAUTHCTRL_FSDMA_Msk [3/4]

#define DCB_DAUTHCTRL_FSDMA_Msk   (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask

Definition at line 3426 of file core_cm85.h.

◆ DCB_DAUTHCTRL_FSDMA_Msk [4/4]

#define DCB_DAUTHCTRL_FSDMA_Msk   (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask

Definition at line 2967 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_FSDMA_Pos [1/4]

#define DCB_DAUTHCTRL_FSDMA_Pos   8U

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position

Definition at line 2966 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_FSDMA_Pos [2/4]

#define DCB_DAUTHCTRL_FSDMA_Pos   8U

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position

Definition at line 3520 of file core_cm55.h.

◆ DCB_DAUTHCTRL_FSDMA_Pos [3/4]

#define DCB_DAUTHCTRL_FSDMA_Pos   8U

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position

Definition at line 3425 of file core_cm85.h.

◆ DCB_DAUTHCTRL_FSDMA_Pos [4/4]

#define DCB_DAUTHCTRL_FSDMA_Pos   8U

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position

Definition at line 2966 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Msk [1/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask

Definition at line 2976 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Msk [2/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask

Definition at line 1177 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Msk [3/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask

Definition at line 2018 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Msk [4/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask

Definition at line 1252 of file core_cm23.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Msk [5/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask

Definition at line 2093 of file core_cm33.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Msk [6/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask

Definition at line 2093 of file core_cm35p.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Msk [7/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask

Definition at line 3530 of file core_cm55.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Msk [8/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask

Definition at line 3435 of file core_cm85.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Msk [9/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask

Definition at line 2020 of file core_starmc1.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Msk [10/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask

Definition at line 2976 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Msk [11/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask

Definition at line 1177 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Msk [12/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask

Definition at line 2018 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Msk [13/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask

Definition at line 2093 of file core_cm33.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Pos [1/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position

Definition at line 2975 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Pos [2/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position

Definition at line 1176 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Pos [3/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position

Definition at line 2017 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Pos [4/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position

Definition at line 1251 of file core_cm23.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Pos [5/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position

Definition at line 2092 of file core_cm33.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Pos [6/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position

Definition at line 2092 of file core_cm35p.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Pos [7/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position

Definition at line 3529 of file core_cm55.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Pos [8/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position

Definition at line 3434 of file core_cm85.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Pos [9/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position

Definition at line 2019 of file core_starmc1.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Pos [10/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position

Definition at line 2975 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Pos [11/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position

Definition at line 1176 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Pos [12/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position

Definition at line 2017 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Pos [13/13]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos   1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position

Definition at line 2092 of file core_cm33.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Msk [1/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask

Definition at line 2970 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Msk [2/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask

Definition at line 1171 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Msk [3/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask

Definition at line 2012 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Msk [4/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask

Definition at line 1246 of file core_cm23.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Msk [5/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask

Definition at line 2087 of file core_cm33.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Msk [6/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask

Definition at line 2087 of file core_cm35p.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Msk [7/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask

Definition at line 3524 of file core_cm55.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Msk [8/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask

Definition at line 3429 of file core_cm85.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Msk [9/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask

Definition at line 2014 of file core_starmc1.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Msk [10/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask

Definition at line 2970 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Msk [11/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask

Definition at line 1171 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Msk [12/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask

Definition at line 2012 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Msk [13/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask

Definition at line 2087 of file core_cm33.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Pos [1/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position

Definition at line 2969 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Pos [2/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position

Definition at line 1170 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Pos [3/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position

Definition at line 2011 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Pos [4/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position

Definition at line 1245 of file core_cm23.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Pos [5/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position

Definition at line 2086 of file core_cm33.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Pos [6/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position

Definition at line 2086 of file core_cm35p.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Pos [7/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position

Definition at line 3523 of file core_cm55.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Pos [8/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position

Definition at line 3428 of file core_cm85.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Pos [9/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position

Definition at line 2013 of file core_starmc1.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Pos [10/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position

Definition at line 2969 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Pos [11/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position

Definition at line 1170 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Pos [12/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position

Definition at line 2011 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Pos [13/13]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position

Definition at line 2086 of file core_cm33.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Msk [1/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask

Definition at line 2979 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Msk [2/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask

Definition at line 1180 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Msk [3/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask

Definition at line 2021 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Msk [4/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask

Definition at line 1255 of file core_cm23.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Msk [5/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask

Definition at line 2096 of file core_cm33.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Msk [6/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask

Definition at line 2096 of file core_cm35p.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Msk [7/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask

Definition at line 3533 of file core_cm55.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Msk [8/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask

Definition at line 3438 of file core_cm85.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Msk [9/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask

Definition at line 2023 of file core_starmc1.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Msk [10/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask

Definition at line 2979 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Msk [11/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask

Definition at line 1180 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Msk [12/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask

Definition at line 2021 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Msk [13/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask

Definition at line 2096 of file core_cm33.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Pos [1/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U

DCB DAUTHCTRL: Secure invasive debug enable select Position

Definition at line 2978 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Pos [2/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U

DCB DAUTHCTRL: Secure invasive debug enable select Position

Definition at line 1179 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Pos [3/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U

DCB DAUTHCTRL: Secure invasive debug enable select Position

Definition at line 2020 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Pos [4/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U

DCB DAUTHCTRL: Secure invasive debug enable select Position

Definition at line 1254 of file core_cm23.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Pos [5/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U

DCB DAUTHCTRL: Secure invasive debug enable select Position

Definition at line 2095 of file core_cm33.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Pos [6/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U

DCB DAUTHCTRL: Secure invasive debug enable select Position

Definition at line 2095 of file core_cm35p.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Pos [7/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U

DCB DAUTHCTRL: Secure invasive debug enable select Position

Definition at line 3532 of file core_cm55.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Pos [8/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U

DCB DAUTHCTRL: Secure invasive debug enable select Position

Definition at line 3437 of file core_cm85.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Pos [9/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U

DCB DAUTHCTRL: Secure invasive debug enable select Position

Definition at line 2022 of file core_starmc1.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Pos [10/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U

DCB DAUTHCTRL: Secure invasive debug enable select Position

Definition at line 2978 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Pos [11/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U

DCB DAUTHCTRL: Secure invasive debug enable select Position

Definition at line 1179 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Pos [12/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U

DCB DAUTHCTRL: Secure invasive debug enable select Position

Definition at line 2020 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Pos [13/13]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos   0U

DCB DAUTHCTRL: Secure invasive debug enable select Position

Definition at line 2095 of file core_cm33.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Msk [1/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask

Definition at line 2973 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Msk [2/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask

Definition at line 1174 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Msk [3/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask

Definition at line 2015 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Msk [4/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask

Definition at line 1249 of file core_cm23.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Msk [5/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask

Definition at line 2090 of file core_cm33.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Msk [6/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask

Definition at line 2090 of file core_cm35p.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Msk [7/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask

Definition at line 3527 of file core_cm55.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Msk [8/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask

Definition at line 3432 of file core_cm85.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Msk [9/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask

Definition at line 2017 of file core_starmc1.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Msk [10/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask

Definition at line 2973 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Msk [11/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask

Definition at line 1174 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Msk [12/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask

Definition at line 2015 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Msk [13/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask

Definition at line 2090 of file core_cm33.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Pos [1/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position

Definition at line 2972 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Pos [2/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position

Definition at line 1173 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Pos [3/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position

Definition at line 2014 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Pos [4/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position

Definition at line 1248 of file core_cm23.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Pos [5/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position

Definition at line 2089 of file core_cm33.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Pos [6/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position

Definition at line 2089 of file core_cm35p.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Pos [7/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position

Definition at line 3526 of file core_cm55.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Pos [8/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position

Definition at line 3431 of file core_cm85.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Pos [9/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position

Definition at line 2016 of file core_starmc1.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Pos [10/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position

Definition at line 2972 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Pos [11/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position

Definition at line 1173 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Pos [12/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position

Definition at line 2014 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Pos [13/13]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position

Definition at line 2089 of file core_cm33.h.

◆ DCB_DAUTHCTRL_UIDAPEN_Msk [1/4]

#define DCB_DAUTHCTRL_UIDAPEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask

Definition at line 2964 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_UIDAPEN_Msk [2/4]

#define DCB_DAUTHCTRL_UIDAPEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask

Definition at line 3518 of file core_cm55.h.

◆ DCB_DAUTHCTRL_UIDAPEN_Msk [3/4]

#define DCB_DAUTHCTRL_UIDAPEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask

Definition at line 3423 of file core_cm85.h.

◆ DCB_DAUTHCTRL_UIDAPEN_Msk [4/4]

#define DCB_DAUTHCTRL_UIDAPEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask

Definition at line 2964 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_UIDAPEN_Pos [1/4]

#define DCB_DAUTHCTRL_UIDAPEN_Pos   9U

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position

Definition at line 2963 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_UIDAPEN_Pos [2/4]

#define DCB_DAUTHCTRL_UIDAPEN_Pos   9U

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position

Definition at line 3517 of file core_cm55.h.

◆ DCB_DAUTHCTRL_UIDAPEN_Pos [3/4]

#define DCB_DAUTHCTRL_UIDAPEN_Pos   9U

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position

Definition at line 3422 of file core_cm85.h.

◆ DCB_DAUTHCTRL_UIDAPEN_Pos [4/4]

#define DCB_DAUTHCTRL_UIDAPEN_Pos   9U

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position

Definition at line 2963 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_UIDEN_Msk [1/4]

#define DCB_DAUTHCTRL_UIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask

Definition at line 2961 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_UIDEN_Msk [2/4]

#define DCB_DAUTHCTRL_UIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask

Definition at line 3515 of file core_cm55.h.

◆ DCB_DAUTHCTRL_UIDEN_Msk [3/4]

#define DCB_DAUTHCTRL_UIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask

Definition at line 3420 of file core_cm85.h.

◆ DCB_DAUTHCTRL_UIDEN_Msk [4/4]

#define DCB_DAUTHCTRL_UIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask

Definition at line 2961 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_UIDEN_Pos [1/4]

#define DCB_DAUTHCTRL_UIDEN_Pos   10U

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position

Definition at line 2960 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_UIDEN_Pos [2/4]

#define DCB_DAUTHCTRL_UIDEN_Pos   10U

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position

Definition at line 3514 of file core_cm55.h.

◆ DCB_DAUTHCTRL_UIDEN_Pos [3/4]

#define DCB_DAUTHCTRL_UIDEN_Pos   10U

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position

Definition at line 3419 of file core_cm85.h.

◆ DCB_DAUTHCTRL_UIDEN_Pos [4/4]

#define DCB_DAUTHCTRL_UIDEN_Pos   10U

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position

Definition at line 2960 of file core_armv81mml.h.

◆ DCB_DCRDR_DBGTMP_Msk [1/13]

#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)

DCB DCRDR: Data temporary buffer Mask

Definition at line 2892 of file core_armv81mml.h.

◆ DCB_DCRDR_DBGTMP_Msk [2/13]

#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)

DCB DCRDR: Data temporary buffer Mask

Definition at line 1157 of file core_armv8mbl.h.

◆ DCB_DCRDR_DBGTMP_Msk [3/13]

#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)

DCB DCRDR: Data temporary buffer Mask

Definition at line 1956 of file core_armv8mml.h.

◆ DCB_DCRDR_DBGTMP_Msk [4/13]

#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)

DCB DCRDR: Data temporary buffer Mask

Definition at line 1232 of file core_cm23.h.

◆ DCB_DCRDR_DBGTMP_Msk [5/13]

#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)

DCB DCRDR: Data temporary buffer Mask

Definition at line 2031 of file core_cm33.h.

◆ DCB_DCRDR_DBGTMP_Msk [6/13]

#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)

DCB DCRDR: Data temporary buffer Mask

Definition at line 2031 of file core_cm35p.h.

◆ DCB_DCRDR_DBGTMP_Msk [7/13]

#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)

DCB DCRDR: Data temporary buffer Mask

Definition at line 3446 of file core_cm55.h.

◆ DCB_DCRDR_DBGTMP_Msk [8/13]

#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)

DCB DCRDR: Data temporary buffer Mask

Definition at line 3351 of file core_cm85.h.

◆ DCB_DCRDR_DBGTMP_Msk [9/13]

#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)

DCB DCRDR: Data temporary buffer Mask

Definition at line 1958 of file core_starmc1.h.

◆ DCB_DCRDR_DBGTMP_Msk [10/13]

#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)

DCB DCRDR: Data temporary buffer Mask

Definition at line 2892 of file core_armv81mml.h.

◆ DCB_DCRDR_DBGTMP_Msk [11/13]

#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)

DCB DCRDR: Data temporary buffer Mask

Definition at line 1157 of file core_armv8mbl.h.

◆ DCB_DCRDR_DBGTMP_Msk [12/13]

#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)

DCB DCRDR: Data temporary buffer Mask

Definition at line 1956 of file core_armv8mml.h.

◆ DCB_DCRDR_DBGTMP_Msk [13/13]

#define DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)

DCB DCRDR: Data temporary buffer Mask

Definition at line 2031 of file core_cm33.h.

◆ DCB_DCRDR_DBGTMP_Pos [1/13]

#define DCB_DCRDR_DBGTMP_Pos   0U

DCB DCRDR: Data temporary buffer Position

Definition at line 2891 of file core_armv81mml.h.

◆ DCB_DCRDR_DBGTMP_Pos [2/13]

#define DCB_DCRDR_DBGTMP_Pos   0U

DCB DCRDR: Data temporary buffer Position

Definition at line 1156 of file core_armv8mbl.h.

◆ DCB_DCRDR_DBGTMP_Pos [3/13]

#define DCB_DCRDR_DBGTMP_Pos   0U

DCB DCRDR: Data temporary buffer Position

Definition at line 1955 of file core_armv8mml.h.

◆ DCB_DCRDR_DBGTMP_Pos [4/13]

#define DCB_DCRDR_DBGTMP_Pos   0U

DCB DCRDR: Data temporary buffer Position

Definition at line 1231 of file core_cm23.h.

◆ DCB_DCRDR_DBGTMP_Pos [5/13]

#define DCB_DCRDR_DBGTMP_Pos   0U

DCB DCRDR: Data temporary buffer Position

Definition at line 2030 of file core_cm33.h.

◆ DCB_DCRDR_DBGTMP_Pos [6/13]

#define DCB_DCRDR_DBGTMP_Pos   0U

DCB DCRDR: Data temporary buffer Position

Definition at line 2030 of file core_cm35p.h.

◆ DCB_DCRDR_DBGTMP_Pos [7/13]

#define DCB_DCRDR_DBGTMP_Pos   0U

DCB DCRDR: Data temporary buffer Position

Definition at line 3445 of file core_cm55.h.

◆ DCB_DCRDR_DBGTMP_Pos [8/13]

#define DCB_DCRDR_DBGTMP_Pos   0U

DCB DCRDR: Data temporary buffer Position

Definition at line 3350 of file core_cm85.h.

◆ DCB_DCRDR_DBGTMP_Pos [9/13]

#define DCB_DCRDR_DBGTMP_Pos   0U

DCB DCRDR: Data temporary buffer Position

Definition at line 1957 of file core_starmc1.h.

◆ DCB_DCRDR_DBGTMP_Pos [10/13]

#define DCB_DCRDR_DBGTMP_Pos   0U

DCB DCRDR: Data temporary buffer Position

Definition at line 2891 of file core_armv81mml.h.

◆ DCB_DCRDR_DBGTMP_Pos [11/13]

#define DCB_DCRDR_DBGTMP_Pos   0U

DCB DCRDR: Data temporary buffer Position

Definition at line 1156 of file core_armv8mbl.h.

◆ DCB_DCRDR_DBGTMP_Pos [12/13]

#define DCB_DCRDR_DBGTMP_Pos   0U

DCB DCRDR: Data temporary buffer Position

Definition at line 1955 of file core_armv8mml.h.

◆ DCB_DCRDR_DBGTMP_Pos [13/13]

#define DCB_DCRDR_DBGTMP_Pos   0U

DCB DCRDR: Data temporary buffer Position

Definition at line 2030 of file core_cm33.h.

◆ DCB_DCRSR_REGSEL_Msk [1/13]

#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)

DCB DCRSR: Register selector Mask

Definition at line 2888 of file core_armv81mml.h.

◆ DCB_DCRSR_REGSEL_Msk [2/13]

#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)

DCB DCRSR: Register selector Mask

Definition at line 1153 of file core_armv8mbl.h.

◆ DCB_DCRSR_REGSEL_Msk [3/13]

#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)

DCB DCRSR: Register selector Mask

Definition at line 1952 of file core_armv8mml.h.

◆ DCB_DCRSR_REGSEL_Msk [4/13]

#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)

DCB DCRSR: Register selector Mask

Definition at line 1228 of file core_cm23.h.

◆ DCB_DCRSR_REGSEL_Msk [5/13]

#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)

DCB DCRSR: Register selector Mask

Definition at line 2027 of file core_cm33.h.

◆ DCB_DCRSR_REGSEL_Msk [6/13]

#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)

DCB DCRSR: Register selector Mask

Definition at line 2027 of file core_cm35p.h.

◆ DCB_DCRSR_REGSEL_Msk [7/13]

#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)

DCB DCRSR: Register selector Mask

Definition at line 3442 of file core_cm55.h.

◆ DCB_DCRSR_REGSEL_Msk [8/13]

#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)

DCB DCRSR: Register selector Mask

Definition at line 3347 of file core_cm85.h.

◆ DCB_DCRSR_REGSEL_Msk [9/13]

#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)

DCB DCRSR: Register selector Mask

Definition at line 1954 of file core_starmc1.h.

◆ DCB_DCRSR_REGSEL_Msk [10/13]

#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)

DCB DCRSR: Register selector Mask

Definition at line 2888 of file core_armv81mml.h.

◆ DCB_DCRSR_REGSEL_Msk [11/13]

#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)

DCB DCRSR: Register selector Mask

Definition at line 1153 of file core_armv8mbl.h.

◆ DCB_DCRSR_REGSEL_Msk [12/13]

#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)

DCB DCRSR: Register selector Mask

Definition at line 1952 of file core_armv8mml.h.

◆ DCB_DCRSR_REGSEL_Msk [13/13]

#define DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)

DCB DCRSR: Register selector Mask

Definition at line 2027 of file core_cm33.h.

◆ DCB_DCRSR_REGSEL_Pos [1/13]

#define DCB_DCRSR_REGSEL_Pos   0U

DCB DCRSR: Register selector Position

Definition at line 2887 of file core_armv81mml.h.

◆ DCB_DCRSR_REGSEL_Pos [2/13]

#define DCB_DCRSR_REGSEL_Pos   0U

DCB DCRSR: Register selector Position

Definition at line 1152 of file core_armv8mbl.h.

◆ DCB_DCRSR_REGSEL_Pos [3/13]

#define DCB_DCRSR_REGSEL_Pos   0U

DCB DCRSR: Register selector Position

Definition at line 1951 of file core_armv8mml.h.

◆ DCB_DCRSR_REGSEL_Pos [4/13]

#define DCB_DCRSR_REGSEL_Pos   0U

DCB DCRSR: Register selector Position

Definition at line 1227 of file core_cm23.h.

◆ DCB_DCRSR_REGSEL_Pos [5/13]

#define DCB_DCRSR_REGSEL_Pos   0U

DCB DCRSR: Register selector Position

Definition at line 2026 of file core_cm33.h.

◆ DCB_DCRSR_REGSEL_Pos [6/13]

#define DCB_DCRSR_REGSEL_Pos   0U

DCB DCRSR: Register selector Position

Definition at line 2026 of file core_cm35p.h.

◆ DCB_DCRSR_REGSEL_Pos [7/13]

#define DCB_DCRSR_REGSEL_Pos   0U

DCB DCRSR: Register selector Position

Definition at line 3441 of file core_cm55.h.

◆ DCB_DCRSR_REGSEL_Pos [8/13]

#define DCB_DCRSR_REGSEL_Pos   0U

DCB DCRSR: Register selector Position

Definition at line 3346 of file core_cm85.h.

◆ DCB_DCRSR_REGSEL_Pos [9/13]

#define DCB_DCRSR_REGSEL_Pos   0U

DCB DCRSR: Register selector Position

Definition at line 1953 of file core_starmc1.h.

◆ DCB_DCRSR_REGSEL_Pos [10/13]

#define DCB_DCRSR_REGSEL_Pos   0U

DCB DCRSR: Register selector Position

Definition at line 2887 of file core_armv81mml.h.

◆ DCB_DCRSR_REGSEL_Pos [11/13]

#define DCB_DCRSR_REGSEL_Pos   0U

DCB DCRSR: Register selector Position

Definition at line 1152 of file core_armv8mbl.h.

◆ DCB_DCRSR_REGSEL_Pos [12/13]

#define DCB_DCRSR_REGSEL_Pos   0U

DCB DCRSR: Register selector Position

Definition at line 1951 of file core_armv8mml.h.

◆ DCB_DCRSR_REGSEL_Pos [13/13]

#define DCB_DCRSR_REGSEL_Pos   0U

DCB DCRSR: Register selector Position

Definition at line 2026 of file core_cm33.h.

◆ DCB_DCRSR_REGWnR_Msk [1/13]

#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)

DCB DCRSR: Register write/not-read Mask

Definition at line 2885 of file core_armv81mml.h.

◆ DCB_DCRSR_REGWnR_Msk [2/13]

#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)

DCB DCRSR: Register write/not-read Mask

Definition at line 1150 of file core_armv8mbl.h.

◆ DCB_DCRSR_REGWnR_Msk [3/13]

#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)

DCB DCRSR: Register write/not-read Mask

Definition at line 1949 of file core_armv8mml.h.

◆ DCB_DCRSR_REGWnR_Msk [4/13]

#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)

DCB DCRSR: Register write/not-read Mask

Definition at line 1225 of file core_cm23.h.

◆ DCB_DCRSR_REGWnR_Msk [5/13]

#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)

DCB DCRSR: Register write/not-read Mask

Definition at line 2024 of file core_cm33.h.

◆ DCB_DCRSR_REGWnR_Msk [6/13]

#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)

DCB DCRSR: Register write/not-read Mask

Definition at line 2024 of file core_cm35p.h.

◆ DCB_DCRSR_REGWnR_Msk [7/13]

#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)

DCB DCRSR: Register write/not-read Mask

Definition at line 3439 of file core_cm55.h.

◆ DCB_DCRSR_REGWnR_Msk [8/13]

#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)

DCB DCRSR: Register write/not-read Mask

Definition at line 3344 of file core_cm85.h.

◆ DCB_DCRSR_REGWnR_Msk [9/13]

#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)

DCB DCRSR: Register write/not-read Mask

Definition at line 1951 of file core_starmc1.h.

◆ DCB_DCRSR_REGWnR_Msk [10/13]

#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)

DCB DCRSR: Register write/not-read Mask

Definition at line 2885 of file core_armv81mml.h.

◆ DCB_DCRSR_REGWnR_Msk [11/13]

#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)

DCB DCRSR: Register write/not-read Mask

Definition at line 1150 of file core_armv8mbl.h.

◆ DCB_DCRSR_REGWnR_Msk [12/13]

#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)

DCB DCRSR: Register write/not-read Mask

Definition at line 1949 of file core_armv8mml.h.

◆ DCB_DCRSR_REGWnR_Msk [13/13]

#define DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)

DCB DCRSR: Register write/not-read Mask

Definition at line 2024 of file core_cm33.h.

◆ DCB_DCRSR_REGWnR_Pos [1/13]

#define DCB_DCRSR_REGWnR_Pos   16U

DCB DCRSR: Register write/not-read Position

Definition at line 2884 of file core_armv81mml.h.

◆ DCB_DCRSR_REGWnR_Pos [2/13]

#define DCB_DCRSR_REGWnR_Pos   16U

DCB DCRSR: Register write/not-read Position

Definition at line 1149 of file core_armv8mbl.h.

◆ DCB_DCRSR_REGWnR_Pos [3/13]

#define DCB_DCRSR_REGWnR_Pos   16U

DCB DCRSR: Register write/not-read Position

Definition at line 1948 of file core_armv8mml.h.

◆ DCB_DCRSR_REGWnR_Pos [4/13]

#define DCB_DCRSR_REGWnR_Pos   16U

DCB DCRSR: Register write/not-read Position

Definition at line 1224 of file core_cm23.h.

◆ DCB_DCRSR_REGWnR_Pos [5/13]

#define DCB_DCRSR_REGWnR_Pos   16U

DCB DCRSR: Register write/not-read Position

Definition at line 2023 of file core_cm33.h.

◆ DCB_DCRSR_REGWnR_Pos [6/13]

#define DCB_DCRSR_REGWnR_Pos   16U

DCB DCRSR: Register write/not-read Position

Definition at line 2023 of file core_cm35p.h.

◆ DCB_DCRSR_REGWnR_Pos [7/13]

#define DCB_DCRSR_REGWnR_Pos   16U

DCB DCRSR: Register write/not-read Position

Definition at line 3438 of file core_cm55.h.

◆ DCB_DCRSR_REGWnR_Pos [8/13]

#define DCB_DCRSR_REGWnR_Pos   16U

DCB DCRSR: Register write/not-read Position

Definition at line 3343 of file core_cm85.h.

◆ DCB_DCRSR_REGWnR_Pos [9/13]

#define DCB_DCRSR_REGWnR_Pos   16U

DCB DCRSR: Register write/not-read Position

Definition at line 1950 of file core_starmc1.h.

◆ DCB_DCRSR_REGWnR_Pos [10/13]

#define DCB_DCRSR_REGWnR_Pos   16U

DCB DCRSR: Register write/not-read Position

Definition at line 2884 of file core_armv81mml.h.

◆ DCB_DCRSR_REGWnR_Pos [11/13]

#define DCB_DCRSR_REGWnR_Pos   16U

DCB DCRSR: Register write/not-read Position

Definition at line 1149 of file core_armv8mbl.h.

◆ DCB_DCRSR_REGWnR_Pos [12/13]

#define DCB_DCRSR_REGWnR_Pos   16U

DCB DCRSR: Register write/not-read Position

Definition at line 1948 of file core_armv8mml.h.

◆ DCB_DCRSR_REGWnR_Pos [13/13]

#define DCB_DCRSR_REGWnR_Pos   16U

DCB DCRSR: Register write/not-read Position

Definition at line 2023 of file core_cm33.h.

◆ DCB_DEMCR_MON_EN_Msk [1/10]

#define DCB_DEMCR_MON_EN_Msk   (0x1UL << DCB_DEMCR_MON_EN_Pos)

DCB DEMCR: Monitor enable Mask

Definition at line 2917 of file core_armv81mml.h.

◆ DCB_DEMCR_MON_EN_Msk [2/10]

#define DCB_DEMCR_MON_EN_Msk   (0x1UL << DCB_DEMCR_MON_EN_Pos)

DCB DEMCR: Monitor enable Mask

Definition at line 1981 of file core_armv8mml.h.

◆ DCB_DEMCR_MON_EN_Msk [3/10]

#define DCB_DEMCR_MON_EN_Msk   (0x1UL << DCB_DEMCR_MON_EN_Pos)

DCB DEMCR: Monitor enable Mask

Definition at line 2056 of file core_cm33.h.

◆ DCB_DEMCR_MON_EN_Msk [4/10]

#define DCB_DEMCR_MON_EN_Msk   (0x1UL << DCB_DEMCR_MON_EN_Pos)

DCB DEMCR: Monitor enable Mask

Definition at line 2056 of file core_cm35p.h.

◆ DCB_DEMCR_MON_EN_Msk [5/10]

#define DCB_DEMCR_MON_EN_Msk   (0x1UL << DCB_DEMCR_MON_EN_Pos)

DCB DEMCR: Monitor enable Mask

Definition at line 3471 of file core_cm55.h.

◆ DCB_DEMCR_MON_EN_Msk [6/10]

#define DCB_DEMCR_MON_EN_Msk   (0x1UL << DCB_DEMCR_MON_EN_Pos)

DCB DEMCR: Monitor enable Mask

Definition at line 3376 of file core_cm85.h.

◆ DCB_DEMCR_MON_EN_Msk [7/10]

#define DCB_DEMCR_MON_EN_Msk   (0x1UL << DCB_DEMCR_MON_EN_Pos)

DCB DEMCR: Monitor enable Mask

Definition at line 1983 of file core_starmc1.h.

◆ DCB_DEMCR_MON_EN_Msk [8/10]

#define DCB_DEMCR_MON_EN_Msk   (0x1UL << DCB_DEMCR_MON_EN_Pos)

DCB DEMCR: Monitor enable Mask

Definition at line 2917 of file core_armv81mml.h.

◆ DCB_DEMCR_MON_EN_Msk [9/10]

#define DCB_DEMCR_MON_EN_Msk   (0x1UL << DCB_DEMCR_MON_EN_Pos)

DCB DEMCR: Monitor enable Mask

Definition at line 1981 of file core_armv8mml.h.

◆ DCB_DEMCR_MON_EN_Msk [10/10]

#define DCB_DEMCR_MON_EN_Msk   (0x1UL << DCB_DEMCR_MON_EN_Pos)

DCB DEMCR: Monitor enable Mask

Definition at line 2056 of file core_cm33.h.

◆ DCB_DEMCR_MON_EN_Pos [1/10]

#define DCB_DEMCR_MON_EN_Pos   16U

DCB DEMCR: Monitor enable Position

Definition at line 2916 of file core_armv81mml.h.

◆ DCB_DEMCR_MON_EN_Pos [2/10]

#define DCB_DEMCR_MON_EN_Pos   16U

DCB DEMCR: Monitor enable Position

Definition at line 1980 of file core_armv8mml.h.

◆ DCB_DEMCR_MON_EN_Pos [3/10]

#define DCB_DEMCR_MON_EN_Pos   16U

DCB DEMCR: Monitor enable Position

Definition at line 2055 of file core_cm33.h.

◆ DCB_DEMCR_MON_EN_Pos [4/10]

#define DCB_DEMCR_MON_EN_Pos   16U

DCB DEMCR: Monitor enable Position

Definition at line 2055 of file core_cm35p.h.

◆ DCB_DEMCR_MON_EN_Pos [5/10]

#define DCB_DEMCR_MON_EN_Pos   16U

DCB DEMCR: Monitor enable Position

Definition at line 3470 of file core_cm55.h.

◆ DCB_DEMCR_MON_EN_Pos [6/10]

#define DCB_DEMCR_MON_EN_Pos   16U

DCB DEMCR: Monitor enable Position

Definition at line 3375 of file core_cm85.h.

◆ DCB_DEMCR_MON_EN_Pos [7/10]

#define DCB_DEMCR_MON_EN_Pos   16U

DCB DEMCR: Monitor enable Position

Definition at line 1982 of file core_starmc1.h.

◆ DCB_DEMCR_MON_EN_Pos [8/10]

#define DCB_DEMCR_MON_EN_Pos   16U

DCB DEMCR: Monitor enable Position

Definition at line 2916 of file core_armv81mml.h.

◆ DCB_DEMCR_MON_EN_Pos [9/10]

#define DCB_DEMCR_MON_EN_Pos   16U

DCB DEMCR: Monitor enable Position

Definition at line 1980 of file core_armv8mml.h.

◆ DCB_DEMCR_MON_EN_Pos [10/10]

#define DCB_DEMCR_MON_EN_Pos   16U

DCB DEMCR: Monitor enable Position

Definition at line 2055 of file core_cm33.h.

◆ DCB_DEMCR_MON_PEND_Msk [1/10]

#define DCB_DEMCR_MON_PEND_Msk   (0x1UL << DCB_DEMCR_MON_PEND_Pos)

DCB DEMCR: Monitor pend Mask

Definition at line 2914 of file core_armv81mml.h.

◆ DCB_DEMCR_MON_PEND_Msk [2/10]

#define DCB_DEMCR_MON_PEND_Msk   (0x1UL << DCB_DEMCR_MON_PEND_Pos)

DCB DEMCR: Monitor pend Mask

Definition at line 1978 of file core_armv8mml.h.

◆ DCB_DEMCR_MON_PEND_Msk [3/10]

#define DCB_DEMCR_MON_PEND_Msk   (0x1UL << DCB_DEMCR_MON_PEND_Pos)

DCB DEMCR: Monitor pend Mask

Definition at line 2053 of file core_cm33.h.

◆ DCB_DEMCR_MON_PEND_Msk [4/10]

#define DCB_DEMCR_MON_PEND_Msk   (0x1UL << DCB_DEMCR_MON_PEND_Pos)

DCB DEMCR: Monitor pend Mask

Definition at line 2053 of file core_cm35p.h.

◆ DCB_DEMCR_MON_PEND_Msk [5/10]

#define DCB_DEMCR_MON_PEND_Msk   (0x1UL << DCB_DEMCR_MON_PEND_Pos)

DCB DEMCR: Monitor pend Mask

Definition at line 3468 of file core_cm55.h.

◆ DCB_DEMCR_MON_PEND_Msk [6/10]

#define DCB_DEMCR_MON_PEND_Msk   (0x1UL << DCB_DEMCR_MON_PEND_Pos)

DCB DEMCR: Monitor pend Mask

Definition at line 3373 of file core_cm85.h.

◆ DCB_DEMCR_MON_PEND_Msk [7/10]

#define DCB_DEMCR_MON_PEND_Msk   (0x1UL << DCB_DEMCR_MON_PEND_Pos)

DCB DEMCR: Monitor pend Mask

Definition at line 1980 of file core_starmc1.h.

◆ DCB_DEMCR_MON_PEND_Msk [8/10]

#define DCB_DEMCR_MON_PEND_Msk   (0x1UL << DCB_DEMCR_MON_PEND_Pos)

DCB DEMCR: Monitor pend Mask

Definition at line 2914 of file core_armv81mml.h.

◆ DCB_DEMCR_MON_PEND_Msk [9/10]

#define DCB_DEMCR_MON_PEND_Msk   (0x1UL << DCB_DEMCR_MON_PEND_Pos)

DCB DEMCR: Monitor pend Mask

Definition at line 1978 of file core_armv8mml.h.

◆ DCB_DEMCR_MON_PEND_Msk [10/10]

#define DCB_DEMCR_MON_PEND_Msk   (0x1UL << DCB_DEMCR_MON_PEND_Pos)

DCB DEMCR: Monitor pend Mask

Definition at line 2053 of file core_cm33.h.

◆ DCB_DEMCR_MON_PEND_Pos [1/10]

#define DCB_DEMCR_MON_PEND_Pos   17U

DCB DEMCR: Monitor pend Position

Definition at line 2913 of file core_armv81mml.h.

◆ DCB_DEMCR_MON_PEND_Pos [2/10]

#define DCB_DEMCR_MON_PEND_Pos   17U

DCB DEMCR: Monitor pend Position

Definition at line 1977 of file core_armv8mml.h.

◆ DCB_DEMCR_MON_PEND_Pos [3/10]

#define DCB_DEMCR_MON_PEND_Pos   17U

DCB DEMCR: Monitor pend Position

Definition at line 2052 of file core_cm33.h.

◆ DCB_DEMCR_MON_PEND_Pos [4/10]

#define DCB_DEMCR_MON_PEND_Pos   17U

DCB DEMCR: Monitor pend Position

Definition at line 2052 of file core_cm35p.h.

◆ DCB_DEMCR_MON_PEND_Pos [5/10]

#define DCB_DEMCR_MON_PEND_Pos   17U

DCB DEMCR: Monitor pend Position

Definition at line 3467 of file core_cm55.h.

◆ DCB_DEMCR_MON_PEND_Pos [6/10]

#define DCB_DEMCR_MON_PEND_Pos   17U

DCB DEMCR: Monitor pend Position

Definition at line 3372 of file core_cm85.h.

◆ DCB_DEMCR_MON_PEND_Pos [7/10]

#define DCB_DEMCR_MON_PEND_Pos   17U

DCB DEMCR: Monitor pend Position

Definition at line 1979 of file core_starmc1.h.

◆ DCB_DEMCR_MON_PEND_Pos [8/10]

#define DCB_DEMCR_MON_PEND_Pos   17U

DCB DEMCR: Monitor pend Position

Definition at line 2913 of file core_armv81mml.h.

◆ DCB_DEMCR_MON_PEND_Pos [9/10]

#define DCB_DEMCR_MON_PEND_Pos   17U

DCB DEMCR: Monitor pend Position

Definition at line 1977 of file core_armv8mml.h.

◆ DCB_DEMCR_MON_PEND_Pos [10/10]

#define DCB_DEMCR_MON_PEND_Pos   17U

DCB DEMCR: Monitor pend Position

Definition at line 2052 of file core_cm33.h.

◆ DCB_DEMCR_MON_REQ_Msk [1/10]

#define DCB_DEMCR_MON_REQ_Msk   (0x1UL << DCB_DEMCR_MON_REQ_Pos)

DCB DEMCR: Monitor request Mask

Definition at line 2908 of file core_armv81mml.h.

◆ DCB_DEMCR_MON_REQ_Msk [2/10]

#define DCB_DEMCR_MON_REQ_Msk   (0x1UL << DCB_DEMCR_MON_REQ_Pos)

DCB DEMCR: Monitor request Mask

Definition at line 1972 of file core_armv8mml.h.

◆ DCB_DEMCR_MON_REQ_Msk [3/10]

#define DCB_DEMCR_MON_REQ_Msk   (0x1UL << DCB_DEMCR_MON_REQ_Pos)

DCB DEMCR: Monitor request Mask

Definition at line 2047 of file core_cm33.h.

◆ DCB_DEMCR_MON_REQ_Msk [4/10]

#define DCB_DEMCR_MON_REQ_Msk   (0x1UL << DCB_DEMCR_MON_REQ_Pos)

DCB DEMCR: Monitor request Mask

Definition at line 2047 of file core_cm35p.h.

◆ DCB_DEMCR_MON_REQ_Msk [5/10]

#define DCB_DEMCR_MON_REQ_Msk   (0x1UL << DCB_DEMCR_MON_REQ_Pos)

DCB DEMCR: Monitor request Mask

Definition at line 3462 of file core_cm55.h.

◆ DCB_DEMCR_MON_REQ_Msk [6/10]

#define DCB_DEMCR_MON_REQ_Msk   (0x1UL << DCB_DEMCR_MON_REQ_Pos)

DCB DEMCR: Monitor request Mask

Definition at line 3367 of file core_cm85.h.

◆ DCB_DEMCR_MON_REQ_Msk [7/10]

#define DCB_DEMCR_MON_REQ_Msk   (0x1UL << DCB_DEMCR_MON_REQ_Pos)

DCB DEMCR: Monitor request Mask

Definition at line 1974 of file core_starmc1.h.

◆ DCB_DEMCR_MON_REQ_Msk [8/10]

#define DCB_DEMCR_MON_REQ_Msk   (0x1UL << DCB_DEMCR_MON_REQ_Pos)

DCB DEMCR: Monitor request Mask

Definition at line 2908 of file core_armv81mml.h.

◆ DCB_DEMCR_MON_REQ_Msk [9/10]

#define DCB_DEMCR_MON_REQ_Msk   (0x1UL << DCB_DEMCR_MON_REQ_Pos)

DCB DEMCR: Monitor request Mask

Definition at line 1972 of file core_armv8mml.h.

◆ DCB_DEMCR_MON_REQ_Msk [10/10]

#define DCB_DEMCR_MON_REQ_Msk   (0x1UL << DCB_DEMCR_MON_REQ_Pos)

DCB DEMCR: Monitor request Mask

Definition at line 2047 of file core_cm33.h.

◆ DCB_DEMCR_MON_REQ_Pos [1/10]

#define DCB_DEMCR_MON_REQ_Pos   19U

DCB DEMCR: Monitor request Position

Definition at line 2907 of file core_armv81mml.h.

◆ DCB_DEMCR_MON_REQ_Pos [2/10]

#define DCB_DEMCR_MON_REQ_Pos   19U

DCB DEMCR: Monitor request Position

Definition at line 1971 of file core_armv8mml.h.

◆ DCB_DEMCR_MON_REQ_Pos [3/10]

#define DCB_DEMCR_MON_REQ_Pos   19U

DCB DEMCR: Monitor request Position

Definition at line 2046 of file core_cm33.h.

◆ DCB_DEMCR_MON_REQ_Pos [4/10]

#define DCB_DEMCR_MON_REQ_Pos   19U

DCB DEMCR: Monitor request Position

Definition at line 2046 of file core_cm35p.h.

◆ DCB_DEMCR_MON_REQ_Pos [5/10]

#define DCB_DEMCR_MON_REQ_Pos   19U

DCB DEMCR: Monitor request Position

Definition at line 3461 of file core_cm55.h.

◆ DCB_DEMCR_MON_REQ_Pos [6/10]

#define DCB_DEMCR_MON_REQ_Pos   19U

DCB DEMCR: Monitor request Position

Definition at line 3366 of file core_cm85.h.

◆ DCB_DEMCR_MON_REQ_Pos [7/10]

#define DCB_DEMCR_MON_REQ_Pos   19U

DCB DEMCR: Monitor request Position

Definition at line 1973 of file core_starmc1.h.

◆ DCB_DEMCR_MON_REQ_Pos [8/10]

#define DCB_DEMCR_MON_REQ_Pos   19U

DCB DEMCR: Monitor request Position

Definition at line 2907 of file core_armv81mml.h.

◆ DCB_DEMCR_MON_REQ_Pos [9/10]

#define DCB_DEMCR_MON_REQ_Pos   19U

DCB DEMCR: Monitor request Position

Definition at line 1971 of file core_armv8mml.h.

◆ DCB_DEMCR_MON_REQ_Pos [10/10]

#define DCB_DEMCR_MON_REQ_Pos   19U

DCB DEMCR: Monitor request Position

Definition at line 2046 of file core_cm33.h.

◆ DCB_DEMCR_MON_STEP_Msk [1/10]

#define DCB_DEMCR_MON_STEP_Msk   (0x1UL << DCB_DEMCR_MON_STEP_Pos)

DCB DEMCR: Monitor step Mask

Definition at line 2911 of file core_armv81mml.h.

◆ DCB_DEMCR_MON_STEP_Msk [2/10]

#define DCB_DEMCR_MON_STEP_Msk   (0x1UL << DCB_DEMCR_MON_STEP_Pos)

DCB DEMCR: Monitor step Mask

Definition at line 1975 of file core_armv8mml.h.

◆ DCB_DEMCR_MON_STEP_Msk [3/10]

#define DCB_DEMCR_MON_STEP_Msk   (0x1UL << DCB_DEMCR_MON_STEP_Pos)

DCB DEMCR: Monitor step Mask

Definition at line 2050 of file core_cm33.h.

◆ DCB_DEMCR_MON_STEP_Msk [4/10]

#define DCB_DEMCR_MON_STEP_Msk   (0x1UL << DCB_DEMCR_MON_STEP_Pos)

DCB DEMCR: Monitor step Mask

Definition at line 2050 of file core_cm35p.h.

◆ DCB_DEMCR_MON_STEP_Msk [5/10]

#define DCB_DEMCR_MON_STEP_Msk   (0x1UL << DCB_DEMCR_MON_STEP_Pos)

DCB DEMCR: Monitor step Mask

Definition at line 3465 of file core_cm55.h.

◆ DCB_DEMCR_MON_STEP_Msk [6/10]

#define DCB_DEMCR_MON_STEP_Msk   (0x1UL << DCB_DEMCR_MON_STEP_Pos)

DCB DEMCR: Monitor step Mask

Definition at line 3370 of file core_cm85.h.

◆ DCB_DEMCR_MON_STEP_Msk [7/10]

#define DCB_DEMCR_MON_STEP_Msk   (0x1UL << DCB_DEMCR_MON_STEP_Pos)

DCB DEMCR: Monitor step Mask

Definition at line 1977 of file core_starmc1.h.

◆ DCB_DEMCR_MON_STEP_Msk [8/10]

#define DCB_DEMCR_MON_STEP_Msk   (0x1UL << DCB_DEMCR_MON_STEP_Pos)

DCB DEMCR: Monitor step Mask

Definition at line 2911 of file core_armv81mml.h.

◆ DCB_DEMCR_MON_STEP_Msk [9/10]

#define DCB_DEMCR_MON_STEP_Msk   (0x1UL << DCB_DEMCR_MON_STEP_Pos)

DCB DEMCR: Monitor step Mask

Definition at line 1975 of file core_armv8mml.h.

◆ DCB_DEMCR_MON_STEP_Msk [10/10]

#define DCB_DEMCR_MON_STEP_Msk   (0x1UL << DCB_DEMCR_MON_STEP_Pos)

DCB DEMCR: Monitor step Mask

Definition at line 2050 of file core_cm33.h.

◆ DCB_DEMCR_MON_STEP_Pos [1/10]

#define DCB_DEMCR_MON_STEP_Pos   18U

DCB DEMCR: Monitor step Position

Definition at line 2910 of file core_armv81mml.h.

◆ DCB_DEMCR_MON_STEP_Pos [2/10]

#define DCB_DEMCR_MON_STEP_Pos   18U

DCB DEMCR: Monitor step Position

Definition at line 1974 of file core_armv8mml.h.

◆ DCB_DEMCR_MON_STEP_Pos [3/10]

#define DCB_DEMCR_MON_STEP_Pos   18U

DCB DEMCR: Monitor step Position

Definition at line 2049 of file core_cm33.h.

◆ DCB_DEMCR_MON_STEP_Pos [4/10]

#define DCB_DEMCR_MON_STEP_Pos   18U

DCB DEMCR: Monitor step Position

Definition at line 2049 of file core_cm35p.h.

◆ DCB_DEMCR_MON_STEP_Pos [5/10]

#define DCB_DEMCR_MON_STEP_Pos   18U

DCB DEMCR: Monitor step Position

Definition at line 3464 of file core_cm55.h.

◆ DCB_DEMCR_MON_STEP_Pos [6/10]

#define DCB_DEMCR_MON_STEP_Pos   18U

DCB DEMCR: Monitor step Position

Definition at line 3369 of file core_cm85.h.

◆ DCB_DEMCR_MON_STEP_Pos [7/10]

#define DCB_DEMCR_MON_STEP_Pos   18U

DCB DEMCR: Monitor step Position

Definition at line 1976 of file core_starmc1.h.

◆ DCB_DEMCR_MON_STEP_Pos [8/10]

#define DCB_DEMCR_MON_STEP_Pos   18U

DCB DEMCR: Monitor step Position

Definition at line 2910 of file core_armv81mml.h.

◆ DCB_DEMCR_MON_STEP_Pos [9/10]

#define DCB_DEMCR_MON_STEP_Pos   18U

DCB DEMCR: Monitor step Position

Definition at line 1974 of file core_armv8mml.h.

◆ DCB_DEMCR_MON_STEP_Pos [10/10]

#define DCB_DEMCR_MON_STEP_Pos   18U

DCB DEMCR: Monitor step Position

Definition at line 2049 of file core_cm33.h.

◆ DCB_DEMCR_MONPRKEY_Msk [1/10]

#define DCB_DEMCR_MONPRKEY_Msk   (0x1UL << DCB_DEMCR_MONPRKEY_Pos)

DCB DEMCR: Monitor pend req key Mask

Definition at line 2899 of file core_armv81mml.h.

◆ DCB_DEMCR_MONPRKEY_Msk [2/10]

#define DCB_DEMCR_MONPRKEY_Msk   (0x1UL << DCB_DEMCR_MONPRKEY_Pos)

DCB DEMCR: Monitor pend req key Mask

Definition at line 1963 of file core_armv8mml.h.

◆ DCB_DEMCR_MONPRKEY_Msk [3/10]

#define DCB_DEMCR_MONPRKEY_Msk   (0x1UL << DCB_DEMCR_MONPRKEY_Pos)

DCB DEMCR: Monitor pend req key Mask

Definition at line 2038 of file core_cm33.h.

◆ DCB_DEMCR_MONPRKEY_Msk [4/10]

#define DCB_DEMCR_MONPRKEY_Msk   (0x1UL << DCB_DEMCR_MONPRKEY_Pos)

DCB DEMCR: Monitor pend req key Mask

Definition at line 2038 of file core_cm35p.h.

◆ DCB_DEMCR_MONPRKEY_Msk [5/10]

#define DCB_DEMCR_MONPRKEY_Msk   (0x1UL << DCB_DEMCR_MONPRKEY_Pos)

DCB DEMCR: Monitor pend req key Mask

Definition at line 3453 of file core_cm55.h.

◆ DCB_DEMCR_MONPRKEY_Msk [6/10]

#define DCB_DEMCR_MONPRKEY_Msk   (0x1UL << DCB_DEMCR_MONPRKEY_Pos)

DCB DEMCR: Monitor pend req key Mask

Definition at line 3358 of file core_cm85.h.

◆ DCB_DEMCR_MONPRKEY_Msk [7/10]

#define DCB_DEMCR_MONPRKEY_Msk   (0x1UL << DCB_DEMCR_MONPRKEY_Pos)

DCB DEMCR: Monitor pend req key Mask

Definition at line 1965 of file core_starmc1.h.

◆ DCB_DEMCR_MONPRKEY_Msk [8/10]

#define DCB_DEMCR_MONPRKEY_Msk   (0x1UL << DCB_DEMCR_MONPRKEY_Pos)

DCB DEMCR: Monitor pend req key Mask

Definition at line 2899 of file core_armv81mml.h.

◆ DCB_DEMCR_MONPRKEY_Msk [9/10]

#define DCB_DEMCR_MONPRKEY_Msk   (0x1UL << DCB_DEMCR_MONPRKEY_Pos)

DCB DEMCR: Monitor pend req key Mask

Definition at line 1963 of file core_armv8mml.h.

◆ DCB_DEMCR_MONPRKEY_Msk [10/10]

#define DCB_DEMCR_MONPRKEY_Msk   (0x1UL << DCB_DEMCR_MONPRKEY_Pos)

DCB DEMCR: Monitor pend req key Mask

Definition at line 2038 of file core_cm33.h.

◆ DCB_DEMCR_MONPRKEY_Pos [1/10]

#define DCB_DEMCR_MONPRKEY_Pos   23U

DCB DEMCR: Monitor pend req key Position

Definition at line 2898 of file core_armv81mml.h.

◆ DCB_DEMCR_MONPRKEY_Pos [2/10]

#define DCB_DEMCR_MONPRKEY_Pos   23U

DCB DEMCR: Monitor pend req key Position

Definition at line 1962 of file core_armv8mml.h.

◆ DCB_DEMCR_MONPRKEY_Pos [3/10]

#define DCB_DEMCR_MONPRKEY_Pos   23U

DCB DEMCR: Monitor pend req key Position

Definition at line 2037 of file core_cm33.h.

◆ DCB_DEMCR_MONPRKEY_Pos [4/10]

#define DCB_DEMCR_MONPRKEY_Pos   23U

DCB DEMCR: Monitor pend req key Position

Definition at line 2037 of file core_cm35p.h.

◆ DCB_DEMCR_MONPRKEY_Pos [5/10]

#define DCB_DEMCR_MONPRKEY_Pos   23U

DCB DEMCR: Monitor pend req key Position

Definition at line 3452 of file core_cm55.h.

◆ DCB_DEMCR_MONPRKEY_Pos [6/10]

#define DCB_DEMCR_MONPRKEY_Pos   23U

DCB DEMCR: Monitor pend req key Position

Definition at line 3357 of file core_cm85.h.

◆ DCB_DEMCR_MONPRKEY_Pos [7/10]

#define DCB_DEMCR_MONPRKEY_Pos   23U

DCB DEMCR: Monitor pend req key Position

Definition at line 1964 of file core_starmc1.h.

◆ DCB_DEMCR_MONPRKEY_Pos [8/10]

#define DCB_DEMCR_MONPRKEY_Pos   23U

DCB DEMCR: Monitor pend req key Position

Definition at line 2898 of file core_armv81mml.h.

◆ DCB_DEMCR_MONPRKEY_Pos [9/10]

#define DCB_DEMCR_MONPRKEY_Pos   23U

DCB DEMCR: Monitor pend req key Position

Definition at line 1962 of file core_armv8mml.h.

◆ DCB_DEMCR_MONPRKEY_Pos [10/10]

#define DCB_DEMCR_MONPRKEY_Pos   23U

DCB DEMCR: Monitor pend req key Position

Definition at line 2037 of file core_cm33.h.

◆ DCB_DEMCR_SDME_Msk [1/10]

#define DCB_DEMCR_SDME_Msk   (0x1UL << DCB_DEMCR_SDME_Pos)

DCB DEMCR: Secure DebugMonitor enable Mask

Definition at line 2905 of file core_armv81mml.h.

◆ DCB_DEMCR_SDME_Msk [2/10]

#define DCB_DEMCR_SDME_Msk   (0x1UL << DCB_DEMCR_SDME_Pos)

DCB DEMCR: Secure DebugMonitor enable Mask

Definition at line 1969 of file core_armv8mml.h.

◆ DCB_DEMCR_SDME_Msk [3/10]

#define DCB_DEMCR_SDME_Msk   (0x1UL << DCB_DEMCR_SDME_Pos)

DCB DEMCR: Secure DebugMonitor enable Mask

Definition at line 2044 of file core_cm33.h.

◆ DCB_DEMCR_SDME_Msk [4/10]

#define DCB_DEMCR_SDME_Msk   (0x1UL << DCB_DEMCR_SDME_Pos)

DCB DEMCR: Secure DebugMonitor enable Mask

Definition at line 2044 of file core_cm35p.h.

◆ DCB_DEMCR_SDME_Msk [5/10]

#define DCB_DEMCR_SDME_Msk   (0x1UL << DCB_DEMCR_SDME_Pos)

DCB DEMCR: Secure DebugMonitor enable Mask

Definition at line 3459 of file core_cm55.h.

◆ DCB_DEMCR_SDME_Msk [6/10]

#define DCB_DEMCR_SDME_Msk   (0x1UL << DCB_DEMCR_SDME_Pos)

DCB DEMCR: Secure DebugMonitor enable Mask

Definition at line 3364 of file core_cm85.h.

◆ DCB_DEMCR_SDME_Msk [7/10]

#define DCB_DEMCR_SDME_Msk   (0x1UL << DCB_DEMCR_SDME_Pos)

DCB DEMCR: Secure DebugMonitor enable Mask

Definition at line 1971 of file core_starmc1.h.

◆ DCB_DEMCR_SDME_Msk [8/10]

#define DCB_DEMCR_SDME_Msk   (0x1UL << DCB_DEMCR_SDME_Pos)

DCB DEMCR: Secure DebugMonitor enable Mask

Definition at line 2905 of file core_armv81mml.h.

◆ DCB_DEMCR_SDME_Msk [9/10]

#define DCB_DEMCR_SDME_Msk   (0x1UL << DCB_DEMCR_SDME_Pos)

DCB DEMCR: Secure DebugMonitor enable Mask

Definition at line 1969 of file core_armv8mml.h.

◆ DCB_DEMCR_SDME_Msk [10/10]

#define DCB_DEMCR_SDME_Msk   (0x1UL << DCB_DEMCR_SDME_Pos)

DCB DEMCR: Secure DebugMonitor enable Mask

Definition at line 2044 of file core_cm33.h.

◆ DCB_DEMCR_SDME_Pos [1/10]

#define DCB_DEMCR_SDME_Pos   20U

DCB DEMCR: Secure DebugMonitor enable Position

Definition at line 2904 of file core_armv81mml.h.

◆ DCB_DEMCR_SDME_Pos [2/10]

#define DCB_DEMCR_SDME_Pos   20U

DCB DEMCR: Secure DebugMonitor enable Position

Definition at line 1968 of file core_armv8mml.h.

◆ DCB_DEMCR_SDME_Pos [3/10]

#define DCB_DEMCR_SDME_Pos   20U

DCB DEMCR: Secure DebugMonitor enable Position

Definition at line 2043 of file core_cm33.h.

◆ DCB_DEMCR_SDME_Pos [4/10]

#define DCB_DEMCR_SDME_Pos   20U

DCB DEMCR: Secure DebugMonitor enable Position

Definition at line 2043 of file core_cm35p.h.

◆ DCB_DEMCR_SDME_Pos [5/10]

#define DCB_DEMCR_SDME_Pos   20U

DCB DEMCR: Secure DebugMonitor enable Position

Definition at line 3458 of file core_cm55.h.

◆ DCB_DEMCR_SDME_Pos [6/10]

#define DCB_DEMCR_SDME_Pos   20U

DCB DEMCR: Secure DebugMonitor enable Position

Definition at line 3363 of file core_cm85.h.

◆ DCB_DEMCR_SDME_Pos [7/10]

#define DCB_DEMCR_SDME_Pos   20U

DCB DEMCR: Secure DebugMonitor enable Position

Definition at line 1970 of file core_starmc1.h.

◆ DCB_DEMCR_SDME_Pos [8/10]

#define DCB_DEMCR_SDME_Pos   20U

DCB DEMCR: Secure DebugMonitor enable Position

Definition at line 2904 of file core_armv81mml.h.

◆ DCB_DEMCR_SDME_Pos [9/10]

#define DCB_DEMCR_SDME_Pos   20U

DCB DEMCR: Secure DebugMonitor enable Position

Definition at line 1968 of file core_armv8mml.h.

◆ DCB_DEMCR_SDME_Pos [10/10]

#define DCB_DEMCR_SDME_Pos   20U

DCB DEMCR: Secure DebugMonitor enable Position

Definition at line 2043 of file core_cm33.h.

◆ DCB_DEMCR_TRCENA_Msk [1/13]

#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)

DCB DEMCR: Trace enable Mask

Definition at line 2896 of file core_armv81mml.h.

◆ DCB_DEMCR_TRCENA_Msk [2/13]

#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)

DCB DEMCR: Trace enable Mask

Definition at line 1161 of file core_armv8mbl.h.

◆ DCB_DEMCR_TRCENA_Msk [3/13]

#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)

DCB DEMCR: Trace enable Mask

Definition at line 1960 of file core_armv8mml.h.

◆ DCB_DEMCR_TRCENA_Msk [4/13]

#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)

DCB DEMCR: Trace enable Mask

Definition at line 1236 of file core_cm23.h.

◆ DCB_DEMCR_TRCENA_Msk [5/13]

#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)

DCB DEMCR: Trace enable Mask

Definition at line 2035 of file core_cm33.h.

◆ DCB_DEMCR_TRCENA_Msk [6/13]

#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)

DCB DEMCR: Trace enable Mask

Definition at line 2035 of file core_cm35p.h.

◆ DCB_DEMCR_TRCENA_Msk [7/13]

#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)

DCB DEMCR: Trace enable Mask

Definition at line 3450 of file core_cm55.h.

◆ DCB_DEMCR_TRCENA_Msk [8/13]

#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)

DCB DEMCR: Trace enable Mask

Definition at line 3355 of file core_cm85.h.

◆ DCB_DEMCR_TRCENA_Msk [9/13]

#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)

DCB DEMCR: Trace enable Mask

Definition at line 1962 of file core_starmc1.h.

◆ DCB_DEMCR_TRCENA_Msk [10/13]

#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)

DCB DEMCR: Trace enable Mask

Definition at line 2896 of file core_armv81mml.h.

◆ DCB_DEMCR_TRCENA_Msk [11/13]

#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)

DCB DEMCR: Trace enable Mask

Definition at line 1161 of file core_armv8mbl.h.

◆ DCB_DEMCR_TRCENA_Msk [12/13]

#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)

DCB DEMCR: Trace enable Mask

Definition at line 1960 of file core_armv8mml.h.

◆ DCB_DEMCR_TRCENA_Msk [13/13]

#define DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)

DCB DEMCR: Trace enable Mask

Definition at line 2035 of file core_cm33.h.

◆ DCB_DEMCR_TRCENA_Pos [1/13]

#define DCB_DEMCR_TRCENA_Pos   24U

DCB DEMCR: Trace enable Position

Definition at line 2895 of file core_armv81mml.h.

◆ DCB_DEMCR_TRCENA_Pos [2/13]

#define DCB_DEMCR_TRCENA_Pos   24U

DCB DEMCR: Trace enable Position

Definition at line 1160 of file core_armv8mbl.h.

◆ DCB_DEMCR_TRCENA_Pos [3/13]

#define DCB_DEMCR_TRCENA_Pos   24U

DCB DEMCR: Trace enable Position

Definition at line 1959 of file core_armv8mml.h.

◆ DCB_DEMCR_TRCENA_Pos [4/13]

#define DCB_DEMCR_TRCENA_Pos   24U

DCB DEMCR: Trace enable Position

Definition at line 1235 of file core_cm23.h.

◆ DCB_DEMCR_TRCENA_Pos [5/13]

#define DCB_DEMCR_TRCENA_Pos   24U

DCB DEMCR: Trace enable Position

Definition at line 2034 of file core_cm33.h.

◆ DCB_DEMCR_TRCENA_Pos [6/13]

#define DCB_DEMCR_TRCENA_Pos   24U

DCB DEMCR: Trace enable Position

Definition at line 2034 of file core_cm35p.h.

◆ DCB_DEMCR_TRCENA_Pos [7/13]

#define DCB_DEMCR_TRCENA_Pos   24U

DCB DEMCR: Trace enable Position

Definition at line 3449 of file core_cm55.h.

◆ DCB_DEMCR_TRCENA_Pos [8/13]

#define DCB_DEMCR_TRCENA_Pos   24U

DCB DEMCR: Trace enable Position

Definition at line 3354 of file core_cm85.h.

◆ DCB_DEMCR_TRCENA_Pos [9/13]

#define DCB_DEMCR_TRCENA_Pos   24U

DCB DEMCR: Trace enable Position

Definition at line 1961 of file core_starmc1.h.

◆ DCB_DEMCR_TRCENA_Pos [10/13]

#define DCB_DEMCR_TRCENA_Pos   24U

DCB DEMCR: Trace enable Position

Definition at line 2895 of file core_armv81mml.h.

◆ DCB_DEMCR_TRCENA_Pos [11/13]

#define DCB_DEMCR_TRCENA_Pos   24U

DCB DEMCR: Trace enable Position

Definition at line 1160 of file core_armv8mbl.h.

◆ DCB_DEMCR_TRCENA_Pos [12/13]

#define DCB_DEMCR_TRCENA_Pos   24U

DCB DEMCR: Trace enable Position

Definition at line 1959 of file core_armv8mml.h.

◆ DCB_DEMCR_TRCENA_Pos [13/13]

#define DCB_DEMCR_TRCENA_Pos   24U

DCB DEMCR: Trace enable Position

Definition at line 2034 of file core_cm33.h.

◆ DCB_DEMCR_UMON_EN_Msk [1/10]

#define DCB_DEMCR_UMON_EN_Msk   (0x1UL << DCB_DEMCR_UMON_EN_Pos)

DCB DEMCR: Unprivileged monitor enable Mask

Definition at line 2902 of file core_armv81mml.h.

◆ DCB_DEMCR_UMON_EN_Msk [2/10]

#define DCB_DEMCR_UMON_EN_Msk   (0x1UL << DCB_DEMCR_UMON_EN_Pos)

DCB DEMCR: Unprivileged monitor enable Mask

Definition at line 1966 of file core_armv8mml.h.

◆ DCB_DEMCR_UMON_EN_Msk [3/10]

#define DCB_DEMCR_UMON_EN_Msk   (0x1UL << DCB_DEMCR_UMON_EN_Pos)

DCB DEMCR: Unprivileged monitor enable Mask

Definition at line 2041 of file core_cm33.h.

◆ DCB_DEMCR_UMON_EN_Msk [4/10]

#define DCB_DEMCR_UMON_EN_Msk   (0x1UL << DCB_DEMCR_UMON_EN_Pos)

DCB DEMCR: Unprivileged monitor enable Mask

Definition at line 2041 of file core_cm35p.h.

◆ DCB_DEMCR_UMON_EN_Msk [5/10]

#define DCB_DEMCR_UMON_EN_Msk   (0x1UL << DCB_DEMCR_UMON_EN_Pos)

DCB DEMCR: Unprivileged monitor enable Mask

Definition at line 3456 of file core_cm55.h.

◆ DCB_DEMCR_UMON_EN_Msk [6/10]

#define DCB_DEMCR_UMON_EN_Msk   (0x1UL << DCB_DEMCR_UMON_EN_Pos)

DCB DEMCR: Unprivileged monitor enable Mask

Definition at line 3361 of file core_cm85.h.

◆ DCB_DEMCR_UMON_EN_Msk [7/10]

#define DCB_DEMCR_UMON_EN_Msk   (0x1UL << DCB_DEMCR_UMON_EN_Pos)

DCB DEMCR: Unprivileged monitor enable Mask

Definition at line 1968 of file core_starmc1.h.

◆ DCB_DEMCR_UMON_EN_Msk [8/10]

#define DCB_DEMCR_UMON_EN_Msk   (0x1UL << DCB_DEMCR_UMON_EN_Pos)

DCB DEMCR: Unprivileged monitor enable Mask

Definition at line 2902 of file core_armv81mml.h.

◆ DCB_DEMCR_UMON_EN_Msk [9/10]

#define DCB_DEMCR_UMON_EN_Msk   (0x1UL << DCB_DEMCR_UMON_EN_Pos)

DCB DEMCR: Unprivileged monitor enable Mask

Definition at line 1966 of file core_armv8mml.h.

◆ DCB_DEMCR_UMON_EN_Msk [10/10]

#define DCB_DEMCR_UMON_EN_Msk   (0x1UL << DCB_DEMCR_UMON_EN_Pos)

DCB DEMCR: Unprivileged monitor enable Mask

Definition at line 2041 of file core_cm33.h.

◆ DCB_DEMCR_UMON_EN_Pos [1/10]

#define DCB_DEMCR_UMON_EN_Pos   21U

DCB DEMCR: Unprivileged monitor enable Position

Definition at line 2901 of file core_armv81mml.h.

◆ DCB_DEMCR_UMON_EN_Pos [2/10]

#define DCB_DEMCR_UMON_EN_Pos   21U

DCB DEMCR: Unprivileged monitor enable Position

Definition at line 1965 of file core_armv8mml.h.

◆ DCB_DEMCR_UMON_EN_Pos [3/10]

#define DCB_DEMCR_UMON_EN_Pos   21U

DCB DEMCR: Unprivileged monitor enable Position

Definition at line 2040 of file core_cm33.h.

◆ DCB_DEMCR_UMON_EN_Pos [4/10]

#define DCB_DEMCR_UMON_EN_Pos   21U

DCB DEMCR: Unprivileged monitor enable Position

Definition at line 2040 of file core_cm35p.h.

◆ DCB_DEMCR_UMON_EN_Pos [5/10]

#define DCB_DEMCR_UMON_EN_Pos   21U

DCB DEMCR: Unprivileged monitor enable Position

Definition at line 3455 of file core_cm55.h.

◆ DCB_DEMCR_UMON_EN_Pos [6/10]

#define DCB_DEMCR_UMON_EN_Pos   21U

DCB DEMCR: Unprivileged monitor enable Position

Definition at line 3360 of file core_cm85.h.

◆ DCB_DEMCR_UMON_EN_Pos [7/10]

#define DCB_DEMCR_UMON_EN_Pos   21U

DCB DEMCR: Unprivileged monitor enable Position

Definition at line 1967 of file core_starmc1.h.

◆ DCB_DEMCR_UMON_EN_Pos [8/10]

#define DCB_DEMCR_UMON_EN_Pos   21U

DCB DEMCR: Unprivileged monitor enable Position

Definition at line 2901 of file core_armv81mml.h.

◆ DCB_DEMCR_UMON_EN_Pos [9/10]

#define DCB_DEMCR_UMON_EN_Pos   21U

DCB DEMCR: Unprivileged monitor enable Position

Definition at line 1965 of file core_armv8mml.h.

◆ DCB_DEMCR_UMON_EN_Pos [10/10]

#define DCB_DEMCR_UMON_EN_Pos   21U

DCB DEMCR: Unprivileged monitor enable Position

Definition at line 2040 of file core_cm33.h.

◆ DCB_DEMCR_VC_BUSERR_Msk [1/10]

#define DCB_DEMCR_VC_BUSERR_Msk   (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)

DCB DEMCR: Vector Catch BusFault errors Mask

Definition at line 2929 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_BUSERR_Msk [2/10]

#define DCB_DEMCR_VC_BUSERR_Msk   (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)

DCB DEMCR: Vector Catch BusFault errors Mask

Definition at line 1993 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_BUSERR_Msk [3/10]

#define DCB_DEMCR_VC_BUSERR_Msk   (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)

DCB DEMCR: Vector Catch BusFault errors Mask

Definition at line 2068 of file core_cm33.h.

◆ DCB_DEMCR_VC_BUSERR_Msk [4/10]

#define DCB_DEMCR_VC_BUSERR_Msk   (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)

DCB DEMCR: Vector Catch BusFault errors Mask

Definition at line 2068 of file core_cm35p.h.

◆ DCB_DEMCR_VC_BUSERR_Msk [5/10]

#define DCB_DEMCR_VC_BUSERR_Msk   (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)

DCB DEMCR: Vector Catch BusFault errors Mask

Definition at line 3483 of file core_cm55.h.

◆ DCB_DEMCR_VC_BUSERR_Msk [6/10]

#define DCB_DEMCR_VC_BUSERR_Msk   (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)

DCB DEMCR: Vector Catch BusFault errors Mask

Definition at line 3388 of file core_cm85.h.

◆ DCB_DEMCR_VC_BUSERR_Msk [7/10]

#define DCB_DEMCR_VC_BUSERR_Msk   (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)

DCB DEMCR: Vector Catch BusFault errors Mask

Definition at line 1995 of file core_starmc1.h.

◆ DCB_DEMCR_VC_BUSERR_Msk [8/10]

#define DCB_DEMCR_VC_BUSERR_Msk   (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)

DCB DEMCR: Vector Catch BusFault errors Mask

Definition at line 2929 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_BUSERR_Msk [9/10]

#define DCB_DEMCR_VC_BUSERR_Msk   (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)

DCB DEMCR: Vector Catch BusFault errors Mask

Definition at line 1993 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_BUSERR_Msk [10/10]

#define DCB_DEMCR_VC_BUSERR_Msk   (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)

DCB DEMCR: Vector Catch BusFault errors Mask

Definition at line 2068 of file core_cm33.h.

◆ DCB_DEMCR_VC_BUSERR_Pos [1/10]

#define DCB_DEMCR_VC_BUSERR_Pos   8U

DCB DEMCR: Vector Catch BusFault errors Position

Definition at line 2928 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_BUSERR_Pos [2/10]

#define DCB_DEMCR_VC_BUSERR_Pos   8U

DCB DEMCR: Vector Catch BusFault errors Position

Definition at line 1992 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_BUSERR_Pos [3/10]

#define DCB_DEMCR_VC_BUSERR_Pos   8U

DCB DEMCR: Vector Catch BusFault errors Position

Definition at line 2067 of file core_cm33.h.

◆ DCB_DEMCR_VC_BUSERR_Pos [4/10]

#define DCB_DEMCR_VC_BUSERR_Pos   8U

DCB DEMCR: Vector Catch BusFault errors Position

Definition at line 2067 of file core_cm35p.h.

◆ DCB_DEMCR_VC_BUSERR_Pos [5/10]

#define DCB_DEMCR_VC_BUSERR_Pos   8U

DCB DEMCR: Vector Catch BusFault errors Position

Definition at line 3482 of file core_cm55.h.

◆ DCB_DEMCR_VC_BUSERR_Pos [6/10]

#define DCB_DEMCR_VC_BUSERR_Pos   8U

DCB DEMCR: Vector Catch BusFault errors Position

Definition at line 3387 of file core_cm85.h.

◆ DCB_DEMCR_VC_BUSERR_Pos [7/10]

#define DCB_DEMCR_VC_BUSERR_Pos   8U

DCB DEMCR: Vector Catch BusFault errors Position

Definition at line 1994 of file core_starmc1.h.

◆ DCB_DEMCR_VC_BUSERR_Pos [8/10]

#define DCB_DEMCR_VC_BUSERR_Pos   8U

DCB DEMCR: Vector Catch BusFault errors Position

Definition at line 2928 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_BUSERR_Pos [9/10]

#define DCB_DEMCR_VC_BUSERR_Pos   8U

DCB DEMCR: Vector Catch BusFault errors Position

Definition at line 1992 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_BUSERR_Pos [10/10]

#define DCB_DEMCR_VC_BUSERR_Pos   8U

DCB DEMCR: Vector Catch BusFault errors Position

Definition at line 2067 of file core_cm33.h.

◆ DCB_DEMCR_VC_CHKERR_Msk [1/10]

#define DCB_DEMCR_VC_CHKERR_Msk   (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)

DCB DEMCR: Vector Catch check errors Mask

Definition at line 2935 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_CHKERR_Msk [2/10]

#define DCB_DEMCR_VC_CHKERR_Msk   (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)

DCB DEMCR: Vector Catch check errors Mask

Definition at line 1999 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_CHKERR_Msk [3/10]

#define DCB_DEMCR_VC_CHKERR_Msk   (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)

DCB DEMCR: Vector Catch check errors Mask

Definition at line 2074 of file core_cm33.h.

◆ DCB_DEMCR_VC_CHKERR_Msk [4/10]

#define DCB_DEMCR_VC_CHKERR_Msk   (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)

DCB DEMCR: Vector Catch check errors Mask

Definition at line 2074 of file core_cm35p.h.

◆ DCB_DEMCR_VC_CHKERR_Msk [5/10]

#define DCB_DEMCR_VC_CHKERR_Msk   (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)

DCB DEMCR: Vector Catch check errors Mask

Definition at line 3489 of file core_cm55.h.

◆ DCB_DEMCR_VC_CHKERR_Msk [6/10]

#define DCB_DEMCR_VC_CHKERR_Msk   (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)

DCB DEMCR: Vector Catch check errors Mask

Definition at line 3394 of file core_cm85.h.

◆ DCB_DEMCR_VC_CHKERR_Msk [7/10]

#define DCB_DEMCR_VC_CHKERR_Msk   (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)

DCB DEMCR: Vector Catch check errors Mask

Definition at line 2001 of file core_starmc1.h.

◆ DCB_DEMCR_VC_CHKERR_Msk [8/10]

#define DCB_DEMCR_VC_CHKERR_Msk   (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)

DCB DEMCR: Vector Catch check errors Mask

Definition at line 2935 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_CHKERR_Msk [9/10]

#define DCB_DEMCR_VC_CHKERR_Msk   (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)

DCB DEMCR: Vector Catch check errors Mask

Definition at line 1999 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_CHKERR_Msk [10/10]

#define DCB_DEMCR_VC_CHKERR_Msk   (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)

DCB DEMCR: Vector Catch check errors Mask

Definition at line 2074 of file core_cm33.h.

◆ DCB_DEMCR_VC_CHKERR_Pos [1/10]

#define DCB_DEMCR_VC_CHKERR_Pos   6U

DCB DEMCR: Vector Catch check errors Position

Definition at line 2934 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_CHKERR_Pos [2/10]

#define DCB_DEMCR_VC_CHKERR_Pos   6U

DCB DEMCR: Vector Catch check errors Position

Definition at line 1998 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_CHKERR_Pos [3/10]

#define DCB_DEMCR_VC_CHKERR_Pos   6U

DCB DEMCR: Vector Catch check errors Position

Definition at line 2073 of file core_cm33.h.

◆ DCB_DEMCR_VC_CHKERR_Pos [4/10]

#define DCB_DEMCR_VC_CHKERR_Pos   6U

DCB DEMCR: Vector Catch check errors Position

Definition at line 2073 of file core_cm35p.h.

◆ DCB_DEMCR_VC_CHKERR_Pos [5/10]

#define DCB_DEMCR_VC_CHKERR_Pos   6U

DCB DEMCR: Vector Catch check errors Position

Definition at line 3488 of file core_cm55.h.

◆ DCB_DEMCR_VC_CHKERR_Pos [6/10]

#define DCB_DEMCR_VC_CHKERR_Pos   6U

DCB DEMCR: Vector Catch check errors Position

Definition at line 3393 of file core_cm85.h.

◆ DCB_DEMCR_VC_CHKERR_Pos [7/10]

#define DCB_DEMCR_VC_CHKERR_Pos   6U

DCB DEMCR: Vector Catch check errors Position

Definition at line 2000 of file core_starmc1.h.

◆ DCB_DEMCR_VC_CHKERR_Pos [8/10]

#define DCB_DEMCR_VC_CHKERR_Pos   6U

DCB DEMCR: Vector Catch check errors Position

Definition at line 2934 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_CHKERR_Pos [9/10]

#define DCB_DEMCR_VC_CHKERR_Pos   6U

DCB DEMCR: Vector Catch check errors Position

Definition at line 1998 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_CHKERR_Pos [10/10]

#define DCB_DEMCR_VC_CHKERR_Pos   6U

DCB DEMCR: Vector Catch check errors Position

Definition at line 2073 of file core_cm33.h.

◆ DCB_DEMCR_VC_CORERESET_Msk [1/13]

#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)

DCB DEMCR: Vector Catch Core reset Mask

Definition at line 2944 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_CORERESET_Msk [2/13]

#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)

DCB DEMCR: Vector Catch Core reset Mask

Definition at line 1167 of file core_armv8mbl.h.

◆ DCB_DEMCR_VC_CORERESET_Msk [3/13]

#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)

DCB DEMCR: Vector Catch Core reset Mask

Definition at line 2008 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_CORERESET_Msk [4/13]

#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)

DCB DEMCR: Vector Catch Core reset Mask

Definition at line 1242 of file core_cm23.h.

◆ DCB_DEMCR_VC_CORERESET_Msk [5/13]

#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)

DCB DEMCR: Vector Catch Core reset Mask

Definition at line 2083 of file core_cm33.h.

◆ DCB_DEMCR_VC_CORERESET_Msk [6/13]

#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)

DCB DEMCR: Vector Catch Core reset Mask

Definition at line 2083 of file core_cm35p.h.

◆ DCB_DEMCR_VC_CORERESET_Msk [7/13]

#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)

DCB DEMCR: Vector Catch Core reset Mask

Definition at line 3498 of file core_cm55.h.

◆ DCB_DEMCR_VC_CORERESET_Msk [8/13]

#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)

DCB DEMCR: Vector Catch Core reset Mask

Definition at line 3403 of file core_cm85.h.

◆ DCB_DEMCR_VC_CORERESET_Msk [9/13]

#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)

DCB DEMCR: Vector Catch Core reset Mask

Definition at line 2010 of file core_starmc1.h.

◆ DCB_DEMCR_VC_CORERESET_Msk [10/13]

#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)

DCB DEMCR: Vector Catch Core reset Mask

Definition at line 2944 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_CORERESET_Msk [11/13]

#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)

DCB DEMCR: Vector Catch Core reset Mask

Definition at line 1167 of file core_armv8mbl.h.

◆ DCB_DEMCR_VC_CORERESET_Msk [12/13]

#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)

DCB DEMCR: Vector Catch Core reset Mask

Definition at line 2008 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_CORERESET_Msk [13/13]

#define DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)

DCB DEMCR: Vector Catch Core reset Mask

Definition at line 2083 of file core_cm33.h.

◆ DCB_DEMCR_VC_CORERESET_Pos [1/13]

#define DCB_DEMCR_VC_CORERESET_Pos   0U

DCB DEMCR: Vector Catch Core reset Position

Definition at line 2943 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_CORERESET_Pos [2/13]

#define DCB_DEMCR_VC_CORERESET_Pos   0U

DCB DEMCR: Vector Catch Core reset Position

Definition at line 1166 of file core_armv8mbl.h.

◆ DCB_DEMCR_VC_CORERESET_Pos [3/13]

#define DCB_DEMCR_VC_CORERESET_Pos   0U

DCB DEMCR: Vector Catch Core reset Position

Definition at line 2007 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_CORERESET_Pos [4/13]

#define DCB_DEMCR_VC_CORERESET_Pos   0U

DCB DEMCR: Vector Catch Core reset Position

Definition at line 1241 of file core_cm23.h.

◆ DCB_DEMCR_VC_CORERESET_Pos [5/13]

#define DCB_DEMCR_VC_CORERESET_Pos   0U

DCB DEMCR: Vector Catch Core reset Position

Definition at line 2082 of file core_cm33.h.

◆ DCB_DEMCR_VC_CORERESET_Pos [6/13]

#define DCB_DEMCR_VC_CORERESET_Pos   0U

DCB DEMCR: Vector Catch Core reset Position

Definition at line 2082 of file core_cm35p.h.

◆ DCB_DEMCR_VC_CORERESET_Pos [7/13]

#define DCB_DEMCR_VC_CORERESET_Pos   0U

DCB DEMCR: Vector Catch Core reset Position

Definition at line 3497 of file core_cm55.h.

◆ DCB_DEMCR_VC_CORERESET_Pos [8/13]

#define DCB_DEMCR_VC_CORERESET_Pos   0U

DCB DEMCR: Vector Catch Core reset Position

Definition at line 3402 of file core_cm85.h.

◆ DCB_DEMCR_VC_CORERESET_Pos [9/13]

#define DCB_DEMCR_VC_CORERESET_Pos   0U

DCB DEMCR: Vector Catch Core reset Position

Definition at line 2009 of file core_starmc1.h.

◆ DCB_DEMCR_VC_CORERESET_Pos [10/13]

#define DCB_DEMCR_VC_CORERESET_Pos   0U

DCB DEMCR: Vector Catch Core reset Position

Definition at line 2943 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_CORERESET_Pos [11/13]

#define DCB_DEMCR_VC_CORERESET_Pos   0U

DCB DEMCR: Vector Catch Core reset Position

Definition at line 1166 of file core_armv8mbl.h.

◆ DCB_DEMCR_VC_CORERESET_Pos [12/13]

#define DCB_DEMCR_VC_CORERESET_Pos   0U

DCB DEMCR: Vector Catch Core reset Position

Definition at line 2007 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_CORERESET_Pos [13/13]

#define DCB_DEMCR_VC_CORERESET_Pos   0U

DCB DEMCR: Vector Catch Core reset Position

Definition at line 2082 of file core_cm33.h.

◆ DCB_DEMCR_VC_HARDERR_Msk [1/13]

#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)

DCB DEMCR: Vector Catch HardFault errors Mask

Definition at line 2923 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_HARDERR_Msk [2/13]

#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)

DCB DEMCR: Vector Catch HardFault errors Mask

Definition at line 1164 of file core_armv8mbl.h.

◆ DCB_DEMCR_VC_HARDERR_Msk [3/13]

#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)

DCB DEMCR: Vector Catch HardFault errors Mask

Definition at line 1987 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_HARDERR_Msk [4/13]

#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)

DCB DEMCR: Vector Catch HardFault errors Mask

Definition at line 1239 of file core_cm23.h.

◆ DCB_DEMCR_VC_HARDERR_Msk [5/13]

#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)

DCB DEMCR: Vector Catch HardFault errors Mask

Definition at line 2062 of file core_cm33.h.

◆ DCB_DEMCR_VC_HARDERR_Msk [6/13]

#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)

DCB DEMCR: Vector Catch HardFault errors Mask

Definition at line 2062 of file core_cm35p.h.

◆ DCB_DEMCR_VC_HARDERR_Msk [7/13]

#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)

DCB DEMCR: Vector Catch HardFault errors Mask

Definition at line 3477 of file core_cm55.h.

◆ DCB_DEMCR_VC_HARDERR_Msk [8/13]

#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)

DCB DEMCR: Vector Catch HardFault errors Mask

Definition at line 3382 of file core_cm85.h.

◆ DCB_DEMCR_VC_HARDERR_Msk [9/13]

#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)

DCB DEMCR: Vector Catch HardFault errors Mask

Definition at line 1989 of file core_starmc1.h.

◆ DCB_DEMCR_VC_HARDERR_Msk [10/13]

#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)

DCB DEMCR: Vector Catch HardFault errors Mask

Definition at line 2923 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_HARDERR_Msk [11/13]

#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)

DCB DEMCR: Vector Catch HardFault errors Mask

Definition at line 1164 of file core_armv8mbl.h.

◆ DCB_DEMCR_VC_HARDERR_Msk [12/13]

#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)

DCB DEMCR: Vector Catch HardFault errors Mask

Definition at line 1987 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_HARDERR_Msk [13/13]

#define DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)

DCB DEMCR: Vector Catch HardFault errors Mask

Definition at line 2062 of file core_cm33.h.

◆ DCB_DEMCR_VC_HARDERR_Pos [1/13]

#define DCB_DEMCR_VC_HARDERR_Pos   10U

DCB DEMCR: Vector Catch HardFault errors Position

Definition at line 2922 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_HARDERR_Pos [2/13]

#define DCB_DEMCR_VC_HARDERR_Pos   10U

DCB DEMCR: Vector Catch HardFault errors Position

Definition at line 1163 of file core_armv8mbl.h.

◆ DCB_DEMCR_VC_HARDERR_Pos [3/13]

#define DCB_DEMCR_VC_HARDERR_Pos   10U

DCB DEMCR: Vector Catch HardFault errors Position

Definition at line 1986 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_HARDERR_Pos [4/13]

#define DCB_DEMCR_VC_HARDERR_Pos   10U

DCB DEMCR: Vector Catch HardFault errors Position

Definition at line 1238 of file core_cm23.h.

◆ DCB_DEMCR_VC_HARDERR_Pos [5/13]

#define DCB_DEMCR_VC_HARDERR_Pos   10U

DCB DEMCR: Vector Catch HardFault errors Position

Definition at line 2061 of file core_cm33.h.

◆ DCB_DEMCR_VC_HARDERR_Pos [6/13]

#define DCB_DEMCR_VC_HARDERR_Pos   10U

DCB DEMCR: Vector Catch HardFault errors Position

Definition at line 2061 of file core_cm35p.h.

◆ DCB_DEMCR_VC_HARDERR_Pos [7/13]

#define DCB_DEMCR_VC_HARDERR_Pos   10U

DCB DEMCR: Vector Catch HardFault errors Position

Definition at line 3476 of file core_cm55.h.

◆ DCB_DEMCR_VC_HARDERR_Pos [8/13]

#define DCB_DEMCR_VC_HARDERR_Pos   10U

DCB DEMCR: Vector Catch HardFault errors Position

Definition at line 3381 of file core_cm85.h.

◆ DCB_DEMCR_VC_HARDERR_Pos [9/13]

#define DCB_DEMCR_VC_HARDERR_Pos   10U

DCB DEMCR: Vector Catch HardFault errors Position

Definition at line 1988 of file core_starmc1.h.

◆ DCB_DEMCR_VC_HARDERR_Pos [10/13]

#define DCB_DEMCR_VC_HARDERR_Pos   10U

DCB DEMCR: Vector Catch HardFault errors Position

Definition at line 2922 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_HARDERR_Pos [11/13]

#define DCB_DEMCR_VC_HARDERR_Pos   10U

DCB DEMCR: Vector Catch HardFault errors Position

Definition at line 1163 of file core_armv8mbl.h.

◆ DCB_DEMCR_VC_HARDERR_Pos [12/13]

#define DCB_DEMCR_VC_HARDERR_Pos   10U

DCB DEMCR: Vector Catch HardFault errors Position

Definition at line 1986 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_HARDERR_Pos [13/13]

#define DCB_DEMCR_VC_HARDERR_Pos   10U

DCB DEMCR: Vector Catch HardFault errors Position

Definition at line 2061 of file core_cm33.h.

◆ DCB_DEMCR_VC_INTERR_Msk [1/10]

#define DCB_DEMCR_VC_INTERR_Msk   (0x1UL << DCB_DEMCR_VC_INTERR_Pos)

DCB DEMCR: Vector Catch interrupt errors Mask

Definition at line 2926 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_INTERR_Msk [2/10]

#define DCB_DEMCR_VC_INTERR_Msk   (0x1UL << DCB_DEMCR_VC_INTERR_Pos)

DCB DEMCR: Vector Catch interrupt errors Mask

Definition at line 1990 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_INTERR_Msk [3/10]

#define DCB_DEMCR_VC_INTERR_Msk   (0x1UL << DCB_DEMCR_VC_INTERR_Pos)

DCB DEMCR: Vector Catch interrupt errors Mask

Definition at line 2065 of file core_cm33.h.

◆ DCB_DEMCR_VC_INTERR_Msk [4/10]

#define DCB_DEMCR_VC_INTERR_Msk   (0x1UL << DCB_DEMCR_VC_INTERR_Pos)

DCB DEMCR: Vector Catch interrupt errors Mask

Definition at line 2065 of file core_cm35p.h.

◆ DCB_DEMCR_VC_INTERR_Msk [5/10]

#define DCB_DEMCR_VC_INTERR_Msk   (0x1UL << DCB_DEMCR_VC_INTERR_Pos)

DCB DEMCR: Vector Catch interrupt errors Mask

Definition at line 3480 of file core_cm55.h.

◆ DCB_DEMCR_VC_INTERR_Msk [6/10]

#define DCB_DEMCR_VC_INTERR_Msk   (0x1UL << DCB_DEMCR_VC_INTERR_Pos)

DCB DEMCR: Vector Catch interrupt errors Mask

Definition at line 3385 of file core_cm85.h.

◆ DCB_DEMCR_VC_INTERR_Msk [7/10]

#define DCB_DEMCR_VC_INTERR_Msk   (0x1UL << DCB_DEMCR_VC_INTERR_Pos)

DCB DEMCR: Vector Catch interrupt errors Mask

Definition at line 1992 of file core_starmc1.h.

◆ DCB_DEMCR_VC_INTERR_Msk [8/10]

#define DCB_DEMCR_VC_INTERR_Msk   (0x1UL << DCB_DEMCR_VC_INTERR_Pos)

DCB DEMCR: Vector Catch interrupt errors Mask

Definition at line 2926 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_INTERR_Msk [9/10]

#define DCB_DEMCR_VC_INTERR_Msk   (0x1UL << DCB_DEMCR_VC_INTERR_Pos)

DCB DEMCR: Vector Catch interrupt errors Mask

Definition at line 1990 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_INTERR_Msk [10/10]

#define DCB_DEMCR_VC_INTERR_Msk   (0x1UL << DCB_DEMCR_VC_INTERR_Pos)

DCB DEMCR: Vector Catch interrupt errors Mask

Definition at line 2065 of file core_cm33.h.

◆ DCB_DEMCR_VC_INTERR_Pos [1/10]

#define DCB_DEMCR_VC_INTERR_Pos   9U

DCB DEMCR: Vector Catch interrupt errors Position

Definition at line 2925 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_INTERR_Pos [2/10]

#define DCB_DEMCR_VC_INTERR_Pos   9U

DCB DEMCR: Vector Catch interrupt errors Position

Definition at line 1989 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_INTERR_Pos [3/10]

#define DCB_DEMCR_VC_INTERR_Pos   9U

DCB DEMCR: Vector Catch interrupt errors Position

Definition at line 2064 of file core_cm33.h.

◆ DCB_DEMCR_VC_INTERR_Pos [4/10]

#define DCB_DEMCR_VC_INTERR_Pos   9U

DCB DEMCR: Vector Catch interrupt errors Position

Definition at line 2064 of file core_cm35p.h.

◆ DCB_DEMCR_VC_INTERR_Pos [5/10]

#define DCB_DEMCR_VC_INTERR_Pos   9U

DCB DEMCR: Vector Catch interrupt errors Position

Definition at line 3479 of file core_cm55.h.

◆ DCB_DEMCR_VC_INTERR_Pos [6/10]

#define DCB_DEMCR_VC_INTERR_Pos   9U

DCB DEMCR: Vector Catch interrupt errors Position

Definition at line 3384 of file core_cm85.h.

◆ DCB_DEMCR_VC_INTERR_Pos [7/10]

#define DCB_DEMCR_VC_INTERR_Pos   9U

DCB DEMCR: Vector Catch interrupt errors Position

Definition at line 1991 of file core_starmc1.h.

◆ DCB_DEMCR_VC_INTERR_Pos [8/10]

#define DCB_DEMCR_VC_INTERR_Pos   9U

DCB DEMCR: Vector Catch interrupt errors Position

Definition at line 2925 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_INTERR_Pos [9/10]

#define DCB_DEMCR_VC_INTERR_Pos   9U

DCB DEMCR: Vector Catch interrupt errors Position

Definition at line 1989 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_INTERR_Pos [10/10]

#define DCB_DEMCR_VC_INTERR_Pos   9U

DCB DEMCR: Vector Catch interrupt errors Position

Definition at line 2064 of file core_cm33.h.

◆ DCB_DEMCR_VC_MMERR_Msk [1/10]

#define DCB_DEMCR_VC_MMERR_Msk   (0x1UL << DCB_DEMCR_VC_MMERR_Pos)

DCB DEMCR: Vector Catch MemManage errors Mask

Definition at line 2941 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_MMERR_Msk [2/10]

#define DCB_DEMCR_VC_MMERR_Msk   (0x1UL << DCB_DEMCR_VC_MMERR_Pos)

DCB DEMCR: Vector Catch MemManage errors Mask

Definition at line 2005 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_MMERR_Msk [3/10]

#define DCB_DEMCR_VC_MMERR_Msk   (0x1UL << DCB_DEMCR_VC_MMERR_Pos)

DCB DEMCR: Vector Catch MemManage errors Mask

Definition at line 2080 of file core_cm33.h.

◆ DCB_DEMCR_VC_MMERR_Msk [4/10]

#define DCB_DEMCR_VC_MMERR_Msk   (0x1UL << DCB_DEMCR_VC_MMERR_Pos)

DCB DEMCR: Vector Catch MemManage errors Mask

Definition at line 2080 of file core_cm35p.h.

◆ DCB_DEMCR_VC_MMERR_Msk [5/10]

#define DCB_DEMCR_VC_MMERR_Msk   (0x1UL << DCB_DEMCR_VC_MMERR_Pos)

DCB DEMCR: Vector Catch MemManage errors Mask

Definition at line 3495 of file core_cm55.h.

◆ DCB_DEMCR_VC_MMERR_Msk [6/10]

#define DCB_DEMCR_VC_MMERR_Msk   (0x1UL << DCB_DEMCR_VC_MMERR_Pos)

DCB DEMCR: Vector Catch MemManage errors Mask

Definition at line 3400 of file core_cm85.h.

◆ DCB_DEMCR_VC_MMERR_Msk [7/10]

#define DCB_DEMCR_VC_MMERR_Msk   (0x1UL << DCB_DEMCR_VC_MMERR_Pos)

DCB DEMCR: Vector Catch MemManage errors Mask

Definition at line 2007 of file core_starmc1.h.

◆ DCB_DEMCR_VC_MMERR_Msk [8/10]

#define DCB_DEMCR_VC_MMERR_Msk   (0x1UL << DCB_DEMCR_VC_MMERR_Pos)

DCB DEMCR: Vector Catch MemManage errors Mask

Definition at line 2941 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_MMERR_Msk [9/10]

#define DCB_DEMCR_VC_MMERR_Msk   (0x1UL << DCB_DEMCR_VC_MMERR_Pos)

DCB DEMCR: Vector Catch MemManage errors Mask

Definition at line 2005 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_MMERR_Msk [10/10]

#define DCB_DEMCR_VC_MMERR_Msk   (0x1UL << DCB_DEMCR_VC_MMERR_Pos)

DCB DEMCR: Vector Catch MemManage errors Mask

Definition at line 2080 of file core_cm33.h.

◆ DCB_DEMCR_VC_MMERR_Pos [1/10]

#define DCB_DEMCR_VC_MMERR_Pos   4U

DCB DEMCR: Vector Catch MemManage errors Position

Definition at line 2940 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_MMERR_Pos [2/10]

#define DCB_DEMCR_VC_MMERR_Pos   4U

DCB DEMCR: Vector Catch MemManage errors Position

Definition at line 2004 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_MMERR_Pos [3/10]

#define DCB_DEMCR_VC_MMERR_Pos   4U

DCB DEMCR: Vector Catch MemManage errors Position

Definition at line 2079 of file core_cm33.h.

◆ DCB_DEMCR_VC_MMERR_Pos [4/10]

#define DCB_DEMCR_VC_MMERR_Pos   4U

DCB DEMCR: Vector Catch MemManage errors Position

Definition at line 2079 of file core_cm35p.h.

◆ DCB_DEMCR_VC_MMERR_Pos [5/10]

#define DCB_DEMCR_VC_MMERR_Pos   4U

DCB DEMCR: Vector Catch MemManage errors Position

Definition at line 3494 of file core_cm55.h.

◆ DCB_DEMCR_VC_MMERR_Pos [6/10]

#define DCB_DEMCR_VC_MMERR_Pos   4U

DCB DEMCR: Vector Catch MemManage errors Position

Definition at line 3399 of file core_cm85.h.

◆ DCB_DEMCR_VC_MMERR_Pos [7/10]

#define DCB_DEMCR_VC_MMERR_Pos   4U

DCB DEMCR: Vector Catch MemManage errors Position

Definition at line 2006 of file core_starmc1.h.

◆ DCB_DEMCR_VC_MMERR_Pos [8/10]

#define DCB_DEMCR_VC_MMERR_Pos   4U

DCB DEMCR: Vector Catch MemManage errors Position

Definition at line 2940 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_MMERR_Pos [9/10]

#define DCB_DEMCR_VC_MMERR_Pos   4U

DCB DEMCR: Vector Catch MemManage errors Position

Definition at line 2004 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_MMERR_Pos [10/10]

#define DCB_DEMCR_VC_MMERR_Pos   4U

DCB DEMCR: Vector Catch MemManage errors Position

Definition at line 2079 of file core_cm33.h.

◆ DCB_DEMCR_VC_NOCPERR_Msk [1/10]

#define DCB_DEMCR_VC_NOCPERR_Msk   (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)

DCB DEMCR: Vector Catch NOCP errors Mask

Definition at line 2938 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_NOCPERR_Msk [2/10]

#define DCB_DEMCR_VC_NOCPERR_Msk   (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)

DCB DEMCR: Vector Catch NOCP errors Mask

Definition at line 2002 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_NOCPERR_Msk [3/10]

#define DCB_DEMCR_VC_NOCPERR_Msk   (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)

DCB DEMCR: Vector Catch NOCP errors Mask

Definition at line 2077 of file core_cm33.h.

◆ DCB_DEMCR_VC_NOCPERR_Msk [4/10]

#define DCB_DEMCR_VC_NOCPERR_Msk   (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)

DCB DEMCR: Vector Catch NOCP errors Mask

Definition at line 2077 of file core_cm35p.h.

◆ DCB_DEMCR_VC_NOCPERR_Msk [5/10]

#define DCB_DEMCR_VC_NOCPERR_Msk   (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)

DCB DEMCR: Vector Catch NOCP errors Mask

Definition at line 3492 of file core_cm55.h.

◆ DCB_DEMCR_VC_NOCPERR_Msk [6/10]

#define DCB_DEMCR_VC_NOCPERR_Msk   (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)

DCB DEMCR: Vector Catch NOCP errors Mask

Definition at line 3397 of file core_cm85.h.

◆ DCB_DEMCR_VC_NOCPERR_Msk [7/10]

#define DCB_DEMCR_VC_NOCPERR_Msk   (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)

DCB DEMCR: Vector Catch NOCP errors Mask

Definition at line 2004 of file core_starmc1.h.

◆ DCB_DEMCR_VC_NOCPERR_Msk [8/10]

#define DCB_DEMCR_VC_NOCPERR_Msk   (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)

DCB DEMCR: Vector Catch NOCP errors Mask

Definition at line 2938 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_NOCPERR_Msk [9/10]

#define DCB_DEMCR_VC_NOCPERR_Msk   (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)

DCB DEMCR: Vector Catch NOCP errors Mask

Definition at line 2002 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_NOCPERR_Msk [10/10]

#define DCB_DEMCR_VC_NOCPERR_Msk   (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)

DCB DEMCR: Vector Catch NOCP errors Mask

Definition at line 2077 of file core_cm33.h.

◆ DCB_DEMCR_VC_NOCPERR_Pos [1/10]

#define DCB_DEMCR_VC_NOCPERR_Pos   5U

DCB DEMCR: Vector Catch NOCP errors Position

Definition at line 2937 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_NOCPERR_Pos [2/10]

#define DCB_DEMCR_VC_NOCPERR_Pos   5U

DCB DEMCR: Vector Catch NOCP errors Position

Definition at line 2001 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_NOCPERR_Pos [3/10]

#define DCB_DEMCR_VC_NOCPERR_Pos   5U

DCB DEMCR: Vector Catch NOCP errors Position

Definition at line 2076 of file core_cm33.h.

◆ DCB_DEMCR_VC_NOCPERR_Pos [4/10]

#define DCB_DEMCR_VC_NOCPERR_Pos   5U

DCB DEMCR: Vector Catch NOCP errors Position

Definition at line 2076 of file core_cm35p.h.

◆ DCB_DEMCR_VC_NOCPERR_Pos [5/10]

#define DCB_DEMCR_VC_NOCPERR_Pos   5U

DCB DEMCR: Vector Catch NOCP errors Position

Definition at line 3491 of file core_cm55.h.

◆ DCB_DEMCR_VC_NOCPERR_Pos [6/10]

#define DCB_DEMCR_VC_NOCPERR_Pos   5U

DCB DEMCR: Vector Catch NOCP errors Position

Definition at line 3396 of file core_cm85.h.

◆ DCB_DEMCR_VC_NOCPERR_Pos [7/10]

#define DCB_DEMCR_VC_NOCPERR_Pos   5U

DCB DEMCR: Vector Catch NOCP errors Position

Definition at line 2003 of file core_starmc1.h.

◆ DCB_DEMCR_VC_NOCPERR_Pos [8/10]

#define DCB_DEMCR_VC_NOCPERR_Pos   5U

DCB DEMCR: Vector Catch NOCP errors Position

Definition at line 2937 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_NOCPERR_Pos [9/10]

#define DCB_DEMCR_VC_NOCPERR_Pos   5U

DCB DEMCR: Vector Catch NOCP errors Position

Definition at line 2001 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_NOCPERR_Pos [10/10]

#define DCB_DEMCR_VC_NOCPERR_Pos   5U

DCB DEMCR: Vector Catch NOCP errors Position

Definition at line 2076 of file core_cm33.h.

◆ DCB_DEMCR_VC_SFERR_Msk [1/10]

#define DCB_DEMCR_VC_SFERR_Msk   (0x1UL << DCB_DEMCR_VC_SFERR_Pos)

DCB DEMCR: Vector Catch SecureFault Mask

Definition at line 2920 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_SFERR_Msk [2/10]

#define DCB_DEMCR_VC_SFERR_Msk   (0x1UL << DCB_DEMCR_VC_SFERR_Pos)

DCB DEMCR: Vector Catch SecureFault Mask

Definition at line 1984 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_SFERR_Msk [3/10]

#define DCB_DEMCR_VC_SFERR_Msk   (0x1UL << DCB_DEMCR_VC_SFERR_Pos)

DCB DEMCR: Vector Catch SecureFault Mask

Definition at line 2059 of file core_cm33.h.

◆ DCB_DEMCR_VC_SFERR_Msk [4/10]

#define DCB_DEMCR_VC_SFERR_Msk   (0x1UL << DCB_DEMCR_VC_SFERR_Pos)

DCB DEMCR: Vector Catch SecureFault Mask

Definition at line 2059 of file core_cm35p.h.

◆ DCB_DEMCR_VC_SFERR_Msk [5/10]

#define DCB_DEMCR_VC_SFERR_Msk   (0x1UL << DCB_DEMCR_VC_SFERR_Pos)

DCB DEMCR: Vector Catch SecureFault Mask

Definition at line 3474 of file core_cm55.h.

◆ DCB_DEMCR_VC_SFERR_Msk [6/10]

#define DCB_DEMCR_VC_SFERR_Msk   (0x1UL << DCB_DEMCR_VC_SFERR_Pos)

DCB DEMCR: Vector Catch SecureFault Mask

Definition at line 3379 of file core_cm85.h.

◆ DCB_DEMCR_VC_SFERR_Msk [7/10]

#define DCB_DEMCR_VC_SFERR_Msk   (0x1UL << DCB_DEMCR_VC_SFERR_Pos)

DCB DEMCR: Vector Catch SecureFault Mask

Definition at line 1986 of file core_starmc1.h.

◆ DCB_DEMCR_VC_SFERR_Msk [8/10]

#define DCB_DEMCR_VC_SFERR_Msk   (0x1UL << DCB_DEMCR_VC_SFERR_Pos)

DCB DEMCR: Vector Catch SecureFault Mask

Definition at line 2920 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_SFERR_Msk [9/10]

#define DCB_DEMCR_VC_SFERR_Msk   (0x1UL << DCB_DEMCR_VC_SFERR_Pos)

DCB DEMCR: Vector Catch SecureFault Mask

Definition at line 1984 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_SFERR_Msk [10/10]

#define DCB_DEMCR_VC_SFERR_Msk   (0x1UL << DCB_DEMCR_VC_SFERR_Pos)

DCB DEMCR: Vector Catch SecureFault Mask

Definition at line 2059 of file core_cm33.h.

◆ DCB_DEMCR_VC_SFERR_Pos [1/10]

#define DCB_DEMCR_VC_SFERR_Pos   11U

DCB DEMCR: Vector Catch SecureFault Position

Definition at line 2919 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_SFERR_Pos [2/10]

#define DCB_DEMCR_VC_SFERR_Pos   11U

DCB DEMCR: Vector Catch SecureFault Position

Definition at line 1983 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_SFERR_Pos [3/10]

#define DCB_DEMCR_VC_SFERR_Pos   11U

DCB DEMCR: Vector Catch SecureFault Position

Definition at line 2058 of file core_cm33.h.

◆ DCB_DEMCR_VC_SFERR_Pos [4/10]

#define DCB_DEMCR_VC_SFERR_Pos   11U

DCB DEMCR: Vector Catch SecureFault Position

Definition at line 2058 of file core_cm35p.h.

◆ DCB_DEMCR_VC_SFERR_Pos [5/10]

#define DCB_DEMCR_VC_SFERR_Pos   11U

DCB DEMCR: Vector Catch SecureFault Position

Definition at line 3473 of file core_cm55.h.

◆ DCB_DEMCR_VC_SFERR_Pos [6/10]

#define DCB_DEMCR_VC_SFERR_Pos   11U

DCB DEMCR: Vector Catch SecureFault Position

Definition at line 3378 of file core_cm85.h.

◆ DCB_DEMCR_VC_SFERR_Pos [7/10]

#define DCB_DEMCR_VC_SFERR_Pos   11U

DCB DEMCR: Vector Catch SecureFault Position

Definition at line 1985 of file core_starmc1.h.

◆ DCB_DEMCR_VC_SFERR_Pos [8/10]

#define DCB_DEMCR_VC_SFERR_Pos   11U

DCB DEMCR: Vector Catch SecureFault Position

Definition at line 2919 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_SFERR_Pos [9/10]

#define DCB_DEMCR_VC_SFERR_Pos   11U

DCB DEMCR: Vector Catch SecureFault Position

Definition at line 1983 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_SFERR_Pos [10/10]

#define DCB_DEMCR_VC_SFERR_Pos   11U

DCB DEMCR: Vector Catch SecureFault Position

Definition at line 2058 of file core_cm33.h.

◆ DCB_DEMCR_VC_STATERR_Msk [1/10]

#define DCB_DEMCR_VC_STATERR_Msk   (0x1UL << DCB_DEMCR_VC_STATERR_Pos)

DCB DEMCR: Vector Catch state errors Mask

Definition at line 2932 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_STATERR_Msk [2/10]

#define DCB_DEMCR_VC_STATERR_Msk   (0x1UL << DCB_DEMCR_VC_STATERR_Pos)

DCB DEMCR: Vector Catch state errors Mask

Definition at line 1996 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_STATERR_Msk [3/10]

#define DCB_DEMCR_VC_STATERR_Msk   (0x1UL << DCB_DEMCR_VC_STATERR_Pos)

DCB DEMCR: Vector Catch state errors Mask

Definition at line 2071 of file core_cm33.h.

◆ DCB_DEMCR_VC_STATERR_Msk [4/10]

#define DCB_DEMCR_VC_STATERR_Msk   (0x1UL << DCB_DEMCR_VC_STATERR_Pos)

DCB DEMCR: Vector Catch state errors Mask

Definition at line 2071 of file core_cm35p.h.

◆ DCB_DEMCR_VC_STATERR_Msk [5/10]

#define DCB_DEMCR_VC_STATERR_Msk   (0x1UL << DCB_DEMCR_VC_STATERR_Pos)

DCB DEMCR: Vector Catch state errors Mask

Definition at line 3486 of file core_cm55.h.

◆ DCB_DEMCR_VC_STATERR_Msk [6/10]

#define DCB_DEMCR_VC_STATERR_Msk   (0x1UL << DCB_DEMCR_VC_STATERR_Pos)

DCB DEMCR: Vector Catch state errors Mask

Definition at line 3391 of file core_cm85.h.

◆ DCB_DEMCR_VC_STATERR_Msk [7/10]

#define DCB_DEMCR_VC_STATERR_Msk   (0x1UL << DCB_DEMCR_VC_STATERR_Pos)

DCB DEMCR: Vector Catch state errors Mask

Definition at line 1998 of file core_starmc1.h.

◆ DCB_DEMCR_VC_STATERR_Msk [8/10]

#define DCB_DEMCR_VC_STATERR_Msk   (0x1UL << DCB_DEMCR_VC_STATERR_Pos)

DCB DEMCR: Vector Catch state errors Mask

Definition at line 2932 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_STATERR_Msk [9/10]

#define DCB_DEMCR_VC_STATERR_Msk   (0x1UL << DCB_DEMCR_VC_STATERR_Pos)

DCB DEMCR: Vector Catch state errors Mask

Definition at line 1996 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_STATERR_Msk [10/10]

#define DCB_DEMCR_VC_STATERR_Msk   (0x1UL << DCB_DEMCR_VC_STATERR_Pos)

DCB DEMCR: Vector Catch state errors Mask

Definition at line 2071 of file core_cm33.h.

◆ DCB_DEMCR_VC_STATERR_Pos [1/10]

#define DCB_DEMCR_VC_STATERR_Pos   7U

DCB DEMCR: Vector Catch state errors Position

Definition at line 2931 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_STATERR_Pos [2/10]

#define DCB_DEMCR_VC_STATERR_Pos   7U

DCB DEMCR: Vector Catch state errors Position

Definition at line 1995 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_STATERR_Pos [3/10]

#define DCB_DEMCR_VC_STATERR_Pos   7U

DCB DEMCR: Vector Catch state errors Position

Definition at line 2070 of file core_cm33.h.

◆ DCB_DEMCR_VC_STATERR_Pos [4/10]

#define DCB_DEMCR_VC_STATERR_Pos   7U

DCB DEMCR: Vector Catch state errors Position

Definition at line 2070 of file core_cm35p.h.

◆ DCB_DEMCR_VC_STATERR_Pos [5/10]

#define DCB_DEMCR_VC_STATERR_Pos   7U

DCB DEMCR: Vector Catch state errors Position

Definition at line 3485 of file core_cm55.h.

◆ DCB_DEMCR_VC_STATERR_Pos [6/10]

#define DCB_DEMCR_VC_STATERR_Pos   7U

DCB DEMCR: Vector Catch state errors Position

Definition at line 3390 of file core_cm85.h.

◆ DCB_DEMCR_VC_STATERR_Pos [7/10]

#define DCB_DEMCR_VC_STATERR_Pos   7U

DCB DEMCR: Vector Catch state errors Position

Definition at line 1997 of file core_starmc1.h.

◆ DCB_DEMCR_VC_STATERR_Pos [8/10]

#define DCB_DEMCR_VC_STATERR_Pos   7U

DCB DEMCR: Vector Catch state errors Position

Definition at line 2931 of file core_armv81mml.h.

◆ DCB_DEMCR_VC_STATERR_Pos [9/10]

#define DCB_DEMCR_VC_STATERR_Pos   7U

DCB DEMCR: Vector Catch state errors Position

Definition at line 1995 of file core_armv8mml.h.

◆ DCB_DEMCR_VC_STATERR_Pos [10/10]

#define DCB_DEMCR_VC_STATERR_Pos   7U

DCB DEMCR: Vector Catch state errors Position

Definition at line 2070 of file core_cm33.h.

◆ DCB_DHCSR_C_DEBUGEN_Msk [1/13]

#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)

DCB DHCSR: Debug enable control Mask

Definition at line 2881 of file core_armv81mml.h.

◆ DCB_DHCSR_C_DEBUGEN_Msk [2/13]

#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)

DCB DHCSR: Debug enable control Mask

Definition at line 1146 of file core_armv8mbl.h.

◆ DCB_DHCSR_C_DEBUGEN_Msk [3/13]

#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)

DCB DHCSR: Debug enable control Mask

Definition at line 1945 of file core_armv8mml.h.

◆ DCB_DHCSR_C_DEBUGEN_Msk [4/13]

#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)

DCB DHCSR: Debug enable control Mask

Definition at line 1221 of file core_cm23.h.

◆ DCB_DHCSR_C_DEBUGEN_Msk [5/13]

#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)

DCB DHCSR: Debug enable control Mask

Definition at line 2020 of file core_cm33.h.

◆ DCB_DHCSR_C_DEBUGEN_Msk [6/13]

#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)

DCB DHCSR: Debug enable control Mask

Definition at line 2020 of file core_cm35p.h.

◆ DCB_DHCSR_C_DEBUGEN_Msk [7/13]

#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)

DCB DHCSR: Debug enable control Mask

Definition at line 3435 of file core_cm55.h.

◆ DCB_DHCSR_C_DEBUGEN_Msk [8/13]

#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)

DCB DHCSR: Debug enable control Mask

Definition at line 3340 of file core_cm85.h.

◆ DCB_DHCSR_C_DEBUGEN_Msk [9/13]

#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)

DCB DHCSR: Debug enable control Mask

Definition at line 1947 of file core_starmc1.h.

◆ DCB_DHCSR_C_DEBUGEN_Msk [10/13]

#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)

DCB DHCSR: Debug enable control Mask

Definition at line 2881 of file core_armv81mml.h.

◆ DCB_DHCSR_C_DEBUGEN_Msk [11/13]

#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)

DCB DHCSR: Debug enable control Mask

Definition at line 1146 of file core_armv8mbl.h.

◆ DCB_DHCSR_C_DEBUGEN_Msk [12/13]

#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)

DCB DHCSR: Debug enable control Mask

Definition at line 1945 of file core_armv8mml.h.

◆ DCB_DHCSR_C_DEBUGEN_Msk [13/13]

#define DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)

DCB DHCSR: Debug enable control Mask

Definition at line 2020 of file core_cm33.h.

◆ DCB_DHCSR_C_DEBUGEN_Pos [1/13]

#define DCB_DHCSR_C_DEBUGEN_Pos   0U

DCB DHCSR: Debug enable control Position

Definition at line 2880 of file core_armv81mml.h.

◆ DCB_DHCSR_C_DEBUGEN_Pos [2/13]

#define DCB_DHCSR_C_DEBUGEN_Pos   0U

DCB DHCSR: Debug enable control Position

Definition at line 1145 of file core_armv8mbl.h.

◆ DCB_DHCSR_C_DEBUGEN_Pos [3/13]

#define DCB_DHCSR_C_DEBUGEN_Pos   0U

DCB DHCSR: Debug enable control Position

Definition at line 1944 of file core_armv8mml.h.

◆ DCB_DHCSR_C_DEBUGEN_Pos [4/13]

#define DCB_DHCSR_C_DEBUGEN_Pos   0U

DCB DHCSR: Debug enable control Position

Definition at line 1220 of file core_cm23.h.

◆ DCB_DHCSR_C_DEBUGEN_Pos [5/13]

#define DCB_DHCSR_C_DEBUGEN_Pos   0U

DCB DHCSR: Debug enable control Position

Definition at line 2019 of file core_cm33.h.

◆ DCB_DHCSR_C_DEBUGEN_Pos [6/13]

#define DCB_DHCSR_C_DEBUGEN_Pos   0U

DCB DHCSR: Debug enable control Position

Definition at line 2019 of file core_cm35p.h.

◆ DCB_DHCSR_C_DEBUGEN_Pos [7/13]

#define DCB_DHCSR_C_DEBUGEN_Pos   0U

DCB DHCSR: Debug enable control Position

Definition at line 3434 of file core_cm55.h.

◆ DCB_DHCSR_C_DEBUGEN_Pos [8/13]

#define DCB_DHCSR_C_DEBUGEN_Pos   0U

DCB DHCSR: Debug enable control Position

Definition at line 3339 of file core_cm85.h.

◆ DCB_DHCSR_C_DEBUGEN_Pos [9/13]

#define DCB_DHCSR_C_DEBUGEN_Pos   0U

DCB DHCSR: Debug enable control Position

Definition at line 1946 of file core_starmc1.h.

◆ DCB_DHCSR_C_DEBUGEN_Pos [10/13]

#define DCB_DHCSR_C_DEBUGEN_Pos   0U

DCB DHCSR: Debug enable control Position

Definition at line 2880 of file core_armv81mml.h.

◆ DCB_DHCSR_C_DEBUGEN_Pos [11/13]

#define DCB_DHCSR_C_DEBUGEN_Pos   0U

DCB DHCSR: Debug enable control Position

Definition at line 1145 of file core_armv8mbl.h.

◆ DCB_DHCSR_C_DEBUGEN_Pos [12/13]

#define DCB_DHCSR_C_DEBUGEN_Pos   0U

DCB DHCSR: Debug enable control Position

Definition at line 1944 of file core_armv8mml.h.

◆ DCB_DHCSR_C_DEBUGEN_Pos [13/13]

#define DCB_DHCSR_C_DEBUGEN_Pos   0U

DCB DHCSR: Debug enable control Position

Definition at line 2019 of file core_cm33.h.

◆ DCB_DHCSR_C_HALT_Msk [1/13]

#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)

DCB DHCSR: Halt control Mask

Definition at line 2878 of file core_armv81mml.h.

◆ DCB_DHCSR_C_HALT_Msk [2/13]

#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)

DCB DHCSR: Halt control Mask

Definition at line 1143 of file core_armv8mbl.h.

◆ DCB_DHCSR_C_HALT_Msk [3/13]

#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)

DCB DHCSR: Halt control Mask

Definition at line 1942 of file core_armv8mml.h.

◆ DCB_DHCSR_C_HALT_Msk [4/13]

#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)

DCB DHCSR: Halt control Mask

Definition at line 1218 of file core_cm23.h.

◆ DCB_DHCSR_C_HALT_Msk [5/13]

#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)

DCB DHCSR: Halt control Mask

Definition at line 2017 of file core_cm33.h.

◆ DCB_DHCSR_C_HALT_Msk [6/13]

#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)

DCB DHCSR: Halt control Mask

Definition at line 2017 of file core_cm35p.h.

◆ DCB_DHCSR_C_HALT_Msk [7/13]

#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)

DCB DHCSR: Halt control Mask

Definition at line 3432 of file core_cm55.h.

◆ DCB_DHCSR_C_HALT_Msk [8/13]

#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)

DCB DHCSR: Halt control Mask

Definition at line 3337 of file core_cm85.h.

◆ DCB_DHCSR_C_HALT_Msk [9/13]

#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)

DCB DHCSR: Halt control Mask

Definition at line 1944 of file core_starmc1.h.

◆ DCB_DHCSR_C_HALT_Msk [10/13]

#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)

DCB DHCSR: Halt control Mask

Definition at line 2878 of file core_armv81mml.h.

◆ DCB_DHCSR_C_HALT_Msk [11/13]

#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)

DCB DHCSR: Halt control Mask

Definition at line 1143 of file core_armv8mbl.h.

◆ DCB_DHCSR_C_HALT_Msk [12/13]

#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)

DCB DHCSR: Halt control Mask

Definition at line 1942 of file core_armv8mml.h.

◆ DCB_DHCSR_C_HALT_Msk [13/13]

#define DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)

DCB DHCSR: Halt control Mask

Definition at line 2017 of file core_cm33.h.

◆ DCB_DHCSR_C_HALT_Pos [1/13]

#define DCB_DHCSR_C_HALT_Pos   1U

DCB DHCSR: Halt control Position

Definition at line 2877 of file core_armv81mml.h.

◆ DCB_DHCSR_C_HALT_Pos [2/13]

#define DCB_DHCSR_C_HALT_Pos   1U

DCB DHCSR: Halt control Position

Definition at line 1142 of file core_armv8mbl.h.

◆ DCB_DHCSR_C_HALT_Pos [3/13]

#define DCB_DHCSR_C_HALT_Pos   1U

DCB DHCSR: Halt control Position

Definition at line 1941 of file core_armv8mml.h.

◆ DCB_DHCSR_C_HALT_Pos [4/13]

#define DCB_DHCSR_C_HALT_Pos   1U

DCB DHCSR: Halt control Position

Definition at line 1217 of file core_cm23.h.

◆ DCB_DHCSR_C_HALT_Pos [5/13]

#define DCB_DHCSR_C_HALT_Pos   1U

DCB DHCSR: Halt control Position

Definition at line 2016 of file core_cm33.h.

◆ DCB_DHCSR_C_HALT_Pos [6/13]

#define DCB_DHCSR_C_HALT_Pos   1U

DCB DHCSR: Halt control Position

Definition at line 2016 of file core_cm35p.h.

◆ DCB_DHCSR_C_HALT_Pos [7/13]

#define DCB_DHCSR_C_HALT_Pos   1U

DCB DHCSR: Halt control Position

Definition at line 3431 of file core_cm55.h.

◆ DCB_DHCSR_C_HALT_Pos [8/13]

#define DCB_DHCSR_C_HALT_Pos   1U

DCB DHCSR: Halt control Position

Definition at line 3336 of file core_cm85.h.

◆ DCB_DHCSR_C_HALT_Pos [9/13]

#define DCB_DHCSR_C_HALT_Pos   1U

DCB DHCSR: Halt control Position

Definition at line 1943 of file core_starmc1.h.

◆ DCB_DHCSR_C_HALT_Pos [10/13]

#define DCB_DHCSR_C_HALT_Pos   1U

DCB DHCSR: Halt control Position

Definition at line 2877 of file core_armv81mml.h.

◆ DCB_DHCSR_C_HALT_Pos [11/13]

#define DCB_DHCSR_C_HALT_Pos   1U

DCB DHCSR: Halt control Position

Definition at line 1142 of file core_armv8mbl.h.

◆ DCB_DHCSR_C_HALT_Pos [12/13]

#define DCB_DHCSR_C_HALT_Pos   1U

DCB DHCSR: Halt control Position

Definition at line 1941 of file core_armv8mml.h.

◆ DCB_DHCSR_C_HALT_Pos [13/13]

#define DCB_DHCSR_C_HALT_Pos   1U

DCB DHCSR: Halt control Position

Definition at line 2016 of file core_cm33.h.

◆ DCB_DHCSR_C_MASKINTS_Msk [1/13]

#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)

DCB DHCSR: Mask interrupts control Mask

Definition at line 2872 of file core_armv81mml.h.

◆ DCB_DHCSR_C_MASKINTS_Msk [2/13]

#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)

DCB DHCSR: Mask interrupts control Mask

Definition at line 1137 of file core_armv8mbl.h.

◆ DCB_DHCSR_C_MASKINTS_Msk [3/13]

#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)

DCB DHCSR: Mask interrupts control Mask

Definition at line 1936 of file core_armv8mml.h.

◆ DCB_DHCSR_C_MASKINTS_Msk [4/13]

#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)

DCB DHCSR: Mask interrupts control Mask

Definition at line 1212 of file core_cm23.h.

◆ DCB_DHCSR_C_MASKINTS_Msk [5/13]

#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)

DCB DHCSR: Mask interrupts control Mask

Definition at line 2011 of file core_cm33.h.

◆ DCB_DHCSR_C_MASKINTS_Msk [6/13]

#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)

DCB DHCSR: Mask interrupts control Mask

Definition at line 2011 of file core_cm35p.h.

◆ DCB_DHCSR_C_MASKINTS_Msk [7/13]

#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)

DCB DHCSR: Mask interrupts control Mask

Definition at line 3426 of file core_cm55.h.

◆ DCB_DHCSR_C_MASKINTS_Msk [8/13]

#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)

DCB DHCSR: Mask interrupts control Mask

Definition at line 3331 of file core_cm85.h.

◆ DCB_DHCSR_C_MASKINTS_Msk [9/13]

#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)

DCB DHCSR: Mask interrupts control Mask

Definition at line 1938 of file core_starmc1.h.

◆ DCB_DHCSR_C_MASKINTS_Msk [10/13]

#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)

DCB DHCSR: Mask interrupts control Mask

Definition at line 2872 of file core_armv81mml.h.

◆ DCB_DHCSR_C_MASKINTS_Msk [11/13]

#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)

DCB DHCSR: Mask interrupts control Mask

Definition at line 1137 of file core_armv8mbl.h.

◆ DCB_DHCSR_C_MASKINTS_Msk [12/13]

#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)

DCB DHCSR: Mask interrupts control Mask

Definition at line 1936 of file core_armv8mml.h.

◆ DCB_DHCSR_C_MASKINTS_Msk [13/13]

#define DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)

DCB DHCSR: Mask interrupts control Mask

Definition at line 2011 of file core_cm33.h.

◆ DCB_DHCSR_C_MASKINTS_Pos [1/13]

#define DCB_DHCSR_C_MASKINTS_Pos   3U

DCB DHCSR: Mask interrupts control Position

Definition at line 2871 of file core_armv81mml.h.

◆ DCB_DHCSR_C_MASKINTS_Pos [2/13]

#define DCB_DHCSR_C_MASKINTS_Pos   3U

DCB DHCSR: Mask interrupts control Position

Definition at line 1136 of file core_armv8mbl.h.

◆ DCB_DHCSR_C_MASKINTS_Pos [3/13]

#define DCB_DHCSR_C_MASKINTS_Pos   3U

DCB DHCSR: Mask interrupts control Position

Definition at line 1935 of file core_armv8mml.h.

◆ DCB_DHCSR_C_MASKINTS_Pos [4/13]

#define DCB_DHCSR_C_MASKINTS_Pos   3U

DCB DHCSR: Mask interrupts control Position

Definition at line 1211 of file core_cm23.h.

◆ DCB_DHCSR_C_MASKINTS_Pos [5/13]

#define DCB_DHCSR_C_MASKINTS_Pos   3U

DCB DHCSR: Mask interrupts control Position

Definition at line 2010 of file core_cm33.h.

◆ DCB_DHCSR_C_MASKINTS_Pos [6/13]

#define DCB_DHCSR_C_MASKINTS_Pos   3U

DCB DHCSR: Mask interrupts control Position

Definition at line 2010 of file core_cm35p.h.

◆ DCB_DHCSR_C_MASKINTS_Pos [7/13]

#define DCB_DHCSR_C_MASKINTS_Pos   3U

DCB DHCSR: Mask interrupts control Position

Definition at line 3425 of file core_cm55.h.

◆ DCB_DHCSR_C_MASKINTS_Pos [8/13]

#define DCB_DHCSR_C_MASKINTS_Pos   3U

DCB DHCSR: Mask interrupts control Position

Definition at line 3330 of file core_cm85.h.

◆ DCB_DHCSR_C_MASKINTS_Pos [9/13]

#define DCB_DHCSR_C_MASKINTS_Pos   3U

DCB DHCSR: Mask interrupts control Position

Definition at line 1937 of file core_starmc1.h.

◆ DCB_DHCSR_C_MASKINTS_Pos [10/13]

#define DCB_DHCSR_C_MASKINTS_Pos   3U

DCB DHCSR: Mask interrupts control Position

Definition at line 2871 of file core_armv81mml.h.

◆ DCB_DHCSR_C_MASKINTS_Pos [11/13]

#define DCB_DHCSR_C_MASKINTS_Pos   3U

DCB DHCSR: Mask interrupts control Position

Definition at line 1136 of file core_armv8mbl.h.

◆ DCB_DHCSR_C_MASKINTS_Pos [12/13]

#define DCB_DHCSR_C_MASKINTS_Pos   3U

DCB DHCSR: Mask interrupts control Position

Definition at line 1935 of file core_armv8mml.h.

◆ DCB_DHCSR_C_MASKINTS_Pos [13/13]

#define DCB_DHCSR_C_MASKINTS_Pos   3U

DCB DHCSR: Mask interrupts control Position

Definition at line 2010 of file core_cm33.h.

◆ DCB_DHCSR_C_PMOV_Msk [1/4]

#define DCB_DHCSR_C_PMOV_Msk   (0x1UL << DCB_DHCSR_C_PMOV_Pos)

DCB DHCSR: Halt on PMU overflow control Mask

Definition at line 2866 of file core_armv81mml.h.

◆ DCB_DHCSR_C_PMOV_Msk [2/4]

#define DCB_DHCSR_C_PMOV_Msk   (0x1UL << DCB_DHCSR_C_PMOV_Pos)

DCB DHCSR: Halt on PMU overflow control Mask

Definition at line 3420 of file core_cm55.h.

◆ DCB_DHCSR_C_PMOV_Msk [3/4]

#define DCB_DHCSR_C_PMOV_Msk   (0x1UL << DCB_DHCSR_C_PMOV_Pos)

DCB DHCSR: Halt on PMU overflow control Mask

Definition at line 3325 of file core_cm85.h.

◆ DCB_DHCSR_C_PMOV_Msk [4/4]

#define DCB_DHCSR_C_PMOV_Msk   (0x1UL << DCB_DHCSR_C_PMOV_Pos)

DCB DHCSR: Halt on PMU overflow control Mask

Definition at line 2866 of file core_armv81mml.h.

◆ DCB_DHCSR_C_PMOV_Pos [1/4]

#define DCB_DHCSR_C_PMOV_Pos   6U

DCB DHCSR: Halt on PMU overflow control Position

Definition at line 2865 of file core_armv81mml.h.

◆ DCB_DHCSR_C_PMOV_Pos [2/4]

#define DCB_DHCSR_C_PMOV_Pos   6U

DCB DHCSR: Halt on PMU overflow control Position

Definition at line 3419 of file core_cm55.h.

◆ DCB_DHCSR_C_PMOV_Pos [3/4]

#define DCB_DHCSR_C_PMOV_Pos   6U

DCB DHCSR: Halt on PMU overflow control Position

Definition at line 3324 of file core_cm85.h.

◆ DCB_DHCSR_C_PMOV_Pos [4/4]

#define DCB_DHCSR_C_PMOV_Pos   6U

DCB DHCSR: Halt on PMU overflow control Position

Definition at line 2865 of file core_armv81mml.h.

◆ DCB_DHCSR_C_SNAPSTALL_Msk [1/10]

#define DCB_DHCSR_C_SNAPSTALL_Msk   (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)

DCB DHCSR: Snap stall control Mask

Definition at line 2869 of file core_armv81mml.h.

◆ DCB_DHCSR_C_SNAPSTALL_Msk [2/10]

#define DCB_DHCSR_C_SNAPSTALL_Msk   (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)

DCB DHCSR: Snap stall control Mask

Definition at line 1933 of file core_armv8mml.h.

◆ DCB_DHCSR_C_SNAPSTALL_Msk [3/10]

#define DCB_DHCSR_C_SNAPSTALL_Msk   (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)

DCB DHCSR: Snap stall control Mask

Definition at line 2008 of file core_cm33.h.

◆ DCB_DHCSR_C_SNAPSTALL_Msk [4/10]

#define DCB_DHCSR_C_SNAPSTALL_Msk   (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)

DCB DHCSR: Snap stall control Mask

Definition at line 2008 of file core_cm35p.h.

◆ DCB_DHCSR_C_SNAPSTALL_Msk [5/10]

#define DCB_DHCSR_C_SNAPSTALL_Msk   (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)

DCB DHCSR: Snap stall control Mask

Definition at line 3423 of file core_cm55.h.

◆ DCB_DHCSR_C_SNAPSTALL_Msk [6/10]

#define DCB_DHCSR_C_SNAPSTALL_Msk   (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)

DCB DHCSR: Snap stall control Mask

Definition at line 3328 of file core_cm85.h.

◆ DCB_DHCSR_C_SNAPSTALL_Msk [7/10]

#define DCB_DHCSR_C_SNAPSTALL_Msk   (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)

DCB DHCSR: Snap stall control Mask

Definition at line 1935 of file core_starmc1.h.

◆ DCB_DHCSR_C_SNAPSTALL_Msk [8/10]

#define DCB_DHCSR_C_SNAPSTALL_Msk   (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)

DCB DHCSR: Snap stall control Mask

Definition at line 2869 of file core_armv81mml.h.

◆ DCB_DHCSR_C_SNAPSTALL_Msk [9/10]

#define DCB_DHCSR_C_SNAPSTALL_Msk   (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)

DCB DHCSR: Snap stall control Mask

Definition at line 1933 of file core_armv8mml.h.

◆ DCB_DHCSR_C_SNAPSTALL_Msk [10/10]

#define DCB_DHCSR_C_SNAPSTALL_Msk   (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)

DCB DHCSR: Snap stall control Mask

Definition at line 2008 of file core_cm33.h.

◆ DCB_DHCSR_C_SNAPSTALL_Pos [1/10]

#define DCB_DHCSR_C_SNAPSTALL_Pos   5U

DCB DHCSR: Snap stall control Position

Definition at line 2868 of file core_armv81mml.h.

◆ DCB_DHCSR_C_SNAPSTALL_Pos [2/10]

#define DCB_DHCSR_C_SNAPSTALL_Pos   5U

DCB DHCSR: Snap stall control Position

Definition at line 1932 of file core_armv8mml.h.

◆ DCB_DHCSR_C_SNAPSTALL_Pos [3/10]

#define DCB_DHCSR_C_SNAPSTALL_Pos   5U

DCB DHCSR: Snap stall control Position

Definition at line 2007 of file core_cm33.h.

◆ DCB_DHCSR_C_SNAPSTALL_Pos [4/10]

#define DCB_DHCSR_C_SNAPSTALL_Pos   5U

DCB DHCSR: Snap stall control Position

Definition at line 2007 of file core_cm35p.h.

◆ DCB_DHCSR_C_SNAPSTALL_Pos [5/10]

#define DCB_DHCSR_C_SNAPSTALL_Pos   5U

DCB DHCSR: Snap stall control Position

Definition at line 3422 of file core_cm55.h.

◆ DCB_DHCSR_C_SNAPSTALL_Pos [6/10]

#define DCB_DHCSR_C_SNAPSTALL_Pos   5U

DCB DHCSR: Snap stall control Position

Definition at line 3327 of file core_cm85.h.

◆ DCB_DHCSR_C_SNAPSTALL_Pos [7/10]

#define DCB_DHCSR_C_SNAPSTALL_Pos   5U

DCB DHCSR: Snap stall control Position

Definition at line 1934 of file core_starmc1.h.

◆ DCB_DHCSR_C_SNAPSTALL_Pos [8/10]

#define DCB_DHCSR_C_SNAPSTALL_Pos   5U

DCB DHCSR: Snap stall control Position

Definition at line 2868 of file core_armv81mml.h.

◆ DCB_DHCSR_C_SNAPSTALL_Pos [9/10]

#define DCB_DHCSR_C_SNAPSTALL_Pos   5U

DCB DHCSR: Snap stall control Position

Definition at line 1932 of file core_armv8mml.h.

◆ DCB_DHCSR_C_SNAPSTALL_Pos [10/10]

#define DCB_DHCSR_C_SNAPSTALL_Pos   5U

DCB DHCSR: Snap stall control Position

Definition at line 2007 of file core_cm33.h.

◆ DCB_DHCSR_C_STEP_Msk [1/13]

#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)

DCB DHCSR: Step control Mask

Definition at line 2875 of file core_armv81mml.h.

◆ DCB_DHCSR_C_STEP_Msk [2/13]

#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)

DCB DHCSR: Step control Mask

Definition at line 1140 of file core_armv8mbl.h.

◆ DCB_DHCSR_C_STEP_Msk [3/13]

#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)

DCB DHCSR: Step control Mask

Definition at line 1939 of file core_armv8mml.h.

◆ DCB_DHCSR_C_STEP_Msk [4/13]

#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)

DCB DHCSR: Step control Mask

Definition at line 1215 of file core_cm23.h.

◆ DCB_DHCSR_C_STEP_Msk [5/13]

#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)

DCB DHCSR: Step control Mask

Definition at line 2014 of file core_cm33.h.

◆ DCB_DHCSR_C_STEP_Msk [6/13]

#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)

DCB DHCSR: Step control Mask

Definition at line 2014 of file core_cm35p.h.

◆ DCB_DHCSR_C_STEP_Msk [7/13]

#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)

DCB DHCSR: Step control Mask

Definition at line 3429 of file core_cm55.h.

◆ DCB_DHCSR_C_STEP_Msk [8/13]

#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)

DCB DHCSR: Step control Mask

Definition at line 3334 of file core_cm85.h.

◆ DCB_DHCSR_C_STEP_Msk [9/13]

#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)

DCB DHCSR: Step control Mask

Definition at line 1941 of file core_starmc1.h.

◆ DCB_DHCSR_C_STEP_Msk [10/13]

#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)

DCB DHCSR: Step control Mask

Definition at line 2875 of file core_armv81mml.h.

◆ DCB_DHCSR_C_STEP_Msk [11/13]

#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)

DCB DHCSR: Step control Mask

Definition at line 1140 of file core_armv8mbl.h.

◆ DCB_DHCSR_C_STEP_Msk [12/13]

#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)

DCB DHCSR: Step control Mask

Definition at line 1939 of file core_armv8mml.h.

◆ DCB_DHCSR_C_STEP_Msk [13/13]

#define DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)

DCB DHCSR: Step control Mask

Definition at line 2014 of file core_cm33.h.

◆ DCB_DHCSR_C_STEP_Pos [1/13]

#define DCB_DHCSR_C_STEP_Pos   2U

DCB DHCSR: Step control Position

Definition at line 2874 of file core_armv81mml.h.

◆ DCB_DHCSR_C_STEP_Pos [2/13]

#define DCB_DHCSR_C_STEP_Pos   2U

DCB DHCSR: Step control Position

Definition at line 1139 of file core_armv8mbl.h.

◆ DCB_DHCSR_C_STEP_Pos [3/13]

#define DCB_DHCSR_C_STEP_Pos   2U

DCB DHCSR: Step control Position

Definition at line 1938 of file core_armv8mml.h.

◆ DCB_DHCSR_C_STEP_Pos [4/13]

#define DCB_DHCSR_C_STEP_Pos   2U

DCB DHCSR: Step control Position

Definition at line 1214 of file core_cm23.h.

◆ DCB_DHCSR_C_STEP_Pos [5/13]

#define DCB_DHCSR_C_STEP_Pos   2U

DCB DHCSR: Step control Position

Definition at line 2013 of file core_cm33.h.

◆ DCB_DHCSR_C_STEP_Pos [6/13]

#define DCB_DHCSR_C_STEP_Pos   2U

DCB DHCSR: Step control Position

Definition at line 2013 of file core_cm35p.h.

◆ DCB_DHCSR_C_STEP_Pos [7/13]

#define DCB_DHCSR_C_STEP_Pos   2U

DCB DHCSR: Step control Position

Definition at line 3428 of file core_cm55.h.

◆ DCB_DHCSR_C_STEP_Pos [8/13]

#define DCB_DHCSR_C_STEP_Pos   2U

DCB DHCSR: Step control Position

Definition at line 3333 of file core_cm85.h.

◆ DCB_DHCSR_C_STEP_Pos [9/13]

#define DCB_DHCSR_C_STEP_Pos   2U

DCB DHCSR: Step control Position

Definition at line 1940 of file core_starmc1.h.

◆ DCB_DHCSR_C_STEP_Pos [10/13]

#define DCB_DHCSR_C_STEP_Pos   2U

DCB DHCSR: Step control Position

Definition at line 2874 of file core_armv81mml.h.

◆ DCB_DHCSR_C_STEP_Pos [11/13]

#define DCB_DHCSR_C_STEP_Pos   2U

DCB DHCSR: Step control Position

Definition at line 1139 of file core_armv8mbl.h.

◆ DCB_DHCSR_C_STEP_Pos [12/13]

#define DCB_DHCSR_C_STEP_Pos   2U

DCB DHCSR: Step control Position

Definition at line 1938 of file core_armv8mml.h.

◆ DCB_DHCSR_C_STEP_Pos [13/13]

#define DCB_DHCSR_C_STEP_Pos   2U

DCB DHCSR: Step control Position

Definition at line 2013 of file core_cm33.h.

◆ DCB_DHCSR_DBGKEY_Msk [1/13]

#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)

DCB DHCSR: Debug key Mask

Definition at line 2830 of file core_armv81mml.h.

◆ DCB_DHCSR_DBGKEY_Msk [2/13]

#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)

DCB DHCSR: Debug key Mask

Definition at line 1110 of file core_armv8mbl.h.

◆ DCB_DHCSR_DBGKEY_Msk [3/13]

#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)

DCB DHCSR: Debug key Mask

Definition at line 1906 of file core_armv8mml.h.

◆ DCB_DHCSR_DBGKEY_Msk [4/13]

#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)

DCB DHCSR: Debug key Mask

Definition at line 1185 of file core_cm23.h.

◆ DCB_DHCSR_DBGKEY_Msk [5/13]

#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)

DCB DHCSR: Debug key Mask

Definition at line 1981 of file core_cm33.h.

◆ DCB_DHCSR_DBGKEY_Msk [6/13]

#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)

DCB DHCSR: Debug key Mask

Definition at line 1981 of file core_cm35p.h.

◆ DCB_DHCSR_DBGKEY_Msk [7/13]

#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)

DCB DHCSR: Debug key Mask

Definition at line 3384 of file core_cm55.h.

◆ DCB_DHCSR_DBGKEY_Msk [8/13]

#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)

DCB DHCSR: Debug key Mask

Definition at line 3289 of file core_cm85.h.

◆ DCB_DHCSR_DBGKEY_Msk [9/13]

#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)

DCB DHCSR: Debug key Mask

Definition at line 1908 of file core_starmc1.h.

◆ DCB_DHCSR_DBGKEY_Msk [10/13]

#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)

DCB DHCSR: Debug key Mask

Definition at line 2830 of file core_armv81mml.h.

◆ DCB_DHCSR_DBGKEY_Msk [11/13]

#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)

DCB DHCSR: Debug key Mask

Definition at line 1110 of file core_armv8mbl.h.

◆ DCB_DHCSR_DBGKEY_Msk [12/13]

#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)

DCB DHCSR: Debug key Mask

Definition at line 1906 of file core_armv8mml.h.

◆ DCB_DHCSR_DBGKEY_Msk [13/13]

#define DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)

DCB DHCSR: Debug key Mask

Definition at line 1981 of file core_cm33.h.

◆ DCB_DHCSR_DBGKEY_Pos [1/13]

#define DCB_DHCSR_DBGKEY_Pos   16U

DCB DHCSR: Debug key Position

Definition at line 2829 of file core_armv81mml.h.

◆ DCB_DHCSR_DBGKEY_Pos [2/13]

#define DCB_DHCSR_DBGKEY_Pos   16U

DCB DHCSR: Debug key Position

Definition at line 1109 of file core_armv8mbl.h.

◆ DCB_DHCSR_DBGKEY_Pos [3/13]

#define DCB_DHCSR_DBGKEY_Pos   16U

DCB DHCSR: Debug key Position

Definition at line 1905 of file core_armv8mml.h.

◆ DCB_DHCSR_DBGKEY_Pos [4/13]

#define DCB_DHCSR_DBGKEY_Pos   16U

DCB DHCSR: Debug key Position

Definition at line 1184 of file core_cm23.h.

◆ DCB_DHCSR_DBGKEY_Pos [5/13]

#define DCB_DHCSR_DBGKEY_Pos   16U

DCB DHCSR: Debug key Position

Definition at line 1980 of file core_cm33.h.

◆ DCB_DHCSR_DBGKEY_Pos [6/13]

#define DCB_DHCSR_DBGKEY_Pos   16U

DCB DHCSR: Debug key Position

Definition at line 1980 of file core_cm35p.h.

◆ DCB_DHCSR_DBGKEY_Pos [7/13]

#define DCB_DHCSR_DBGKEY_Pos   16U

DCB DHCSR: Debug key Position

Definition at line 3383 of file core_cm55.h.

◆ DCB_DHCSR_DBGKEY_Pos [8/13]

#define DCB_DHCSR_DBGKEY_Pos   16U

DCB DHCSR: Debug key Position

Definition at line 3288 of file core_cm85.h.

◆ DCB_DHCSR_DBGKEY_Pos [9/13]

#define DCB_DHCSR_DBGKEY_Pos   16U

DCB DHCSR: Debug key Position

Definition at line 1907 of file core_starmc1.h.

◆ DCB_DHCSR_DBGKEY_Pos [10/13]

#define DCB_DHCSR_DBGKEY_Pos   16U

DCB DHCSR: Debug key Position

Definition at line 2829 of file core_armv81mml.h.

◆ DCB_DHCSR_DBGKEY_Pos [11/13]

#define DCB_DHCSR_DBGKEY_Pos   16U

DCB DHCSR: Debug key Position

Definition at line 1109 of file core_armv8mbl.h.

◆ DCB_DHCSR_DBGKEY_Pos [12/13]

#define DCB_DHCSR_DBGKEY_Pos   16U

DCB DHCSR: Debug key Position

Definition at line 1905 of file core_armv8mml.h.

◆ DCB_DHCSR_DBGKEY_Pos [13/13]

#define DCB_DHCSR_DBGKEY_Pos   16U

DCB DHCSR: Debug key Position

Definition at line 1980 of file core_cm33.h.

◆ DCB_DHCSR_S_FPD_Msk [1/4]

#define DCB_DHCSR_S_FPD_Msk   (0x1UL << DCB_DHCSR_S_FPD_Pos)

DCB DHCSR: Floating-point registers Debuggable Mask

Definition at line 2842 of file core_armv81mml.h.

◆ DCB_DHCSR_S_FPD_Msk [2/4]

#define DCB_DHCSR_S_FPD_Msk   (0x1UL << DCB_DHCSR_S_FPD_Pos)

DCB DHCSR: Floating-point registers Debuggable Mask

Definition at line 3396 of file core_cm55.h.

◆ DCB_DHCSR_S_FPD_Msk [3/4]

#define DCB_DHCSR_S_FPD_Msk   (0x1UL << DCB_DHCSR_S_FPD_Pos)

DCB DHCSR: Floating-point registers Debuggable Mask

Definition at line 3301 of file core_cm85.h.

◆ DCB_DHCSR_S_FPD_Msk [4/4]

#define DCB_DHCSR_S_FPD_Msk   (0x1UL << DCB_DHCSR_S_FPD_Pos)

DCB DHCSR: Floating-point registers Debuggable Mask

Definition at line 2842 of file core_armv81mml.h.

◆ DCB_DHCSR_S_FPD_Pos [1/4]

#define DCB_DHCSR_S_FPD_Pos   23U

DCB DHCSR: Floating-point registers Debuggable Position

Definition at line 2841 of file core_armv81mml.h.

◆ DCB_DHCSR_S_FPD_Pos [2/4]

#define DCB_DHCSR_S_FPD_Pos   23U

DCB DHCSR: Floating-point registers Debuggable Position

Definition at line 3395 of file core_cm55.h.

◆ DCB_DHCSR_S_FPD_Pos [3/4]

#define DCB_DHCSR_S_FPD_Pos   23U

DCB DHCSR: Floating-point registers Debuggable Position

Definition at line 3300 of file core_cm85.h.

◆ DCB_DHCSR_S_FPD_Pos [4/4]

#define DCB_DHCSR_S_FPD_Pos   23U

DCB DHCSR: Floating-point registers Debuggable Position

Definition at line 2841 of file core_armv81mml.h.

◆ DCB_DHCSR_S_HALT_Msk [1/13]

#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)

DCB DHCSR: Halted status Mask

Definition at line 2860 of file core_armv81mml.h.

◆ DCB_DHCSR_S_HALT_Msk [2/13]

#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)

DCB DHCSR: Halted status Mask

Definition at line 1131 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_HALT_Msk [3/13]

#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)

DCB DHCSR: Halted status Mask

Definition at line 1927 of file core_armv8mml.h.

◆ DCB_DHCSR_S_HALT_Msk [4/13]

#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)

DCB DHCSR: Halted status Mask

Definition at line 1206 of file core_cm23.h.

◆ DCB_DHCSR_S_HALT_Msk [5/13]

#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)

DCB DHCSR: Halted status Mask

Definition at line 2002 of file core_cm33.h.

◆ DCB_DHCSR_S_HALT_Msk [6/13]

#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)

DCB DHCSR: Halted status Mask

Definition at line 2002 of file core_cm35p.h.

◆ DCB_DHCSR_S_HALT_Msk [7/13]

#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)

DCB DHCSR: Halted status Mask

Definition at line 3414 of file core_cm55.h.

◆ DCB_DHCSR_S_HALT_Msk [8/13]

#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)

DCB DHCSR: Halted status Mask

Definition at line 3319 of file core_cm85.h.

◆ DCB_DHCSR_S_HALT_Msk [9/13]

#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)

DCB DHCSR: Halted status Mask

Definition at line 1929 of file core_starmc1.h.

◆ DCB_DHCSR_S_HALT_Msk [10/13]

#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)

DCB DHCSR: Halted status Mask

Definition at line 2860 of file core_armv81mml.h.

◆ DCB_DHCSR_S_HALT_Msk [11/13]

#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)

DCB DHCSR: Halted status Mask

Definition at line 1131 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_HALT_Msk [12/13]

#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)

DCB DHCSR: Halted status Mask

Definition at line 1927 of file core_armv8mml.h.

◆ DCB_DHCSR_S_HALT_Msk [13/13]

#define DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)

DCB DHCSR: Halted status Mask

Definition at line 2002 of file core_cm33.h.

◆ DCB_DHCSR_S_HALT_Pos [1/13]

#define DCB_DHCSR_S_HALT_Pos   17U

DCB DHCSR: Halted status Position

Definition at line 2859 of file core_armv81mml.h.

◆ DCB_DHCSR_S_HALT_Pos [2/13]

#define DCB_DHCSR_S_HALT_Pos   17U

DCB DHCSR: Halted status Position

Definition at line 1130 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_HALT_Pos [3/13]

#define DCB_DHCSR_S_HALT_Pos   17U

DCB DHCSR: Halted status Position

Definition at line 1926 of file core_armv8mml.h.

◆ DCB_DHCSR_S_HALT_Pos [4/13]

#define DCB_DHCSR_S_HALT_Pos   17U

DCB DHCSR: Halted status Position

Definition at line 1205 of file core_cm23.h.

◆ DCB_DHCSR_S_HALT_Pos [5/13]

#define DCB_DHCSR_S_HALT_Pos   17U

DCB DHCSR: Halted status Position

Definition at line 2001 of file core_cm33.h.

◆ DCB_DHCSR_S_HALT_Pos [6/13]

#define DCB_DHCSR_S_HALT_Pos   17U

DCB DHCSR: Halted status Position

Definition at line 2001 of file core_cm35p.h.

◆ DCB_DHCSR_S_HALT_Pos [7/13]

#define DCB_DHCSR_S_HALT_Pos   17U

DCB DHCSR: Halted status Position

Definition at line 3413 of file core_cm55.h.

◆ DCB_DHCSR_S_HALT_Pos [8/13]

#define DCB_DHCSR_S_HALT_Pos   17U

DCB DHCSR: Halted status Position

Definition at line 3318 of file core_cm85.h.

◆ DCB_DHCSR_S_HALT_Pos [9/13]

#define DCB_DHCSR_S_HALT_Pos   17U

DCB DHCSR: Halted status Position

Definition at line 1928 of file core_starmc1.h.

◆ DCB_DHCSR_S_HALT_Pos [10/13]

#define DCB_DHCSR_S_HALT_Pos   17U

DCB DHCSR: Halted status Position

Definition at line 2859 of file core_armv81mml.h.

◆ DCB_DHCSR_S_HALT_Pos [11/13]

#define DCB_DHCSR_S_HALT_Pos   17U

DCB DHCSR: Halted status Position

Definition at line 1130 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_HALT_Pos [12/13]

#define DCB_DHCSR_S_HALT_Pos   17U

DCB DHCSR: Halted status Position

Definition at line 1926 of file core_armv8mml.h.

◆ DCB_DHCSR_S_HALT_Pos [13/13]

#define DCB_DHCSR_S_HALT_Pos   17U

DCB DHCSR: Halted status Position

Definition at line 2001 of file core_cm33.h.

◆ DCB_DHCSR_S_LOCKUP_Msk [1/13]

#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)

DCB DHCSR: Lockup status Mask

Definition at line 2854 of file core_armv81mml.h.

◆ DCB_DHCSR_S_LOCKUP_Msk [2/13]

#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)

DCB DHCSR: Lockup status Mask

Definition at line 1125 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_LOCKUP_Msk [3/13]

#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)

DCB DHCSR: Lockup status Mask

Definition at line 1921 of file core_armv8mml.h.

◆ DCB_DHCSR_S_LOCKUP_Msk [4/13]

#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)

DCB DHCSR: Lockup status Mask

Definition at line 1200 of file core_cm23.h.

◆ DCB_DHCSR_S_LOCKUP_Msk [5/13]

#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)

DCB DHCSR: Lockup status Mask

Definition at line 1996 of file core_cm33.h.

◆ DCB_DHCSR_S_LOCKUP_Msk [6/13]

#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)

DCB DHCSR: Lockup status Mask

Definition at line 1996 of file core_cm35p.h.

◆ DCB_DHCSR_S_LOCKUP_Msk [7/13]

#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)

DCB DHCSR: Lockup status Mask

Definition at line 3408 of file core_cm55.h.

◆ DCB_DHCSR_S_LOCKUP_Msk [8/13]

#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)

DCB DHCSR: Lockup status Mask

Definition at line 3313 of file core_cm85.h.

◆ DCB_DHCSR_S_LOCKUP_Msk [9/13]

#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)

DCB DHCSR: Lockup status Mask

Definition at line 1923 of file core_starmc1.h.

◆ DCB_DHCSR_S_LOCKUP_Msk [10/13]

#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)

DCB DHCSR: Lockup status Mask

Definition at line 2854 of file core_armv81mml.h.

◆ DCB_DHCSR_S_LOCKUP_Msk [11/13]

#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)

DCB DHCSR: Lockup status Mask

Definition at line 1125 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_LOCKUP_Msk [12/13]

#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)

DCB DHCSR: Lockup status Mask

Definition at line 1921 of file core_armv8mml.h.

◆ DCB_DHCSR_S_LOCKUP_Msk [13/13]

#define DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)

DCB DHCSR: Lockup status Mask

Definition at line 1996 of file core_cm33.h.

◆ DCB_DHCSR_S_LOCKUP_Pos [1/13]

#define DCB_DHCSR_S_LOCKUP_Pos   19U

DCB DHCSR: Lockup status Position

Definition at line 2853 of file core_armv81mml.h.

◆ DCB_DHCSR_S_LOCKUP_Pos [2/13]

#define DCB_DHCSR_S_LOCKUP_Pos   19U

DCB DHCSR: Lockup status Position

Definition at line 1124 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_LOCKUP_Pos [3/13]

#define DCB_DHCSR_S_LOCKUP_Pos   19U

DCB DHCSR: Lockup status Position

Definition at line 1920 of file core_armv8mml.h.

◆ DCB_DHCSR_S_LOCKUP_Pos [4/13]

#define DCB_DHCSR_S_LOCKUP_Pos   19U

DCB DHCSR: Lockup status Position

Definition at line 1199 of file core_cm23.h.

◆ DCB_DHCSR_S_LOCKUP_Pos [5/13]

#define DCB_DHCSR_S_LOCKUP_Pos   19U

DCB DHCSR: Lockup status Position

Definition at line 1995 of file core_cm33.h.

◆ DCB_DHCSR_S_LOCKUP_Pos [6/13]

#define DCB_DHCSR_S_LOCKUP_Pos   19U

DCB DHCSR: Lockup status Position

Definition at line 1995 of file core_cm35p.h.

◆ DCB_DHCSR_S_LOCKUP_Pos [7/13]

#define DCB_DHCSR_S_LOCKUP_Pos   19U

DCB DHCSR: Lockup status Position

Definition at line 3407 of file core_cm55.h.

◆ DCB_DHCSR_S_LOCKUP_Pos [8/13]

#define DCB_DHCSR_S_LOCKUP_Pos   19U

DCB DHCSR: Lockup status Position

Definition at line 3312 of file core_cm85.h.

◆ DCB_DHCSR_S_LOCKUP_Pos [9/13]

#define DCB_DHCSR_S_LOCKUP_Pos   19U

DCB DHCSR: Lockup status Position

Definition at line 1922 of file core_starmc1.h.

◆ DCB_DHCSR_S_LOCKUP_Pos [10/13]

#define DCB_DHCSR_S_LOCKUP_Pos   19U

DCB DHCSR: Lockup status Position

Definition at line 2853 of file core_armv81mml.h.

◆ DCB_DHCSR_S_LOCKUP_Pos [11/13]

#define DCB_DHCSR_S_LOCKUP_Pos   19U

DCB DHCSR: Lockup status Position

Definition at line 1124 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_LOCKUP_Pos [12/13]

#define DCB_DHCSR_S_LOCKUP_Pos   19U

DCB DHCSR: Lockup status Position

Definition at line 1920 of file core_armv8mml.h.

◆ DCB_DHCSR_S_LOCKUP_Pos [13/13]

#define DCB_DHCSR_S_LOCKUP_Pos   19U

DCB DHCSR: Lockup status Position

Definition at line 1995 of file core_cm33.h.

◆ DCB_DHCSR_S_NSUIDE_Msk [1/4]

#define DCB_DHCSR_S_NSUIDE_Msk   (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)

DCB DHCSR: Non-secure unprivileged halting debug enabled Mask

Definition at line 2848 of file core_armv81mml.h.

◆ DCB_DHCSR_S_NSUIDE_Msk [2/4]

#define DCB_DHCSR_S_NSUIDE_Msk   (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)

DCB DHCSR: Non-secure unprivileged halting debug enabled Mask

Definition at line 3402 of file core_cm55.h.

◆ DCB_DHCSR_S_NSUIDE_Msk [3/4]

#define DCB_DHCSR_S_NSUIDE_Msk   (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)

DCB DHCSR: Non-secure unprivileged halting debug enabled Mask

Definition at line 3307 of file core_cm85.h.

◆ DCB_DHCSR_S_NSUIDE_Msk [4/4]

#define DCB_DHCSR_S_NSUIDE_Msk   (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)

DCB DHCSR: Non-secure unprivileged halting debug enabled Mask

Definition at line 2848 of file core_armv81mml.h.

◆ DCB_DHCSR_S_NSUIDE_Pos [1/4]

#define DCB_DHCSR_S_NSUIDE_Pos   21U

DCB DHCSR: Non-secure unprivileged halting debug enabled Position

Definition at line 2847 of file core_armv81mml.h.

◆ DCB_DHCSR_S_NSUIDE_Pos [2/4]

#define DCB_DHCSR_S_NSUIDE_Pos   21U

DCB DHCSR: Non-secure unprivileged halting debug enabled Position

Definition at line 3401 of file core_cm55.h.

◆ DCB_DHCSR_S_NSUIDE_Pos [3/4]

#define DCB_DHCSR_S_NSUIDE_Pos   21U

DCB DHCSR: Non-secure unprivileged halting debug enabled Position

Definition at line 3306 of file core_cm85.h.

◆ DCB_DHCSR_S_NSUIDE_Pos [4/4]

#define DCB_DHCSR_S_NSUIDE_Pos   21U

DCB DHCSR: Non-secure unprivileged halting debug enabled Position

Definition at line 2847 of file core_armv81mml.h.

◆ DCB_DHCSR_S_REGRDY_Msk [1/13]

#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)

DCB DHCSR: Register ready status Mask

Definition at line 2863 of file core_armv81mml.h.

◆ DCB_DHCSR_S_REGRDY_Msk [2/13]

#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)

DCB DHCSR: Register ready status Mask

Definition at line 1134 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_REGRDY_Msk [3/13]

#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)

DCB DHCSR: Register ready status Mask

Definition at line 1930 of file core_armv8mml.h.

◆ DCB_DHCSR_S_REGRDY_Msk [4/13]

#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)

DCB DHCSR: Register ready status Mask

Definition at line 1209 of file core_cm23.h.

◆ DCB_DHCSR_S_REGRDY_Msk [5/13]

#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)

DCB DHCSR: Register ready status Mask

Definition at line 2005 of file core_cm33.h.

◆ DCB_DHCSR_S_REGRDY_Msk [6/13]

#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)

DCB DHCSR: Register ready status Mask

Definition at line 2005 of file core_cm35p.h.

◆ DCB_DHCSR_S_REGRDY_Msk [7/13]

#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)

DCB DHCSR: Register ready status Mask

Definition at line 3417 of file core_cm55.h.

◆ DCB_DHCSR_S_REGRDY_Msk [8/13]

#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)

DCB DHCSR: Register ready status Mask

Definition at line 3322 of file core_cm85.h.

◆ DCB_DHCSR_S_REGRDY_Msk [9/13]

#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)

DCB DHCSR: Register ready status Mask

Definition at line 1932 of file core_starmc1.h.

◆ DCB_DHCSR_S_REGRDY_Msk [10/13]

#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)

DCB DHCSR: Register ready status Mask

Definition at line 2863 of file core_armv81mml.h.

◆ DCB_DHCSR_S_REGRDY_Msk [11/13]

#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)

DCB DHCSR: Register ready status Mask

Definition at line 1134 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_REGRDY_Msk [12/13]

#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)

DCB DHCSR: Register ready status Mask

Definition at line 1930 of file core_armv8mml.h.

◆ DCB_DHCSR_S_REGRDY_Msk [13/13]

#define DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)

DCB DHCSR: Register ready status Mask

Definition at line 2005 of file core_cm33.h.

◆ DCB_DHCSR_S_REGRDY_Pos [1/13]

#define DCB_DHCSR_S_REGRDY_Pos   16U

DCB DHCSR: Register ready status Position

Definition at line 2862 of file core_armv81mml.h.

◆ DCB_DHCSR_S_REGRDY_Pos [2/13]

#define DCB_DHCSR_S_REGRDY_Pos   16U

DCB DHCSR: Register ready status Position

Definition at line 1133 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_REGRDY_Pos [3/13]

#define DCB_DHCSR_S_REGRDY_Pos   16U

DCB DHCSR: Register ready status Position

Definition at line 1929 of file core_armv8mml.h.

◆ DCB_DHCSR_S_REGRDY_Pos [4/13]

#define DCB_DHCSR_S_REGRDY_Pos   16U

DCB DHCSR: Register ready status Position

Definition at line 1208 of file core_cm23.h.

◆ DCB_DHCSR_S_REGRDY_Pos [5/13]

#define DCB_DHCSR_S_REGRDY_Pos   16U

DCB DHCSR: Register ready status Position

Definition at line 2004 of file core_cm33.h.

◆ DCB_DHCSR_S_REGRDY_Pos [6/13]

#define DCB_DHCSR_S_REGRDY_Pos   16U

DCB DHCSR: Register ready status Position

Definition at line 2004 of file core_cm35p.h.

◆ DCB_DHCSR_S_REGRDY_Pos [7/13]

#define DCB_DHCSR_S_REGRDY_Pos   16U

DCB DHCSR: Register ready status Position

Definition at line 3416 of file core_cm55.h.

◆ DCB_DHCSR_S_REGRDY_Pos [8/13]

#define DCB_DHCSR_S_REGRDY_Pos   16U

DCB DHCSR: Register ready status Position

Definition at line 3321 of file core_cm85.h.

◆ DCB_DHCSR_S_REGRDY_Pos [9/13]

#define DCB_DHCSR_S_REGRDY_Pos   16U

DCB DHCSR: Register ready status Position

Definition at line 1931 of file core_starmc1.h.

◆ DCB_DHCSR_S_REGRDY_Pos [10/13]

#define DCB_DHCSR_S_REGRDY_Pos   16U

DCB DHCSR: Register ready status Position

Definition at line 2862 of file core_armv81mml.h.

◆ DCB_DHCSR_S_REGRDY_Pos [11/13]

#define DCB_DHCSR_S_REGRDY_Pos   16U

DCB DHCSR: Register ready status Position

Definition at line 1133 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_REGRDY_Pos [12/13]

#define DCB_DHCSR_S_REGRDY_Pos   16U

DCB DHCSR: Register ready status Position

Definition at line 1929 of file core_armv8mml.h.

◆ DCB_DHCSR_S_REGRDY_Pos [13/13]

#define DCB_DHCSR_S_REGRDY_Pos   16U

DCB DHCSR: Register ready status Position

Definition at line 2004 of file core_cm33.h.

◆ DCB_DHCSR_S_RESET_ST_Msk [1/13]

#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)

DCB DHCSR: Reset sticky status Mask

Definition at line 2836 of file core_armv81mml.h.

◆ DCB_DHCSR_S_RESET_ST_Msk [2/13]

#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)

DCB DHCSR: Reset sticky status Mask

Definition at line 1116 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_RESET_ST_Msk [3/13]

#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)

DCB DHCSR: Reset sticky status Mask

Definition at line 1912 of file core_armv8mml.h.

◆ DCB_DHCSR_S_RESET_ST_Msk [4/13]

#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)

DCB DHCSR: Reset sticky status Mask

Definition at line 1191 of file core_cm23.h.

◆ DCB_DHCSR_S_RESET_ST_Msk [5/13]

#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)

DCB DHCSR: Reset sticky status Mask

Definition at line 1987 of file core_cm33.h.

◆ DCB_DHCSR_S_RESET_ST_Msk [6/13]

#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)

DCB DHCSR: Reset sticky status Mask

Definition at line 1987 of file core_cm35p.h.

◆ DCB_DHCSR_S_RESET_ST_Msk [7/13]

#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)

DCB DHCSR: Reset sticky status Mask

Definition at line 3390 of file core_cm55.h.

◆ DCB_DHCSR_S_RESET_ST_Msk [8/13]

#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)

DCB DHCSR: Reset sticky status Mask

Definition at line 3295 of file core_cm85.h.

◆ DCB_DHCSR_S_RESET_ST_Msk [9/13]

#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)

DCB DHCSR: Reset sticky status Mask

Definition at line 1914 of file core_starmc1.h.

◆ DCB_DHCSR_S_RESET_ST_Msk [10/13]

#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)

DCB DHCSR: Reset sticky status Mask

Definition at line 2836 of file core_armv81mml.h.

◆ DCB_DHCSR_S_RESET_ST_Msk [11/13]

#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)

DCB DHCSR: Reset sticky status Mask

Definition at line 1116 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_RESET_ST_Msk [12/13]

#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)

DCB DHCSR: Reset sticky status Mask

Definition at line 1912 of file core_armv8mml.h.

◆ DCB_DHCSR_S_RESET_ST_Msk [13/13]

#define DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)

DCB DHCSR: Reset sticky status Mask

Definition at line 1987 of file core_cm33.h.

◆ DCB_DHCSR_S_RESET_ST_Pos [1/13]

#define DCB_DHCSR_S_RESET_ST_Pos   25U

DCB DHCSR: Reset sticky status Position

Definition at line 2835 of file core_armv81mml.h.

◆ DCB_DHCSR_S_RESET_ST_Pos [2/13]

#define DCB_DHCSR_S_RESET_ST_Pos   25U

DCB DHCSR: Reset sticky status Position

Definition at line 1115 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_RESET_ST_Pos [3/13]

#define DCB_DHCSR_S_RESET_ST_Pos   25U

DCB DHCSR: Reset sticky status Position

Definition at line 1911 of file core_armv8mml.h.

◆ DCB_DHCSR_S_RESET_ST_Pos [4/13]

#define DCB_DHCSR_S_RESET_ST_Pos   25U

DCB DHCSR: Reset sticky status Position

Definition at line 1190 of file core_cm23.h.

◆ DCB_DHCSR_S_RESET_ST_Pos [5/13]

#define DCB_DHCSR_S_RESET_ST_Pos   25U

DCB DHCSR: Reset sticky status Position

Definition at line 1986 of file core_cm33.h.

◆ DCB_DHCSR_S_RESET_ST_Pos [6/13]

#define DCB_DHCSR_S_RESET_ST_Pos   25U

DCB DHCSR: Reset sticky status Position

Definition at line 1986 of file core_cm35p.h.

◆ DCB_DHCSR_S_RESET_ST_Pos [7/13]

#define DCB_DHCSR_S_RESET_ST_Pos   25U

DCB DHCSR: Reset sticky status Position

Definition at line 3389 of file core_cm55.h.

◆ DCB_DHCSR_S_RESET_ST_Pos [8/13]

#define DCB_DHCSR_S_RESET_ST_Pos   25U

DCB DHCSR: Reset sticky status Position

Definition at line 3294 of file core_cm85.h.

◆ DCB_DHCSR_S_RESET_ST_Pos [9/13]

#define DCB_DHCSR_S_RESET_ST_Pos   25U

DCB DHCSR: Reset sticky status Position

Definition at line 1913 of file core_starmc1.h.

◆ DCB_DHCSR_S_RESET_ST_Pos [10/13]

#define DCB_DHCSR_S_RESET_ST_Pos   25U

DCB DHCSR: Reset sticky status Position

Definition at line 2835 of file core_armv81mml.h.

◆ DCB_DHCSR_S_RESET_ST_Pos [11/13]

#define DCB_DHCSR_S_RESET_ST_Pos   25U

DCB DHCSR: Reset sticky status Position

Definition at line 1115 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_RESET_ST_Pos [12/13]

#define DCB_DHCSR_S_RESET_ST_Pos   25U

DCB DHCSR: Reset sticky status Position

Definition at line 1911 of file core_armv8mml.h.

◆ DCB_DHCSR_S_RESET_ST_Pos [13/13]

#define DCB_DHCSR_S_RESET_ST_Pos   25U

DCB DHCSR: Reset sticky status Position

Definition at line 1986 of file core_cm33.h.

◆ DCB_DHCSR_S_RESTART_ST_Msk [1/13]

#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)

DCB DHCSR: Restart sticky status Mask

Definition at line 2833 of file core_armv81mml.h.

◆ DCB_DHCSR_S_RESTART_ST_Msk [2/13]

#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)

DCB DHCSR: Restart sticky status Mask

Definition at line 1113 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_RESTART_ST_Msk [3/13]

#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)

DCB DHCSR: Restart sticky status Mask

Definition at line 1909 of file core_armv8mml.h.

◆ DCB_DHCSR_S_RESTART_ST_Msk [4/13]

#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)

DCB DHCSR: Restart sticky status Mask

Definition at line 1188 of file core_cm23.h.

◆ DCB_DHCSR_S_RESTART_ST_Msk [5/13]

#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)

DCB DHCSR: Restart sticky status Mask

Definition at line 1984 of file core_cm33.h.

◆ DCB_DHCSR_S_RESTART_ST_Msk [6/13]

#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)

DCB DHCSR: Restart sticky status Mask

Definition at line 1984 of file core_cm35p.h.

◆ DCB_DHCSR_S_RESTART_ST_Msk [7/13]

#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)

DCB DHCSR: Restart sticky status Mask

Definition at line 3387 of file core_cm55.h.

◆ DCB_DHCSR_S_RESTART_ST_Msk [8/13]

#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)

DCB DHCSR: Restart sticky status Mask

Definition at line 3292 of file core_cm85.h.

◆ DCB_DHCSR_S_RESTART_ST_Msk [9/13]

#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)

DCB DHCSR: Restart sticky status Mask

Definition at line 1911 of file core_starmc1.h.

◆ DCB_DHCSR_S_RESTART_ST_Msk [10/13]

#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)

DCB DHCSR: Restart sticky status Mask

Definition at line 2833 of file core_armv81mml.h.

◆ DCB_DHCSR_S_RESTART_ST_Msk [11/13]

#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)

DCB DHCSR: Restart sticky status Mask

Definition at line 1113 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_RESTART_ST_Msk [12/13]

#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)

DCB DHCSR: Restart sticky status Mask

Definition at line 1909 of file core_armv8mml.h.

◆ DCB_DHCSR_S_RESTART_ST_Msk [13/13]

#define DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)

DCB DHCSR: Restart sticky status Mask

Definition at line 1984 of file core_cm33.h.

◆ DCB_DHCSR_S_RESTART_ST_Pos [1/13]

#define DCB_DHCSR_S_RESTART_ST_Pos   26U

DCB DHCSR: Restart sticky status Position

Definition at line 2832 of file core_armv81mml.h.

◆ DCB_DHCSR_S_RESTART_ST_Pos [2/13]

#define DCB_DHCSR_S_RESTART_ST_Pos   26U

DCB DHCSR: Restart sticky status Position

Definition at line 1112 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_RESTART_ST_Pos [3/13]

#define DCB_DHCSR_S_RESTART_ST_Pos   26U

DCB DHCSR: Restart sticky status Position

Definition at line 1908 of file core_armv8mml.h.

◆ DCB_DHCSR_S_RESTART_ST_Pos [4/13]

#define DCB_DHCSR_S_RESTART_ST_Pos   26U

DCB DHCSR: Restart sticky status Position

Definition at line 1187 of file core_cm23.h.

◆ DCB_DHCSR_S_RESTART_ST_Pos [5/13]

#define DCB_DHCSR_S_RESTART_ST_Pos   26U

DCB DHCSR: Restart sticky status Position

Definition at line 1983 of file core_cm33.h.

◆ DCB_DHCSR_S_RESTART_ST_Pos [6/13]

#define DCB_DHCSR_S_RESTART_ST_Pos   26U

DCB DHCSR: Restart sticky status Position

Definition at line 1983 of file core_cm35p.h.

◆ DCB_DHCSR_S_RESTART_ST_Pos [7/13]

#define DCB_DHCSR_S_RESTART_ST_Pos   26U

DCB DHCSR: Restart sticky status Position

Definition at line 3386 of file core_cm55.h.

◆ DCB_DHCSR_S_RESTART_ST_Pos [8/13]

#define DCB_DHCSR_S_RESTART_ST_Pos   26U

DCB DHCSR: Restart sticky status Position

Definition at line 3291 of file core_cm85.h.

◆ DCB_DHCSR_S_RESTART_ST_Pos [9/13]

#define DCB_DHCSR_S_RESTART_ST_Pos   26U

DCB DHCSR: Restart sticky status Position

Definition at line 1910 of file core_starmc1.h.

◆ DCB_DHCSR_S_RESTART_ST_Pos [10/13]

#define DCB_DHCSR_S_RESTART_ST_Pos   26U

DCB DHCSR: Restart sticky status Position

Definition at line 2832 of file core_armv81mml.h.

◆ DCB_DHCSR_S_RESTART_ST_Pos [11/13]

#define DCB_DHCSR_S_RESTART_ST_Pos   26U

DCB DHCSR: Restart sticky status Position

Definition at line 1112 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_RESTART_ST_Pos [12/13]

#define DCB_DHCSR_S_RESTART_ST_Pos   26U

DCB DHCSR: Restart sticky status Position

Definition at line 1908 of file core_armv8mml.h.

◆ DCB_DHCSR_S_RESTART_ST_Pos [13/13]

#define DCB_DHCSR_S_RESTART_ST_Pos   26U

DCB DHCSR: Restart sticky status Position

Definition at line 1983 of file core_cm33.h.

◆ DCB_DHCSR_S_RETIRE_ST_Msk [1/13]

#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)

DCB DHCSR: Retire sticky status Mask

Definition at line 2839 of file core_armv81mml.h.

◆ DCB_DHCSR_S_RETIRE_ST_Msk [2/13]

#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)

DCB DHCSR: Retire sticky status Mask

Definition at line 1119 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_RETIRE_ST_Msk [3/13]

#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)

DCB DHCSR: Retire sticky status Mask

Definition at line 1915 of file core_armv8mml.h.

◆ DCB_DHCSR_S_RETIRE_ST_Msk [4/13]

#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)

DCB DHCSR: Retire sticky status Mask

Definition at line 1194 of file core_cm23.h.

◆ DCB_DHCSR_S_RETIRE_ST_Msk [5/13]

#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)

DCB DHCSR: Retire sticky status Mask

Definition at line 1990 of file core_cm33.h.

◆ DCB_DHCSR_S_RETIRE_ST_Msk [6/13]

#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)

DCB DHCSR: Retire sticky status Mask

Definition at line 1990 of file core_cm35p.h.

◆ DCB_DHCSR_S_RETIRE_ST_Msk [7/13]

#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)

DCB DHCSR: Retire sticky status Mask

Definition at line 3393 of file core_cm55.h.

◆ DCB_DHCSR_S_RETIRE_ST_Msk [8/13]

#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)

DCB DHCSR: Retire sticky status Mask

Definition at line 3298 of file core_cm85.h.

◆ DCB_DHCSR_S_RETIRE_ST_Msk [9/13]

#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)

DCB DHCSR: Retire sticky status Mask

Definition at line 1917 of file core_starmc1.h.

◆ DCB_DHCSR_S_RETIRE_ST_Msk [10/13]

#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)

DCB DHCSR: Retire sticky status Mask

Definition at line 2839 of file core_armv81mml.h.

◆ DCB_DHCSR_S_RETIRE_ST_Msk [11/13]

#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)

DCB DHCSR: Retire sticky status Mask

Definition at line 1119 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_RETIRE_ST_Msk [12/13]

#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)

DCB DHCSR: Retire sticky status Mask

Definition at line 1915 of file core_armv8mml.h.

◆ DCB_DHCSR_S_RETIRE_ST_Msk [13/13]

#define DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)

DCB DHCSR: Retire sticky status Mask

Definition at line 1990 of file core_cm33.h.

◆ DCB_DHCSR_S_RETIRE_ST_Pos [1/13]

#define DCB_DHCSR_S_RETIRE_ST_Pos   24U

DCB DHCSR: Retire sticky status Position

Definition at line 2838 of file core_armv81mml.h.

◆ DCB_DHCSR_S_RETIRE_ST_Pos [2/13]

#define DCB_DHCSR_S_RETIRE_ST_Pos   24U

DCB DHCSR: Retire sticky status Position

Definition at line 1118 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_RETIRE_ST_Pos [3/13]

#define DCB_DHCSR_S_RETIRE_ST_Pos   24U

DCB DHCSR: Retire sticky status Position

Definition at line 1914 of file core_armv8mml.h.

◆ DCB_DHCSR_S_RETIRE_ST_Pos [4/13]

#define DCB_DHCSR_S_RETIRE_ST_Pos   24U

DCB DHCSR: Retire sticky status Position

Definition at line 1193 of file core_cm23.h.

◆ DCB_DHCSR_S_RETIRE_ST_Pos [5/13]

#define DCB_DHCSR_S_RETIRE_ST_Pos   24U

DCB DHCSR: Retire sticky status Position

Definition at line 1989 of file core_cm33.h.

◆ DCB_DHCSR_S_RETIRE_ST_Pos [6/13]

#define DCB_DHCSR_S_RETIRE_ST_Pos   24U

DCB DHCSR: Retire sticky status Position

Definition at line 1989 of file core_cm35p.h.

◆ DCB_DHCSR_S_RETIRE_ST_Pos [7/13]

#define DCB_DHCSR_S_RETIRE_ST_Pos   24U

DCB DHCSR: Retire sticky status Position

Definition at line 3392 of file core_cm55.h.

◆ DCB_DHCSR_S_RETIRE_ST_Pos [8/13]

#define DCB_DHCSR_S_RETIRE_ST_Pos   24U

DCB DHCSR: Retire sticky status Position

Definition at line 3297 of file core_cm85.h.

◆ DCB_DHCSR_S_RETIRE_ST_Pos [9/13]

#define DCB_DHCSR_S_RETIRE_ST_Pos   24U

DCB DHCSR: Retire sticky status Position

Definition at line 1916 of file core_starmc1.h.

◆ DCB_DHCSR_S_RETIRE_ST_Pos [10/13]

#define DCB_DHCSR_S_RETIRE_ST_Pos   24U

DCB DHCSR: Retire sticky status Position

Definition at line 2838 of file core_armv81mml.h.

◆ DCB_DHCSR_S_RETIRE_ST_Pos [11/13]

#define DCB_DHCSR_S_RETIRE_ST_Pos   24U

DCB DHCSR: Retire sticky status Position

Definition at line 1118 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_RETIRE_ST_Pos [12/13]

#define DCB_DHCSR_S_RETIRE_ST_Pos   24U

DCB DHCSR: Retire sticky status Position

Definition at line 1914 of file core_armv8mml.h.

◆ DCB_DHCSR_S_RETIRE_ST_Pos [13/13]

#define DCB_DHCSR_S_RETIRE_ST_Pos   24U

DCB DHCSR: Retire sticky status Position

Definition at line 1989 of file core_cm33.h.

◆ DCB_DHCSR_S_SDE_Msk [1/13]

#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)

DCB DHCSR: Secure debug enabled Mask

Definition at line 2851 of file core_armv81mml.h.

◆ DCB_DHCSR_S_SDE_Msk [2/13]

#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)

DCB DHCSR: Secure debug enabled Mask

Definition at line 1122 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_SDE_Msk [3/13]

#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)

DCB DHCSR: Secure debug enabled Mask

Definition at line 1918 of file core_armv8mml.h.

◆ DCB_DHCSR_S_SDE_Msk [4/13]

#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)

DCB DHCSR: Secure debug enabled Mask

Definition at line 1197 of file core_cm23.h.

◆ DCB_DHCSR_S_SDE_Msk [5/13]

#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)

DCB DHCSR: Secure debug enabled Mask

Definition at line 1993 of file core_cm33.h.

◆ DCB_DHCSR_S_SDE_Msk [6/13]

#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)

DCB DHCSR: Secure debug enabled Mask

Definition at line 1993 of file core_cm35p.h.

◆ DCB_DHCSR_S_SDE_Msk [7/13]

#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)

DCB DHCSR: Secure debug enabled Mask

Definition at line 3405 of file core_cm55.h.

◆ DCB_DHCSR_S_SDE_Msk [8/13]

#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)

DCB DHCSR: Secure debug enabled Mask

Definition at line 3310 of file core_cm85.h.

◆ DCB_DHCSR_S_SDE_Msk [9/13]

#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)

DCB DHCSR: Secure debug enabled Mask

Definition at line 1920 of file core_starmc1.h.

◆ DCB_DHCSR_S_SDE_Msk [10/13]

#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)

DCB DHCSR: Secure debug enabled Mask

Definition at line 2851 of file core_armv81mml.h.

◆ DCB_DHCSR_S_SDE_Msk [11/13]

#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)

DCB DHCSR: Secure debug enabled Mask

Definition at line 1122 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_SDE_Msk [12/13]

#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)

DCB DHCSR: Secure debug enabled Mask

Definition at line 1918 of file core_armv8mml.h.

◆ DCB_DHCSR_S_SDE_Msk [13/13]

#define DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)

DCB DHCSR: Secure debug enabled Mask

Definition at line 1993 of file core_cm33.h.

◆ DCB_DHCSR_S_SDE_Pos [1/13]

#define DCB_DHCSR_S_SDE_Pos   20U

DCB DHCSR: Secure debug enabled Position

Definition at line 2850 of file core_armv81mml.h.

◆ DCB_DHCSR_S_SDE_Pos [2/13]

#define DCB_DHCSR_S_SDE_Pos   20U

DCB DHCSR: Secure debug enabled Position

Definition at line 1121 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_SDE_Pos [3/13]

#define DCB_DHCSR_S_SDE_Pos   20U

DCB DHCSR: Secure debug enabled Position

Definition at line 1917 of file core_armv8mml.h.

◆ DCB_DHCSR_S_SDE_Pos [4/13]

#define DCB_DHCSR_S_SDE_Pos   20U

DCB DHCSR: Secure debug enabled Position

Definition at line 1196 of file core_cm23.h.

◆ DCB_DHCSR_S_SDE_Pos [5/13]

#define DCB_DHCSR_S_SDE_Pos   20U

DCB DHCSR: Secure debug enabled Position

Definition at line 1992 of file core_cm33.h.

◆ DCB_DHCSR_S_SDE_Pos [6/13]

#define DCB_DHCSR_S_SDE_Pos   20U

DCB DHCSR: Secure debug enabled Position

Definition at line 1992 of file core_cm35p.h.

◆ DCB_DHCSR_S_SDE_Pos [7/13]

#define DCB_DHCSR_S_SDE_Pos   20U

DCB DHCSR: Secure debug enabled Position

Definition at line 3404 of file core_cm55.h.

◆ DCB_DHCSR_S_SDE_Pos [8/13]

#define DCB_DHCSR_S_SDE_Pos   20U

DCB DHCSR: Secure debug enabled Position

Definition at line 3309 of file core_cm85.h.

◆ DCB_DHCSR_S_SDE_Pos [9/13]

#define DCB_DHCSR_S_SDE_Pos   20U

DCB DHCSR: Secure debug enabled Position

Definition at line 1919 of file core_starmc1.h.

◆ DCB_DHCSR_S_SDE_Pos [10/13]

#define DCB_DHCSR_S_SDE_Pos   20U

DCB DHCSR: Secure debug enabled Position

Definition at line 2850 of file core_armv81mml.h.

◆ DCB_DHCSR_S_SDE_Pos [11/13]

#define DCB_DHCSR_S_SDE_Pos   20U

DCB DHCSR: Secure debug enabled Position

Definition at line 1121 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_SDE_Pos [12/13]

#define DCB_DHCSR_S_SDE_Pos   20U

DCB DHCSR: Secure debug enabled Position

Definition at line 1917 of file core_armv8mml.h.

◆ DCB_DHCSR_S_SDE_Pos [13/13]

#define DCB_DHCSR_S_SDE_Pos   20U

DCB DHCSR: Secure debug enabled Position

Definition at line 1992 of file core_cm33.h.

◆ DCB_DHCSR_S_SLEEP_Msk [1/13]

#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)

DCB DHCSR: Sleeping status Mask

Definition at line 2857 of file core_armv81mml.h.

◆ DCB_DHCSR_S_SLEEP_Msk [2/13]

#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)

DCB DHCSR: Sleeping status Mask

Definition at line 1128 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_SLEEP_Msk [3/13]

#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)

DCB DHCSR: Sleeping status Mask

Definition at line 1924 of file core_armv8mml.h.

◆ DCB_DHCSR_S_SLEEP_Msk [4/13]

#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)

DCB DHCSR: Sleeping status Mask

Definition at line 1203 of file core_cm23.h.

◆ DCB_DHCSR_S_SLEEP_Msk [5/13]

#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)

DCB DHCSR: Sleeping status Mask

Definition at line 1999 of file core_cm33.h.

◆ DCB_DHCSR_S_SLEEP_Msk [6/13]

#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)

DCB DHCSR: Sleeping status Mask

Definition at line 1999 of file core_cm35p.h.

◆ DCB_DHCSR_S_SLEEP_Msk [7/13]

#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)

DCB DHCSR: Sleeping status Mask

Definition at line 3411 of file core_cm55.h.

◆ DCB_DHCSR_S_SLEEP_Msk [8/13]

#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)

DCB DHCSR: Sleeping status Mask

Definition at line 3316 of file core_cm85.h.

◆ DCB_DHCSR_S_SLEEP_Msk [9/13]

#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)

DCB DHCSR: Sleeping status Mask

Definition at line 1926 of file core_starmc1.h.

◆ DCB_DHCSR_S_SLEEP_Msk [10/13]

#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)

DCB DHCSR: Sleeping status Mask

Definition at line 2857 of file core_armv81mml.h.

◆ DCB_DHCSR_S_SLEEP_Msk [11/13]

#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)

DCB DHCSR: Sleeping status Mask

Definition at line 1128 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_SLEEP_Msk [12/13]

#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)

DCB DHCSR: Sleeping status Mask

Definition at line 1924 of file core_armv8mml.h.

◆ DCB_DHCSR_S_SLEEP_Msk [13/13]

#define DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)

DCB DHCSR: Sleeping status Mask

Definition at line 1999 of file core_cm33.h.

◆ DCB_DHCSR_S_SLEEP_Pos [1/13]

#define DCB_DHCSR_S_SLEEP_Pos   18U

DCB DHCSR: Sleeping status Position

Definition at line 2856 of file core_armv81mml.h.

◆ DCB_DHCSR_S_SLEEP_Pos [2/13]

#define DCB_DHCSR_S_SLEEP_Pos   18U

DCB DHCSR: Sleeping status Position

Definition at line 1127 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_SLEEP_Pos [3/13]

#define DCB_DHCSR_S_SLEEP_Pos   18U

DCB DHCSR: Sleeping status Position

Definition at line 1923 of file core_armv8mml.h.

◆ DCB_DHCSR_S_SLEEP_Pos [4/13]

#define DCB_DHCSR_S_SLEEP_Pos   18U

DCB DHCSR: Sleeping status Position

Definition at line 1202 of file core_cm23.h.

◆ DCB_DHCSR_S_SLEEP_Pos [5/13]

#define DCB_DHCSR_S_SLEEP_Pos   18U

DCB DHCSR: Sleeping status Position

Definition at line 1998 of file core_cm33.h.

◆ DCB_DHCSR_S_SLEEP_Pos [6/13]

#define DCB_DHCSR_S_SLEEP_Pos   18U

DCB DHCSR: Sleeping status Position

Definition at line 1998 of file core_cm35p.h.

◆ DCB_DHCSR_S_SLEEP_Pos [7/13]

#define DCB_DHCSR_S_SLEEP_Pos   18U

DCB DHCSR: Sleeping status Position

Definition at line 3410 of file core_cm55.h.

◆ DCB_DHCSR_S_SLEEP_Pos [8/13]

#define DCB_DHCSR_S_SLEEP_Pos   18U

DCB DHCSR: Sleeping status Position

Definition at line 3315 of file core_cm85.h.

◆ DCB_DHCSR_S_SLEEP_Pos [9/13]

#define DCB_DHCSR_S_SLEEP_Pos   18U

DCB DHCSR: Sleeping status Position

Definition at line 1925 of file core_starmc1.h.

◆ DCB_DHCSR_S_SLEEP_Pos [10/13]

#define DCB_DHCSR_S_SLEEP_Pos   18U

DCB DHCSR: Sleeping status Position

Definition at line 2856 of file core_armv81mml.h.

◆ DCB_DHCSR_S_SLEEP_Pos [11/13]

#define DCB_DHCSR_S_SLEEP_Pos   18U

DCB DHCSR: Sleeping status Position

Definition at line 1127 of file core_armv8mbl.h.

◆ DCB_DHCSR_S_SLEEP_Pos [12/13]

#define DCB_DHCSR_S_SLEEP_Pos   18U

DCB DHCSR: Sleeping status Position

Definition at line 1923 of file core_armv8mml.h.

◆ DCB_DHCSR_S_SLEEP_Pos [13/13]

#define DCB_DHCSR_S_SLEEP_Pos   18U

DCB DHCSR: Sleeping status Position

Definition at line 1998 of file core_cm33.h.

◆ DCB_DHCSR_S_SUIDE_Msk [1/4]

#define DCB_DHCSR_S_SUIDE_Msk   (0x1UL << DCB_DHCSR_S_SUIDE_Pos)

DCB DHCSR: Secure unprivileged halting debug enabled Mask

Definition at line 2845 of file core_armv81mml.h.

◆ DCB_DHCSR_S_SUIDE_Msk [2/4]

#define DCB_DHCSR_S_SUIDE_Msk   (0x1UL << DCB_DHCSR_S_SUIDE_Pos)

DCB DHCSR: Secure unprivileged halting debug enabled Mask

Definition at line 3399 of file core_cm55.h.

◆ DCB_DHCSR_S_SUIDE_Msk [3/4]

#define DCB_DHCSR_S_SUIDE_Msk   (0x1UL << DCB_DHCSR_S_SUIDE_Pos)

DCB DHCSR: Secure unprivileged halting debug enabled Mask

Definition at line 3304 of file core_cm85.h.

◆ DCB_DHCSR_S_SUIDE_Msk [4/4]

#define DCB_DHCSR_S_SUIDE_Msk   (0x1UL << DCB_DHCSR_S_SUIDE_Pos)

DCB DHCSR: Secure unprivileged halting debug enabled Mask

Definition at line 2845 of file core_armv81mml.h.

◆ DCB_DHCSR_S_SUIDE_Pos [1/4]

#define DCB_DHCSR_S_SUIDE_Pos   22U

DCB DHCSR: Secure unprivileged halting debug enabled Position

Definition at line 2844 of file core_armv81mml.h.

◆ DCB_DHCSR_S_SUIDE_Pos [2/4]

#define DCB_DHCSR_S_SUIDE_Pos   22U

DCB DHCSR: Secure unprivileged halting debug enabled Position

Definition at line 3398 of file core_cm55.h.

◆ DCB_DHCSR_S_SUIDE_Pos [3/4]

#define DCB_DHCSR_S_SUIDE_Pos   22U

DCB DHCSR: Secure unprivileged halting debug enabled Position

Definition at line 3303 of file core_cm85.h.

◆ DCB_DHCSR_S_SUIDE_Pos [4/4]

#define DCB_DHCSR_S_SUIDE_Pos   22U

DCB DHCSR: Secure unprivileged halting debug enabled Position

Definition at line 2844 of file core_armv81mml.h.

◆ DCB_DSCEMCR_CLR_MON_PEND_Msk [1/4]

#define DCB_DSCEMCR_CLR_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)

DCB DSCEMCR: Clear monitor pend Mask

Definition at line 2951 of file core_armv81mml.h.

◆ DCB_DSCEMCR_CLR_MON_PEND_Msk [2/4]

#define DCB_DSCEMCR_CLR_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)

DCB DSCEMCR: Clear monitor pend Mask

Definition at line 3505 of file core_cm55.h.

◆ DCB_DSCEMCR_CLR_MON_PEND_Msk [3/4]

#define DCB_DSCEMCR_CLR_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)

DCB DSCEMCR: Clear monitor pend Mask

Definition at line 3410 of file core_cm85.h.

◆ DCB_DSCEMCR_CLR_MON_PEND_Msk [4/4]

#define DCB_DSCEMCR_CLR_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)

DCB DSCEMCR: Clear monitor pend Mask

Definition at line 2951 of file core_armv81mml.h.

◆ DCB_DSCEMCR_CLR_MON_PEND_Pos [1/4]

#define DCB_DSCEMCR_CLR_MON_PEND_Pos   17U

DCB DSCEMCR: Clear monitor pend Position

Definition at line 2950 of file core_armv81mml.h.

◆ DCB_DSCEMCR_CLR_MON_PEND_Pos [2/4]

#define DCB_DSCEMCR_CLR_MON_PEND_Pos   17U

DCB DSCEMCR: Clear monitor pend Position

Definition at line 3504 of file core_cm55.h.

◆ DCB_DSCEMCR_CLR_MON_PEND_Pos [3/4]

#define DCB_DSCEMCR_CLR_MON_PEND_Pos   17U

DCB DSCEMCR: Clear monitor pend Position

Definition at line 3409 of file core_cm85.h.

◆ DCB_DSCEMCR_CLR_MON_PEND_Pos [4/4]

#define DCB_DSCEMCR_CLR_MON_PEND_Pos   17U

DCB DSCEMCR: Clear monitor pend Position

Definition at line 2950 of file core_armv81mml.h.

◆ DCB_DSCEMCR_CLR_MON_REQ_Msk [1/4]

#define DCB_DSCEMCR_CLR_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)

DCB DSCEMCR: Clear monitor request Mask

Definition at line 2948 of file core_armv81mml.h.

◆ DCB_DSCEMCR_CLR_MON_REQ_Msk [2/4]

#define DCB_DSCEMCR_CLR_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)

DCB DSCEMCR: Clear monitor request Mask

Definition at line 3502 of file core_cm55.h.

◆ DCB_DSCEMCR_CLR_MON_REQ_Msk [3/4]

#define DCB_DSCEMCR_CLR_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)

DCB DSCEMCR: Clear monitor request Mask

Definition at line 3407 of file core_cm85.h.

◆ DCB_DSCEMCR_CLR_MON_REQ_Msk [4/4]

#define DCB_DSCEMCR_CLR_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)

DCB DSCEMCR: Clear monitor request Mask

Definition at line 2948 of file core_armv81mml.h.

◆ DCB_DSCEMCR_CLR_MON_REQ_Pos [1/4]

#define DCB_DSCEMCR_CLR_MON_REQ_Pos   19U

DCB DSCEMCR: Clear monitor request Position

Definition at line 2947 of file core_armv81mml.h.

◆ DCB_DSCEMCR_CLR_MON_REQ_Pos [2/4]

#define DCB_DSCEMCR_CLR_MON_REQ_Pos   19U

DCB DSCEMCR: Clear monitor request Position

Definition at line 3501 of file core_cm55.h.

◆ DCB_DSCEMCR_CLR_MON_REQ_Pos [3/4]

#define DCB_DSCEMCR_CLR_MON_REQ_Pos   19U

DCB DSCEMCR: Clear monitor request Position

Definition at line 3406 of file core_cm85.h.

◆ DCB_DSCEMCR_CLR_MON_REQ_Pos [4/4]

#define DCB_DSCEMCR_CLR_MON_REQ_Pos   19U

DCB DSCEMCR: Clear monitor request Position

Definition at line 2947 of file core_armv81mml.h.

◆ DCB_DSCEMCR_SET_MON_PEND_Msk [1/4]

#define DCB_DSCEMCR_SET_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)

DCB DSCEMCR: Set monitor pend Mask

Definition at line 2957 of file core_armv81mml.h.

◆ DCB_DSCEMCR_SET_MON_PEND_Msk [2/4]

#define DCB_DSCEMCR_SET_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)

DCB DSCEMCR: Set monitor pend Mask

Definition at line 3511 of file core_cm55.h.

◆ DCB_DSCEMCR_SET_MON_PEND_Msk [3/4]

#define DCB_DSCEMCR_SET_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)

DCB DSCEMCR: Set monitor pend Mask

Definition at line 3416 of file core_cm85.h.

◆ DCB_DSCEMCR_SET_MON_PEND_Msk [4/4]

#define DCB_DSCEMCR_SET_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)

DCB DSCEMCR: Set monitor pend Mask

Definition at line 2957 of file core_armv81mml.h.

◆ DCB_DSCEMCR_SET_MON_PEND_Pos [1/4]

#define DCB_DSCEMCR_SET_MON_PEND_Pos   1U

DCB DSCEMCR: Set monitor pend Position

Definition at line 2956 of file core_armv81mml.h.

◆ DCB_DSCEMCR_SET_MON_PEND_Pos [2/4]

#define DCB_DSCEMCR_SET_MON_PEND_Pos   1U

DCB DSCEMCR: Set monitor pend Position

Definition at line 3510 of file core_cm55.h.

◆ DCB_DSCEMCR_SET_MON_PEND_Pos [3/4]

#define DCB_DSCEMCR_SET_MON_PEND_Pos   1U

DCB DSCEMCR: Set monitor pend Position

Definition at line 3415 of file core_cm85.h.

◆ DCB_DSCEMCR_SET_MON_PEND_Pos [4/4]

#define DCB_DSCEMCR_SET_MON_PEND_Pos   1U

DCB DSCEMCR: Set monitor pend Position

Definition at line 2956 of file core_armv81mml.h.

◆ DCB_DSCEMCR_SET_MON_REQ_Msk [1/4]

#define DCB_DSCEMCR_SET_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)

DCB DSCEMCR: Set monitor request Mask

Definition at line 2954 of file core_armv81mml.h.

◆ DCB_DSCEMCR_SET_MON_REQ_Msk [2/4]

#define DCB_DSCEMCR_SET_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)

DCB DSCEMCR: Set monitor request Mask

Definition at line 3508 of file core_cm55.h.

◆ DCB_DSCEMCR_SET_MON_REQ_Msk [3/4]

#define DCB_DSCEMCR_SET_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)

DCB DSCEMCR: Set monitor request Mask

Definition at line 3413 of file core_cm85.h.

◆ DCB_DSCEMCR_SET_MON_REQ_Msk [4/4]

#define DCB_DSCEMCR_SET_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)

DCB DSCEMCR: Set monitor request Mask

Definition at line 2954 of file core_armv81mml.h.

◆ DCB_DSCEMCR_SET_MON_REQ_Pos [1/4]

#define DCB_DSCEMCR_SET_MON_REQ_Pos   3U

DCB DSCEMCR: Set monitor request Position

Definition at line 2953 of file core_armv81mml.h.

◆ DCB_DSCEMCR_SET_MON_REQ_Pos [2/4]

#define DCB_DSCEMCR_SET_MON_REQ_Pos   3U

DCB DSCEMCR: Set monitor request Position

Definition at line 3507 of file core_cm55.h.

◆ DCB_DSCEMCR_SET_MON_REQ_Pos [3/4]

#define DCB_DSCEMCR_SET_MON_REQ_Pos   3U

DCB DSCEMCR: Set monitor request Position

Definition at line 3412 of file core_cm85.h.

◆ DCB_DSCEMCR_SET_MON_REQ_Pos [4/4]

#define DCB_DSCEMCR_SET_MON_REQ_Pos   3U

DCB DSCEMCR: Set monitor request Position

Definition at line 2953 of file core_armv81mml.h.

◆ DCB_DSCSR_CDS_Msk [1/13]

#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)

DCB DSCSR: Current domain Secure Mask

Definition at line 2986 of file core_armv81mml.h.

◆ DCB_DSCSR_CDS_Msk [2/13]

#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)

DCB DSCSR: Current domain Secure Mask

Definition at line 1187 of file core_armv8mbl.h.

◆ DCB_DSCSR_CDS_Msk [3/13]

#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)

DCB DSCSR: Current domain Secure Mask

Definition at line 2028 of file core_armv8mml.h.

◆ DCB_DSCSR_CDS_Msk [4/13]

#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)

DCB DSCSR: Current domain Secure Mask

Definition at line 1262 of file core_cm23.h.

◆ DCB_DSCSR_CDS_Msk [5/13]

#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)

DCB DSCSR: Current domain Secure Mask

Definition at line 2103 of file core_cm33.h.

◆ DCB_DSCSR_CDS_Msk [6/13]

#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)

DCB DSCSR: Current domain Secure Mask

Definition at line 2103 of file core_cm35p.h.

◆ DCB_DSCSR_CDS_Msk [7/13]

#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)

DCB DSCSR: Current domain Secure Mask

Definition at line 3540 of file core_cm55.h.

◆ DCB_DSCSR_CDS_Msk [8/13]

#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)

DCB DSCSR: Current domain Secure Mask

Definition at line 3445 of file core_cm85.h.

◆ DCB_DSCSR_CDS_Msk [9/13]

#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)

DCB DSCSR: Current domain Secure Mask

Definition at line 2030 of file core_starmc1.h.

◆ DCB_DSCSR_CDS_Msk [10/13]

#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)

DCB DSCSR: Current domain Secure Mask

Definition at line 2986 of file core_armv81mml.h.

◆ DCB_DSCSR_CDS_Msk [11/13]

#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)

DCB DSCSR: Current domain Secure Mask

Definition at line 1187 of file core_armv8mbl.h.

◆ DCB_DSCSR_CDS_Msk [12/13]

#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)

DCB DSCSR: Current domain Secure Mask

Definition at line 2028 of file core_armv8mml.h.

◆ DCB_DSCSR_CDS_Msk [13/13]

#define DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)

DCB DSCSR: Current domain Secure Mask

Definition at line 2103 of file core_cm33.h.

◆ DCB_DSCSR_CDS_Pos [1/13]

#define DCB_DSCSR_CDS_Pos   16U

DCB DSCSR: Current domain Secure Position

Definition at line 2985 of file core_armv81mml.h.

◆ DCB_DSCSR_CDS_Pos [2/13]

#define DCB_DSCSR_CDS_Pos   16U

DCB DSCSR: Current domain Secure Position

Definition at line 1186 of file core_armv8mbl.h.

◆ DCB_DSCSR_CDS_Pos [3/13]

#define DCB_DSCSR_CDS_Pos   16U

DCB DSCSR: Current domain Secure Position

Definition at line 2027 of file core_armv8mml.h.

◆ DCB_DSCSR_CDS_Pos [4/13]

#define DCB_DSCSR_CDS_Pos   16U

DCB DSCSR: Current domain Secure Position

Definition at line 1261 of file core_cm23.h.

◆ DCB_DSCSR_CDS_Pos [5/13]

#define DCB_DSCSR_CDS_Pos   16U

DCB DSCSR: Current domain Secure Position

Definition at line 2102 of file core_cm33.h.

◆ DCB_DSCSR_CDS_Pos [6/13]

#define DCB_DSCSR_CDS_Pos   16U

DCB DSCSR: Current domain Secure Position

Definition at line 2102 of file core_cm35p.h.

◆ DCB_DSCSR_CDS_Pos [7/13]

#define DCB_DSCSR_CDS_Pos   16U

DCB DSCSR: Current domain Secure Position

Definition at line 3539 of file core_cm55.h.

◆ DCB_DSCSR_CDS_Pos [8/13]

#define DCB_DSCSR_CDS_Pos   16U

DCB DSCSR: Current domain Secure Position

Definition at line 3444 of file core_cm85.h.

◆ DCB_DSCSR_CDS_Pos [9/13]

#define DCB_DSCSR_CDS_Pos   16U

DCB DSCSR: Current domain Secure Position

Definition at line 2029 of file core_starmc1.h.

◆ DCB_DSCSR_CDS_Pos [10/13]

#define DCB_DSCSR_CDS_Pos   16U

DCB DSCSR: Current domain Secure Position

Definition at line 2985 of file core_armv81mml.h.

◆ DCB_DSCSR_CDS_Pos [11/13]

#define DCB_DSCSR_CDS_Pos   16U

DCB DSCSR: Current domain Secure Position

Definition at line 1186 of file core_armv8mbl.h.

◆ DCB_DSCSR_CDS_Pos [12/13]

#define DCB_DSCSR_CDS_Pos   16U

DCB DSCSR: Current domain Secure Position

Definition at line 2027 of file core_armv8mml.h.

◆ DCB_DSCSR_CDS_Pos [13/13]

#define DCB_DSCSR_CDS_Pos   16U

DCB DSCSR: Current domain Secure Position

Definition at line 2102 of file core_cm33.h.

◆ DCB_DSCSR_CDSKEY_Msk [1/13]

#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)

DCB DSCSR: CDS write-enable key Mask

Definition at line 2983 of file core_armv81mml.h.

◆ DCB_DSCSR_CDSKEY_Msk [2/13]

#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)

DCB DSCSR: CDS write-enable key Mask

Definition at line 1184 of file core_armv8mbl.h.

◆ DCB_DSCSR_CDSKEY_Msk [3/13]

#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)

DCB DSCSR: CDS write-enable key Mask

Definition at line 2025 of file core_armv8mml.h.

◆ DCB_DSCSR_CDSKEY_Msk [4/13]

#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)

DCB DSCSR: CDS write-enable key Mask

Definition at line 1259 of file core_cm23.h.

◆ DCB_DSCSR_CDSKEY_Msk [5/13]

#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)

DCB DSCSR: CDS write-enable key Mask

Definition at line 2100 of file core_cm33.h.

◆ DCB_DSCSR_CDSKEY_Msk [6/13]

#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)

DCB DSCSR: CDS write-enable key Mask

Definition at line 2100 of file core_cm35p.h.

◆ DCB_DSCSR_CDSKEY_Msk [7/13]

#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)

DCB DSCSR: CDS write-enable key Mask

Definition at line 3537 of file core_cm55.h.

◆ DCB_DSCSR_CDSKEY_Msk [8/13]

#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)

DCB DSCSR: CDS write-enable key Mask

Definition at line 3442 of file core_cm85.h.

◆ DCB_DSCSR_CDSKEY_Msk [9/13]

#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)

DCB DSCSR: CDS write-enable key Mask

Definition at line 2027 of file core_starmc1.h.

◆ DCB_DSCSR_CDSKEY_Msk [10/13]

#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)

DCB DSCSR: CDS write-enable key Mask

Definition at line 2983 of file core_armv81mml.h.

◆ DCB_DSCSR_CDSKEY_Msk [11/13]

#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)

DCB DSCSR: CDS write-enable key Mask

Definition at line 1184 of file core_armv8mbl.h.

◆ DCB_DSCSR_CDSKEY_Msk [12/13]

#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)

DCB DSCSR: CDS write-enable key Mask

Definition at line 2025 of file core_armv8mml.h.

◆ DCB_DSCSR_CDSKEY_Msk [13/13]

#define DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)

DCB DSCSR: CDS write-enable key Mask

Definition at line 2100 of file core_cm33.h.

◆ DCB_DSCSR_CDSKEY_Pos [1/13]

#define DCB_DSCSR_CDSKEY_Pos   17U

DCB DSCSR: CDS write-enable key Position

Definition at line 2982 of file core_armv81mml.h.

◆ DCB_DSCSR_CDSKEY_Pos [2/13]

#define DCB_DSCSR_CDSKEY_Pos   17U

DCB DSCSR: CDS write-enable key Position

Definition at line 1183 of file core_armv8mbl.h.

◆ DCB_DSCSR_CDSKEY_Pos [3/13]

#define DCB_DSCSR_CDSKEY_Pos   17U

DCB DSCSR: CDS write-enable key Position

Definition at line 2024 of file core_armv8mml.h.

◆ DCB_DSCSR_CDSKEY_Pos [4/13]

#define DCB_DSCSR_CDSKEY_Pos   17U

DCB DSCSR: CDS write-enable key Position

Definition at line 1258 of file core_cm23.h.

◆ DCB_DSCSR_CDSKEY_Pos [5/13]

#define DCB_DSCSR_CDSKEY_Pos   17U

DCB DSCSR: CDS write-enable key Position

Definition at line 2099 of file core_cm33.h.

◆ DCB_DSCSR_CDSKEY_Pos [6/13]

#define DCB_DSCSR_CDSKEY_Pos   17U

DCB DSCSR: CDS write-enable key Position

Definition at line 2099 of file core_cm35p.h.

◆ DCB_DSCSR_CDSKEY_Pos [7/13]

#define DCB_DSCSR_CDSKEY_Pos   17U

DCB DSCSR: CDS write-enable key Position

Definition at line 3536 of file core_cm55.h.

◆ DCB_DSCSR_CDSKEY_Pos [8/13]

#define DCB_DSCSR_CDSKEY_Pos   17U

DCB DSCSR: CDS write-enable key Position

Definition at line 3441 of file core_cm85.h.

◆ DCB_DSCSR_CDSKEY_Pos [9/13]

#define DCB_DSCSR_CDSKEY_Pos   17U

DCB DSCSR: CDS write-enable key Position

Definition at line 2026 of file core_starmc1.h.

◆ DCB_DSCSR_CDSKEY_Pos [10/13]

#define DCB_DSCSR_CDSKEY_Pos   17U

DCB DSCSR: CDS write-enable key Position

Definition at line 2982 of file core_armv81mml.h.

◆ DCB_DSCSR_CDSKEY_Pos [11/13]

#define DCB_DSCSR_CDSKEY_Pos   17U

DCB DSCSR: CDS write-enable key Position

Definition at line 1183 of file core_armv8mbl.h.

◆ DCB_DSCSR_CDSKEY_Pos [12/13]

#define DCB_DSCSR_CDSKEY_Pos   17U

DCB DSCSR: CDS write-enable key Position

Definition at line 2024 of file core_armv8mml.h.

◆ DCB_DSCSR_CDSKEY_Pos [13/13]

#define DCB_DSCSR_CDSKEY_Pos   17U

DCB DSCSR: CDS write-enable key Position

Definition at line 2099 of file core_cm33.h.

◆ DCB_DSCSR_SBRSEL_Msk [1/13]

#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)

DCB DSCSR: Secure banked register select Mask

Definition at line 2989 of file core_armv81mml.h.

◆ DCB_DSCSR_SBRSEL_Msk [2/13]

#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)

DCB DSCSR: Secure banked register select Mask

Definition at line 1190 of file core_armv8mbl.h.

◆ DCB_DSCSR_SBRSEL_Msk [3/13]

#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)

DCB DSCSR: Secure banked register select Mask

Definition at line 2031 of file core_armv8mml.h.

◆ DCB_DSCSR_SBRSEL_Msk [4/13]

#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)

DCB DSCSR: Secure banked register select Mask

Definition at line 1265 of file core_cm23.h.

◆ DCB_DSCSR_SBRSEL_Msk [5/13]

#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)

DCB DSCSR: Secure banked register select Mask

Definition at line 2106 of file core_cm33.h.

◆ DCB_DSCSR_SBRSEL_Msk [6/13]

#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)

DCB DSCSR: Secure banked register select Mask

Definition at line 2106 of file core_cm35p.h.

◆ DCB_DSCSR_SBRSEL_Msk [7/13]

#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)

DCB DSCSR: Secure banked register select Mask

Definition at line 3543 of file core_cm55.h.

◆ DCB_DSCSR_SBRSEL_Msk [8/13]

#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)

DCB DSCSR: Secure banked register select Mask

Definition at line 3448 of file core_cm85.h.

◆ DCB_DSCSR_SBRSEL_Msk [9/13]

#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)

DCB DSCSR: Secure banked register select Mask

Definition at line 2033 of file core_starmc1.h.

◆ DCB_DSCSR_SBRSEL_Msk [10/13]

#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)

DCB DSCSR: Secure banked register select Mask

Definition at line 2989 of file core_armv81mml.h.

◆ DCB_DSCSR_SBRSEL_Msk [11/13]

#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)

DCB DSCSR: Secure banked register select Mask

Definition at line 1190 of file core_armv8mbl.h.

◆ DCB_DSCSR_SBRSEL_Msk [12/13]

#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)

DCB DSCSR: Secure banked register select Mask

Definition at line 2031 of file core_armv8mml.h.

◆ DCB_DSCSR_SBRSEL_Msk [13/13]

#define DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)

DCB DSCSR: Secure banked register select Mask

Definition at line 2106 of file core_cm33.h.

◆ DCB_DSCSR_SBRSEL_Pos [1/13]

#define DCB_DSCSR_SBRSEL_Pos   1U

DCB DSCSR: Secure banked register select Position

Definition at line 2988 of file core_armv81mml.h.

◆ DCB_DSCSR_SBRSEL_Pos [2/13]

#define DCB_DSCSR_SBRSEL_Pos   1U

DCB DSCSR: Secure banked register select Position

Definition at line 1189 of file core_armv8mbl.h.

◆ DCB_DSCSR_SBRSEL_Pos [3/13]

#define DCB_DSCSR_SBRSEL_Pos   1U

DCB DSCSR: Secure banked register select Position

Definition at line 2030 of file core_armv8mml.h.

◆ DCB_DSCSR_SBRSEL_Pos [4/13]

#define DCB_DSCSR_SBRSEL_Pos   1U

DCB DSCSR: Secure banked register select Position

Definition at line 1264 of file core_cm23.h.

◆ DCB_DSCSR_SBRSEL_Pos [5/13]

#define DCB_DSCSR_SBRSEL_Pos   1U

DCB DSCSR: Secure banked register select Position

Definition at line 2105 of file core_cm33.h.

◆ DCB_DSCSR_SBRSEL_Pos [6/13]

#define DCB_DSCSR_SBRSEL_Pos   1U

DCB DSCSR: Secure banked register select Position

Definition at line 2105 of file core_cm35p.h.

◆ DCB_DSCSR_SBRSEL_Pos [7/13]

#define DCB_DSCSR_SBRSEL_Pos   1U

DCB DSCSR: Secure banked register select Position

Definition at line 3542 of file core_cm55.h.

◆ DCB_DSCSR_SBRSEL_Pos [8/13]

#define DCB_DSCSR_SBRSEL_Pos   1U

DCB DSCSR: Secure banked register select Position

Definition at line 3447 of file core_cm85.h.

◆ DCB_DSCSR_SBRSEL_Pos [9/13]

#define DCB_DSCSR_SBRSEL_Pos   1U

DCB DSCSR: Secure banked register select Position

Definition at line 2032 of file core_starmc1.h.

◆ DCB_DSCSR_SBRSEL_Pos [10/13]

#define DCB_DSCSR_SBRSEL_Pos   1U

DCB DSCSR: Secure banked register select Position

Definition at line 2988 of file core_armv81mml.h.

◆ DCB_DSCSR_SBRSEL_Pos [11/13]

#define DCB_DSCSR_SBRSEL_Pos   1U

DCB DSCSR: Secure banked register select Position

Definition at line 1189 of file core_armv8mbl.h.

◆ DCB_DSCSR_SBRSEL_Pos [12/13]

#define DCB_DSCSR_SBRSEL_Pos   1U

DCB DSCSR: Secure banked register select Position

Definition at line 2030 of file core_armv8mml.h.

◆ DCB_DSCSR_SBRSEL_Pos [13/13]

#define DCB_DSCSR_SBRSEL_Pos   1U

DCB DSCSR: Secure banked register select Position

Definition at line 2105 of file core_cm33.h.

◆ DCB_DSCSR_SBRSELEN_Msk [1/13]

#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)

DCB DSCSR: Secure banked register select enable Mask

Definition at line 2992 of file core_armv81mml.h.

◆ DCB_DSCSR_SBRSELEN_Msk [2/13]

#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)

DCB DSCSR: Secure banked register select enable Mask

Definition at line 1193 of file core_armv8mbl.h.

◆ DCB_DSCSR_SBRSELEN_Msk [3/13]

#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)

DCB DSCSR: Secure banked register select enable Mask

Definition at line 2034 of file core_armv8mml.h.

◆ DCB_DSCSR_SBRSELEN_Msk [4/13]

#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)

DCB DSCSR: Secure banked register select enable Mask

Definition at line 1268 of file core_cm23.h.

◆ DCB_DSCSR_SBRSELEN_Msk [5/13]

#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)

DCB DSCSR: Secure banked register select enable Mask

Definition at line 2109 of file core_cm33.h.

◆ DCB_DSCSR_SBRSELEN_Msk [6/13]

#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)

DCB DSCSR: Secure banked register select enable Mask

Definition at line 2109 of file core_cm35p.h.

◆ DCB_DSCSR_SBRSELEN_Msk [7/13]

#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)

DCB DSCSR: Secure banked register select enable Mask

Definition at line 3546 of file core_cm55.h.

◆ DCB_DSCSR_SBRSELEN_Msk [8/13]

#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)

DCB DSCSR: Secure banked register select enable Mask

Definition at line 3451 of file core_cm85.h.

◆ DCB_DSCSR_SBRSELEN_Msk [9/13]

#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)

DCB DSCSR: Secure banked register select enable Mask

Definition at line 2036 of file core_starmc1.h.

◆ DCB_DSCSR_SBRSELEN_Msk [10/13]

#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)

DCB DSCSR: Secure banked register select enable Mask

Definition at line 2992 of file core_armv81mml.h.

◆ DCB_DSCSR_SBRSELEN_Msk [11/13]

#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)

DCB DSCSR: Secure banked register select enable Mask

Definition at line 1193 of file core_armv8mbl.h.

◆ DCB_DSCSR_SBRSELEN_Msk [12/13]

#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)

DCB DSCSR: Secure banked register select enable Mask

Definition at line 2034 of file core_armv8mml.h.

◆ DCB_DSCSR_SBRSELEN_Msk [13/13]

#define DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)

DCB DSCSR: Secure banked register select enable Mask

Definition at line 2109 of file core_cm33.h.

◆ DCB_DSCSR_SBRSELEN_Pos [1/13]

#define DCB_DSCSR_SBRSELEN_Pos   0U

DCB DSCSR: Secure banked register select enable Position

Definition at line 2991 of file core_armv81mml.h.

◆ DCB_DSCSR_SBRSELEN_Pos [2/13]

#define DCB_DSCSR_SBRSELEN_Pos   0U

DCB DSCSR: Secure banked register select enable Position

Definition at line 1192 of file core_armv8mbl.h.

◆ DCB_DSCSR_SBRSELEN_Pos [3/13]

#define DCB_DSCSR_SBRSELEN_Pos   0U

DCB DSCSR: Secure banked register select enable Position

Definition at line 2033 of file core_armv8mml.h.

◆ DCB_DSCSR_SBRSELEN_Pos [4/13]

#define DCB_DSCSR_SBRSELEN_Pos   0U

DCB DSCSR: Secure banked register select enable Position

Definition at line 1267 of file core_cm23.h.

◆ DCB_DSCSR_SBRSELEN_Pos [5/13]

#define DCB_DSCSR_SBRSELEN_Pos   0U

DCB DSCSR: Secure banked register select enable Position

Definition at line 2108 of file core_cm33.h.

◆ DCB_DSCSR_SBRSELEN_Pos [6/13]

#define DCB_DSCSR_SBRSELEN_Pos   0U

DCB DSCSR: Secure banked register select enable Position

Definition at line 2108 of file core_cm35p.h.

◆ DCB_DSCSR_SBRSELEN_Pos [7/13]

#define DCB_DSCSR_SBRSELEN_Pos   0U

DCB DSCSR: Secure banked register select enable Position

Definition at line 3545 of file core_cm55.h.

◆ DCB_DSCSR_SBRSELEN_Pos [8/13]

#define DCB_DSCSR_SBRSELEN_Pos   0U

DCB DSCSR: Secure banked register select enable Position

Definition at line 3450 of file core_cm85.h.

◆ DCB_DSCSR_SBRSELEN_Pos [9/13]

#define DCB_DSCSR_SBRSELEN_Pos   0U

DCB DSCSR: Secure banked register select enable Position

Definition at line 2035 of file core_starmc1.h.

◆ DCB_DSCSR_SBRSELEN_Pos [10/13]

#define DCB_DSCSR_SBRSELEN_Pos   0U

DCB DSCSR: Secure banked register select enable Position

Definition at line 2991 of file core_armv81mml.h.

◆ DCB_DSCSR_SBRSELEN_Pos [11/13]

#define DCB_DSCSR_SBRSELEN_Pos   0U

DCB DSCSR: Secure banked register select enable Position

Definition at line 1192 of file core_armv8mbl.h.

◆ DCB_DSCSR_SBRSELEN_Pos [12/13]

#define DCB_DSCSR_SBRSELEN_Pos   0U

DCB DSCSR: Secure banked register select enable Position

Definition at line 2033 of file core_armv8mml.h.

◆ DCB_DSCSR_SBRSELEN_Pos [13/13]

#define DCB_DSCSR_SBRSELEN_Pos   0U

DCB DSCSR: Secure banked register select enable Position

Definition at line 2108 of file core_cm33.h.

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