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Yet Another Hardware Abstraction Library
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Floating Point Unit (FPU)
Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » Implementation Control Block register (ICB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » Implementation Control Block register (ICB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Memory System Control Registers (IMPLEMENTATION DEFINED) » Power Mode Control Registers » External Wakeup Interrupt Controller Registers » External Wakeup Interrupt Controller (EWIC) interrupt status access registers » Error Banking Registers (IMPLEMENTATION DEFINED) » Processor Configuration Information Registers (IMPLEMENTATION DEFINED) » Software Test Library Observation Registers » Trace Port Interface (TPI)

Type definitions for the Floating Point Unit (FPU) More...

Topics

 Core Debug Registers (CoreDebug)
 Type definitions for the Core Debug Registers.
 

Classes

struct  FPU_Type
 Structure type to access the Floating Point Unit (FPU). More...
 
#define FPU_FPCCR_ASPEN_Pos   31U
 
#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
 
#define FPU_FPCCR_LSPEN_Pos   30U
 
#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
 
#define FPU_FPCCR_MONRDY_Pos   8U
 
#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
 
#define FPU_FPCCR_BFRDY_Pos   6U
 
#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
 
#define FPU_FPCCR_MMRDY_Pos   5U
 
#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
 
#define FPU_FPCCR_HFRDY_Pos   4U
 
#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
 
#define FPU_FPCCR_THREAD_Pos   3U
 
#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
 
#define FPU_FPCCR_USER_Pos   1U
 
#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
 
#define FPU_FPCCR_LSPACT_Pos   0U
 
#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
 
#define FPU_FPCAR_ADDRESS_Pos   3U
 
#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
 
#define FPU_FPDSCR_AHP_Pos   26U
 
#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
 
#define FPU_FPDSCR_DN_Pos   25U
 
#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
 
#define FPU_FPDSCR_FZ_Pos   24U
 
#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
 
#define FPU_FPDSCR_RMode_Pos   22U
 
#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
 
#define FPU_FPCCR_ASPEN_Pos   31U
 
#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
 
#define FPU_FPCCR_LSPEN_Pos   30U
 
#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
 
#define FPU_FPCCR_MONRDY_Pos   8U
 
#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
 
#define FPU_FPCCR_BFRDY_Pos   6U
 
#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
 
#define FPU_FPCCR_MMRDY_Pos   5U
 
#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
 
#define FPU_FPCCR_HFRDY_Pos   4U
 
#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
 
#define FPU_FPCCR_THREAD_Pos   3U
 
#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
 
#define FPU_FPCCR_USER_Pos   1U
 
#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
 
#define FPU_FPCCR_LSPACT_Pos   0U
 
#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
 
#define FPU_FPCAR_ADDRESS_Pos   3U
 
#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
 
#define FPU_FPDSCR_AHP_Pos   26U
 
#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
 
#define FPU_FPDSCR_DN_Pos   25U
 
#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
 
#define FPU_FPDSCR_FZ_Pos   24U
 
#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
 
#define FPU_FPDSCR_RMode_Pos   22U
 
#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
 
#define FPU_MVFR0_FP_rounding_modes_Pos   28U
 
#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
 
#define FPU_MVFR0_Short_vectors_Pos   24U
 
#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)
 
#define FPU_MVFR0_Square_root_Pos   20U
 
#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)
 
#define FPU_MVFR0_Divide_Pos   16U
 
#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)
 
#define FPU_MVFR0_FP_excep_trapping_Pos   12U
 
#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
 
#define FPU_MVFR0_Double_precision_Pos   8U
 
#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)
 
#define FPU_MVFR0_Single_precision_Pos   4U
 
#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)
 
#define FPU_MVFR0_A_SIMD_registers_Pos   0U
 
#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
 
#define FPU_MVFR1_FP_fused_MAC_Pos   28U
 
#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
 
#define FPU_MVFR1_FP_HPFP_Pos   24U
 
#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
 
#define FPU_MVFR1_D_NaN_mode_Pos   4U
 
#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
 
#define FPU_MVFR1_FtZ_mode_Pos   0U
 
#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
 
#define FPU_FPCCR_ASPEN_Pos   31U
 
#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
 
#define FPU_FPCCR_LSPEN_Pos   30U
 
#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
 
#define FPU_FPCCR_MONRDY_Pos   8U
 
#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
 
#define FPU_FPCCR_BFRDY_Pos   6U
 
#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
 
#define FPU_FPCCR_MMRDY_Pos   5U
 
#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
 
#define FPU_FPCCR_HFRDY_Pos   4U
 
#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
 
#define FPU_FPCCR_THREAD_Pos   3U
 
#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
 
#define FPU_FPCCR_USER_Pos   1U
 
#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
 
#define FPU_FPCCR_LSPACT_Pos   0U
 
#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
 
#define FPU_FPCAR_ADDRESS_Pos   3U
 
#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
 
#define FPU_FPDSCR_AHP_Pos   26U
 
#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
 
#define FPU_FPDSCR_DN_Pos   25U
 
#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
 
#define FPU_FPDSCR_FZ_Pos   24U
 
#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
 
#define FPU_FPDSCR_RMode_Pos   22U
 
#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
 
#define FPU_MVFR0_FP_rounding_modes_Pos   28U
 
#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
 
#define FPU_MVFR0_Short_vectors_Pos   24U
 
#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)
 
#define FPU_MVFR0_Square_root_Pos   20U
 
#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)
 
#define FPU_MVFR0_Divide_Pos   16U
 
#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)
 
#define FPU_MVFR0_FP_excep_trapping_Pos   12U
 
#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
 
#define FPU_MVFR0_Double_precision_Pos   8U
 
#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)
 
#define FPU_MVFR0_Single_precision_Pos   4U
 
#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)
 
#define FPU_MVFR0_A_SIMD_registers_Pos   0U
 
#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
 
#define FPU_MVFR1_FP_fused_MAC_Pos   28U
 
#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
 
#define FPU_MVFR1_FP_HPFP_Pos   24U
 
#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
 
#define FPU_MVFR1_D_NaN_mode_Pos   4U
 
#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
 
#define FPU_MVFR1_FtZ_mode_Pos   0U
 
#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
 
#define FPU_FPCCR_ASPEN_Pos   31U
 
#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
 
#define FPU_FPCCR_LSPEN_Pos   30U
 
#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
 
#define FPU_FPCCR_MONRDY_Pos   8U
 
#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
 
#define FPU_FPCCR_BFRDY_Pos   6U
 
#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
 
#define FPU_FPCCR_MMRDY_Pos   5U
 
#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
 
#define FPU_FPCCR_HFRDY_Pos   4U
 
#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
 
#define FPU_FPCCR_THREAD_Pos   3U
 
#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
 
#define FPU_FPCCR_USER_Pos   1U
 
#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
 
#define FPU_FPCCR_LSPACT_Pos   0U
 
#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
 
#define FPU_FPCAR_ADDRESS_Pos   3U
 
#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
 
#define FPU_FPDSCR_AHP_Pos   26U
 
#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
 
#define FPU_FPDSCR_DN_Pos   25U
 
#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
 
#define FPU_FPDSCR_FZ_Pos   24U
 
#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
 
#define FPU_FPDSCR_RMode_Pos   22U
 
#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
 
#define FPU_MVFR0_FP_rounding_modes_Pos   28U
 
#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
 
#define FPU_MVFR0_Short_vectors_Pos   24U
 
#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)
 
#define FPU_MVFR0_Square_root_Pos   20U
 
#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)
 
#define FPU_MVFR0_Divide_Pos   16U
 
#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)
 
#define FPU_MVFR0_FP_excep_trapping_Pos   12U
 
#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
 
#define FPU_MVFR0_Double_precision_Pos   8U
 
#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)
 
#define FPU_MVFR0_Single_precision_Pos   4U
 
#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)
 
#define FPU_MVFR0_A_SIMD_registers_Pos   0U
 
#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
 
#define FPU_MVFR1_FP_fused_MAC_Pos   28U
 
#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
 
#define FPU_MVFR1_FP_HPFP_Pos   24U
 
#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
 
#define FPU_MVFR1_D_NaN_mode_Pos   4U
 
#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
 
#define FPU_MVFR1_FtZ_mode_Pos   0U
 
#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
 
#define FPU_FPCCR_ASPEN_Pos   31U
 
#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
 
#define FPU_FPCCR_LSPEN_Pos   30U
 
#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
 
#define FPU_FPCCR_MONRDY_Pos   8U
 
#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
 
#define FPU_FPCCR_BFRDY_Pos   6U
 
#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
 
#define FPU_FPCCR_MMRDY_Pos   5U
 
#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
 
#define FPU_FPCCR_HFRDY_Pos   4U
 
#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
 
#define FPU_FPCCR_THREAD_Pos   3U
 
#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
 
#define FPU_FPCCR_USER_Pos   1U
 
#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
 
#define FPU_FPCCR_LSPACT_Pos   0U
 
#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
 
#define FPU_FPCAR_ADDRESS_Pos   3U
 
#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
 
#define FPU_FPDSCR_AHP_Pos   26U
 
#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
 
#define FPU_FPDSCR_DN_Pos   25U
 
#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
 
#define FPU_FPDSCR_FZ_Pos   24U
 
#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
 
#define FPU_FPDSCR_RMode_Pos   22U
 
#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
 
#define FPU_MVFR0_FP_rounding_modes_Pos   28U
 
#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
 
#define FPU_MVFR0_Short_vectors_Pos   24U
 
#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)
 
#define FPU_MVFR0_Square_root_Pos   20U
 
#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)
 
#define FPU_MVFR0_Divide_Pos   16U
 
#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)
 
#define FPU_MVFR0_FP_excep_trapping_Pos   12U
 
#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
 
#define FPU_MVFR0_Double_precision_Pos   8U
 
#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)
 
#define FPU_MVFR0_Single_precision_Pos   4U
 
#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)
 
#define FPU_MVFR0_A_SIMD_registers_Pos   0U
 
#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
 
#define FPU_MVFR1_FP_fused_MAC_Pos   28U
 
#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
 
#define FPU_MVFR1_FP_HPFP_Pos   24U
 
#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
 
#define FPU_MVFR1_D_NaN_mode_Pos   4U
 
#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
 
#define FPU_MVFR1_FtZ_mode_Pos   0U
 
#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
 
#define FPU_MVFR2_VFP_Misc_Pos   4U
 
#define FPU_MVFR2_VFP_Misc_Msk   (0xFUL << FPU_MVFR2_VFP_Misc_Pos)
 
#define FPU_FPCCR_ASPEN_Pos   31U
 
#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
 
#define FPU_FPCCR_LSPEN_Pos   30U
 
#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
 
#define FPU_FPCCR_MONRDY_Pos   8U
 
#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
 
#define FPU_FPCCR_BFRDY_Pos   6U
 
#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
 
#define FPU_FPCCR_MMRDY_Pos   5U
 
#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
 
#define FPU_FPCCR_HFRDY_Pos   4U
 
#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
 
#define FPU_FPCCR_THREAD_Pos   3U
 
#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
 
#define FPU_FPCCR_USER_Pos   1U
 
#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
 
#define FPU_FPCCR_LSPACT_Pos   0U
 
#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
 
#define FPU_FPCAR_ADDRESS_Pos   3U
 
#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
 
#define FPU_FPDSCR_AHP_Pos   26U
 
#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
 
#define FPU_FPDSCR_DN_Pos   25U
 
#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
 
#define FPU_FPDSCR_FZ_Pos   24U
 
#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
 
#define FPU_FPDSCR_RMode_Pos   22U
 
#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
 
#define FPU_FPCCR_ASPEN_Pos   31U
 
#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
 
#define FPU_FPCCR_LSPEN_Pos   30U
 
#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
 
#define FPU_FPCCR_MONRDY_Pos   8U
 
#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
 
#define FPU_FPCCR_BFRDY_Pos   6U
 
#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
 
#define FPU_FPCCR_MMRDY_Pos   5U
 
#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
 
#define FPU_FPCCR_HFRDY_Pos   4U
 
#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
 
#define FPU_FPCCR_THREAD_Pos   3U
 
#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
 
#define FPU_FPCCR_USER_Pos   1U
 
#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
 
#define FPU_FPCCR_LSPACT_Pos   0U
 
#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
 
#define FPU_FPCAR_ADDRESS_Pos   3U
 
#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
 
#define FPU_FPDSCR_AHP_Pos   26U
 
#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
 
#define FPU_FPDSCR_DN_Pos   25U
 
#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
 
#define FPU_FPDSCR_FZ_Pos   24U
 
#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
 
#define FPU_FPDSCR_RMode_Pos   22U
 
#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
 
#define FPU_MVFR0_FP_rounding_modes_Pos   28U
 
#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
 
#define FPU_MVFR0_Short_vectors_Pos   24U
 
#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)
 
#define FPU_MVFR0_Square_root_Pos   20U
 
#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)
 
#define FPU_MVFR0_Divide_Pos   16U
 
#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)
 
#define FPU_MVFR0_FP_excep_trapping_Pos   12U
 
#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
 
#define FPU_MVFR0_Double_precision_Pos   8U
 
#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)
 
#define FPU_MVFR0_Single_precision_Pos   4U
 
#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)
 
#define FPU_MVFR0_A_SIMD_registers_Pos   0U
 
#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
 
#define FPU_MVFR1_FP_fused_MAC_Pos   28U
 
#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
 
#define FPU_MVFR1_FP_HPFP_Pos   24U
 
#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
 
#define FPU_MVFR1_D_NaN_mode_Pos   4U
 
#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
 
#define FPU_MVFR1_FtZ_mode_Pos   0U
 
#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
 
#define FPU_MVFR2_VFP_Misc_Pos   4U
 
#define FPU_MVFR2_VFP_Misc_Msk   (0xFUL << FPU_MVFR2_VFP_Misc_Pos)
 
#define FPU_FPCCR_ASPEN_Pos   31U
 
#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
 
#define FPU_FPCCR_LSPEN_Pos   30U
 
#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
 
#define FPU_FPCCR_MONRDY_Pos   8U
 
#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
 
#define FPU_FPCCR_BFRDY_Pos   6U
 
#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
 
#define FPU_FPCCR_MMRDY_Pos   5U
 
#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
 
#define FPU_FPCCR_HFRDY_Pos   4U
 
#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
 
#define FPU_FPCCR_THREAD_Pos   3U
 
#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
 
#define FPU_FPCCR_USER_Pos   1U
 
#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
 
#define FPU_FPCCR_LSPACT_Pos   0U
 
#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
 
#define FPU_FPCAR_ADDRESS_Pos   3U
 
#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
 
#define FPU_FPDSCR_AHP_Pos   26U
 
#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
 
#define FPU_FPDSCR_DN_Pos   25U
 
#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
 
#define FPU_FPDSCR_FZ_Pos   24U
 
#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
 
#define FPU_FPDSCR_RMode_Pos   22U
 
#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
 
#define FPU_FPCCR_ASPEN_Pos   31U
 
#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
 
#define FPU_FPCCR_LSPEN_Pos   30U
 
#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
 
#define FPU_FPCCR_MONRDY_Pos   8U
 
#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
 
#define FPU_FPCCR_BFRDY_Pos   6U
 
#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
 
#define FPU_FPCCR_MMRDY_Pos   5U
 
#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
 
#define FPU_FPCCR_HFRDY_Pos   4U
 
#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
 
#define FPU_FPCCR_THREAD_Pos   3U
 
#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
 
#define FPU_FPCCR_USER_Pos   1U
 
#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
 
#define FPU_FPCCR_LSPACT_Pos   0U
 
#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
 
#define FPU_FPCAR_ADDRESS_Pos   3U
 
#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
 
#define FPU_FPDSCR_AHP_Pos   26U
 
#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
 
#define FPU_FPDSCR_DN_Pos   25U
 
#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
 
#define FPU_FPDSCR_FZ_Pos   24U
 
#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
 
#define FPU_FPDSCR_RMode_Pos   22U
 
#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
 
#define FPU_MVFR0_FP_rounding_modes_Pos   28U
 
#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
 
#define FPU_MVFR0_Short_vectors_Pos   24U
 
#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)
 
#define FPU_MVFR0_Square_root_Pos   20U
 
#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)
 
#define FPU_MVFR0_Divide_Pos   16U
 
#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)
 
#define FPU_MVFR0_FP_excep_trapping_Pos   12U
 
#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
 
#define FPU_MVFR0_Double_precision_Pos   8U
 
#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)
 
#define FPU_MVFR0_Single_precision_Pos   4U
 
#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)
 
#define FPU_MVFR0_A_SIMD_registers_Pos   0U
 
#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
 
#define FPU_MVFR1_FP_fused_MAC_Pos   28U
 
#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
 
#define FPU_MVFR1_FP_HPFP_Pos   24U
 
#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
 
#define FPU_MVFR1_D_NaN_mode_Pos   4U
 
#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
 
#define FPU_MVFR1_FtZ_mode_Pos   0U
 
#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
 
#define FPU_FPCCR_ASPEN_Pos   31U
 
#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
 
#define FPU_FPCCR_LSPEN_Pos   30U
 
#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
 
#define FPU_FPCCR_MONRDY_Pos   8U
 
#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
 
#define FPU_FPCCR_BFRDY_Pos   6U
 
#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
 
#define FPU_FPCCR_MMRDY_Pos   5U
 
#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
 
#define FPU_FPCCR_HFRDY_Pos   4U
 
#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
 
#define FPU_FPCCR_THREAD_Pos   3U
 
#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
 
#define FPU_FPCCR_USER_Pos   1U
 
#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
 
#define FPU_FPCCR_LSPACT_Pos   0U
 
#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
 
#define FPU_FPCAR_ADDRESS_Pos   3U
 
#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
 
#define FPU_FPDSCR_AHP_Pos   26U
 
#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
 
#define FPU_FPDSCR_DN_Pos   25U
 
#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
 
#define FPU_FPDSCR_FZ_Pos   24U
 
#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
 
#define FPU_FPDSCR_RMode_Pos   22U
 
#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
 
#define FPU_FPCCR_ASPEN_Pos   31U
 
#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
 
#define FPU_FPCCR_LSPEN_Pos   30U
 
#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
 
#define FPU_FPCCR_MONRDY_Pos   8U
 
#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
 
#define FPU_FPCCR_BFRDY_Pos   6U
 
#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
 
#define FPU_FPCCR_MMRDY_Pos   5U
 
#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
 
#define FPU_FPCCR_HFRDY_Pos   4U
 
#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
 
#define FPU_FPCCR_THREAD_Pos   3U
 
#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
 
#define FPU_FPCCR_USER_Pos   1U
 
#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
 
#define FPU_FPCCR_LSPACT_Pos   0U
 
#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
 
#define FPU_FPCAR_ADDRESS_Pos   3U
 
#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
 
#define FPU_FPDSCR_AHP_Pos   26U
 
#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
 
#define FPU_FPDSCR_DN_Pos   25U
 
#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
 
#define FPU_FPDSCR_FZ_Pos   24U
 
#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
 
#define FPU_FPDSCR_RMode_Pos   22U
 
#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
 
#define FPU_MVFR0_FP_rounding_modes_Pos   28U
 
#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
 
#define FPU_MVFR0_Short_vectors_Pos   24U
 
#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)
 
#define FPU_MVFR0_Square_root_Pos   20U
 
#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)
 
#define FPU_MVFR0_Divide_Pos   16U
 
#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)
 
#define FPU_MVFR0_FP_excep_trapping_Pos   12U
 
#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
 
#define FPU_MVFR0_Double_precision_Pos   8U
 
#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)
 
#define FPU_MVFR0_Single_precision_Pos   4U
 
#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)
 
#define FPU_MVFR0_A_SIMD_registers_Pos   0U
 
#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
 
#define FPU_MVFR1_FP_fused_MAC_Pos   28U
 
#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
 
#define FPU_MVFR1_FP_HPFP_Pos   24U
 
#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
 
#define FPU_MVFR1_D_NaN_mode_Pos   4U
 
#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
 
#define FPU_MVFR1_FtZ_mode_Pos   0U
 
#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
 
#define FPU_FPCCR_ASPEN_Pos   31U
 
#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
 
#define FPU_FPCCR_LSPEN_Pos   30U
 
#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
 
#define FPU_FPCCR_MONRDY_Pos   8U
 
#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
 
#define FPU_FPCCR_BFRDY_Pos   6U
 
#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
 
#define FPU_FPCCR_MMRDY_Pos   5U
 
#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
 
#define FPU_FPCCR_HFRDY_Pos   4U
 
#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
 
#define FPU_FPCCR_THREAD_Pos   3U
 
#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
 
#define FPU_FPCCR_USER_Pos   1U
 
#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
 
#define FPU_FPCCR_LSPACT_Pos   0U
 
#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
 
#define FPU_FPCAR_ADDRESS_Pos   3U
 
#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
 
#define FPU_FPDSCR_AHP_Pos   26U
 
#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
 
#define FPU_FPDSCR_DN_Pos   25U
 
#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
 
#define FPU_FPDSCR_FZ_Pos   24U
 
#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
 
#define FPU_FPDSCR_RMode_Pos   22U
 
#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
 
#define FPU_MVFR0_FP_rounding_modes_Pos   28U
 
#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
 
#define FPU_MVFR0_Short_vectors_Pos   24U
 
#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)
 
#define FPU_MVFR0_Square_root_Pos   20U
 
#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)
 
#define FPU_MVFR0_Divide_Pos   16U
 
#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)
 
#define FPU_MVFR0_FP_excep_trapping_Pos   12U
 
#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
 
#define FPU_MVFR0_Double_precision_Pos   8U
 
#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)
 
#define FPU_MVFR0_Single_precision_Pos   4U
 
#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)
 
#define FPU_MVFR0_A_SIMD_registers_Pos   0U
 
#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
 
#define FPU_MVFR1_FP_fused_MAC_Pos   28U
 
#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
 
#define FPU_MVFR1_FP_HPFP_Pos   24U
 
#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
 
#define FPU_MVFR1_D_NaN_mode_Pos   4U
 
#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
 
#define FPU_MVFR1_FtZ_mode_Pos   0U
 
#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
 
#define FPU_FPCCR_ASPEN_Pos   31U
 
#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
 
#define FPU_FPCCR_LSPEN_Pos   30U
 
#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
 
#define FPU_FPCCR_MONRDY_Pos   8U
 
#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
 
#define FPU_FPCCR_BFRDY_Pos   6U
 
#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
 
#define FPU_FPCCR_MMRDY_Pos   5U
 
#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
 
#define FPU_FPCCR_HFRDY_Pos   4U
 
#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
 
#define FPU_FPCCR_THREAD_Pos   3U
 
#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
 
#define FPU_FPCCR_USER_Pos   1U
 
#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
 
#define FPU_FPCCR_LSPACT_Pos   0U
 
#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
 
#define FPU_FPCAR_ADDRESS_Pos   3U
 
#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
 
#define FPU_FPDSCR_AHP_Pos   26U
 
#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
 
#define FPU_FPDSCR_DN_Pos   25U
 
#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
 
#define FPU_FPDSCR_FZ_Pos   24U
 
#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
 
#define FPU_FPDSCR_RMode_Pos   22U
 
#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
 
#define FPU_MVFR0_FP_rounding_modes_Pos   28U
 
#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
 
#define FPU_MVFR0_Short_vectors_Pos   24U
 
#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)
 
#define FPU_MVFR0_Square_root_Pos   20U
 
#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)
 
#define FPU_MVFR0_Divide_Pos   16U
 
#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)
 
#define FPU_MVFR0_FP_excep_trapping_Pos   12U
 
#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
 
#define FPU_MVFR0_Double_precision_Pos   8U
 
#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)
 
#define FPU_MVFR0_Single_precision_Pos   4U
 
#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)
 
#define FPU_MVFR0_A_SIMD_registers_Pos   0U
 
#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
 
#define FPU_MVFR1_FP_fused_MAC_Pos   28U
 
#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
 
#define FPU_MVFR1_FP_HPFP_Pos   24U
 
#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
 
#define FPU_MVFR1_D_NaN_mode_Pos   4U
 
#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
 
#define FPU_MVFR1_FtZ_mode_Pos   0U
 
#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
 
#define FPU_MVFR2_VFP_Misc_Pos   4U
 
#define FPU_MVFR2_VFP_Misc_Msk   (0xFUL << FPU_MVFR2_VFP_Misc_Pos)
 
#define FPU_FPCCR_LSPENS_Pos   29U
 
#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)
 
#define FPU_FPCCR_CLRONRET_Pos   28U
 
#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)
 
#define FPU_FPCCR_CLRONRETS_Pos   27U
 
#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)
 
#define FPU_FPCCR_TS_Pos   26U
 
#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)
 
#define FPU_FPCCR_UFRDY_Pos   10U
 
#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)
 
#define FPU_FPCCR_SPLIMVIOL_Pos   9U
 
#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
 
#define FPU_FPCCR_SFRDY_Pos   7U
 
#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)
 
#define FPU_FPCCR_S_Pos   2U
 
#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)
 
#define FPU_MVFR2_FPMisc_Pos   4U
 
#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)
 
#define FPU_FPCCR_LSPENS_Pos   29U
 
#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)
 
#define FPU_FPCCR_CLRONRET_Pos   28U
 
#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)
 
#define FPU_FPCCR_CLRONRETS_Pos   27U
 
#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)
 
#define FPU_FPCCR_TS_Pos   26U
 
#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)
 
#define FPU_FPCCR_UFRDY_Pos   10U
 
#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)
 
#define FPU_FPCCR_SPLIMVIOL_Pos   9U
 
#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
 
#define FPU_FPCCR_SFRDY_Pos   7U
 
#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)
 
#define FPU_FPCCR_S_Pos   2U
 
#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)
 
#define FPU_MVFR2_FPMisc_Pos   4U
 
#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)
 
#define FPU_FPCCR_LSPENS_Pos   29U
 
#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)
 
#define FPU_FPCCR_CLRONRET_Pos   28U
 
#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)
 
#define FPU_FPCCR_CLRONRETS_Pos   27U
 
#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)
 
#define FPU_FPCCR_TS_Pos   26U
 
#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)
 
#define FPU_FPCCR_UFRDY_Pos   10U
 
#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)
 
#define FPU_FPCCR_SPLIMVIOL_Pos   9U
 
#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
 
#define FPU_FPCCR_SFRDY_Pos   7U
 
#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)
 
#define FPU_FPCCR_S_Pos   2U
 
#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)
 
#define FPU_MVFR2_FPMisc_Pos   4U
 
#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)
 
#define FPU_FPCCR_LSPENS_Pos   29U
 
#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)
 
#define FPU_FPCCR_CLRONRET_Pos   28U
 
#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)
 
#define FPU_FPCCR_CLRONRETS_Pos   27U
 
#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)
 
#define FPU_FPCCR_TS_Pos   26U
 
#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)
 
#define FPU_FPCCR_UFRDY_Pos   10U
 
#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)
 
#define FPU_FPCCR_SPLIMVIOL_Pos   9U
 
#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
 
#define FPU_FPCCR_SFRDY_Pos   7U
 
#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)
 
#define FPU_FPCCR_S_Pos   2U
 
#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)
 
#define FPU_MVFR2_FPMisc_Pos   4U
 
#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)
 
#define FPU_FPCCR_LSPENS_Pos   29U
 
#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)
 
#define FPU_FPCCR_CLRONRET_Pos   28U
 
#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)
 
#define FPU_FPCCR_CLRONRETS_Pos   27U
 
#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)
 
#define FPU_FPCCR_TS_Pos   26U
 
#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)
 
#define FPU_FPCCR_UFRDY_Pos   10U
 
#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)
 
#define FPU_FPCCR_SPLIMVIOL_Pos   9U
 
#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
 
#define FPU_FPCCR_SFRDY_Pos   7U
 
#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)
 
#define FPU_FPCCR_S_Pos   2U
 
#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)
 
#define FPU_MVFR2_FPMisc_Pos   4U
 
#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)
 
#define FPU_FPCCR_LSPENS_Pos   29U
 
#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)
 
#define FPU_FPCCR_CLRONRET_Pos   28U
 
#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)
 
#define FPU_FPCCR_CLRONRETS_Pos   27U
 
#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)
 
#define FPU_FPCCR_TS_Pos   26U
 
#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)
 
#define FPU_FPCCR_UFRDY_Pos   10U
 
#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)
 
#define FPU_FPCCR_SPLIMVIOL_Pos   9U
 
#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
 
#define FPU_FPCCR_SFRDY_Pos   7U
 
#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)
 
#define FPU_FPCCR_S_Pos   2U
 
#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)
 
#define FPU_MVFR2_FPMisc_Pos   4U
 
#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)
 
#define FPU_FPCCR_LSPENS_Pos   29U
 
#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)
 
#define FPU_FPCCR_CLRONRET_Pos   28U
 
#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)
 
#define FPU_FPCCR_CLRONRETS_Pos   27U
 
#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)
 
#define FPU_FPCCR_TS_Pos   26U
 
#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)
 
#define FPU_FPCCR_UFRDY_Pos   10U
 
#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)
 
#define FPU_FPCCR_SPLIMVIOL_Pos   9U
 
#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
 
#define FPU_FPCCR_SFRDY_Pos   7U
 
#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)
 
#define FPU_FPCCR_S_Pos   2U
 
#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)
 
#define FPU_MVFR2_FPMisc_Pos   4U
 
#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)
 
#define FPU_FPCCR_LSPENS_Pos   29U
 
#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)
 
#define FPU_FPCCR_CLRONRET_Pos   28U
 
#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)
 
#define FPU_FPCCR_CLRONRETS_Pos   27U
 
#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)
 
#define FPU_FPCCR_TS_Pos   26U
 
#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)
 
#define FPU_FPCCR_UFRDY_Pos   10U
 
#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)
 
#define FPU_FPCCR_SPLIMVIOL_Pos   9U
 
#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
 
#define FPU_FPCCR_SFRDY_Pos   7U
 
#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)
 
#define FPU_FPCCR_S_Pos   2U
 
#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)
 
#define FPU_MVFR2_FPMisc_Pos   4U
 
#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)
 
#define FPU_FPCCR_LSPENS_Pos   29U
 
#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)
 
#define FPU_FPCCR_CLRONRET_Pos   28U
 
#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)
 
#define FPU_FPCCR_CLRONRETS_Pos   27U
 
#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)
 
#define FPU_FPCCR_TS_Pos   26U
 
#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)
 
#define FPU_FPCCR_UFRDY_Pos   10U
 
#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)
 
#define FPU_FPCCR_SPLIMVIOL_Pos   9U
 
#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
 
#define FPU_FPCCR_SFRDY_Pos   7U
 
#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)
 
#define FPU_FPCCR_S_Pos   2U
 
#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)
 
#define FPU_MVFR2_FPMisc_Pos   4U
 
#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)
 
#define FPU_FPCCR_LSPENS_Pos   29U
 
#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)
 
#define FPU_FPCCR_CLRONRET_Pos   28U
 
#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)
 
#define FPU_FPCCR_CLRONRETS_Pos   27U
 
#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)
 
#define FPU_FPCCR_TS_Pos   26U
 
#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)
 
#define FPU_FPCCR_UFRDY_Pos   10U
 
#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)
 
#define FPU_FPCCR_SPLIMVIOL_Pos   9U
 
#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
 
#define FPU_FPCCR_SFRDY_Pos   7U
 
#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)
 
#define FPU_FPCCR_S_Pos   2U
 
#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)
 
#define FPU_MVFR2_FPMisc_Pos   4U
 
#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)
 
#define FPU_FPDSCR_FZ16_Pos   19U
 
#define FPU_FPDSCR_FZ16_Msk   (1UL << FPU_FPDSCR_FZ16_Pos)
 
#define FPU_FPDSCR_LTPSIZE_Pos   16U
 
#define FPU_FPDSCR_LTPSIZE_Msk   (7UL << FPU_FPDSCR_LTPSIZE_Pos)
 
#define FPU_MVFR0_FPRound_Pos   28U
 
#define FPU_MVFR0_FPRound_Msk   (0xFUL << FPU_MVFR0_FPRound_Pos)
 
#define FPU_MVFR0_FPSqrt_Pos   20U
 
#define FPU_MVFR0_FPSqrt_Msk   (0xFUL << FPU_MVFR0_FPSqrt_Pos)
 
#define FPU_MVFR0_FPDivide_Pos   16U
 
#define FPU_MVFR0_FPDivide_Msk   (0xFUL << FPU_MVFR0_FPDivide_Pos)
 
#define FPU_MVFR0_FPDP_Pos   8U
 
#define FPU_MVFR0_FPDP_Msk   (0xFUL << FPU_MVFR0_FPDP_Pos)
 
#define FPU_MVFR0_FPSP_Pos   4U
 
#define FPU_MVFR0_FPSP_Msk   (0xFUL << FPU_MVFR0_FPSP_Pos)
 
#define FPU_MVFR0_SIMDReg_Pos   0U
 
#define FPU_MVFR0_SIMDReg_Msk   (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)
 
#define FPU_MVFR1_FMAC_Pos   28U
 
#define FPU_MVFR1_FMAC_Msk   (0xFUL << FPU_MVFR1_FMAC_Pos)
 
#define FPU_MVFR1_FPHP_Pos   24U
 
#define FPU_MVFR1_FPHP_Msk   (0xFUL << FPU_MVFR1_FPHP_Pos)
 
#define FPU_MVFR1_FP16_Pos   20U
 
#define FPU_MVFR1_FP16_Msk   (0xFUL << FPU_MVFR1_FP16_Pos)
 
#define FPU_MVFR1_MVE_Pos   8U
 
#define FPU_MVFR1_MVE_Msk   (0xFUL << FPU_MVFR1_MVE_Pos)
 
#define FPU_MVFR1_FPDNaN_Pos   4U
 
#define FPU_MVFR1_FPDNaN_Msk   (0xFUL << FPU_MVFR1_FPDNaN_Pos)
 
#define FPU_MVFR1_FPFtZ_Pos   0U
 
#define FPU_MVFR1_FPFtZ_Msk   (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)
 
#define FPU_FPDSCR_FZ16_Pos   19U
 
#define FPU_FPDSCR_FZ16_Msk   (1UL << FPU_FPDSCR_FZ16_Pos)
 
#define FPU_FPDSCR_LTPSIZE_Pos   16U
 
#define FPU_FPDSCR_LTPSIZE_Msk   (7UL << FPU_FPDSCR_LTPSIZE_Pos)
 
#define FPU_MVFR0_FPRound_Pos   28U
 
#define FPU_MVFR0_FPRound_Msk   (0xFUL << FPU_MVFR0_FPRound_Pos)
 
#define FPU_MVFR0_FPSqrt_Pos   20U
 
#define FPU_MVFR0_FPSqrt_Msk   (0xFUL << FPU_MVFR0_FPSqrt_Pos)
 
#define FPU_MVFR0_FPDivide_Pos   16U
 
#define FPU_MVFR0_FPDivide_Msk   (0xFUL << FPU_MVFR0_FPDivide_Pos)
 
#define FPU_MVFR0_FPDP_Pos   8U
 
#define FPU_MVFR0_FPDP_Msk   (0xFUL << FPU_MVFR0_FPDP_Pos)
 
#define FPU_MVFR0_FPSP_Pos   4U
 
#define FPU_MVFR0_FPSP_Msk   (0xFUL << FPU_MVFR0_FPSP_Pos)
 
#define FPU_MVFR0_SIMDReg_Pos   0U
 
#define FPU_MVFR0_SIMDReg_Msk   (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)
 
#define FPU_MVFR1_FMAC_Pos   28U
 
#define FPU_MVFR1_FMAC_Msk   (0xFUL << FPU_MVFR1_FMAC_Pos)
 
#define FPU_MVFR1_FPHP_Pos   24U
 
#define FPU_MVFR1_FPHP_Msk   (0xFUL << FPU_MVFR1_FPHP_Pos)
 
#define FPU_MVFR1_FP16_Pos   20U
 
#define FPU_MVFR1_FP16_Msk   (0xFUL << FPU_MVFR1_FP16_Pos)
 
#define FPU_MVFR1_MVE_Pos   8U
 
#define FPU_MVFR1_MVE_Msk   (0xFUL << FPU_MVFR1_MVE_Pos)
 
#define FPU_MVFR1_FPDNaN_Pos   4U
 
#define FPU_MVFR1_FPDNaN_Msk   (0xFUL << FPU_MVFR1_FPDNaN_Pos)
 
#define FPU_MVFR1_FPFtZ_Pos   0U
 
#define FPU_MVFR1_FPFtZ_Msk   (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)
 
#define FPU_FPDSCR_FZ16_Pos   19U
 
#define FPU_FPDSCR_FZ16_Msk   (1UL << FPU_FPDSCR_FZ16_Pos)
 
#define FPU_FPDSCR_LTPSIZE_Pos   16U
 
#define FPU_FPDSCR_LTPSIZE_Msk   (7UL << FPU_FPDSCR_LTPSIZE_Pos)
 
#define FPU_MVFR0_FPRound_Pos   28U
 
#define FPU_MVFR0_FPRound_Msk   (0xFUL << FPU_MVFR0_FPRound_Pos)
 
#define FPU_MVFR0_FPSqrt_Pos   20U
 
#define FPU_MVFR0_FPSqrt_Msk   (0xFUL << FPU_MVFR0_FPSqrt_Pos)
 
#define FPU_MVFR0_FPDivide_Pos   16U
 
#define FPU_MVFR0_FPDivide_Msk   (0xFUL << FPU_MVFR0_FPDivide_Pos)
 
#define FPU_MVFR0_FPDP_Pos   8U
 
#define FPU_MVFR0_FPDP_Msk   (0xFUL << FPU_MVFR0_FPDP_Pos)
 
#define FPU_MVFR0_FPSP_Pos   4U
 
#define FPU_MVFR0_FPSP_Msk   (0xFUL << FPU_MVFR0_FPSP_Pos)
 
#define FPU_MVFR0_SIMDReg_Pos   0U
 
#define FPU_MVFR0_SIMDReg_Msk   (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)
 
#define FPU_MVFR1_FMAC_Pos   28U
 
#define FPU_MVFR1_FMAC_Msk   (0xFUL << FPU_MVFR1_FMAC_Pos)
 
#define FPU_MVFR1_FPHP_Pos   24U
 
#define FPU_MVFR1_FPHP_Msk   (0xFUL << FPU_MVFR1_FPHP_Pos)
 
#define FPU_MVFR1_FP16_Pos   20U
 
#define FPU_MVFR1_FP16_Msk   (0xFUL << FPU_MVFR1_FP16_Pos)
 
#define FPU_MVFR1_MVE_Pos   8U
 
#define FPU_MVFR1_MVE_Msk   (0xFUL << FPU_MVFR1_MVE_Pos)
 
#define FPU_MVFR1_FPDNaN_Pos   4U
 
#define FPU_MVFR1_FPDNaN_Msk   (0xFUL << FPU_MVFR1_FPDNaN_Pos)
 
#define FPU_MVFR1_FPFtZ_Pos   0U
 
#define FPU_MVFR1_FPFtZ_Msk   (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)
 
#define FPU_FPDSCR_FZ16_Pos   19U
 
#define FPU_FPDSCR_FZ16_Msk   (1UL << FPU_FPDSCR_FZ16_Pos)
 
#define FPU_FPDSCR_LTPSIZE_Pos   16U
 
#define FPU_FPDSCR_LTPSIZE_Msk   (7UL << FPU_FPDSCR_LTPSIZE_Pos)
 
#define FPU_MVFR0_FPRound_Pos   28U
 
#define FPU_MVFR0_FPRound_Msk   (0xFUL << FPU_MVFR0_FPRound_Pos)
 
#define FPU_MVFR0_FPSqrt_Pos   20U
 
#define FPU_MVFR0_FPSqrt_Msk   (0xFUL << FPU_MVFR0_FPSqrt_Pos)
 
#define FPU_MVFR0_FPDivide_Pos   16U
 
#define FPU_MVFR0_FPDivide_Msk   (0xFUL << FPU_MVFR0_FPDivide_Pos)
 
#define FPU_MVFR0_FPDP_Pos   8U
 
#define FPU_MVFR0_FPDP_Msk   (0xFUL << FPU_MVFR0_FPDP_Pos)
 
#define FPU_MVFR0_FPSP_Pos   4U
 
#define FPU_MVFR0_FPSP_Msk   (0xFUL << FPU_MVFR0_FPSP_Pos)
 
#define FPU_MVFR0_SIMDReg_Pos   0U
 
#define FPU_MVFR0_SIMDReg_Msk   (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)
 
#define FPU_MVFR1_FMAC_Pos   28U
 
#define FPU_MVFR1_FMAC_Msk   (0xFUL << FPU_MVFR1_FMAC_Pos)
 
#define FPU_MVFR1_FPHP_Pos   24U
 
#define FPU_MVFR1_FPHP_Msk   (0xFUL << FPU_MVFR1_FPHP_Pos)
 
#define FPU_MVFR1_FP16_Pos   20U
 
#define FPU_MVFR1_FP16_Msk   (0xFUL << FPU_MVFR1_FP16_Pos)
 
#define FPU_MVFR1_MVE_Pos   8U
 
#define FPU_MVFR1_MVE_Msk   (0xFUL << FPU_MVFR1_MVE_Pos)
 
#define FPU_MVFR1_FPDNaN_Pos   4U
 
#define FPU_MVFR1_FPDNaN_Msk   (0xFUL << FPU_MVFR1_FPDNaN_Pos)
 
#define FPU_MVFR1_FPFtZ_Pos   0U
 
#define FPU_MVFR1_FPFtZ_Msk   (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)
 

Detailed Description

Type definitions for the Floating Point Unit (FPU)

Macro Definition Documentation

◆ FPU_FPCAR_ADDRESS_Msk [1/13]

#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 2570 of file core_armv81mml.h.

◆ FPU_FPCAR_ADDRESS_Msk [2/13]

#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1689 of file core_armv8mml.h.

◆ FPU_FPCAR_ADDRESS_Msk [3/13]

#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1764 of file core_cm33.h.

◆ FPU_FPCAR_ADDRESS_Msk [4/13]

#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1764 of file core_cm35p.h.

◆ FPU_FPCAR_ADDRESS_Msk [5/13]

#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1362 of file core_cm4.h.

◆ FPU_FPCAR_ADDRESS_Msk [6/13]

#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 3124 of file core_cm55.h.

◆ FPU_FPCAR_ADDRESS_Msk [7/13]

#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1589 of file core_cm7.h.

◆ FPU_FPCAR_ADDRESS_Msk [8/13]

#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 3029 of file core_cm85.h.

◆ FPU_FPCAR_ADDRESS_Msk [9/13]

#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1822 of file core_starmc1.h.

◆ FPU_FPCAR_ADDRESS_Msk [10/13]

#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 2570 of file core_armv81mml.h.

◆ FPU_FPCAR_ADDRESS_Msk [11/13]

#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1689 of file core_armv8mml.h.

◆ FPU_FPCAR_ADDRESS_Msk [12/13]

#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1764 of file core_cm33.h.

◆ FPU_FPCAR_ADDRESS_Msk [13/13]

#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1362 of file core_cm4.h.

◆ FPU_FPCAR_ADDRESS_Pos [1/13]

#define FPU_FPCAR_ADDRESS_Pos   3U

FPCAR: ADDRESS bit Position

Definition at line 2569 of file core_armv81mml.h.

◆ FPU_FPCAR_ADDRESS_Pos [2/13]

#define FPU_FPCAR_ADDRESS_Pos   3U

FPCAR: ADDRESS bit Position

Definition at line 1688 of file core_armv8mml.h.

◆ FPU_FPCAR_ADDRESS_Pos [3/13]

#define FPU_FPCAR_ADDRESS_Pos   3U

FPCAR: ADDRESS bit Position

Definition at line 1763 of file core_cm33.h.

◆ FPU_FPCAR_ADDRESS_Pos [4/13]

#define FPU_FPCAR_ADDRESS_Pos   3U

FPCAR: ADDRESS bit Position

Definition at line 1763 of file core_cm35p.h.

◆ FPU_FPCAR_ADDRESS_Pos [5/13]

#define FPU_FPCAR_ADDRESS_Pos   3U

FPCAR: ADDRESS bit Position

Definition at line 1361 of file core_cm4.h.

◆ FPU_FPCAR_ADDRESS_Pos [6/13]

#define FPU_FPCAR_ADDRESS_Pos   3U

FPCAR: ADDRESS bit Position

Definition at line 3123 of file core_cm55.h.

◆ FPU_FPCAR_ADDRESS_Pos [7/13]

#define FPU_FPCAR_ADDRESS_Pos   3U

FPCAR: ADDRESS bit Position

Definition at line 1588 of file core_cm7.h.

◆ FPU_FPCAR_ADDRESS_Pos [8/13]

#define FPU_FPCAR_ADDRESS_Pos   3U

FPCAR: ADDRESS bit Position

Definition at line 3028 of file core_cm85.h.

◆ FPU_FPCAR_ADDRESS_Pos [9/13]

#define FPU_FPCAR_ADDRESS_Pos   3U

FPCAR: ADDRESS bit Position

Definition at line 1821 of file core_starmc1.h.

◆ FPU_FPCAR_ADDRESS_Pos [10/13]

#define FPU_FPCAR_ADDRESS_Pos   3U

FPCAR: ADDRESS bit Position

Definition at line 2569 of file core_armv81mml.h.

◆ FPU_FPCAR_ADDRESS_Pos [11/13]

#define FPU_FPCAR_ADDRESS_Pos   3U

FPCAR: ADDRESS bit Position

Definition at line 1688 of file core_armv8mml.h.

◆ FPU_FPCAR_ADDRESS_Pos [12/13]

#define FPU_FPCAR_ADDRESS_Pos   3U

FPCAR: ADDRESS bit Position

Definition at line 1763 of file core_cm33.h.

◆ FPU_FPCAR_ADDRESS_Pos [13/13]

#define FPU_FPCAR_ADDRESS_Pos   3U

FPCAR: ADDRESS bit Position

Definition at line 1361 of file core_cm4.h.

◆ FPU_FPCCR_ASPEN_Msk [1/13]

#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 2518 of file core_armv81mml.h.

◆ FPU_FPCCR_ASPEN_Msk [2/13]

#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1637 of file core_armv8mml.h.

◆ FPU_FPCCR_ASPEN_Msk [3/13]

#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1712 of file core_cm33.h.

◆ FPU_FPCCR_ASPEN_Msk [4/13]

#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1712 of file core_cm35p.h.

◆ FPU_FPCCR_ASPEN_Msk [5/13]

#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1334 of file core_cm4.h.

◆ FPU_FPCCR_ASPEN_Msk [6/13]

#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 3072 of file core_cm55.h.

◆ FPU_FPCCR_ASPEN_Msk [7/13]

#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1561 of file core_cm7.h.

◆ FPU_FPCCR_ASPEN_Msk [8/13]

#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 2977 of file core_cm85.h.

◆ FPU_FPCCR_ASPEN_Msk [9/13]

#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1770 of file core_starmc1.h.

◆ FPU_FPCCR_ASPEN_Msk [10/13]

#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 2518 of file core_armv81mml.h.

◆ FPU_FPCCR_ASPEN_Msk [11/13]

#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1637 of file core_armv8mml.h.

◆ FPU_FPCCR_ASPEN_Msk [12/13]

#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1712 of file core_cm33.h.

◆ FPU_FPCCR_ASPEN_Msk [13/13]

#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1334 of file core_cm4.h.

◆ FPU_FPCCR_ASPEN_Pos [1/13]

#define FPU_FPCCR_ASPEN_Pos   31U

FPCCR: ASPEN bit Position

Definition at line 2517 of file core_armv81mml.h.

◆ FPU_FPCCR_ASPEN_Pos [2/13]

#define FPU_FPCCR_ASPEN_Pos   31U

FPCCR: ASPEN bit Position

Definition at line 1636 of file core_armv8mml.h.

◆ FPU_FPCCR_ASPEN_Pos [3/13]

#define FPU_FPCCR_ASPEN_Pos   31U

FPCCR: ASPEN bit Position

Definition at line 1711 of file core_cm33.h.

◆ FPU_FPCCR_ASPEN_Pos [4/13]

#define FPU_FPCCR_ASPEN_Pos   31U

FPCCR: ASPEN bit Position

Definition at line 1711 of file core_cm35p.h.

◆ FPU_FPCCR_ASPEN_Pos [5/13]

#define FPU_FPCCR_ASPEN_Pos   31U

FPCCR: ASPEN bit Position

Definition at line 1333 of file core_cm4.h.

◆ FPU_FPCCR_ASPEN_Pos [6/13]

#define FPU_FPCCR_ASPEN_Pos   31U

FPCCR: ASPEN bit Position

Definition at line 3071 of file core_cm55.h.

◆ FPU_FPCCR_ASPEN_Pos [7/13]

#define FPU_FPCCR_ASPEN_Pos   31U

FPCCR: ASPEN bit Position

Definition at line 1560 of file core_cm7.h.

◆ FPU_FPCCR_ASPEN_Pos [8/13]

#define FPU_FPCCR_ASPEN_Pos   31U

FPCCR: ASPEN bit Position

Definition at line 2976 of file core_cm85.h.

◆ FPU_FPCCR_ASPEN_Pos [9/13]

#define FPU_FPCCR_ASPEN_Pos   31U

FPCCR: ASPEN bit Position

Definition at line 1769 of file core_starmc1.h.

◆ FPU_FPCCR_ASPEN_Pos [10/13]

#define FPU_FPCCR_ASPEN_Pos   31U

FPCCR: ASPEN bit Position

Definition at line 2517 of file core_armv81mml.h.

◆ FPU_FPCCR_ASPEN_Pos [11/13]

#define FPU_FPCCR_ASPEN_Pos   31U

FPCCR: ASPEN bit Position

Definition at line 1636 of file core_armv8mml.h.

◆ FPU_FPCCR_ASPEN_Pos [12/13]

#define FPU_FPCCR_ASPEN_Pos   31U

FPCCR: ASPEN bit Position

Definition at line 1711 of file core_cm33.h.

◆ FPU_FPCCR_ASPEN_Pos [13/13]

#define FPU_FPCCR_ASPEN_Pos   31U

FPCCR: ASPEN bit Position

Definition at line 1333 of file core_cm4.h.

◆ FPU_FPCCR_BFRDY_Msk [1/13]

#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 2548 of file core_armv81mml.h.

◆ FPU_FPCCR_BFRDY_Msk [2/13]

#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1667 of file core_armv8mml.h.

◆ FPU_FPCCR_BFRDY_Msk [3/13]

#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1742 of file core_cm33.h.

◆ FPU_FPCCR_BFRDY_Msk [4/13]

#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1742 of file core_cm35p.h.

◆ FPU_FPCCR_BFRDY_Msk [5/13]

#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1343 of file core_cm4.h.

◆ FPU_FPCCR_BFRDY_Msk [6/13]

#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 3102 of file core_cm55.h.

◆ FPU_FPCCR_BFRDY_Msk [7/13]

#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1570 of file core_cm7.h.

◆ FPU_FPCCR_BFRDY_Msk [8/13]

#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 3007 of file core_cm85.h.

◆ FPU_FPCCR_BFRDY_Msk [9/13]

#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1800 of file core_starmc1.h.

◆ FPU_FPCCR_BFRDY_Msk [10/13]

#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 2548 of file core_armv81mml.h.

◆ FPU_FPCCR_BFRDY_Msk [11/13]

#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1667 of file core_armv8mml.h.

◆ FPU_FPCCR_BFRDY_Msk [12/13]

#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1742 of file core_cm33.h.

◆ FPU_FPCCR_BFRDY_Msk [13/13]

#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1343 of file core_cm4.h.

◆ FPU_FPCCR_BFRDY_Pos [1/13]

#define FPU_FPCCR_BFRDY_Pos   6U

FPCCR: BFRDY Position

Definition at line 2547 of file core_armv81mml.h.

◆ FPU_FPCCR_BFRDY_Pos [2/13]

#define FPU_FPCCR_BFRDY_Pos   6U

FPCCR: BFRDY Position

Definition at line 1666 of file core_armv8mml.h.

◆ FPU_FPCCR_BFRDY_Pos [3/13]

#define FPU_FPCCR_BFRDY_Pos   6U

FPCCR: BFRDY Position

Definition at line 1741 of file core_cm33.h.

◆ FPU_FPCCR_BFRDY_Pos [4/13]

#define FPU_FPCCR_BFRDY_Pos   6U

FPCCR: BFRDY Position

Definition at line 1741 of file core_cm35p.h.

◆ FPU_FPCCR_BFRDY_Pos [5/13]

#define FPU_FPCCR_BFRDY_Pos   6U

FPCCR: BFRDY Position

Definition at line 1342 of file core_cm4.h.

◆ FPU_FPCCR_BFRDY_Pos [6/13]

#define FPU_FPCCR_BFRDY_Pos   6U

FPCCR: BFRDY Position

Definition at line 3101 of file core_cm55.h.

◆ FPU_FPCCR_BFRDY_Pos [7/13]

#define FPU_FPCCR_BFRDY_Pos   6U

FPCCR: BFRDY Position

Definition at line 1569 of file core_cm7.h.

◆ FPU_FPCCR_BFRDY_Pos [8/13]

#define FPU_FPCCR_BFRDY_Pos   6U

FPCCR: BFRDY Position

Definition at line 3006 of file core_cm85.h.

◆ FPU_FPCCR_BFRDY_Pos [9/13]

#define FPU_FPCCR_BFRDY_Pos   6U

FPCCR: BFRDY Position

Definition at line 1799 of file core_starmc1.h.

◆ FPU_FPCCR_BFRDY_Pos [10/13]

#define FPU_FPCCR_BFRDY_Pos   6U

FPCCR: BFRDY Position

Definition at line 2547 of file core_armv81mml.h.

◆ FPU_FPCCR_BFRDY_Pos [11/13]

#define FPU_FPCCR_BFRDY_Pos   6U

FPCCR: BFRDY Position

Definition at line 1666 of file core_armv8mml.h.

◆ FPU_FPCCR_BFRDY_Pos [12/13]

#define FPU_FPCCR_BFRDY_Pos   6U

FPCCR: BFRDY Position

Definition at line 1741 of file core_cm33.h.

◆ FPU_FPCCR_BFRDY_Pos [13/13]

#define FPU_FPCCR_BFRDY_Pos   6U

FPCCR: BFRDY Position

Definition at line 1342 of file core_cm4.h.

◆ FPU_FPCCR_CLRONRET_Msk [1/10]

#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 2527 of file core_armv81mml.h.

◆ FPU_FPCCR_CLRONRET_Msk [2/10]

#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 1646 of file core_armv8mml.h.

◆ FPU_FPCCR_CLRONRET_Msk [3/10]

#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 1721 of file core_cm33.h.

◆ FPU_FPCCR_CLRONRET_Msk [4/10]

#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 1721 of file core_cm35p.h.

◆ FPU_FPCCR_CLRONRET_Msk [5/10]

#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 3081 of file core_cm55.h.

◆ FPU_FPCCR_CLRONRET_Msk [6/10]

#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 2986 of file core_cm85.h.

◆ FPU_FPCCR_CLRONRET_Msk [7/10]

#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 1779 of file core_starmc1.h.

◆ FPU_FPCCR_CLRONRET_Msk [8/10]

#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 2527 of file core_armv81mml.h.

◆ FPU_FPCCR_CLRONRET_Msk [9/10]

#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 1646 of file core_armv8mml.h.

◆ FPU_FPCCR_CLRONRET_Msk [10/10]

#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 1721 of file core_cm33.h.

◆ FPU_FPCCR_CLRONRET_Pos [1/10]

#define FPU_FPCCR_CLRONRET_Pos   28U

FPCCR: CLRONRET Position

Definition at line 2526 of file core_armv81mml.h.

◆ FPU_FPCCR_CLRONRET_Pos [2/10]

#define FPU_FPCCR_CLRONRET_Pos   28U

FPCCR: CLRONRET Position

Definition at line 1645 of file core_armv8mml.h.

◆ FPU_FPCCR_CLRONRET_Pos [3/10]

#define FPU_FPCCR_CLRONRET_Pos   28U

FPCCR: CLRONRET Position

Definition at line 1720 of file core_cm33.h.

◆ FPU_FPCCR_CLRONRET_Pos [4/10]

#define FPU_FPCCR_CLRONRET_Pos   28U

FPCCR: CLRONRET Position

Definition at line 1720 of file core_cm35p.h.

◆ FPU_FPCCR_CLRONRET_Pos [5/10]

#define FPU_FPCCR_CLRONRET_Pos   28U

FPCCR: CLRONRET Position

Definition at line 3080 of file core_cm55.h.

◆ FPU_FPCCR_CLRONRET_Pos [6/10]

#define FPU_FPCCR_CLRONRET_Pos   28U

FPCCR: CLRONRET Position

Definition at line 2985 of file core_cm85.h.

◆ FPU_FPCCR_CLRONRET_Pos [7/10]

#define FPU_FPCCR_CLRONRET_Pos   28U

FPCCR: CLRONRET Position

Definition at line 1778 of file core_starmc1.h.

◆ FPU_FPCCR_CLRONRET_Pos [8/10]

#define FPU_FPCCR_CLRONRET_Pos   28U

FPCCR: CLRONRET Position

Definition at line 2526 of file core_armv81mml.h.

◆ FPU_FPCCR_CLRONRET_Pos [9/10]

#define FPU_FPCCR_CLRONRET_Pos   28U

FPCCR: CLRONRET Position

Definition at line 1645 of file core_armv8mml.h.

◆ FPU_FPCCR_CLRONRET_Pos [10/10]

#define FPU_FPCCR_CLRONRET_Pos   28U

FPCCR: CLRONRET Position

Definition at line 1720 of file core_cm33.h.

◆ FPU_FPCCR_CLRONRETS_Msk [1/10]

#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 2530 of file core_armv81mml.h.

◆ FPU_FPCCR_CLRONRETS_Msk [2/10]

#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 1649 of file core_armv8mml.h.

◆ FPU_FPCCR_CLRONRETS_Msk [3/10]

#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 1724 of file core_cm33.h.

◆ FPU_FPCCR_CLRONRETS_Msk [4/10]

#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 1724 of file core_cm35p.h.

◆ FPU_FPCCR_CLRONRETS_Msk [5/10]

#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 3084 of file core_cm55.h.

◆ FPU_FPCCR_CLRONRETS_Msk [6/10]

#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 2989 of file core_cm85.h.

◆ FPU_FPCCR_CLRONRETS_Msk [7/10]

#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 1782 of file core_starmc1.h.

◆ FPU_FPCCR_CLRONRETS_Msk [8/10]

#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 2530 of file core_armv81mml.h.

◆ FPU_FPCCR_CLRONRETS_Msk [9/10]

#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 1649 of file core_armv8mml.h.

◆ FPU_FPCCR_CLRONRETS_Msk [10/10]

#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 1724 of file core_cm33.h.

◆ FPU_FPCCR_CLRONRETS_Pos [1/10]

#define FPU_FPCCR_CLRONRETS_Pos   27U

FPCCR: CLRONRETS Position

Definition at line 2529 of file core_armv81mml.h.

◆ FPU_FPCCR_CLRONRETS_Pos [2/10]

#define FPU_FPCCR_CLRONRETS_Pos   27U

FPCCR: CLRONRETS Position

Definition at line 1648 of file core_armv8mml.h.

◆ FPU_FPCCR_CLRONRETS_Pos [3/10]

#define FPU_FPCCR_CLRONRETS_Pos   27U

FPCCR: CLRONRETS Position

Definition at line 1723 of file core_cm33.h.

◆ FPU_FPCCR_CLRONRETS_Pos [4/10]

#define FPU_FPCCR_CLRONRETS_Pos   27U

FPCCR: CLRONRETS Position

Definition at line 1723 of file core_cm35p.h.

◆ FPU_FPCCR_CLRONRETS_Pos [5/10]

#define FPU_FPCCR_CLRONRETS_Pos   27U

FPCCR: CLRONRETS Position

Definition at line 3083 of file core_cm55.h.

◆ FPU_FPCCR_CLRONRETS_Pos [6/10]

#define FPU_FPCCR_CLRONRETS_Pos   27U

FPCCR: CLRONRETS Position

Definition at line 2988 of file core_cm85.h.

◆ FPU_FPCCR_CLRONRETS_Pos [7/10]

#define FPU_FPCCR_CLRONRETS_Pos   27U

FPCCR: CLRONRETS Position

Definition at line 1781 of file core_starmc1.h.

◆ FPU_FPCCR_CLRONRETS_Pos [8/10]

#define FPU_FPCCR_CLRONRETS_Pos   27U

FPCCR: CLRONRETS Position

Definition at line 2529 of file core_armv81mml.h.

◆ FPU_FPCCR_CLRONRETS_Pos [9/10]

#define FPU_FPCCR_CLRONRETS_Pos   27U

FPCCR: CLRONRETS Position

Definition at line 1648 of file core_armv8mml.h.

◆ FPU_FPCCR_CLRONRETS_Pos [10/10]

#define FPU_FPCCR_CLRONRETS_Pos   27U

FPCCR: CLRONRETS Position

Definition at line 1723 of file core_cm33.h.

◆ FPU_FPCCR_HFRDY_Msk [1/13]

#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 2554 of file core_armv81mml.h.

◆ FPU_FPCCR_HFRDY_Msk [2/13]

#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1673 of file core_armv8mml.h.

◆ FPU_FPCCR_HFRDY_Msk [3/13]

#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1748 of file core_cm33.h.

◆ FPU_FPCCR_HFRDY_Msk [4/13]

#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1748 of file core_cm35p.h.

◆ FPU_FPCCR_HFRDY_Msk [5/13]

#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1349 of file core_cm4.h.

◆ FPU_FPCCR_HFRDY_Msk [6/13]

#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 3108 of file core_cm55.h.

◆ FPU_FPCCR_HFRDY_Msk [7/13]

#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1576 of file core_cm7.h.

◆ FPU_FPCCR_HFRDY_Msk [8/13]

#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 3013 of file core_cm85.h.

◆ FPU_FPCCR_HFRDY_Msk [9/13]

#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1806 of file core_starmc1.h.

◆ FPU_FPCCR_HFRDY_Msk [10/13]

#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 2554 of file core_armv81mml.h.

◆ FPU_FPCCR_HFRDY_Msk [11/13]

#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1673 of file core_armv8mml.h.

◆ FPU_FPCCR_HFRDY_Msk [12/13]

#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1748 of file core_cm33.h.

◆ FPU_FPCCR_HFRDY_Msk [13/13]

#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1349 of file core_cm4.h.

◆ FPU_FPCCR_HFRDY_Pos [1/13]

#define FPU_FPCCR_HFRDY_Pos   4U

FPCCR: HFRDY Position

Definition at line 2553 of file core_armv81mml.h.

◆ FPU_FPCCR_HFRDY_Pos [2/13]

#define FPU_FPCCR_HFRDY_Pos   4U

FPCCR: HFRDY Position

Definition at line 1672 of file core_armv8mml.h.

◆ FPU_FPCCR_HFRDY_Pos [3/13]

#define FPU_FPCCR_HFRDY_Pos   4U

FPCCR: HFRDY Position

Definition at line 1747 of file core_cm33.h.

◆ FPU_FPCCR_HFRDY_Pos [4/13]

#define FPU_FPCCR_HFRDY_Pos   4U

FPCCR: HFRDY Position

Definition at line 1747 of file core_cm35p.h.

◆ FPU_FPCCR_HFRDY_Pos [5/13]

#define FPU_FPCCR_HFRDY_Pos   4U

FPCCR: HFRDY Position

Definition at line 1348 of file core_cm4.h.

◆ FPU_FPCCR_HFRDY_Pos [6/13]

#define FPU_FPCCR_HFRDY_Pos   4U

FPCCR: HFRDY Position

Definition at line 3107 of file core_cm55.h.

◆ FPU_FPCCR_HFRDY_Pos [7/13]

#define FPU_FPCCR_HFRDY_Pos   4U

FPCCR: HFRDY Position

Definition at line 1575 of file core_cm7.h.

◆ FPU_FPCCR_HFRDY_Pos [8/13]

#define FPU_FPCCR_HFRDY_Pos   4U

FPCCR: HFRDY Position

Definition at line 3012 of file core_cm85.h.

◆ FPU_FPCCR_HFRDY_Pos [9/13]

#define FPU_FPCCR_HFRDY_Pos   4U

FPCCR: HFRDY Position

Definition at line 1805 of file core_starmc1.h.

◆ FPU_FPCCR_HFRDY_Pos [10/13]

#define FPU_FPCCR_HFRDY_Pos   4U

FPCCR: HFRDY Position

Definition at line 2553 of file core_armv81mml.h.

◆ FPU_FPCCR_HFRDY_Pos [11/13]

#define FPU_FPCCR_HFRDY_Pos   4U

FPCCR: HFRDY Position

Definition at line 1672 of file core_armv8mml.h.

◆ FPU_FPCCR_HFRDY_Pos [12/13]

#define FPU_FPCCR_HFRDY_Pos   4U

FPCCR: HFRDY Position

Definition at line 1747 of file core_cm33.h.

◆ FPU_FPCCR_HFRDY_Pos [13/13]

#define FPU_FPCCR_HFRDY_Pos   4U

FPCCR: HFRDY Position

Definition at line 1348 of file core_cm4.h.

◆ FPU_FPCCR_LSPACT_Msk [1/13]

#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 2566 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPACT_Msk [2/13]

#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1685 of file core_armv8mml.h.

◆ FPU_FPCCR_LSPACT_Msk [3/13]

#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1760 of file core_cm33.h.

◆ FPU_FPCCR_LSPACT_Msk [4/13]

#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1760 of file core_cm35p.h.

◆ FPU_FPCCR_LSPACT_Msk [5/13]

#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1358 of file core_cm4.h.

◆ FPU_FPCCR_LSPACT_Msk [6/13]

#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 3120 of file core_cm55.h.

◆ FPU_FPCCR_LSPACT_Msk [7/13]

#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1585 of file core_cm7.h.

◆ FPU_FPCCR_LSPACT_Msk [8/13]

#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 3025 of file core_cm85.h.

◆ FPU_FPCCR_LSPACT_Msk [9/13]

#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1818 of file core_starmc1.h.

◆ FPU_FPCCR_LSPACT_Msk [10/13]

#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 2566 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPACT_Msk [11/13]

#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1685 of file core_armv8mml.h.

◆ FPU_FPCCR_LSPACT_Msk [12/13]

#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1760 of file core_cm33.h.

◆ FPU_FPCCR_LSPACT_Msk [13/13]

#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1358 of file core_cm4.h.

◆ FPU_FPCCR_LSPACT_Pos [1/13]

#define FPU_FPCCR_LSPACT_Pos   0U

FPCCR: Lazy state preservation active bit Position

Definition at line 2565 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPACT_Pos [2/13]

#define FPU_FPCCR_LSPACT_Pos   0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1684 of file core_armv8mml.h.

◆ FPU_FPCCR_LSPACT_Pos [3/13]

#define FPU_FPCCR_LSPACT_Pos   0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1759 of file core_cm33.h.

◆ FPU_FPCCR_LSPACT_Pos [4/13]

#define FPU_FPCCR_LSPACT_Pos   0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1759 of file core_cm35p.h.

◆ FPU_FPCCR_LSPACT_Pos [5/13]

#define FPU_FPCCR_LSPACT_Pos   0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1357 of file core_cm4.h.

◆ FPU_FPCCR_LSPACT_Pos [6/13]

#define FPU_FPCCR_LSPACT_Pos   0U

FPCCR: Lazy state preservation active bit Position

Definition at line 3119 of file core_cm55.h.

◆ FPU_FPCCR_LSPACT_Pos [7/13]

#define FPU_FPCCR_LSPACT_Pos   0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1584 of file core_cm7.h.

◆ FPU_FPCCR_LSPACT_Pos [8/13]

#define FPU_FPCCR_LSPACT_Pos   0U

FPCCR: Lazy state preservation active bit Position

Definition at line 3024 of file core_cm85.h.

◆ FPU_FPCCR_LSPACT_Pos [9/13]

#define FPU_FPCCR_LSPACT_Pos   0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1817 of file core_starmc1.h.

◆ FPU_FPCCR_LSPACT_Pos [10/13]

#define FPU_FPCCR_LSPACT_Pos   0U

FPCCR: Lazy state preservation active bit Position

Definition at line 2565 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPACT_Pos [11/13]

#define FPU_FPCCR_LSPACT_Pos   0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1684 of file core_armv8mml.h.

◆ FPU_FPCCR_LSPACT_Pos [12/13]

#define FPU_FPCCR_LSPACT_Pos   0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1759 of file core_cm33.h.

◆ FPU_FPCCR_LSPACT_Pos [13/13]

#define FPU_FPCCR_LSPACT_Pos   0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1357 of file core_cm4.h.

◆ FPU_FPCCR_LSPEN_Msk [1/13]

#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 2521 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPEN_Msk [2/13]

#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1640 of file core_armv8mml.h.

◆ FPU_FPCCR_LSPEN_Msk [3/13]

#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1715 of file core_cm33.h.

◆ FPU_FPCCR_LSPEN_Msk [4/13]

#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1715 of file core_cm35p.h.

◆ FPU_FPCCR_LSPEN_Msk [5/13]

#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1337 of file core_cm4.h.

◆ FPU_FPCCR_LSPEN_Msk [6/13]

#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 3075 of file core_cm55.h.

◆ FPU_FPCCR_LSPEN_Msk [7/13]

#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1564 of file core_cm7.h.

◆ FPU_FPCCR_LSPEN_Msk [8/13]

#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 2980 of file core_cm85.h.

◆ FPU_FPCCR_LSPEN_Msk [9/13]

#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1773 of file core_starmc1.h.

◆ FPU_FPCCR_LSPEN_Msk [10/13]

#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 2521 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPEN_Msk [11/13]

#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1640 of file core_armv8mml.h.

◆ FPU_FPCCR_LSPEN_Msk [12/13]

#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1715 of file core_cm33.h.

◆ FPU_FPCCR_LSPEN_Msk [13/13]

#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1337 of file core_cm4.h.

◆ FPU_FPCCR_LSPEN_Pos [1/13]

#define FPU_FPCCR_LSPEN_Pos   30U

FPCCR: LSPEN Position

Definition at line 2520 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPEN_Pos [2/13]

#define FPU_FPCCR_LSPEN_Pos   30U

FPCCR: LSPEN Position

Definition at line 1639 of file core_armv8mml.h.

◆ FPU_FPCCR_LSPEN_Pos [3/13]

#define FPU_FPCCR_LSPEN_Pos   30U

FPCCR: LSPEN Position

Definition at line 1714 of file core_cm33.h.

◆ FPU_FPCCR_LSPEN_Pos [4/13]

#define FPU_FPCCR_LSPEN_Pos   30U

FPCCR: LSPEN Position

Definition at line 1714 of file core_cm35p.h.

◆ FPU_FPCCR_LSPEN_Pos [5/13]

#define FPU_FPCCR_LSPEN_Pos   30U

FPCCR: LSPEN Position

Definition at line 1336 of file core_cm4.h.

◆ FPU_FPCCR_LSPEN_Pos [6/13]

#define FPU_FPCCR_LSPEN_Pos   30U

FPCCR: LSPEN Position

Definition at line 3074 of file core_cm55.h.

◆ FPU_FPCCR_LSPEN_Pos [7/13]

#define FPU_FPCCR_LSPEN_Pos   30U

FPCCR: LSPEN Position

Definition at line 1563 of file core_cm7.h.

◆ FPU_FPCCR_LSPEN_Pos [8/13]

#define FPU_FPCCR_LSPEN_Pos   30U

FPCCR: LSPEN Position

Definition at line 2979 of file core_cm85.h.

◆ FPU_FPCCR_LSPEN_Pos [9/13]

#define FPU_FPCCR_LSPEN_Pos   30U

FPCCR: LSPEN Position

Definition at line 1772 of file core_starmc1.h.

◆ FPU_FPCCR_LSPEN_Pos [10/13]

#define FPU_FPCCR_LSPEN_Pos   30U

FPCCR: LSPEN Position

Definition at line 2520 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPEN_Pos [11/13]

#define FPU_FPCCR_LSPEN_Pos   30U

FPCCR: LSPEN Position

Definition at line 1639 of file core_armv8mml.h.

◆ FPU_FPCCR_LSPEN_Pos [12/13]

#define FPU_FPCCR_LSPEN_Pos   30U

FPCCR: LSPEN Position

Definition at line 1714 of file core_cm33.h.

◆ FPU_FPCCR_LSPEN_Pos [13/13]

#define FPU_FPCCR_LSPEN_Pos   30U

FPCCR: LSPEN Position

Definition at line 1336 of file core_cm4.h.

◆ FPU_FPCCR_LSPENS_Msk [1/10]

#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 2524 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPENS_Msk [2/10]

#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 1643 of file core_armv8mml.h.

◆ FPU_FPCCR_LSPENS_Msk [3/10]

#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 1718 of file core_cm33.h.

◆ FPU_FPCCR_LSPENS_Msk [4/10]

#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 1718 of file core_cm35p.h.

◆ FPU_FPCCR_LSPENS_Msk [5/10]

#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 3078 of file core_cm55.h.

◆ FPU_FPCCR_LSPENS_Msk [6/10]

#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 2983 of file core_cm85.h.

◆ FPU_FPCCR_LSPENS_Msk [7/10]

#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 1776 of file core_starmc1.h.

◆ FPU_FPCCR_LSPENS_Msk [8/10]

#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 2524 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPENS_Msk [9/10]

#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 1643 of file core_armv8mml.h.

◆ FPU_FPCCR_LSPENS_Msk [10/10]

#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 1718 of file core_cm33.h.

◆ FPU_FPCCR_LSPENS_Pos [1/10]

#define FPU_FPCCR_LSPENS_Pos   29U

FPCCR: LSPENS Position

Definition at line 2523 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPENS_Pos [2/10]

#define FPU_FPCCR_LSPENS_Pos   29U

FPCCR: LSPENS Position

Definition at line 1642 of file core_armv8mml.h.

◆ FPU_FPCCR_LSPENS_Pos [3/10]

#define FPU_FPCCR_LSPENS_Pos   29U

FPCCR: LSPENS Position

Definition at line 1717 of file core_cm33.h.

◆ FPU_FPCCR_LSPENS_Pos [4/10]

#define FPU_FPCCR_LSPENS_Pos   29U

FPCCR: LSPENS Position

Definition at line 1717 of file core_cm35p.h.

◆ FPU_FPCCR_LSPENS_Pos [5/10]

#define FPU_FPCCR_LSPENS_Pos   29U

FPCCR: LSPENS Position

Definition at line 3077 of file core_cm55.h.

◆ FPU_FPCCR_LSPENS_Pos [6/10]

#define FPU_FPCCR_LSPENS_Pos   29U

FPCCR: LSPENS Position

Definition at line 2982 of file core_cm85.h.

◆ FPU_FPCCR_LSPENS_Pos [7/10]

#define FPU_FPCCR_LSPENS_Pos   29U

FPCCR: LSPENS Position

Definition at line 1775 of file core_starmc1.h.

◆ FPU_FPCCR_LSPENS_Pos [8/10]

#define FPU_FPCCR_LSPENS_Pos   29U

FPCCR: LSPENS Position

Definition at line 2523 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPENS_Pos [9/10]

#define FPU_FPCCR_LSPENS_Pos   29U

FPCCR: LSPENS Position

Definition at line 1642 of file core_armv8mml.h.

◆ FPU_FPCCR_LSPENS_Pos [10/10]

#define FPU_FPCCR_LSPENS_Pos   29U

FPCCR: LSPENS Position

Definition at line 1717 of file core_cm33.h.

◆ FPU_FPCCR_MMRDY_Msk [1/13]

#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 2551 of file core_armv81mml.h.

◆ FPU_FPCCR_MMRDY_Msk [2/13]

#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1670 of file core_armv8mml.h.

◆ FPU_FPCCR_MMRDY_Msk [3/13]

#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1745 of file core_cm33.h.

◆ FPU_FPCCR_MMRDY_Msk [4/13]

#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1745 of file core_cm35p.h.

◆ FPU_FPCCR_MMRDY_Msk [5/13]

#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1346 of file core_cm4.h.

◆ FPU_FPCCR_MMRDY_Msk [6/13]

#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 3105 of file core_cm55.h.

◆ FPU_FPCCR_MMRDY_Msk [7/13]

#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1573 of file core_cm7.h.

◆ FPU_FPCCR_MMRDY_Msk [8/13]

#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 3010 of file core_cm85.h.

◆ FPU_FPCCR_MMRDY_Msk [9/13]

#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1803 of file core_starmc1.h.

◆ FPU_FPCCR_MMRDY_Msk [10/13]

#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 2551 of file core_armv81mml.h.

◆ FPU_FPCCR_MMRDY_Msk [11/13]

#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1670 of file core_armv8mml.h.

◆ FPU_FPCCR_MMRDY_Msk [12/13]

#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1745 of file core_cm33.h.

◆ FPU_FPCCR_MMRDY_Msk [13/13]

#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1346 of file core_cm4.h.

◆ FPU_FPCCR_MMRDY_Pos [1/13]

#define FPU_FPCCR_MMRDY_Pos   5U

FPCCR: MMRDY Position

Definition at line 2550 of file core_armv81mml.h.

◆ FPU_FPCCR_MMRDY_Pos [2/13]

#define FPU_FPCCR_MMRDY_Pos   5U

FPCCR: MMRDY Position

Definition at line 1669 of file core_armv8mml.h.

◆ FPU_FPCCR_MMRDY_Pos [3/13]

#define FPU_FPCCR_MMRDY_Pos   5U

FPCCR: MMRDY Position

Definition at line 1744 of file core_cm33.h.

◆ FPU_FPCCR_MMRDY_Pos [4/13]

#define FPU_FPCCR_MMRDY_Pos   5U

FPCCR: MMRDY Position

Definition at line 1744 of file core_cm35p.h.

◆ FPU_FPCCR_MMRDY_Pos [5/13]

#define FPU_FPCCR_MMRDY_Pos   5U

FPCCR: MMRDY Position

Definition at line 1345 of file core_cm4.h.

◆ FPU_FPCCR_MMRDY_Pos [6/13]

#define FPU_FPCCR_MMRDY_Pos   5U

FPCCR: MMRDY Position

Definition at line 3104 of file core_cm55.h.

◆ FPU_FPCCR_MMRDY_Pos [7/13]

#define FPU_FPCCR_MMRDY_Pos   5U

FPCCR: MMRDY Position

Definition at line 1572 of file core_cm7.h.

◆ FPU_FPCCR_MMRDY_Pos [8/13]

#define FPU_FPCCR_MMRDY_Pos   5U

FPCCR: MMRDY Position

Definition at line 3009 of file core_cm85.h.

◆ FPU_FPCCR_MMRDY_Pos [9/13]

#define FPU_FPCCR_MMRDY_Pos   5U

FPCCR: MMRDY Position

Definition at line 1802 of file core_starmc1.h.

◆ FPU_FPCCR_MMRDY_Pos [10/13]

#define FPU_FPCCR_MMRDY_Pos   5U

FPCCR: MMRDY Position

Definition at line 2550 of file core_armv81mml.h.

◆ FPU_FPCCR_MMRDY_Pos [11/13]

#define FPU_FPCCR_MMRDY_Pos   5U

FPCCR: MMRDY Position

Definition at line 1669 of file core_armv8mml.h.

◆ FPU_FPCCR_MMRDY_Pos [12/13]

#define FPU_FPCCR_MMRDY_Pos   5U

FPCCR: MMRDY Position

Definition at line 1744 of file core_cm33.h.

◆ FPU_FPCCR_MMRDY_Pos [13/13]

#define FPU_FPCCR_MMRDY_Pos   5U

FPCCR: MMRDY Position

Definition at line 1345 of file core_cm4.h.

◆ FPU_FPCCR_MONRDY_Msk [1/13]

#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 2542 of file core_armv81mml.h.

◆ FPU_FPCCR_MONRDY_Msk [2/13]

#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1661 of file core_armv8mml.h.

◆ FPU_FPCCR_MONRDY_Msk [3/13]

#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1736 of file core_cm33.h.

◆ FPU_FPCCR_MONRDY_Msk [4/13]

#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1736 of file core_cm35p.h.

◆ FPU_FPCCR_MONRDY_Msk [5/13]

#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1340 of file core_cm4.h.

◆ FPU_FPCCR_MONRDY_Msk [6/13]

#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 3096 of file core_cm55.h.

◆ FPU_FPCCR_MONRDY_Msk [7/13]

#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1567 of file core_cm7.h.

◆ FPU_FPCCR_MONRDY_Msk [8/13]

#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 3001 of file core_cm85.h.

◆ FPU_FPCCR_MONRDY_Msk [9/13]

#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1794 of file core_starmc1.h.

◆ FPU_FPCCR_MONRDY_Msk [10/13]

#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 2542 of file core_armv81mml.h.

◆ FPU_FPCCR_MONRDY_Msk [11/13]

#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1661 of file core_armv8mml.h.

◆ FPU_FPCCR_MONRDY_Msk [12/13]

#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1736 of file core_cm33.h.

◆ FPU_FPCCR_MONRDY_Msk [13/13]

#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1340 of file core_cm4.h.

◆ FPU_FPCCR_MONRDY_Pos [1/13]

#define FPU_FPCCR_MONRDY_Pos   8U

FPCCR: MONRDY Position

Definition at line 2541 of file core_armv81mml.h.

◆ FPU_FPCCR_MONRDY_Pos [2/13]

#define FPU_FPCCR_MONRDY_Pos   8U

FPCCR: MONRDY Position

Definition at line 1660 of file core_armv8mml.h.

◆ FPU_FPCCR_MONRDY_Pos [3/13]

#define FPU_FPCCR_MONRDY_Pos   8U

FPCCR: MONRDY Position

Definition at line 1735 of file core_cm33.h.

◆ FPU_FPCCR_MONRDY_Pos [4/13]

#define FPU_FPCCR_MONRDY_Pos   8U

FPCCR: MONRDY Position

Definition at line 1735 of file core_cm35p.h.

◆ FPU_FPCCR_MONRDY_Pos [5/13]

#define FPU_FPCCR_MONRDY_Pos   8U

FPCCR: MONRDY Position

Definition at line 1339 of file core_cm4.h.

◆ FPU_FPCCR_MONRDY_Pos [6/13]

#define FPU_FPCCR_MONRDY_Pos   8U

FPCCR: MONRDY Position

Definition at line 3095 of file core_cm55.h.

◆ FPU_FPCCR_MONRDY_Pos [7/13]

#define FPU_FPCCR_MONRDY_Pos   8U

FPCCR: MONRDY Position

Definition at line 1566 of file core_cm7.h.

◆ FPU_FPCCR_MONRDY_Pos [8/13]

#define FPU_FPCCR_MONRDY_Pos   8U

FPCCR: MONRDY Position

Definition at line 3000 of file core_cm85.h.

◆ FPU_FPCCR_MONRDY_Pos [9/13]

#define FPU_FPCCR_MONRDY_Pos   8U

FPCCR: MONRDY Position

Definition at line 1793 of file core_starmc1.h.

◆ FPU_FPCCR_MONRDY_Pos [10/13]

#define FPU_FPCCR_MONRDY_Pos   8U

FPCCR: MONRDY Position

Definition at line 2541 of file core_armv81mml.h.

◆ FPU_FPCCR_MONRDY_Pos [11/13]

#define FPU_FPCCR_MONRDY_Pos   8U

FPCCR: MONRDY Position

Definition at line 1660 of file core_armv8mml.h.

◆ FPU_FPCCR_MONRDY_Pos [12/13]

#define FPU_FPCCR_MONRDY_Pos   8U

FPCCR: MONRDY Position

Definition at line 1735 of file core_cm33.h.

◆ FPU_FPCCR_MONRDY_Pos [13/13]

#define FPU_FPCCR_MONRDY_Pos   8U

FPCCR: MONRDY Position

Definition at line 1339 of file core_cm4.h.

◆ FPU_FPCCR_S_Msk [1/10]

#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 2560 of file core_armv81mml.h.

◆ FPU_FPCCR_S_Msk [2/10]

#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 1679 of file core_armv8mml.h.

◆ FPU_FPCCR_S_Msk [3/10]

#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 1754 of file core_cm33.h.

◆ FPU_FPCCR_S_Msk [4/10]

#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 1754 of file core_cm35p.h.

◆ FPU_FPCCR_S_Msk [5/10]

#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 3114 of file core_cm55.h.

◆ FPU_FPCCR_S_Msk [6/10]

#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 3019 of file core_cm85.h.

◆ FPU_FPCCR_S_Msk [7/10]

#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 1812 of file core_starmc1.h.

◆ FPU_FPCCR_S_Msk [8/10]

#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 2560 of file core_armv81mml.h.

◆ FPU_FPCCR_S_Msk [9/10]

#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 1679 of file core_armv8mml.h.

◆ FPU_FPCCR_S_Msk [10/10]

#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 1754 of file core_cm33.h.

◆ FPU_FPCCR_S_Pos [1/10]

#define FPU_FPCCR_S_Pos   2U

FPCCR: Security status of the FP context bit Position

Definition at line 2559 of file core_armv81mml.h.

◆ FPU_FPCCR_S_Pos [2/10]

#define FPU_FPCCR_S_Pos   2U

FPCCR: Security status of the FP context bit Position

Definition at line 1678 of file core_armv8mml.h.

◆ FPU_FPCCR_S_Pos [3/10]

#define FPU_FPCCR_S_Pos   2U

FPCCR: Security status of the FP context bit Position

Definition at line 1753 of file core_cm33.h.

◆ FPU_FPCCR_S_Pos [4/10]

#define FPU_FPCCR_S_Pos   2U

FPCCR: Security status of the FP context bit Position

Definition at line 1753 of file core_cm35p.h.

◆ FPU_FPCCR_S_Pos [5/10]

#define FPU_FPCCR_S_Pos   2U

FPCCR: Security status of the FP context bit Position

Definition at line 3113 of file core_cm55.h.

◆ FPU_FPCCR_S_Pos [6/10]

#define FPU_FPCCR_S_Pos   2U

FPCCR: Security status of the FP context bit Position

Definition at line 3018 of file core_cm85.h.

◆ FPU_FPCCR_S_Pos [7/10]

#define FPU_FPCCR_S_Pos   2U

FPCCR: Security status of the FP context bit Position

Definition at line 1811 of file core_starmc1.h.

◆ FPU_FPCCR_S_Pos [8/10]

#define FPU_FPCCR_S_Pos   2U

FPCCR: Security status of the FP context bit Position

Definition at line 2559 of file core_armv81mml.h.

◆ FPU_FPCCR_S_Pos [9/10]

#define FPU_FPCCR_S_Pos   2U

FPCCR: Security status of the FP context bit Position

Definition at line 1678 of file core_armv8mml.h.

◆ FPU_FPCCR_S_Pos [10/10]

#define FPU_FPCCR_S_Pos   2U

FPCCR: Security status of the FP context bit Position

Definition at line 1753 of file core_cm33.h.

◆ FPU_FPCCR_SFRDY_Msk [1/10]

#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 2545 of file core_armv81mml.h.

◆ FPU_FPCCR_SFRDY_Msk [2/10]

#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 1664 of file core_armv8mml.h.

◆ FPU_FPCCR_SFRDY_Msk [3/10]

#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 1739 of file core_cm33.h.

◆ FPU_FPCCR_SFRDY_Msk [4/10]

#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 1739 of file core_cm35p.h.

◆ FPU_FPCCR_SFRDY_Msk [5/10]

#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 3099 of file core_cm55.h.

◆ FPU_FPCCR_SFRDY_Msk [6/10]

#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 3004 of file core_cm85.h.

◆ FPU_FPCCR_SFRDY_Msk [7/10]

#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 1797 of file core_starmc1.h.

◆ FPU_FPCCR_SFRDY_Msk [8/10]

#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 2545 of file core_armv81mml.h.

◆ FPU_FPCCR_SFRDY_Msk [9/10]

#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 1664 of file core_armv8mml.h.

◆ FPU_FPCCR_SFRDY_Msk [10/10]

#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 1739 of file core_cm33.h.

◆ FPU_FPCCR_SFRDY_Pos [1/10]

#define FPU_FPCCR_SFRDY_Pos   7U

FPCCR: SFRDY Position

Definition at line 2544 of file core_armv81mml.h.

◆ FPU_FPCCR_SFRDY_Pos [2/10]

#define FPU_FPCCR_SFRDY_Pos   7U

FPCCR: SFRDY Position

Definition at line 1663 of file core_armv8mml.h.

◆ FPU_FPCCR_SFRDY_Pos [3/10]

#define FPU_FPCCR_SFRDY_Pos   7U

FPCCR: SFRDY Position

Definition at line 1738 of file core_cm33.h.

◆ FPU_FPCCR_SFRDY_Pos [4/10]

#define FPU_FPCCR_SFRDY_Pos   7U

FPCCR: SFRDY Position

Definition at line 1738 of file core_cm35p.h.

◆ FPU_FPCCR_SFRDY_Pos [5/10]

#define FPU_FPCCR_SFRDY_Pos   7U

FPCCR: SFRDY Position

Definition at line 3098 of file core_cm55.h.

◆ FPU_FPCCR_SFRDY_Pos [6/10]

#define FPU_FPCCR_SFRDY_Pos   7U

FPCCR: SFRDY Position

Definition at line 3003 of file core_cm85.h.

◆ FPU_FPCCR_SFRDY_Pos [7/10]

#define FPU_FPCCR_SFRDY_Pos   7U

FPCCR: SFRDY Position

Definition at line 1796 of file core_starmc1.h.

◆ FPU_FPCCR_SFRDY_Pos [8/10]

#define FPU_FPCCR_SFRDY_Pos   7U

FPCCR: SFRDY Position

Definition at line 2544 of file core_armv81mml.h.

◆ FPU_FPCCR_SFRDY_Pos [9/10]

#define FPU_FPCCR_SFRDY_Pos   7U

FPCCR: SFRDY Position

Definition at line 1663 of file core_armv8mml.h.

◆ FPU_FPCCR_SFRDY_Pos [10/10]

#define FPU_FPCCR_SFRDY_Pos   7U

FPCCR: SFRDY Position

Definition at line 1738 of file core_cm33.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [1/10]

#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 2539 of file core_armv81mml.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [2/10]

#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 1658 of file core_armv8mml.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [3/10]

#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 1733 of file core_cm33.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [4/10]

#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 1733 of file core_cm35p.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [5/10]

#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 3093 of file core_cm55.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [6/10]

#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 2998 of file core_cm85.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [7/10]

#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 1791 of file core_starmc1.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [8/10]

#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 2539 of file core_armv81mml.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [9/10]

#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 1658 of file core_armv8mml.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [10/10]

#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 1733 of file core_cm33.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [1/10]

#define FPU_FPCCR_SPLIMVIOL_Pos   9U

FPCCR: SPLIMVIOL Position

Definition at line 2538 of file core_armv81mml.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [2/10]

#define FPU_FPCCR_SPLIMVIOL_Pos   9U

FPCCR: SPLIMVIOL Position

Definition at line 1657 of file core_armv8mml.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [3/10]

#define FPU_FPCCR_SPLIMVIOL_Pos   9U

FPCCR: SPLIMVIOL Position

Definition at line 1732 of file core_cm33.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [4/10]

#define FPU_FPCCR_SPLIMVIOL_Pos   9U

FPCCR: SPLIMVIOL Position

Definition at line 1732 of file core_cm35p.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [5/10]

#define FPU_FPCCR_SPLIMVIOL_Pos   9U

FPCCR: SPLIMVIOL Position

Definition at line 3092 of file core_cm55.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [6/10]

#define FPU_FPCCR_SPLIMVIOL_Pos   9U

FPCCR: SPLIMVIOL Position

Definition at line 2997 of file core_cm85.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [7/10]

#define FPU_FPCCR_SPLIMVIOL_Pos   9U

FPCCR: SPLIMVIOL Position

Definition at line 1790 of file core_starmc1.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [8/10]

#define FPU_FPCCR_SPLIMVIOL_Pos   9U

FPCCR: SPLIMVIOL Position

Definition at line 2538 of file core_armv81mml.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [9/10]

#define FPU_FPCCR_SPLIMVIOL_Pos   9U

FPCCR: SPLIMVIOL Position

Definition at line 1657 of file core_armv8mml.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [10/10]

#define FPU_FPCCR_SPLIMVIOL_Pos   9U

FPCCR: SPLIMVIOL Position

Definition at line 1732 of file core_cm33.h.

◆ FPU_FPCCR_THREAD_Msk [1/13]

#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 2557 of file core_armv81mml.h.

◆ FPU_FPCCR_THREAD_Msk [2/13]

#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1676 of file core_armv8mml.h.

◆ FPU_FPCCR_THREAD_Msk [3/13]

#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1751 of file core_cm33.h.

◆ FPU_FPCCR_THREAD_Msk [4/13]

#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1751 of file core_cm35p.h.

◆ FPU_FPCCR_THREAD_Msk [5/13]

#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1352 of file core_cm4.h.

◆ FPU_FPCCR_THREAD_Msk [6/13]

#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 3111 of file core_cm55.h.

◆ FPU_FPCCR_THREAD_Msk [7/13]

#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1579 of file core_cm7.h.

◆ FPU_FPCCR_THREAD_Msk [8/13]

#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 3016 of file core_cm85.h.

◆ FPU_FPCCR_THREAD_Msk [9/13]

#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1809 of file core_starmc1.h.

◆ FPU_FPCCR_THREAD_Msk [10/13]

#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 2557 of file core_armv81mml.h.

◆ FPU_FPCCR_THREAD_Msk [11/13]

#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1676 of file core_armv8mml.h.

◆ FPU_FPCCR_THREAD_Msk [12/13]

#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1751 of file core_cm33.h.

◆ FPU_FPCCR_THREAD_Msk [13/13]

#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1352 of file core_cm4.h.

◆ FPU_FPCCR_THREAD_Pos [1/13]

#define FPU_FPCCR_THREAD_Pos   3U

FPCCR: processor mode bit Position

Definition at line 2556 of file core_armv81mml.h.

◆ FPU_FPCCR_THREAD_Pos [2/13]

#define FPU_FPCCR_THREAD_Pos   3U

FPCCR: processor mode bit Position

Definition at line 1675 of file core_armv8mml.h.

◆ FPU_FPCCR_THREAD_Pos [3/13]

#define FPU_FPCCR_THREAD_Pos   3U

FPCCR: processor mode bit Position

Definition at line 1750 of file core_cm33.h.

◆ FPU_FPCCR_THREAD_Pos [4/13]

#define FPU_FPCCR_THREAD_Pos   3U

FPCCR: processor mode bit Position

Definition at line 1750 of file core_cm35p.h.

◆ FPU_FPCCR_THREAD_Pos [5/13]

#define FPU_FPCCR_THREAD_Pos   3U

FPCCR: processor mode bit Position

Definition at line 1351 of file core_cm4.h.

◆ FPU_FPCCR_THREAD_Pos [6/13]

#define FPU_FPCCR_THREAD_Pos   3U

FPCCR: processor mode bit Position

Definition at line 3110 of file core_cm55.h.

◆ FPU_FPCCR_THREAD_Pos [7/13]

#define FPU_FPCCR_THREAD_Pos   3U

FPCCR: processor mode bit Position

Definition at line 1578 of file core_cm7.h.

◆ FPU_FPCCR_THREAD_Pos [8/13]

#define FPU_FPCCR_THREAD_Pos   3U

FPCCR: processor mode bit Position

Definition at line 3015 of file core_cm85.h.

◆ FPU_FPCCR_THREAD_Pos [9/13]

#define FPU_FPCCR_THREAD_Pos   3U

FPCCR: processor mode bit Position

Definition at line 1808 of file core_starmc1.h.

◆ FPU_FPCCR_THREAD_Pos [10/13]

#define FPU_FPCCR_THREAD_Pos   3U

FPCCR: processor mode bit Position

Definition at line 2556 of file core_armv81mml.h.

◆ FPU_FPCCR_THREAD_Pos [11/13]

#define FPU_FPCCR_THREAD_Pos   3U

FPCCR: processor mode bit Position

Definition at line 1675 of file core_armv8mml.h.

◆ FPU_FPCCR_THREAD_Pos [12/13]

#define FPU_FPCCR_THREAD_Pos   3U

FPCCR: processor mode bit Position

Definition at line 1750 of file core_cm33.h.

◆ FPU_FPCCR_THREAD_Pos [13/13]

#define FPU_FPCCR_THREAD_Pos   3U

FPCCR: processor mode bit Position

Definition at line 1351 of file core_cm4.h.

◆ FPU_FPCCR_TS_Msk [1/10]

#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 2533 of file core_armv81mml.h.

◆ FPU_FPCCR_TS_Msk [2/10]

#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 1652 of file core_armv8mml.h.

◆ FPU_FPCCR_TS_Msk [3/10]

#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 1727 of file core_cm33.h.

◆ FPU_FPCCR_TS_Msk [4/10]

#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 1727 of file core_cm35p.h.

◆ FPU_FPCCR_TS_Msk [5/10]

#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 3087 of file core_cm55.h.

◆ FPU_FPCCR_TS_Msk [6/10]

#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 2992 of file core_cm85.h.

◆ FPU_FPCCR_TS_Msk [7/10]

#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 1785 of file core_starmc1.h.

◆ FPU_FPCCR_TS_Msk [8/10]

#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 2533 of file core_armv81mml.h.

◆ FPU_FPCCR_TS_Msk [9/10]

#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 1652 of file core_armv8mml.h.

◆ FPU_FPCCR_TS_Msk [10/10]

#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 1727 of file core_cm33.h.

◆ FPU_FPCCR_TS_Pos [1/10]

#define FPU_FPCCR_TS_Pos   26U

FPCCR: TS Position

Definition at line 2532 of file core_armv81mml.h.

◆ FPU_FPCCR_TS_Pos [2/10]

#define FPU_FPCCR_TS_Pos   26U

FPCCR: TS Position

Definition at line 1651 of file core_armv8mml.h.

◆ FPU_FPCCR_TS_Pos [3/10]

#define FPU_FPCCR_TS_Pos   26U

FPCCR: TS Position

Definition at line 1726 of file core_cm33.h.

◆ FPU_FPCCR_TS_Pos [4/10]

#define FPU_FPCCR_TS_Pos   26U

FPCCR: TS Position

Definition at line 1726 of file core_cm35p.h.

◆ FPU_FPCCR_TS_Pos [5/10]

#define FPU_FPCCR_TS_Pos   26U

FPCCR: TS Position

Definition at line 3086 of file core_cm55.h.

◆ FPU_FPCCR_TS_Pos [6/10]

#define FPU_FPCCR_TS_Pos   26U

FPCCR: TS Position

Definition at line 2991 of file core_cm85.h.

◆ FPU_FPCCR_TS_Pos [7/10]

#define FPU_FPCCR_TS_Pos   26U

FPCCR: TS Position

Definition at line 1784 of file core_starmc1.h.

◆ FPU_FPCCR_TS_Pos [8/10]

#define FPU_FPCCR_TS_Pos   26U

FPCCR: TS Position

Definition at line 2532 of file core_armv81mml.h.

◆ FPU_FPCCR_TS_Pos [9/10]

#define FPU_FPCCR_TS_Pos   26U

FPCCR: TS Position

Definition at line 1651 of file core_armv8mml.h.

◆ FPU_FPCCR_TS_Pos [10/10]

#define FPU_FPCCR_TS_Pos   26U

FPCCR: TS Position

Definition at line 1726 of file core_cm33.h.

◆ FPU_FPCCR_UFRDY_Msk [1/10]

#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 2536 of file core_armv81mml.h.

◆ FPU_FPCCR_UFRDY_Msk [2/10]

#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 1655 of file core_armv8mml.h.

◆ FPU_FPCCR_UFRDY_Msk [3/10]

#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 1730 of file core_cm33.h.

◆ FPU_FPCCR_UFRDY_Msk [4/10]

#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 1730 of file core_cm35p.h.

◆ FPU_FPCCR_UFRDY_Msk [5/10]

#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 3090 of file core_cm55.h.

◆ FPU_FPCCR_UFRDY_Msk [6/10]

#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 2995 of file core_cm85.h.

◆ FPU_FPCCR_UFRDY_Msk [7/10]

#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 1788 of file core_starmc1.h.

◆ FPU_FPCCR_UFRDY_Msk [8/10]

#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 2536 of file core_armv81mml.h.

◆ FPU_FPCCR_UFRDY_Msk [9/10]

#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 1655 of file core_armv8mml.h.

◆ FPU_FPCCR_UFRDY_Msk [10/10]

#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 1730 of file core_cm33.h.

◆ FPU_FPCCR_UFRDY_Pos [1/10]

#define FPU_FPCCR_UFRDY_Pos   10U

FPCCR: UFRDY Position

Definition at line 2535 of file core_armv81mml.h.

◆ FPU_FPCCR_UFRDY_Pos [2/10]

#define FPU_FPCCR_UFRDY_Pos   10U

FPCCR: UFRDY Position

Definition at line 1654 of file core_armv8mml.h.

◆ FPU_FPCCR_UFRDY_Pos [3/10]

#define FPU_FPCCR_UFRDY_Pos   10U

FPCCR: UFRDY Position

Definition at line 1729 of file core_cm33.h.

◆ FPU_FPCCR_UFRDY_Pos [4/10]

#define FPU_FPCCR_UFRDY_Pos   10U

FPCCR: UFRDY Position

Definition at line 1729 of file core_cm35p.h.

◆ FPU_FPCCR_UFRDY_Pos [5/10]

#define FPU_FPCCR_UFRDY_Pos   10U

FPCCR: UFRDY Position

Definition at line 3089 of file core_cm55.h.

◆ FPU_FPCCR_UFRDY_Pos [6/10]

#define FPU_FPCCR_UFRDY_Pos   10U

FPCCR: UFRDY Position

Definition at line 2994 of file core_cm85.h.

◆ FPU_FPCCR_UFRDY_Pos [7/10]

#define FPU_FPCCR_UFRDY_Pos   10U

FPCCR: UFRDY Position

Definition at line 1787 of file core_starmc1.h.

◆ FPU_FPCCR_UFRDY_Pos [8/10]

#define FPU_FPCCR_UFRDY_Pos   10U

FPCCR: UFRDY Position

Definition at line 2535 of file core_armv81mml.h.

◆ FPU_FPCCR_UFRDY_Pos [9/10]

#define FPU_FPCCR_UFRDY_Pos   10U

FPCCR: UFRDY Position

Definition at line 1654 of file core_armv8mml.h.

◆ FPU_FPCCR_UFRDY_Pos [10/10]

#define FPU_FPCCR_UFRDY_Pos   10U

FPCCR: UFRDY Position

Definition at line 1729 of file core_cm33.h.

◆ FPU_FPCCR_USER_Msk [1/13]

#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 2563 of file core_armv81mml.h.

◆ FPU_FPCCR_USER_Msk [2/13]

#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1682 of file core_armv8mml.h.

◆ FPU_FPCCR_USER_Msk [3/13]

#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1757 of file core_cm33.h.

◆ FPU_FPCCR_USER_Msk [4/13]

#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1757 of file core_cm35p.h.

◆ FPU_FPCCR_USER_Msk [5/13]

#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1355 of file core_cm4.h.

◆ FPU_FPCCR_USER_Msk [6/13]

#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 3117 of file core_cm55.h.

◆ FPU_FPCCR_USER_Msk [7/13]

#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1582 of file core_cm7.h.

◆ FPU_FPCCR_USER_Msk [8/13]

#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 3022 of file core_cm85.h.

◆ FPU_FPCCR_USER_Msk [9/13]

#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1815 of file core_starmc1.h.

◆ FPU_FPCCR_USER_Msk [10/13]

#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 2563 of file core_armv81mml.h.

◆ FPU_FPCCR_USER_Msk [11/13]

#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1682 of file core_armv8mml.h.

◆ FPU_FPCCR_USER_Msk [12/13]

#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1757 of file core_cm33.h.

◆ FPU_FPCCR_USER_Msk [13/13]

#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1355 of file core_cm4.h.

◆ FPU_FPCCR_USER_Pos [1/13]

#define FPU_FPCCR_USER_Pos   1U

FPCCR: privilege level bit Position

Definition at line 2562 of file core_armv81mml.h.

◆ FPU_FPCCR_USER_Pos [2/13]

#define FPU_FPCCR_USER_Pos   1U

FPCCR: privilege level bit Position

Definition at line 1681 of file core_armv8mml.h.

◆ FPU_FPCCR_USER_Pos [3/13]

#define FPU_FPCCR_USER_Pos   1U

FPCCR: privilege level bit Position

Definition at line 1756 of file core_cm33.h.

◆ FPU_FPCCR_USER_Pos [4/13]

#define FPU_FPCCR_USER_Pos   1U

FPCCR: privilege level bit Position

Definition at line 1756 of file core_cm35p.h.

◆ FPU_FPCCR_USER_Pos [5/13]

#define FPU_FPCCR_USER_Pos   1U

FPCCR: privilege level bit Position

Definition at line 1354 of file core_cm4.h.

◆ FPU_FPCCR_USER_Pos [6/13]

#define FPU_FPCCR_USER_Pos   1U

FPCCR: privilege level bit Position

Definition at line 3116 of file core_cm55.h.

◆ FPU_FPCCR_USER_Pos [7/13]

#define FPU_FPCCR_USER_Pos   1U

FPCCR: privilege level bit Position

Definition at line 1581 of file core_cm7.h.

◆ FPU_FPCCR_USER_Pos [8/13]

#define FPU_FPCCR_USER_Pos   1U

FPCCR: privilege level bit Position

Definition at line 3021 of file core_cm85.h.

◆ FPU_FPCCR_USER_Pos [9/13]

#define FPU_FPCCR_USER_Pos   1U

FPCCR: privilege level bit Position

Definition at line 1814 of file core_starmc1.h.

◆ FPU_FPCCR_USER_Pos [10/13]

#define FPU_FPCCR_USER_Pos   1U

FPCCR: privilege level bit Position

Definition at line 2562 of file core_armv81mml.h.

◆ FPU_FPCCR_USER_Pos [11/13]

#define FPU_FPCCR_USER_Pos   1U

FPCCR: privilege level bit Position

Definition at line 1681 of file core_armv8mml.h.

◆ FPU_FPCCR_USER_Pos [12/13]

#define FPU_FPCCR_USER_Pos   1U

FPCCR: privilege level bit Position

Definition at line 1756 of file core_cm33.h.

◆ FPU_FPCCR_USER_Pos [13/13]

#define FPU_FPCCR_USER_Pos   1U

FPCCR: privilege level bit Position

Definition at line 1354 of file core_cm4.h.

◆ FPU_FPDSCR_AHP_Msk [1/13]

#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 2574 of file core_armv81mml.h.

◆ FPU_FPDSCR_AHP_Msk [2/13]

#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1693 of file core_armv8mml.h.

◆ FPU_FPDSCR_AHP_Msk [3/13]

#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1768 of file core_cm33.h.

◆ FPU_FPDSCR_AHP_Msk [4/13]

#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1768 of file core_cm35p.h.

◆ FPU_FPDSCR_AHP_Msk [5/13]

#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1366 of file core_cm4.h.

◆ FPU_FPDSCR_AHP_Msk [6/13]

#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 3128 of file core_cm55.h.

◆ FPU_FPDSCR_AHP_Msk [7/13]

#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1593 of file core_cm7.h.

◆ FPU_FPDSCR_AHP_Msk [8/13]

#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 3033 of file core_cm85.h.

◆ FPU_FPDSCR_AHP_Msk [9/13]

#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1826 of file core_starmc1.h.

◆ FPU_FPDSCR_AHP_Msk [10/13]

#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 2574 of file core_armv81mml.h.

◆ FPU_FPDSCR_AHP_Msk [11/13]

#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1693 of file core_armv8mml.h.

◆ FPU_FPDSCR_AHP_Msk [12/13]

#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1768 of file core_cm33.h.

◆ FPU_FPDSCR_AHP_Msk [13/13]

#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1366 of file core_cm4.h.

◆ FPU_FPDSCR_AHP_Pos [1/13]

#define FPU_FPDSCR_AHP_Pos   26U

FPDSCR: AHP bit Position

Definition at line 2573 of file core_armv81mml.h.

◆ FPU_FPDSCR_AHP_Pos [2/13]

#define FPU_FPDSCR_AHP_Pos   26U

FPDSCR: AHP bit Position

Definition at line 1692 of file core_armv8mml.h.

◆ FPU_FPDSCR_AHP_Pos [3/13]

#define FPU_FPDSCR_AHP_Pos   26U

FPDSCR: AHP bit Position

Definition at line 1767 of file core_cm33.h.

◆ FPU_FPDSCR_AHP_Pos [4/13]

#define FPU_FPDSCR_AHP_Pos   26U

FPDSCR: AHP bit Position

Definition at line 1767 of file core_cm35p.h.

◆ FPU_FPDSCR_AHP_Pos [5/13]

#define FPU_FPDSCR_AHP_Pos   26U

FPDSCR: AHP bit Position

Definition at line 1365 of file core_cm4.h.

◆ FPU_FPDSCR_AHP_Pos [6/13]

#define FPU_FPDSCR_AHP_Pos   26U

FPDSCR: AHP bit Position

Definition at line 3127 of file core_cm55.h.

◆ FPU_FPDSCR_AHP_Pos [7/13]

#define FPU_FPDSCR_AHP_Pos   26U

FPDSCR: AHP bit Position

Definition at line 1592 of file core_cm7.h.

◆ FPU_FPDSCR_AHP_Pos [8/13]

#define FPU_FPDSCR_AHP_Pos   26U

FPDSCR: AHP bit Position

Definition at line 3032 of file core_cm85.h.

◆ FPU_FPDSCR_AHP_Pos [9/13]

#define FPU_FPDSCR_AHP_Pos   26U

FPDSCR: AHP bit Position

Definition at line 1825 of file core_starmc1.h.

◆ FPU_FPDSCR_AHP_Pos [10/13]

#define FPU_FPDSCR_AHP_Pos   26U

FPDSCR: AHP bit Position

Definition at line 2573 of file core_armv81mml.h.

◆ FPU_FPDSCR_AHP_Pos [11/13]

#define FPU_FPDSCR_AHP_Pos   26U

FPDSCR: AHP bit Position

Definition at line 1692 of file core_armv8mml.h.

◆ FPU_FPDSCR_AHP_Pos [12/13]

#define FPU_FPDSCR_AHP_Pos   26U

FPDSCR: AHP bit Position

Definition at line 1767 of file core_cm33.h.

◆ FPU_FPDSCR_AHP_Pos [13/13]

#define FPU_FPDSCR_AHP_Pos   26U

FPDSCR: AHP bit Position

Definition at line 1365 of file core_cm4.h.

◆ FPU_FPDSCR_DN_Msk [1/13]

#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 2577 of file core_armv81mml.h.

◆ FPU_FPDSCR_DN_Msk [2/13]

#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1696 of file core_armv8mml.h.

◆ FPU_FPDSCR_DN_Msk [3/13]

#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1771 of file core_cm33.h.

◆ FPU_FPDSCR_DN_Msk [4/13]

#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1771 of file core_cm35p.h.

◆ FPU_FPDSCR_DN_Msk [5/13]

#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1369 of file core_cm4.h.

◆ FPU_FPDSCR_DN_Msk [6/13]

#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 3131 of file core_cm55.h.

◆ FPU_FPDSCR_DN_Msk [7/13]

#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1596 of file core_cm7.h.

◆ FPU_FPDSCR_DN_Msk [8/13]

#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 3036 of file core_cm85.h.

◆ FPU_FPDSCR_DN_Msk [9/13]

#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1829 of file core_starmc1.h.

◆ FPU_FPDSCR_DN_Msk [10/13]

#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 2577 of file core_armv81mml.h.

◆ FPU_FPDSCR_DN_Msk [11/13]

#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1696 of file core_armv8mml.h.

◆ FPU_FPDSCR_DN_Msk [12/13]

#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1771 of file core_cm33.h.

◆ FPU_FPDSCR_DN_Msk [13/13]

#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1369 of file core_cm4.h.

◆ FPU_FPDSCR_DN_Pos [1/13]

#define FPU_FPDSCR_DN_Pos   25U

FPDSCR: DN bit Position

Definition at line 2576 of file core_armv81mml.h.

◆ FPU_FPDSCR_DN_Pos [2/13]

#define FPU_FPDSCR_DN_Pos   25U

FPDSCR: DN bit Position

Definition at line 1695 of file core_armv8mml.h.

◆ FPU_FPDSCR_DN_Pos [3/13]

#define FPU_FPDSCR_DN_Pos   25U

FPDSCR: DN bit Position

Definition at line 1770 of file core_cm33.h.

◆ FPU_FPDSCR_DN_Pos [4/13]

#define FPU_FPDSCR_DN_Pos   25U

FPDSCR: DN bit Position

Definition at line 1770 of file core_cm35p.h.

◆ FPU_FPDSCR_DN_Pos [5/13]

#define FPU_FPDSCR_DN_Pos   25U

FPDSCR: DN bit Position

Definition at line 1368 of file core_cm4.h.

◆ FPU_FPDSCR_DN_Pos [6/13]

#define FPU_FPDSCR_DN_Pos   25U

FPDSCR: DN bit Position

Definition at line 3130 of file core_cm55.h.

◆ FPU_FPDSCR_DN_Pos [7/13]

#define FPU_FPDSCR_DN_Pos   25U

FPDSCR: DN bit Position

Definition at line 1595 of file core_cm7.h.

◆ FPU_FPDSCR_DN_Pos [8/13]

#define FPU_FPDSCR_DN_Pos   25U

FPDSCR: DN bit Position

Definition at line 3035 of file core_cm85.h.

◆ FPU_FPDSCR_DN_Pos [9/13]

#define FPU_FPDSCR_DN_Pos   25U

FPDSCR: DN bit Position

Definition at line 1828 of file core_starmc1.h.

◆ FPU_FPDSCR_DN_Pos [10/13]

#define FPU_FPDSCR_DN_Pos   25U

FPDSCR: DN bit Position

Definition at line 2576 of file core_armv81mml.h.

◆ FPU_FPDSCR_DN_Pos [11/13]

#define FPU_FPDSCR_DN_Pos   25U

FPDSCR: DN bit Position

Definition at line 1695 of file core_armv8mml.h.

◆ FPU_FPDSCR_DN_Pos [12/13]

#define FPU_FPDSCR_DN_Pos   25U

FPDSCR: DN bit Position

Definition at line 1770 of file core_cm33.h.

◆ FPU_FPDSCR_DN_Pos [13/13]

#define FPU_FPDSCR_DN_Pos   25U

FPDSCR: DN bit Position

Definition at line 1368 of file core_cm4.h.

◆ FPU_FPDSCR_FZ16_Msk [1/4]

#define FPU_FPDSCR_FZ16_Msk   (1UL << FPU_FPDSCR_FZ16_Pos)

FPDSCR: FZ16 bit Mask

Definition at line 2586 of file core_armv81mml.h.

◆ FPU_FPDSCR_FZ16_Msk [2/4]

#define FPU_FPDSCR_FZ16_Msk   (1UL << FPU_FPDSCR_FZ16_Pos)

FPDSCR: FZ16 bit Mask

Definition at line 3140 of file core_cm55.h.

◆ FPU_FPDSCR_FZ16_Msk [3/4]

#define FPU_FPDSCR_FZ16_Msk   (1UL << FPU_FPDSCR_FZ16_Pos)

FPDSCR: FZ16 bit Mask

Definition at line 3045 of file core_cm85.h.

◆ FPU_FPDSCR_FZ16_Msk [4/4]

#define FPU_FPDSCR_FZ16_Msk   (1UL << FPU_FPDSCR_FZ16_Pos)

FPDSCR: FZ16 bit Mask

Definition at line 2586 of file core_armv81mml.h.

◆ FPU_FPDSCR_FZ16_Pos [1/4]

#define FPU_FPDSCR_FZ16_Pos   19U

FPDSCR: FZ16 bit Position

Definition at line 2585 of file core_armv81mml.h.

◆ FPU_FPDSCR_FZ16_Pos [2/4]

#define FPU_FPDSCR_FZ16_Pos   19U

FPDSCR: FZ16 bit Position

Definition at line 3139 of file core_cm55.h.

◆ FPU_FPDSCR_FZ16_Pos [3/4]

#define FPU_FPDSCR_FZ16_Pos   19U

FPDSCR: FZ16 bit Position

Definition at line 3044 of file core_cm85.h.

◆ FPU_FPDSCR_FZ16_Pos [4/4]

#define FPU_FPDSCR_FZ16_Pos   19U

FPDSCR: FZ16 bit Position

Definition at line 2585 of file core_armv81mml.h.

◆ FPU_FPDSCR_FZ_Msk [1/13]

#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 2580 of file core_armv81mml.h.

◆ FPU_FPDSCR_FZ_Msk [2/13]

#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1699 of file core_armv8mml.h.

◆ FPU_FPDSCR_FZ_Msk [3/13]

#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1774 of file core_cm33.h.

◆ FPU_FPDSCR_FZ_Msk [4/13]

#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1774 of file core_cm35p.h.

◆ FPU_FPDSCR_FZ_Msk [5/13]

#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1372 of file core_cm4.h.

◆ FPU_FPDSCR_FZ_Msk [6/13]

#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 3134 of file core_cm55.h.

◆ FPU_FPDSCR_FZ_Msk [7/13]

#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1599 of file core_cm7.h.

◆ FPU_FPDSCR_FZ_Msk [8/13]

#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 3039 of file core_cm85.h.

◆ FPU_FPDSCR_FZ_Msk [9/13]

#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1832 of file core_starmc1.h.

◆ FPU_FPDSCR_FZ_Msk [10/13]

#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 2580 of file core_armv81mml.h.

◆ FPU_FPDSCR_FZ_Msk [11/13]

#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1699 of file core_armv8mml.h.

◆ FPU_FPDSCR_FZ_Msk [12/13]

#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1774 of file core_cm33.h.

◆ FPU_FPDSCR_FZ_Msk [13/13]

#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1372 of file core_cm4.h.

◆ FPU_FPDSCR_FZ_Pos [1/13]

#define FPU_FPDSCR_FZ_Pos   24U

FPDSCR: FZ bit Position

Definition at line 2579 of file core_armv81mml.h.

◆ FPU_FPDSCR_FZ_Pos [2/13]

#define FPU_FPDSCR_FZ_Pos   24U

FPDSCR: FZ bit Position

Definition at line 1698 of file core_armv8mml.h.

◆ FPU_FPDSCR_FZ_Pos [3/13]

#define FPU_FPDSCR_FZ_Pos   24U

FPDSCR: FZ bit Position

Definition at line 1773 of file core_cm33.h.

◆ FPU_FPDSCR_FZ_Pos [4/13]

#define FPU_FPDSCR_FZ_Pos   24U

FPDSCR: FZ bit Position

Definition at line 1773 of file core_cm35p.h.

◆ FPU_FPDSCR_FZ_Pos [5/13]

#define FPU_FPDSCR_FZ_Pos   24U

FPDSCR: FZ bit Position

Definition at line 1371 of file core_cm4.h.

◆ FPU_FPDSCR_FZ_Pos [6/13]

#define FPU_FPDSCR_FZ_Pos   24U

FPDSCR: FZ bit Position

Definition at line 3133 of file core_cm55.h.

◆ FPU_FPDSCR_FZ_Pos [7/13]

#define FPU_FPDSCR_FZ_Pos   24U

FPDSCR: FZ bit Position

Definition at line 1598 of file core_cm7.h.

◆ FPU_FPDSCR_FZ_Pos [8/13]

#define FPU_FPDSCR_FZ_Pos   24U

FPDSCR: FZ bit Position

Definition at line 3038 of file core_cm85.h.

◆ FPU_FPDSCR_FZ_Pos [9/13]

#define FPU_FPDSCR_FZ_Pos   24U

FPDSCR: FZ bit Position

Definition at line 1831 of file core_starmc1.h.

◆ FPU_FPDSCR_FZ_Pos [10/13]

#define FPU_FPDSCR_FZ_Pos   24U

FPDSCR: FZ bit Position

Definition at line 2579 of file core_armv81mml.h.

◆ FPU_FPDSCR_FZ_Pos [11/13]

#define FPU_FPDSCR_FZ_Pos   24U

FPDSCR: FZ bit Position

Definition at line 1698 of file core_armv8mml.h.

◆ FPU_FPDSCR_FZ_Pos [12/13]

#define FPU_FPDSCR_FZ_Pos   24U

FPDSCR: FZ bit Position

Definition at line 1773 of file core_cm33.h.

◆ FPU_FPDSCR_FZ_Pos [13/13]

#define FPU_FPDSCR_FZ_Pos   24U

FPDSCR: FZ bit Position

Definition at line 1371 of file core_cm4.h.

◆ FPU_FPDSCR_LTPSIZE_Msk [1/4]

#define FPU_FPDSCR_LTPSIZE_Msk   (7UL << FPU_FPDSCR_LTPSIZE_Pos)

FPDSCR: LTPSIZE bit Mask

Definition at line 2589 of file core_armv81mml.h.

◆ FPU_FPDSCR_LTPSIZE_Msk [2/4]

#define FPU_FPDSCR_LTPSIZE_Msk   (7UL << FPU_FPDSCR_LTPSIZE_Pos)

FPDSCR: LTPSIZE bit Mask

Definition at line 3143 of file core_cm55.h.

◆ FPU_FPDSCR_LTPSIZE_Msk [3/4]

#define FPU_FPDSCR_LTPSIZE_Msk   (7UL << FPU_FPDSCR_LTPSIZE_Pos)

FPDSCR: LTPSIZE bit Mask

Definition at line 3048 of file core_cm85.h.

◆ FPU_FPDSCR_LTPSIZE_Msk [4/4]

#define FPU_FPDSCR_LTPSIZE_Msk   (7UL << FPU_FPDSCR_LTPSIZE_Pos)

FPDSCR: LTPSIZE bit Mask

Definition at line 2589 of file core_armv81mml.h.

◆ FPU_FPDSCR_LTPSIZE_Pos [1/4]

#define FPU_FPDSCR_LTPSIZE_Pos   16U

FPDSCR: LTPSIZE bit Position

Definition at line 2588 of file core_armv81mml.h.

◆ FPU_FPDSCR_LTPSIZE_Pos [2/4]

#define FPU_FPDSCR_LTPSIZE_Pos   16U

FPDSCR: LTPSIZE bit Position

Definition at line 3142 of file core_cm55.h.

◆ FPU_FPDSCR_LTPSIZE_Pos [3/4]

#define FPU_FPDSCR_LTPSIZE_Pos   16U

FPDSCR: LTPSIZE bit Position

Definition at line 3047 of file core_cm85.h.

◆ FPU_FPDSCR_LTPSIZE_Pos [4/4]

#define FPU_FPDSCR_LTPSIZE_Pos   16U

FPDSCR: LTPSIZE bit Position

Definition at line 2588 of file core_armv81mml.h.

◆ FPU_FPDSCR_RMode_Msk [1/13]

#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 2583 of file core_armv81mml.h.

◆ FPU_FPDSCR_RMode_Msk [2/13]

#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1702 of file core_armv8mml.h.

◆ FPU_FPDSCR_RMode_Msk [3/13]

#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1777 of file core_cm33.h.

◆ FPU_FPDSCR_RMode_Msk [4/13]

#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1777 of file core_cm35p.h.

◆ FPU_FPDSCR_RMode_Msk [5/13]

#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1375 of file core_cm4.h.

◆ FPU_FPDSCR_RMode_Msk [6/13]

#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 3137 of file core_cm55.h.

◆ FPU_FPDSCR_RMode_Msk [7/13]

#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1602 of file core_cm7.h.

◆ FPU_FPDSCR_RMode_Msk [8/13]

#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 3042 of file core_cm85.h.

◆ FPU_FPDSCR_RMode_Msk [9/13]

#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1835 of file core_starmc1.h.

◆ FPU_FPDSCR_RMode_Msk [10/13]

#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 2583 of file core_armv81mml.h.

◆ FPU_FPDSCR_RMode_Msk [11/13]

#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1702 of file core_armv8mml.h.

◆ FPU_FPDSCR_RMode_Msk [12/13]

#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1777 of file core_cm33.h.

◆ FPU_FPDSCR_RMode_Msk [13/13]

#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1375 of file core_cm4.h.

◆ FPU_FPDSCR_RMode_Pos [1/13]

#define FPU_FPDSCR_RMode_Pos   22U

FPDSCR: RMode bit Position

Definition at line 2582 of file core_armv81mml.h.

◆ FPU_FPDSCR_RMode_Pos [2/13]

#define FPU_FPDSCR_RMode_Pos   22U

FPDSCR: RMode bit Position

Definition at line 1701 of file core_armv8mml.h.

◆ FPU_FPDSCR_RMode_Pos [3/13]

#define FPU_FPDSCR_RMode_Pos   22U

FPDSCR: RMode bit Position

Definition at line 1776 of file core_cm33.h.

◆ FPU_FPDSCR_RMode_Pos [4/13]

#define FPU_FPDSCR_RMode_Pos   22U

FPDSCR: RMode bit Position

Definition at line 1776 of file core_cm35p.h.

◆ FPU_FPDSCR_RMode_Pos [5/13]

#define FPU_FPDSCR_RMode_Pos   22U

FPDSCR: RMode bit Position

Definition at line 1374 of file core_cm4.h.

◆ FPU_FPDSCR_RMode_Pos [6/13]

#define FPU_FPDSCR_RMode_Pos   22U

FPDSCR: RMode bit Position

Definition at line 3136 of file core_cm55.h.

◆ FPU_FPDSCR_RMode_Pos [7/13]

#define FPU_FPDSCR_RMode_Pos   22U

FPDSCR: RMode bit Position

Definition at line 1601 of file core_cm7.h.

◆ FPU_FPDSCR_RMode_Pos [8/13]

#define FPU_FPDSCR_RMode_Pos   22U

FPDSCR: RMode bit Position

Definition at line 3041 of file core_cm85.h.

◆ FPU_FPDSCR_RMode_Pos [9/13]

#define FPU_FPDSCR_RMode_Pos   22U

FPDSCR: RMode bit Position

Definition at line 1834 of file core_starmc1.h.

◆ FPU_FPDSCR_RMode_Pos [10/13]

#define FPU_FPDSCR_RMode_Pos   22U

FPDSCR: RMode bit Position

Definition at line 2582 of file core_armv81mml.h.

◆ FPU_FPDSCR_RMode_Pos [11/13]

#define FPU_FPDSCR_RMode_Pos   22U

FPDSCR: RMode bit Position

Definition at line 1701 of file core_armv8mml.h.

◆ FPU_FPDSCR_RMode_Pos [12/13]

#define FPU_FPDSCR_RMode_Pos   22U

FPDSCR: RMode bit Position

Definition at line 1776 of file core_cm33.h.

◆ FPU_FPDSCR_RMode_Pos [13/13]

#define FPU_FPDSCR_RMode_Pos   22U

FPDSCR: RMode bit Position

Definition at line 1374 of file core_cm4.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [1/9]

#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1727 of file core_armv8mml.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [2/9]

#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1802 of file core_cm33.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [3/9]

#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1802 of file core_cm35p.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [4/9]

#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1400 of file core_cm4.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [5/9]

#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1627 of file core_cm7.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [6/9]

#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1860 of file core_starmc1.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [7/9]

#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1727 of file core_armv8mml.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [8/9]

#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1802 of file core_cm33.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [9/9]

#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1400 of file core_cm4.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [1/9]

#define FPU_MVFR0_A_SIMD_registers_Pos   0U

MVFR0: A_SIMD registers bits Position

Definition at line 1726 of file core_armv8mml.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [2/9]

#define FPU_MVFR0_A_SIMD_registers_Pos   0U

MVFR0: A_SIMD registers bits Position

Definition at line 1801 of file core_cm33.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [3/9]

#define FPU_MVFR0_A_SIMD_registers_Pos   0U

MVFR0: A_SIMD registers bits Position

Definition at line 1801 of file core_cm35p.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [4/9]

#define FPU_MVFR0_A_SIMD_registers_Pos   0U

MVFR0: A_SIMD registers bits Position

Definition at line 1399 of file core_cm4.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [5/9]

#define FPU_MVFR0_A_SIMD_registers_Pos   0U

MVFR0: A_SIMD registers bits Position

Definition at line 1626 of file core_cm7.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [6/9]

#define FPU_MVFR0_A_SIMD_registers_Pos   0U

MVFR0: A_SIMD registers bits Position

Definition at line 1859 of file core_starmc1.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [7/9]

#define FPU_MVFR0_A_SIMD_registers_Pos   0U

MVFR0: A_SIMD registers bits Position

Definition at line 1726 of file core_armv8mml.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [8/9]

#define FPU_MVFR0_A_SIMD_registers_Pos   0U

MVFR0: A_SIMD registers bits Position

Definition at line 1801 of file core_cm33.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [9/9]

#define FPU_MVFR0_A_SIMD_registers_Pos   0U

MVFR0: A_SIMD registers bits Position

Definition at line 1399 of file core_cm4.h.

◆ FPU_MVFR0_Divide_Msk [1/9]

#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1715 of file core_armv8mml.h.

◆ FPU_MVFR0_Divide_Msk [2/9]

#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1790 of file core_cm33.h.

◆ FPU_MVFR0_Divide_Msk [3/9]

#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1790 of file core_cm35p.h.

◆ FPU_MVFR0_Divide_Msk [4/9]

#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1388 of file core_cm4.h.

◆ FPU_MVFR0_Divide_Msk [5/9]

#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1615 of file core_cm7.h.

◆ FPU_MVFR0_Divide_Msk [6/9]

#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1848 of file core_starmc1.h.

◆ FPU_MVFR0_Divide_Msk [7/9]

#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1715 of file core_armv8mml.h.

◆ FPU_MVFR0_Divide_Msk [8/9]

#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1790 of file core_cm33.h.

◆ FPU_MVFR0_Divide_Msk [9/9]

#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1388 of file core_cm4.h.

◆ FPU_MVFR0_Divide_Pos [1/9]

#define FPU_MVFR0_Divide_Pos   16U

MVFR0: Divide bits Position

Definition at line 1714 of file core_armv8mml.h.

◆ FPU_MVFR0_Divide_Pos [2/9]

#define FPU_MVFR0_Divide_Pos   16U

MVFR0: Divide bits Position

Definition at line 1789 of file core_cm33.h.

◆ FPU_MVFR0_Divide_Pos [3/9]

#define FPU_MVFR0_Divide_Pos   16U

MVFR0: Divide bits Position

Definition at line 1789 of file core_cm35p.h.

◆ FPU_MVFR0_Divide_Pos [4/9]

#define FPU_MVFR0_Divide_Pos   16U

MVFR0: Divide bits Position

Definition at line 1387 of file core_cm4.h.

◆ FPU_MVFR0_Divide_Pos [5/9]

#define FPU_MVFR0_Divide_Pos   16U

MVFR0: Divide bits Position

Definition at line 1614 of file core_cm7.h.

◆ FPU_MVFR0_Divide_Pos [6/9]

#define FPU_MVFR0_Divide_Pos   16U

MVFR0: Divide bits Position

Definition at line 1847 of file core_starmc1.h.

◆ FPU_MVFR0_Divide_Pos [7/9]

#define FPU_MVFR0_Divide_Pos   16U

MVFR0: Divide bits Position

Definition at line 1714 of file core_armv8mml.h.

◆ FPU_MVFR0_Divide_Pos [8/9]

#define FPU_MVFR0_Divide_Pos   16U

MVFR0: Divide bits Position

Definition at line 1789 of file core_cm33.h.

◆ FPU_MVFR0_Divide_Pos [9/9]

#define FPU_MVFR0_Divide_Pos   16U

MVFR0: Divide bits Position

Definition at line 1387 of file core_cm4.h.

◆ FPU_MVFR0_Double_precision_Msk [1/9]

#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1721 of file core_armv8mml.h.

◆ FPU_MVFR0_Double_precision_Msk [2/9]

#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1796 of file core_cm33.h.

◆ FPU_MVFR0_Double_precision_Msk [3/9]

#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1796 of file core_cm35p.h.

◆ FPU_MVFR0_Double_precision_Msk [4/9]

#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1394 of file core_cm4.h.

◆ FPU_MVFR0_Double_precision_Msk [5/9]

#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1621 of file core_cm7.h.

◆ FPU_MVFR0_Double_precision_Msk [6/9]

#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1854 of file core_starmc1.h.

◆ FPU_MVFR0_Double_precision_Msk [7/9]

#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1721 of file core_armv8mml.h.

◆ FPU_MVFR0_Double_precision_Msk [8/9]

#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1796 of file core_cm33.h.

◆ FPU_MVFR0_Double_precision_Msk [9/9]

#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1394 of file core_cm4.h.

◆ FPU_MVFR0_Double_precision_Pos [1/9]

#define FPU_MVFR0_Double_precision_Pos   8U

MVFR0: Double-precision bits Position

Definition at line 1720 of file core_armv8mml.h.

◆ FPU_MVFR0_Double_precision_Pos [2/9]

#define FPU_MVFR0_Double_precision_Pos   8U

MVFR0: Double-precision bits Position

Definition at line 1795 of file core_cm33.h.

◆ FPU_MVFR0_Double_precision_Pos [3/9]

#define FPU_MVFR0_Double_precision_Pos   8U

MVFR0: Double-precision bits Position

Definition at line 1795 of file core_cm35p.h.

◆ FPU_MVFR0_Double_precision_Pos [4/9]

#define FPU_MVFR0_Double_precision_Pos   8U

MVFR0: Double-precision bits Position

Definition at line 1393 of file core_cm4.h.

◆ FPU_MVFR0_Double_precision_Pos [5/9]

#define FPU_MVFR0_Double_precision_Pos   8U

MVFR0: Double-precision bits Position

Definition at line 1620 of file core_cm7.h.

◆ FPU_MVFR0_Double_precision_Pos [6/9]

#define FPU_MVFR0_Double_precision_Pos   8U

MVFR0: Double-precision bits Position

Definition at line 1853 of file core_starmc1.h.

◆ FPU_MVFR0_Double_precision_Pos [7/9]

#define FPU_MVFR0_Double_precision_Pos   8U

MVFR0: Double-precision bits Position

Definition at line 1720 of file core_armv8mml.h.

◆ FPU_MVFR0_Double_precision_Pos [8/9]

#define FPU_MVFR0_Double_precision_Pos   8U

MVFR0: Double-precision bits Position

Definition at line 1795 of file core_cm33.h.

◆ FPU_MVFR0_Double_precision_Pos [9/9]

#define FPU_MVFR0_Double_precision_Pos   8U

MVFR0: Double-precision bits Position

Definition at line 1393 of file core_cm4.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [1/9]

#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1718 of file core_armv8mml.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [2/9]

#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1793 of file core_cm33.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [3/9]

#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1793 of file core_cm35p.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [4/9]

#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1391 of file core_cm4.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [5/9]

#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1618 of file core_cm7.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [6/9]

#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1851 of file core_starmc1.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [7/9]

#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1718 of file core_armv8mml.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [8/9]

#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1793 of file core_cm33.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [9/9]

#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1391 of file core_cm4.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [1/9]

#define FPU_MVFR0_FP_excep_trapping_Pos   12U

MVFR0: FP exception trapping bits Position

Definition at line 1717 of file core_armv8mml.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [2/9]

#define FPU_MVFR0_FP_excep_trapping_Pos   12U

MVFR0: FP exception trapping bits Position

Definition at line 1792 of file core_cm33.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [3/9]

#define FPU_MVFR0_FP_excep_trapping_Pos   12U

MVFR0: FP exception trapping bits Position

Definition at line 1792 of file core_cm35p.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [4/9]

#define FPU_MVFR0_FP_excep_trapping_Pos   12U

MVFR0: FP exception trapping bits Position

Definition at line 1390 of file core_cm4.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [5/9]

#define FPU_MVFR0_FP_excep_trapping_Pos   12U

MVFR0: FP exception trapping bits Position

Definition at line 1617 of file core_cm7.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [6/9]

#define FPU_MVFR0_FP_excep_trapping_Pos   12U

MVFR0: FP exception trapping bits Position

Definition at line 1850 of file core_starmc1.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [7/9]

#define FPU_MVFR0_FP_excep_trapping_Pos   12U

MVFR0: FP exception trapping bits Position

Definition at line 1717 of file core_armv8mml.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [8/9]

#define FPU_MVFR0_FP_excep_trapping_Pos   12U

MVFR0: FP exception trapping bits Position

Definition at line 1792 of file core_cm33.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [9/9]

#define FPU_MVFR0_FP_excep_trapping_Pos   12U

MVFR0: FP exception trapping bits Position

Definition at line 1390 of file core_cm4.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [1/9]

#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1706 of file core_armv8mml.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [2/9]

#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1781 of file core_cm33.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [3/9]

#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1781 of file core_cm35p.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [4/9]

#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1379 of file core_cm4.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [5/9]

#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1606 of file core_cm7.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [6/9]

#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1839 of file core_starmc1.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [7/9]

#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1706 of file core_armv8mml.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [8/9]

#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1781 of file core_cm33.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [9/9]

#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1379 of file core_cm4.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [1/9]

#define FPU_MVFR0_FP_rounding_modes_Pos   28U

MVFR0: FP rounding modes bits Position

Definition at line 1705 of file core_armv8mml.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [2/9]

#define FPU_MVFR0_FP_rounding_modes_Pos   28U

MVFR0: FP rounding modes bits Position

Definition at line 1780 of file core_cm33.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [3/9]

#define FPU_MVFR0_FP_rounding_modes_Pos   28U

MVFR0: FP rounding modes bits Position

Definition at line 1780 of file core_cm35p.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [4/9]

#define FPU_MVFR0_FP_rounding_modes_Pos   28U

MVFR0: FP rounding modes bits Position

Definition at line 1378 of file core_cm4.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [5/9]

#define FPU_MVFR0_FP_rounding_modes_Pos   28U

MVFR0: FP rounding modes bits Position

Definition at line 1605 of file core_cm7.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [6/9]

#define FPU_MVFR0_FP_rounding_modes_Pos   28U

MVFR0: FP rounding modes bits Position

Definition at line 1838 of file core_starmc1.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [7/9]

#define FPU_MVFR0_FP_rounding_modes_Pos   28U

MVFR0: FP rounding modes bits Position

Definition at line 1705 of file core_armv8mml.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [8/9]

#define FPU_MVFR0_FP_rounding_modes_Pos   28U

MVFR0: FP rounding modes bits Position

Definition at line 1780 of file core_cm33.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [9/9]

#define FPU_MVFR0_FP_rounding_modes_Pos   28U

MVFR0: FP rounding modes bits Position

Definition at line 1378 of file core_cm4.h.

◆ FPU_MVFR0_FPDivide_Msk [1/4]

#define FPU_MVFR0_FPDivide_Msk   (0xFUL << FPU_MVFR0_FPDivide_Pos)

MVFR0: Divide bits Mask

Definition at line 2599 of file core_armv81mml.h.

◆ FPU_MVFR0_FPDivide_Msk [2/4]

#define FPU_MVFR0_FPDivide_Msk   (0xFUL << FPU_MVFR0_FPDivide_Pos)

MVFR0: Divide bits Mask

Definition at line 3153 of file core_cm55.h.

◆ FPU_MVFR0_FPDivide_Msk [3/4]

#define FPU_MVFR0_FPDivide_Msk   (0xFUL << FPU_MVFR0_FPDivide_Pos)

MVFR0: Divide bits Mask

Definition at line 3058 of file core_cm85.h.

◆ FPU_MVFR0_FPDivide_Msk [4/4]

#define FPU_MVFR0_FPDivide_Msk   (0xFUL << FPU_MVFR0_FPDivide_Pos)

MVFR0: Divide bits Mask

Definition at line 2599 of file core_armv81mml.h.

◆ FPU_MVFR0_FPDivide_Pos [1/4]

#define FPU_MVFR0_FPDivide_Pos   16U

MVFR0: FPDivide bits Position

Definition at line 2598 of file core_armv81mml.h.

◆ FPU_MVFR0_FPDivide_Pos [2/4]

#define FPU_MVFR0_FPDivide_Pos   16U

MVFR0: FPDivide bits Position

Definition at line 3152 of file core_cm55.h.

◆ FPU_MVFR0_FPDivide_Pos [3/4]

#define FPU_MVFR0_FPDivide_Pos   16U

MVFR0: FPDivide bits Position

Definition at line 3057 of file core_cm85.h.

◆ FPU_MVFR0_FPDivide_Pos [4/4]

#define FPU_MVFR0_FPDivide_Pos   16U

MVFR0: FPDivide bits Position

Definition at line 2598 of file core_armv81mml.h.

◆ FPU_MVFR0_FPDP_Msk [1/4]

#define FPU_MVFR0_FPDP_Msk   (0xFUL << FPU_MVFR0_FPDP_Pos)

MVFR0: FPDP bits Mask

Definition at line 2602 of file core_armv81mml.h.

◆ FPU_MVFR0_FPDP_Msk [2/4]

#define FPU_MVFR0_FPDP_Msk   (0xFUL << FPU_MVFR0_FPDP_Pos)

MVFR0: FPDP bits Mask

Definition at line 3156 of file core_cm55.h.

◆ FPU_MVFR0_FPDP_Msk [3/4]

#define FPU_MVFR0_FPDP_Msk   (0xFUL << FPU_MVFR0_FPDP_Pos)

MVFR0: FPDP bits Mask

Definition at line 3061 of file core_cm85.h.

◆ FPU_MVFR0_FPDP_Msk [4/4]

#define FPU_MVFR0_FPDP_Msk   (0xFUL << FPU_MVFR0_FPDP_Pos)

MVFR0: FPDP bits Mask

Definition at line 2602 of file core_armv81mml.h.

◆ FPU_MVFR0_FPDP_Pos [1/4]

#define FPU_MVFR0_FPDP_Pos   8U

MVFR0: FPDP bits Position

Definition at line 2601 of file core_armv81mml.h.

◆ FPU_MVFR0_FPDP_Pos [2/4]

#define FPU_MVFR0_FPDP_Pos   8U

MVFR0: FPDP bits Position

Definition at line 3155 of file core_cm55.h.

◆ FPU_MVFR0_FPDP_Pos [3/4]

#define FPU_MVFR0_FPDP_Pos   8U

MVFR0: FPDP bits Position

Definition at line 3060 of file core_cm85.h.

◆ FPU_MVFR0_FPDP_Pos [4/4]

#define FPU_MVFR0_FPDP_Pos   8U

MVFR0: FPDP bits Position

Definition at line 2601 of file core_armv81mml.h.

◆ FPU_MVFR0_FPRound_Msk [1/4]

#define FPU_MVFR0_FPRound_Msk   (0xFUL << FPU_MVFR0_FPRound_Pos)

MVFR0: FPRound bits Mask

Definition at line 2593 of file core_armv81mml.h.

◆ FPU_MVFR0_FPRound_Msk [2/4]

#define FPU_MVFR0_FPRound_Msk   (0xFUL << FPU_MVFR0_FPRound_Pos)

MVFR0: FPRound bits Mask

Definition at line 3147 of file core_cm55.h.

◆ FPU_MVFR0_FPRound_Msk [3/4]

#define FPU_MVFR0_FPRound_Msk   (0xFUL << FPU_MVFR0_FPRound_Pos)

MVFR0: FPRound bits Mask

Definition at line 3052 of file core_cm85.h.

◆ FPU_MVFR0_FPRound_Msk [4/4]

#define FPU_MVFR0_FPRound_Msk   (0xFUL << FPU_MVFR0_FPRound_Pos)

MVFR0: FPRound bits Mask

Definition at line 2593 of file core_armv81mml.h.

◆ FPU_MVFR0_FPRound_Pos [1/4]

#define FPU_MVFR0_FPRound_Pos   28U

MVFR0: FPRound bits Position

Definition at line 2592 of file core_armv81mml.h.

◆ FPU_MVFR0_FPRound_Pos [2/4]

#define FPU_MVFR0_FPRound_Pos   28U

MVFR0: FPRound bits Position

Definition at line 3146 of file core_cm55.h.

◆ FPU_MVFR0_FPRound_Pos [3/4]

#define FPU_MVFR0_FPRound_Pos   28U

MVFR0: FPRound bits Position

Definition at line 3051 of file core_cm85.h.

◆ FPU_MVFR0_FPRound_Pos [4/4]

#define FPU_MVFR0_FPRound_Pos   28U

MVFR0: FPRound bits Position

Definition at line 2592 of file core_armv81mml.h.

◆ FPU_MVFR0_FPSP_Msk [1/4]

#define FPU_MVFR0_FPSP_Msk   (0xFUL << FPU_MVFR0_FPSP_Pos)

MVFR0: FPSP bits Mask

Definition at line 2605 of file core_armv81mml.h.

◆ FPU_MVFR0_FPSP_Msk [2/4]

#define FPU_MVFR0_FPSP_Msk   (0xFUL << FPU_MVFR0_FPSP_Pos)

MVFR0: FPSP bits Mask

Definition at line 3159 of file core_cm55.h.

◆ FPU_MVFR0_FPSP_Msk [3/4]

#define FPU_MVFR0_FPSP_Msk   (0xFUL << FPU_MVFR0_FPSP_Pos)

MVFR0: FPSP bits Mask

Definition at line 3064 of file core_cm85.h.

◆ FPU_MVFR0_FPSP_Msk [4/4]

#define FPU_MVFR0_FPSP_Msk   (0xFUL << FPU_MVFR0_FPSP_Pos)

MVFR0: FPSP bits Mask

Definition at line 2605 of file core_armv81mml.h.

◆ FPU_MVFR0_FPSP_Pos [1/4]

#define FPU_MVFR0_FPSP_Pos   4U

MVFR0: FPSP bits Position

Definition at line 2604 of file core_armv81mml.h.

◆ FPU_MVFR0_FPSP_Pos [2/4]

#define FPU_MVFR0_FPSP_Pos   4U

MVFR0: FPSP bits Position

Definition at line 3158 of file core_cm55.h.

◆ FPU_MVFR0_FPSP_Pos [3/4]

#define FPU_MVFR0_FPSP_Pos   4U

MVFR0: FPSP bits Position

Definition at line 3063 of file core_cm85.h.

◆ FPU_MVFR0_FPSP_Pos [4/4]

#define FPU_MVFR0_FPSP_Pos   4U

MVFR0: FPSP bits Position

Definition at line 2604 of file core_armv81mml.h.

◆ FPU_MVFR0_FPSqrt_Msk [1/4]

#define FPU_MVFR0_FPSqrt_Msk   (0xFUL << FPU_MVFR0_FPSqrt_Pos)

MVFR0: FPSqrt bits Mask

Definition at line 2596 of file core_armv81mml.h.

◆ FPU_MVFR0_FPSqrt_Msk [2/4]

#define FPU_MVFR0_FPSqrt_Msk   (0xFUL << FPU_MVFR0_FPSqrt_Pos)

MVFR0: FPSqrt bits Mask

Definition at line 3150 of file core_cm55.h.

◆ FPU_MVFR0_FPSqrt_Msk [3/4]

#define FPU_MVFR0_FPSqrt_Msk   (0xFUL << FPU_MVFR0_FPSqrt_Pos)

MVFR0: FPSqrt bits Mask

Definition at line 3055 of file core_cm85.h.

◆ FPU_MVFR0_FPSqrt_Msk [4/4]

#define FPU_MVFR0_FPSqrt_Msk   (0xFUL << FPU_MVFR0_FPSqrt_Pos)

MVFR0: FPSqrt bits Mask

Definition at line 2596 of file core_armv81mml.h.

◆ FPU_MVFR0_FPSqrt_Pos [1/4]

#define FPU_MVFR0_FPSqrt_Pos   20U

MVFR0: FPSqrt bits Position

Definition at line 2595 of file core_armv81mml.h.

◆ FPU_MVFR0_FPSqrt_Pos [2/4]

#define FPU_MVFR0_FPSqrt_Pos   20U

MVFR0: FPSqrt bits Position

Definition at line 3149 of file core_cm55.h.

◆ FPU_MVFR0_FPSqrt_Pos [3/4]

#define FPU_MVFR0_FPSqrt_Pos   20U

MVFR0: FPSqrt bits Position

Definition at line 3054 of file core_cm85.h.

◆ FPU_MVFR0_FPSqrt_Pos [4/4]

#define FPU_MVFR0_FPSqrt_Pos   20U

MVFR0: FPSqrt bits Position

Definition at line 2595 of file core_armv81mml.h.

◆ FPU_MVFR0_Short_vectors_Msk [1/9]

#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1709 of file core_armv8mml.h.

◆ FPU_MVFR0_Short_vectors_Msk [2/9]

#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1784 of file core_cm33.h.

◆ FPU_MVFR0_Short_vectors_Msk [3/9]

#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1784 of file core_cm35p.h.

◆ FPU_MVFR0_Short_vectors_Msk [4/9]

#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1382 of file core_cm4.h.

◆ FPU_MVFR0_Short_vectors_Msk [5/9]

#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1609 of file core_cm7.h.

◆ FPU_MVFR0_Short_vectors_Msk [6/9]

#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1842 of file core_starmc1.h.

◆ FPU_MVFR0_Short_vectors_Msk [7/9]

#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1709 of file core_armv8mml.h.

◆ FPU_MVFR0_Short_vectors_Msk [8/9]

#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1784 of file core_cm33.h.

◆ FPU_MVFR0_Short_vectors_Msk [9/9]

#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1382 of file core_cm4.h.

◆ FPU_MVFR0_Short_vectors_Pos [1/9]

#define FPU_MVFR0_Short_vectors_Pos   24U

MVFR0: Short vectors bits Position

Definition at line 1708 of file core_armv8mml.h.

◆ FPU_MVFR0_Short_vectors_Pos [2/9]

#define FPU_MVFR0_Short_vectors_Pos   24U

MVFR0: Short vectors bits Position

Definition at line 1783 of file core_cm33.h.

◆ FPU_MVFR0_Short_vectors_Pos [3/9]

#define FPU_MVFR0_Short_vectors_Pos   24U

MVFR0: Short vectors bits Position

Definition at line 1783 of file core_cm35p.h.

◆ FPU_MVFR0_Short_vectors_Pos [4/9]

#define FPU_MVFR0_Short_vectors_Pos   24U

MVFR0: Short vectors bits Position

Definition at line 1381 of file core_cm4.h.

◆ FPU_MVFR0_Short_vectors_Pos [5/9]

#define FPU_MVFR0_Short_vectors_Pos   24U

MVFR0: Short vectors bits Position

Definition at line 1608 of file core_cm7.h.

◆ FPU_MVFR0_Short_vectors_Pos [6/9]

#define FPU_MVFR0_Short_vectors_Pos   24U

MVFR0: Short vectors bits Position

Definition at line 1841 of file core_starmc1.h.

◆ FPU_MVFR0_Short_vectors_Pos [7/9]

#define FPU_MVFR0_Short_vectors_Pos   24U

MVFR0: Short vectors bits Position

Definition at line 1708 of file core_armv8mml.h.

◆ FPU_MVFR0_Short_vectors_Pos [8/9]

#define FPU_MVFR0_Short_vectors_Pos   24U

MVFR0: Short vectors bits Position

Definition at line 1783 of file core_cm33.h.

◆ FPU_MVFR0_Short_vectors_Pos [9/9]

#define FPU_MVFR0_Short_vectors_Pos   24U

MVFR0: Short vectors bits Position

Definition at line 1381 of file core_cm4.h.

◆ FPU_MVFR0_SIMDReg_Msk [1/4]

#define FPU_MVFR0_SIMDReg_Msk   (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)

MVFR0: SIMDReg bits Mask

Definition at line 2608 of file core_armv81mml.h.

◆ FPU_MVFR0_SIMDReg_Msk [2/4]

#define FPU_MVFR0_SIMDReg_Msk   (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)

MVFR0: SIMDReg bits Mask

Definition at line 3162 of file core_cm55.h.

◆ FPU_MVFR0_SIMDReg_Msk [3/4]

#define FPU_MVFR0_SIMDReg_Msk   (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)

MVFR0: SIMDReg bits Mask

Definition at line 3067 of file core_cm85.h.

◆ FPU_MVFR0_SIMDReg_Msk [4/4]

#define FPU_MVFR0_SIMDReg_Msk   (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)

MVFR0: SIMDReg bits Mask

Definition at line 2608 of file core_armv81mml.h.

◆ FPU_MVFR0_SIMDReg_Pos [1/4]

#define FPU_MVFR0_SIMDReg_Pos   0U

MVFR0: SIMDReg bits Position

Definition at line 2607 of file core_armv81mml.h.

◆ FPU_MVFR0_SIMDReg_Pos [2/4]

#define FPU_MVFR0_SIMDReg_Pos   0U

MVFR0: SIMDReg bits Position

Definition at line 3161 of file core_cm55.h.

◆ FPU_MVFR0_SIMDReg_Pos [3/4]

#define FPU_MVFR0_SIMDReg_Pos   0U

MVFR0: SIMDReg bits Position

Definition at line 3066 of file core_cm85.h.

◆ FPU_MVFR0_SIMDReg_Pos [4/4]

#define FPU_MVFR0_SIMDReg_Pos   0U

MVFR0: SIMDReg bits Position

Definition at line 2607 of file core_armv81mml.h.

◆ FPU_MVFR0_Single_precision_Msk [1/9]

#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1724 of file core_armv8mml.h.

◆ FPU_MVFR0_Single_precision_Msk [2/9]

#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1799 of file core_cm33.h.

◆ FPU_MVFR0_Single_precision_Msk [3/9]

#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1799 of file core_cm35p.h.

◆ FPU_MVFR0_Single_precision_Msk [4/9]

#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1397 of file core_cm4.h.

◆ FPU_MVFR0_Single_precision_Msk [5/9]

#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1624 of file core_cm7.h.

◆ FPU_MVFR0_Single_precision_Msk [6/9]

#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1857 of file core_starmc1.h.

◆ FPU_MVFR0_Single_precision_Msk [7/9]

#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1724 of file core_armv8mml.h.

◆ FPU_MVFR0_Single_precision_Msk [8/9]

#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1799 of file core_cm33.h.

◆ FPU_MVFR0_Single_precision_Msk [9/9]

#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1397 of file core_cm4.h.

◆ FPU_MVFR0_Single_precision_Pos [1/9]

#define FPU_MVFR0_Single_precision_Pos   4U

MVFR0: Single-precision bits Position

Definition at line 1723 of file core_armv8mml.h.

◆ FPU_MVFR0_Single_precision_Pos [2/9]

#define FPU_MVFR0_Single_precision_Pos   4U

MVFR0: Single-precision bits Position

Definition at line 1798 of file core_cm33.h.

◆ FPU_MVFR0_Single_precision_Pos [3/9]

#define FPU_MVFR0_Single_precision_Pos   4U

MVFR0: Single-precision bits Position

Definition at line 1798 of file core_cm35p.h.

◆ FPU_MVFR0_Single_precision_Pos [4/9]

#define FPU_MVFR0_Single_precision_Pos   4U

MVFR0: Single-precision bits Position

Definition at line 1396 of file core_cm4.h.

◆ FPU_MVFR0_Single_precision_Pos [5/9]

#define FPU_MVFR0_Single_precision_Pos   4U

MVFR0: Single-precision bits Position

Definition at line 1623 of file core_cm7.h.

◆ FPU_MVFR0_Single_precision_Pos [6/9]

#define FPU_MVFR0_Single_precision_Pos   4U

MVFR0: Single-precision bits Position

Definition at line 1856 of file core_starmc1.h.

◆ FPU_MVFR0_Single_precision_Pos [7/9]

#define FPU_MVFR0_Single_precision_Pos   4U

MVFR0: Single-precision bits Position

Definition at line 1723 of file core_armv8mml.h.

◆ FPU_MVFR0_Single_precision_Pos [8/9]

#define FPU_MVFR0_Single_precision_Pos   4U

MVFR0: Single-precision bits Position

Definition at line 1798 of file core_cm33.h.

◆ FPU_MVFR0_Single_precision_Pos [9/9]

#define FPU_MVFR0_Single_precision_Pos   4U

MVFR0: Single-precision bits Position

Definition at line 1396 of file core_cm4.h.

◆ FPU_MVFR0_Square_root_Msk [1/9]

#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1712 of file core_armv8mml.h.

◆ FPU_MVFR0_Square_root_Msk [2/9]

#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1787 of file core_cm33.h.

◆ FPU_MVFR0_Square_root_Msk [3/9]

#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1787 of file core_cm35p.h.

◆ FPU_MVFR0_Square_root_Msk [4/9]

#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1385 of file core_cm4.h.

◆ FPU_MVFR0_Square_root_Msk [5/9]

#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1612 of file core_cm7.h.

◆ FPU_MVFR0_Square_root_Msk [6/9]

#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1845 of file core_starmc1.h.

◆ FPU_MVFR0_Square_root_Msk [7/9]

#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1712 of file core_armv8mml.h.

◆ FPU_MVFR0_Square_root_Msk [8/9]

#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1787 of file core_cm33.h.

◆ FPU_MVFR0_Square_root_Msk [9/9]

#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1385 of file core_cm4.h.

◆ FPU_MVFR0_Square_root_Pos [1/9]

#define FPU_MVFR0_Square_root_Pos   20U

MVFR0: Square root bits Position

Definition at line 1711 of file core_armv8mml.h.

◆ FPU_MVFR0_Square_root_Pos [2/9]

#define FPU_MVFR0_Square_root_Pos   20U

MVFR0: Square root bits Position

Definition at line 1786 of file core_cm33.h.

◆ FPU_MVFR0_Square_root_Pos [3/9]

#define FPU_MVFR0_Square_root_Pos   20U

MVFR0: Square root bits Position

Definition at line 1786 of file core_cm35p.h.

◆ FPU_MVFR0_Square_root_Pos [4/9]

#define FPU_MVFR0_Square_root_Pos   20U

MVFR0: Square root bits Position

Definition at line 1384 of file core_cm4.h.

◆ FPU_MVFR0_Square_root_Pos [5/9]

#define FPU_MVFR0_Square_root_Pos   20U

MVFR0: Square root bits Position

Definition at line 1611 of file core_cm7.h.

◆ FPU_MVFR0_Square_root_Pos [6/9]

#define FPU_MVFR0_Square_root_Pos   20U

MVFR0: Square root bits Position

Definition at line 1844 of file core_starmc1.h.

◆ FPU_MVFR0_Square_root_Pos [7/9]

#define FPU_MVFR0_Square_root_Pos   20U

MVFR0: Square root bits Position

Definition at line 1711 of file core_armv8mml.h.

◆ FPU_MVFR0_Square_root_Pos [8/9]

#define FPU_MVFR0_Square_root_Pos   20U

MVFR0: Square root bits Position

Definition at line 1786 of file core_cm33.h.

◆ FPU_MVFR0_Square_root_Pos [9/9]

#define FPU_MVFR0_Square_root_Pos   20U

MVFR0: Square root bits Position

Definition at line 1384 of file core_cm4.h.

◆ FPU_MVFR1_D_NaN_mode_Msk [1/9]

#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

Definition at line 1737 of file core_armv8mml.h.

◆ FPU_MVFR1_D_NaN_mode_Msk [2/9]

#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

Definition at line 1812 of file core_cm33.h.

◆ FPU_MVFR1_D_NaN_mode_Msk [3/9]

#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

Definition at line 1812 of file core_cm35p.h.

◆ FPU_MVFR1_D_NaN_mode_Msk [4/9]

#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

Definition at line 1410 of file core_cm4.h.

◆ FPU_MVFR1_D_NaN_mode_Msk [5/9]

#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

Definition at line 1637 of file core_cm7.h.

◆ FPU_MVFR1_D_NaN_mode_Msk [6/9]

#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

Definition at line 1870 of file core_starmc1.h.

◆ FPU_MVFR1_D_NaN_mode_Msk [7/9]

#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

Definition at line 1737 of file core_armv8mml.h.

◆ FPU_MVFR1_D_NaN_mode_Msk [8/9]

#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

Definition at line 1812 of file core_cm33.h.

◆ FPU_MVFR1_D_NaN_mode_Msk [9/9]

#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

Definition at line 1410 of file core_cm4.h.

◆ FPU_MVFR1_D_NaN_mode_Pos [1/9]

#define FPU_MVFR1_D_NaN_mode_Pos   4U

MVFR1: D_NaN mode bits Position

Definition at line 1736 of file core_armv8mml.h.

◆ FPU_MVFR1_D_NaN_mode_Pos [2/9]

#define FPU_MVFR1_D_NaN_mode_Pos   4U

MVFR1: D_NaN mode bits Position

Definition at line 1811 of file core_cm33.h.

◆ FPU_MVFR1_D_NaN_mode_Pos [3/9]

#define FPU_MVFR1_D_NaN_mode_Pos   4U

MVFR1: D_NaN mode bits Position

Definition at line 1811 of file core_cm35p.h.

◆ FPU_MVFR1_D_NaN_mode_Pos [4/9]

#define FPU_MVFR1_D_NaN_mode_Pos   4U

MVFR1: D_NaN mode bits Position

Definition at line 1409 of file core_cm4.h.

◆ FPU_MVFR1_D_NaN_mode_Pos [5/9]

#define FPU_MVFR1_D_NaN_mode_Pos   4U

MVFR1: D_NaN mode bits Position

Definition at line 1636 of file core_cm7.h.

◆ FPU_MVFR1_D_NaN_mode_Pos [6/9]

#define FPU_MVFR1_D_NaN_mode_Pos   4U

MVFR1: D_NaN mode bits Position

Definition at line 1869 of file core_starmc1.h.

◆ FPU_MVFR1_D_NaN_mode_Pos [7/9]

#define FPU_MVFR1_D_NaN_mode_Pos   4U

MVFR1: D_NaN mode bits Position

Definition at line 1736 of file core_armv8mml.h.

◆ FPU_MVFR1_D_NaN_mode_Pos [8/9]

#define FPU_MVFR1_D_NaN_mode_Pos   4U

MVFR1: D_NaN mode bits Position

Definition at line 1811 of file core_cm33.h.

◆ FPU_MVFR1_D_NaN_mode_Pos [9/9]

#define FPU_MVFR1_D_NaN_mode_Pos   4U

MVFR1: D_NaN mode bits Position

Definition at line 1409 of file core_cm4.h.

◆ FPU_MVFR1_FMAC_Msk [1/4]

#define FPU_MVFR1_FMAC_Msk   (0xFUL << FPU_MVFR1_FMAC_Pos)

MVFR1: FMAC bits Mask

Definition at line 2612 of file core_armv81mml.h.

◆ FPU_MVFR1_FMAC_Msk [2/4]

#define FPU_MVFR1_FMAC_Msk   (0xFUL << FPU_MVFR1_FMAC_Pos)

MVFR1: FMAC bits Mask

Definition at line 3166 of file core_cm55.h.

◆ FPU_MVFR1_FMAC_Msk [3/4]

#define FPU_MVFR1_FMAC_Msk   (0xFUL << FPU_MVFR1_FMAC_Pos)

MVFR1: FMAC bits Mask

Definition at line 3071 of file core_cm85.h.

◆ FPU_MVFR1_FMAC_Msk [4/4]

#define FPU_MVFR1_FMAC_Msk   (0xFUL << FPU_MVFR1_FMAC_Pos)

MVFR1: FMAC bits Mask

Definition at line 2612 of file core_armv81mml.h.

◆ FPU_MVFR1_FMAC_Pos [1/4]

#define FPU_MVFR1_FMAC_Pos   28U

MVFR1: FMAC bits Position

Definition at line 2611 of file core_armv81mml.h.

◆ FPU_MVFR1_FMAC_Pos [2/4]

#define FPU_MVFR1_FMAC_Pos   28U

MVFR1: FMAC bits Position

Definition at line 3165 of file core_cm55.h.

◆ FPU_MVFR1_FMAC_Pos [3/4]

#define FPU_MVFR1_FMAC_Pos   28U

MVFR1: FMAC bits Position

Definition at line 3070 of file core_cm85.h.

◆ FPU_MVFR1_FMAC_Pos [4/4]

#define FPU_MVFR1_FMAC_Pos   28U

MVFR1: FMAC bits Position

Definition at line 2611 of file core_armv81mml.h.

◆ FPU_MVFR1_FP16_Msk [1/4]

#define FPU_MVFR1_FP16_Msk   (0xFUL << FPU_MVFR1_FP16_Pos)

MVFR1: FP16 bits Mask

Definition at line 2618 of file core_armv81mml.h.

◆ FPU_MVFR1_FP16_Msk [2/4]

#define FPU_MVFR1_FP16_Msk   (0xFUL << FPU_MVFR1_FP16_Pos)

MVFR1: FP16 bits Mask

Definition at line 3172 of file core_cm55.h.

◆ FPU_MVFR1_FP16_Msk [3/4]

#define FPU_MVFR1_FP16_Msk   (0xFUL << FPU_MVFR1_FP16_Pos)

MVFR1: FP16 bits Mask

Definition at line 3077 of file core_cm85.h.

◆ FPU_MVFR1_FP16_Msk [4/4]

#define FPU_MVFR1_FP16_Msk   (0xFUL << FPU_MVFR1_FP16_Pos)

MVFR1: FP16 bits Mask

Definition at line 2618 of file core_armv81mml.h.

◆ FPU_MVFR1_FP16_Pos [1/4]

#define FPU_MVFR1_FP16_Pos   20U

MVFR1: FP16 bits Position

Definition at line 2617 of file core_armv81mml.h.

◆ FPU_MVFR1_FP16_Pos [2/4]

#define FPU_MVFR1_FP16_Pos   20U

MVFR1: FP16 bits Position

Definition at line 3171 of file core_cm55.h.

◆ FPU_MVFR1_FP16_Pos [3/4]

#define FPU_MVFR1_FP16_Pos   20U

MVFR1: FP16 bits Position

Definition at line 3076 of file core_cm85.h.

◆ FPU_MVFR1_FP16_Pos [4/4]

#define FPU_MVFR1_FP16_Pos   20U

MVFR1: FP16 bits Position

Definition at line 2617 of file core_armv81mml.h.

◆ FPU_MVFR1_FP_fused_MAC_Msk [1/9]

#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

Definition at line 1731 of file core_armv8mml.h.

◆ FPU_MVFR1_FP_fused_MAC_Msk [2/9]

#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

Definition at line 1806 of file core_cm33.h.

◆ FPU_MVFR1_FP_fused_MAC_Msk [3/9]

#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

Definition at line 1806 of file core_cm35p.h.

◆ FPU_MVFR1_FP_fused_MAC_Msk [4/9]

#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

Definition at line 1404 of file core_cm4.h.

◆ FPU_MVFR1_FP_fused_MAC_Msk [5/9]

#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

Definition at line 1631 of file core_cm7.h.

◆ FPU_MVFR1_FP_fused_MAC_Msk [6/9]

#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

Definition at line 1864 of file core_starmc1.h.

◆ FPU_MVFR1_FP_fused_MAC_Msk [7/9]

#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

Definition at line 1731 of file core_armv8mml.h.

◆ FPU_MVFR1_FP_fused_MAC_Msk [8/9]

#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

Definition at line 1806 of file core_cm33.h.

◆ FPU_MVFR1_FP_fused_MAC_Msk [9/9]

#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

Definition at line 1404 of file core_cm4.h.

◆ FPU_MVFR1_FP_fused_MAC_Pos [1/9]

#define FPU_MVFR1_FP_fused_MAC_Pos   28U

MVFR1: FP fused MAC bits Position

Definition at line 1730 of file core_armv8mml.h.

◆ FPU_MVFR1_FP_fused_MAC_Pos [2/9]

#define FPU_MVFR1_FP_fused_MAC_Pos   28U

MVFR1: FP fused MAC bits Position

Definition at line 1805 of file core_cm33.h.

◆ FPU_MVFR1_FP_fused_MAC_Pos [3/9]

#define FPU_MVFR1_FP_fused_MAC_Pos   28U

MVFR1: FP fused MAC bits Position

Definition at line 1805 of file core_cm35p.h.

◆ FPU_MVFR1_FP_fused_MAC_Pos [4/9]

#define FPU_MVFR1_FP_fused_MAC_Pos   28U

MVFR1: FP fused MAC bits Position

Definition at line 1403 of file core_cm4.h.

◆ FPU_MVFR1_FP_fused_MAC_Pos [5/9]

#define FPU_MVFR1_FP_fused_MAC_Pos   28U

MVFR1: FP fused MAC bits Position

Definition at line 1630 of file core_cm7.h.

◆ FPU_MVFR1_FP_fused_MAC_Pos [6/9]

#define FPU_MVFR1_FP_fused_MAC_Pos   28U

MVFR1: FP fused MAC bits Position

Definition at line 1863 of file core_starmc1.h.

◆ FPU_MVFR1_FP_fused_MAC_Pos [7/9]

#define FPU_MVFR1_FP_fused_MAC_Pos   28U

MVFR1: FP fused MAC bits Position

Definition at line 1730 of file core_armv8mml.h.

◆ FPU_MVFR1_FP_fused_MAC_Pos [8/9]

#define FPU_MVFR1_FP_fused_MAC_Pos   28U

MVFR1: FP fused MAC bits Position

Definition at line 1805 of file core_cm33.h.

◆ FPU_MVFR1_FP_fused_MAC_Pos [9/9]

#define FPU_MVFR1_FP_fused_MAC_Pos   28U

MVFR1: FP fused MAC bits Position

Definition at line 1403 of file core_cm4.h.

◆ FPU_MVFR1_FP_HPFP_Msk [1/9]

#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

Definition at line 1734 of file core_armv8mml.h.

◆ FPU_MVFR1_FP_HPFP_Msk [2/9]

#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

Definition at line 1809 of file core_cm33.h.

◆ FPU_MVFR1_FP_HPFP_Msk [3/9]

#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

Definition at line 1809 of file core_cm35p.h.

◆ FPU_MVFR1_FP_HPFP_Msk [4/9]

#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

Definition at line 1407 of file core_cm4.h.

◆ FPU_MVFR1_FP_HPFP_Msk [5/9]

#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

Definition at line 1634 of file core_cm7.h.

◆ FPU_MVFR1_FP_HPFP_Msk [6/9]

#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

Definition at line 1867 of file core_starmc1.h.

◆ FPU_MVFR1_FP_HPFP_Msk [7/9]

#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

Definition at line 1734 of file core_armv8mml.h.

◆ FPU_MVFR1_FP_HPFP_Msk [8/9]

#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

Definition at line 1809 of file core_cm33.h.

◆ FPU_MVFR1_FP_HPFP_Msk [9/9]

#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

Definition at line 1407 of file core_cm4.h.

◆ FPU_MVFR1_FP_HPFP_Pos [1/9]

#define FPU_MVFR1_FP_HPFP_Pos   24U

MVFR1: FP HPFP bits Position

Definition at line 1733 of file core_armv8mml.h.

◆ FPU_MVFR1_FP_HPFP_Pos [2/9]

#define FPU_MVFR1_FP_HPFP_Pos   24U

MVFR1: FP HPFP bits Position

Definition at line 1808 of file core_cm33.h.

◆ FPU_MVFR1_FP_HPFP_Pos [3/9]

#define FPU_MVFR1_FP_HPFP_Pos   24U

MVFR1: FP HPFP bits Position

Definition at line 1808 of file core_cm35p.h.

◆ FPU_MVFR1_FP_HPFP_Pos [4/9]

#define FPU_MVFR1_FP_HPFP_Pos   24U

MVFR1: FP HPFP bits Position

Definition at line 1406 of file core_cm4.h.

◆ FPU_MVFR1_FP_HPFP_Pos [5/9]

#define FPU_MVFR1_FP_HPFP_Pos   24U

MVFR1: FP HPFP bits Position

Definition at line 1633 of file core_cm7.h.

◆ FPU_MVFR1_FP_HPFP_Pos [6/9]

#define FPU_MVFR1_FP_HPFP_Pos   24U

MVFR1: FP HPFP bits Position

Definition at line 1866 of file core_starmc1.h.

◆ FPU_MVFR1_FP_HPFP_Pos [7/9]

#define FPU_MVFR1_FP_HPFP_Pos   24U

MVFR1: FP HPFP bits Position

Definition at line 1733 of file core_armv8mml.h.

◆ FPU_MVFR1_FP_HPFP_Pos [8/9]

#define FPU_MVFR1_FP_HPFP_Pos   24U

MVFR1: FP HPFP bits Position

Definition at line 1808 of file core_cm33.h.

◆ FPU_MVFR1_FP_HPFP_Pos [9/9]

#define FPU_MVFR1_FP_HPFP_Pos   24U

MVFR1: FP HPFP bits Position

Definition at line 1406 of file core_cm4.h.

◆ FPU_MVFR1_FPDNaN_Msk [1/4]

#define FPU_MVFR1_FPDNaN_Msk   (0xFUL << FPU_MVFR1_FPDNaN_Pos)

MVFR1: FPDNaN bits Mask

Definition at line 2624 of file core_armv81mml.h.

◆ FPU_MVFR1_FPDNaN_Msk [2/4]

#define FPU_MVFR1_FPDNaN_Msk   (0xFUL << FPU_MVFR1_FPDNaN_Pos)

MVFR1: FPDNaN bits Mask

Definition at line 3178 of file core_cm55.h.

◆ FPU_MVFR1_FPDNaN_Msk [3/4]

#define FPU_MVFR1_FPDNaN_Msk   (0xFUL << FPU_MVFR1_FPDNaN_Pos)

MVFR1: FPDNaN bits Mask

Definition at line 3083 of file core_cm85.h.

◆ FPU_MVFR1_FPDNaN_Msk [4/4]

#define FPU_MVFR1_FPDNaN_Msk   (0xFUL << FPU_MVFR1_FPDNaN_Pos)

MVFR1: FPDNaN bits Mask

Definition at line 2624 of file core_armv81mml.h.

◆ FPU_MVFR1_FPDNaN_Pos [1/4]

#define FPU_MVFR1_FPDNaN_Pos   4U

MVFR1: FPDNaN bits Position

Definition at line 2623 of file core_armv81mml.h.

◆ FPU_MVFR1_FPDNaN_Pos [2/4]

#define FPU_MVFR1_FPDNaN_Pos   4U

MVFR1: FPDNaN bits Position

Definition at line 3177 of file core_cm55.h.

◆ FPU_MVFR1_FPDNaN_Pos [3/4]

#define FPU_MVFR1_FPDNaN_Pos   4U

MVFR1: FPDNaN bits Position

Definition at line 3082 of file core_cm85.h.

◆ FPU_MVFR1_FPDNaN_Pos [4/4]

#define FPU_MVFR1_FPDNaN_Pos   4U

MVFR1: FPDNaN bits Position

Definition at line 2623 of file core_armv81mml.h.

◆ FPU_MVFR1_FPFtZ_Msk [1/4]

#define FPU_MVFR1_FPFtZ_Msk   (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)

MVFR1: FPFtZ bits Mask

Definition at line 2627 of file core_armv81mml.h.

◆ FPU_MVFR1_FPFtZ_Msk [2/4]

#define FPU_MVFR1_FPFtZ_Msk   (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)

MVFR1: FPFtZ bits Mask

Definition at line 3181 of file core_cm55.h.

◆ FPU_MVFR1_FPFtZ_Msk [3/4]

#define FPU_MVFR1_FPFtZ_Msk   (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)

MVFR1: FPFtZ bits Mask

Definition at line 3086 of file core_cm85.h.

◆ FPU_MVFR1_FPFtZ_Msk [4/4]

#define FPU_MVFR1_FPFtZ_Msk   (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)

MVFR1: FPFtZ bits Mask

Definition at line 2627 of file core_armv81mml.h.

◆ FPU_MVFR1_FPFtZ_Pos [1/4]

#define FPU_MVFR1_FPFtZ_Pos   0U

MVFR1: FPFtZ bits Position

Definition at line 2626 of file core_armv81mml.h.

◆ FPU_MVFR1_FPFtZ_Pos [2/4]

#define FPU_MVFR1_FPFtZ_Pos   0U

MVFR1: FPFtZ bits Position

Definition at line 3180 of file core_cm55.h.

◆ FPU_MVFR1_FPFtZ_Pos [3/4]

#define FPU_MVFR1_FPFtZ_Pos   0U

MVFR1: FPFtZ bits Position

Definition at line 3085 of file core_cm85.h.

◆ FPU_MVFR1_FPFtZ_Pos [4/4]

#define FPU_MVFR1_FPFtZ_Pos   0U

MVFR1: FPFtZ bits Position

Definition at line 2626 of file core_armv81mml.h.

◆ FPU_MVFR1_FPHP_Msk [1/4]

#define FPU_MVFR1_FPHP_Msk   (0xFUL << FPU_MVFR1_FPHP_Pos)

MVFR1: FPHP bits Mask

Definition at line 2615 of file core_armv81mml.h.

◆ FPU_MVFR1_FPHP_Msk [2/4]

#define FPU_MVFR1_FPHP_Msk   (0xFUL << FPU_MVFR1_FPHP_Pos)

MVFR1: FPHP bits Mask

Definition at line 3169 of file core_cm55.h.

◆ FPU_MVFR1_FPHP_Msk [3/4]

#define FPU_MVFR1_FPHP_Msk   (0xFUL << FPU_MVFR1_FPHP_Pos)

MVFR1: FPHP bits Mask

Definition at line 3074 of file core_cm85.h.

◆ FPU_MVFR1_FPHP_Msk [4/4]

#define FPU_MVFR1_FPHP_Msk   (0xFUL << FPU_MVFR1_FPHP_Pos)

MVFR1: FPHP bits Mask

Definition at line 2615 of file core_armv81mml.h.

◆ FPU_MVFR1_FPHP_Pos [1/4]

#define FPU_MVFR1_FPHP_Pos   24U

MVFR1: FPHP bits Position

Definition at line 2614 of file core_armv81mml.h.

◆ FPU_MVFR1_FPHP_Pos [2/4]

#define FPU_MVFR1_FPHP_Pos   24U

MVFR1: FPHP bits Position

Definition at line 3168 of file core_cm55.h.

◆ FPU_MVFR1_FPHP_Pos [3/4]

#define FPU_MVFR1_FPHP_Pos   24U

MVFR1: FPHP bits Position

Definition at line 3073 of file core_cm85.h.

◆ FPU_MVFR1_FPHP_Pos [4/4]

#define FPU_MVFR1_FPHP_Pos   24U

MVFR1: FPHP bits Position

Definition at line 2614 of file core_armv81mml.h.

◆ FPU_MVFR1_FtZ_mode_Msk [1/9]

#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

Definition at line 1740 of file core_armv8mml.h.

◆ FPU_MVFR1_FtZ_mode_Msk [2/9]

#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

Definition at line 1815 of file core_cm33.h.

◆ FPU_MVFR1_FtZ_mode_Msk [3/9]

#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

Definition at line 1815 of file core_cm35p.h.

◆ FPU_MVFR1_FtZ_mode_Msk [4/9]

#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

Definition at line 1413 of file core_cm4.h.

◆ FPU_MVFR1_FtZ_mode_Msk [5/9]

#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

Definition at line 1640 of file core_cm7.h.

◆ FPU_MVFR1_FtZ_mode_Msk [6/9]

#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

Definition at line 1873 of file core_starmc1.h.

◆ FPU_MVFR1_FtZ_mode_Msk [7/9]

#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

Definition at line 1740 of file core_armv8mml.h.

◆ FPU_MVFR1_FtZ_mode_Msk [8/9]

#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

Definition at line 1815 of file core_cm33.h.

◆ FPU_MVFR1_FtZ_mode_Msk [9/9]

#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

Definition at line 1413 of file core_cm4.h.

◆ FPU_MVFR1_FtZ_mode_Pos [1/9]

#define FPU_MVFR1_FtZ_mode_Pos   0U

MVFR1: FtZ mode bits Position

Definition at line 1739 of file core_armv8mml.h.

◆ FPU_MVFR1_FtZ_mode_Pos [2/9]

#define FPU_MVFR1_FtZ_mode_Pos   0U

MVFR1: FtZ mode bits Position

Definition at line 1814 of file core_cm33.h.

◆ FPU_MVFR1_FtZ_mode_Pos [3/9]

#define FPU_MVFR1_FtZ_mode_Pos   0U

MVFR1: FtZ mode bits Position

Definition at line 1814 of file core_cm35p.h.

◆ FPU_MVFR1_FtZ_mode_Pos [4/9]

#define FPU_MVFR1_FtZ_mode_Pos   0U

MVFR1: FtZ mode bits Position

Definition at line 1412 of file core_cm4.h.

◆ FPU_MVFR1_FtZ_mode_Pos [5/9]

#define FPU_MVFR1_FtZ_mode_Pos   0U

MVFR1: FtZ mode bits Position

Definition at line 1639 of file core_cm7.h.

◆ FPU_MVFR1_FtZ_mode_Pos [6/9]

#define FPU_MVFR1_FtZ_mode_Pos   0U

MVFR1: FtZ mode bits Position

Definition at line 1872 of file core_starmc1.h.

◆ FPU_MVFR1_FtZ_mode_Pos [7/9]

#define FPU_MVFR1_FtZ_mode_Pos   0U

MVFR1: FtZ mode bits Position

Definition at line 1739 of file core_armv8mml.h.

◆ FPU_MVFR1_FtZ_mode_Pos [8/9]

#define FPU_MVFR1_FtZ_mode_Pos   0U

MVFR1: FtZ mode bits Position

Definition at line 1814 of file core_cm33.h.

◆ FPU_MVFR1_FtZ_mode_Pos [9/9]

#define FPU_MVFR1_FtZ_mode_Pos   0U

MVFR1: FtZ mode bits Position

Definition at line 1412 of file core_cm4.h.

◆ FPU_MVFR1_MVE_Msk [1/4]

#define FPU_MVFR1_MVE_Msk   (0xFUL << FPU_MVFR1_MVE_Pos)

MVFR1: MVE bits Mask

Definition at line 2621 of file core_armv81mml.h.

◆ FPU_MVFR1_MVE_Msk [2/4]

#define FPU_MVFR1_MVE_Msk   (0xFUL << FPU_MVFR1_MVE_Pos)

MVFR1: MVE bits Mask

Definition at line 3175 of file core_cm55.h.

◆ FPU_MVFR1_MVE_Msk [3/4]

#define FPU_MVFR1_MVE_Msk   (0xFUL << FPU_MVFR1_MVE_Pos)

MVFR1: MVE bits Mask

Definition at line 3080 of file core_cm85.h.

◆ FPU_MVFR1_MVE_Msk [4/4]

#define FPU_MVFR1_MVE_Msk   (0xFUL << FPU_MVFR1_MVE_Pos)

MVFR1: MVE bits Mask

Definition at line 2621 of file core_armv81mml.h.

◆ FPU_MVFR1_MVE_Pos [1/4]

#define FPU_MVFR1_MVE_Pos   8U

MVFR1: MVE bits Position

Definition at line 2620 of file core_armv81mml.h.

◆ FPU_MVFR1_MVE_Pos [2/4]

#define FPU_MVFR1_MVE_Pos   8U

MVFR1: MVE bits Position

Definition at line 3174 of file core_cm55.h.

◆ FPU_MVFR1_MVE_Pos [3/4]

#define FPU_MVFR1_MVE_Pos   8U

MVFR1: MVE bits Position

Definition at line 3079 of file core_cm85.h.

◆ FPU_MVFR1_MVE_Pos [4/4]

#define FPU_MVFR1_MVE_Pos   8U

MVFR1: MVE bits Position

Definition at line 2620 of file core_armv81mml.h.

◆ FPU_MVFR2_FPMisc_Msk [1/10]

#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)

MVFR2: FPMisc bits Mask

Definition at line 2631 of file core_armv81mml.h.

◆ FPU_MVFR2_FPMisc_Msk [2/10]

#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)

MVFR2: FPMisc bits Mask

Definition at line 1744 of file core_armv8mml.h.

◆ FPU_MVFR2_FPMisc_Msk [3/10]

#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)

MVFR2: FPMisc bits Mask

Definition at line 1819 of file core_cm33.h.

◆ FPU_MVFR2_FPMisc_Msk [4/10]

#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)

MVFR2: FPMisc bits Mask

Definition at line 1819 of file core_cm35p.h.

◆ FPU_MVFR2_FPMisc_Msk [5/10]

#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)

MVFR2: FPMisc bits Mask

Definition at line 3185 of file core_cm55.h.

◆ FPU_MVFR2_FPMisc_Msk [6/10]

#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)

MVFR2: FPMisc bits Mask

Definition at line 3090 of file core_cm85.h.

◆ FPU_MVFR2_FPMisc_Msk [7/10]

#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)

MVFR2: FPMisc bits Mask

Definition at line 1877 of file core_starmc1.h.

◆ FPU_MVFR2_FPMisc_Msk [8/10]

#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)

MVFR2: FPMisc bits Mask

Definition at line 2631 of file core_armv81mml.h.

◆ FPU_MVFR2_FPMisc_Msk [9/10]

#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)

MVFR2: FPMisc bits Mask

Definition at line 1744 of file core_armv8mml.h.

◆ FPU_MVFR2_FPMisc_Msk [10/10]

#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)

MVFR2: FPMisc bits Mask

Definition at line 1819 of file core_cm33.h.

◆ FPU_MVFR2_FPMisc_Pos [1/10]

#define FPU_MVFR2_FPMisc_Pos   4U

MVFR2: FPMisc bits Position

Definition at line 2630 of file core_armv81mml.h.

◆ FPU_MVFR2_FPMisc_Pos [2/10]

#define FPU_MVFR2_FPMisc_Pos   4U

MVFR2: FPMisc bits Position

Definition at line 1743 of file core_armv8mml.h.

◆ FPU_MVFR2_FPMisc_Pos [3/10]

#define FPU_MVFR2_FPMisc_Pos   4U

MVFR2: FPMisc bits Position

Definition at line 1818 of file core_cm33.h.

◆ FPU_MVFR2_FPMisc_Pos [4/10]

#define FPU_MVFR2_FPMisc_Pos   4U

MVFR2: FPMisc bits Position

Definition at line 1818 of file core_cm35p.h.

◆ FPU_MVFR2_FPMisc_Pos [5/10]

#define FPU_MVFR2_FPMisc_Pos   4U

MVFR2: FPMisc bits Position

Definition at line 3184 of file core_cm55.h.

◆ FPU_MVFR2_FPMisc_Pos [6/10]

#define FPU_MVFR2_FPMisc_Pos   4U

MVFR2: FPMisc bits Position

Definition at line 3089 of file core_cm85.h.

◆ FPU_MVFR2_FPMisc_Pos [7/10]

#define FPU_MVFR2_FPMisc_Pos   4U

MVFR2: FPMisc bits Position

Definition at line 1876 of file core_starmc1.h.

◆ FPU_MVFR2_FPMisc_Pos [8/10]

#define FPU_MVFR2_FPMisc_Pos   4U

MVFR2: FPMisc bits Position

Definition at line 2630 of file core_armv81mml.h.

◆ FPU_MVFR2_FPMisc_Pos [9/10]

#define FPU_MVFR2_FPMisc_Pos   4U

MVFR2: FPMisc bits Position

Definition at line 1743 of file core_armv8mml.h.

◆ FPU_MVFR2_FPMisc_Pos [10/10]

#define FPU_MVFR2_FPMisc_Pos   4U

MVFR2: FPMisc bits Position

Definition at line 1818 of file core_cm33.h.

◆ FPU_MVFR2_VFP_Misc_Msk [1/3]

#define FPU_MVFR2_VFP_Misc_Msk   (0xFUL << FPU_MVFR2_VFP_Misc_Pos)

MVFR2: VFP Misc bits Mask

Definition at line 1418 of file core_cm4.h.

◆ FPU_MVFR2_VFP_Misc_Msk [2/3]

#define FPU_MVFR2_VFP_Misc_Msk   (0xFUL << FPU_MVFR2_VFP_Misc_Pos)

MVFR2: VFP Misc bits Mask

Definition at line 1645 of file core_cm7.h.

◆ FPU_MVFR2_VFP_Misc_Msk [3/3]

#define FPU_MVFR2_VFP_Misc_Msk   (0xFUL << FPU_MVFR2_VFP_Misc_Pos)

MVFR2: VFP Misc bits Mask

Definition at line 1418 of file core_cm4.h.

◆ FPU_MVFR2_VFP_Misc_Pos [1/3]

#define FPU_MVFR2_VFP_Misc_Pos   4U

MVFR2: VFP Misc bits Position

Definition at line 1417 of file core_cm4.h.

◆ FPU_MVFR2_VFP_Misc_Pos [2/3]

#define FPU_MVFR2_VFP_Misc_Pos   4U

MVFR2: VFP Misc bits Position

Definition at line 1644 of file core_cm7.h.

◆ FPU_MVFR2_VFP_Misc_Pos [3/3]

#define FPU_MVFR2_VFP_Misc_Pos   4U

MVFR2: VFP Misc bits Position

Definition at line 1417 of file core_cm4.h.

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