YAHAL
Yet Another Hardware Abstraction Library
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core_cm35p.h
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1/**************************************************************************/
7/*
8 * Copyright (c) 2018-2023 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25#if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27#elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29#elif defined ( __GNUC__ )
30 #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
31#endif
32
33#ifndef __CORE_CM35P_H_GENERIC
34#define __CORE_CM35P_H_GENERIC
35
36#include <stdint.h>
37
38#ifdef __cplusplus
39 extern "C" {
40#endif
41
57/*******************************************************************************
58 * CMSIS definitions
59 ******************************************************************************/
65#include "cmsis_version.h"
66
67/* CMSIS CM35P definitions */
68#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
69#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
70#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \
71 __CM35P_CMSIS_VERSION_SUB )
73#define __CORTEX_M (35U)
78#if defined ( __CC_ARM )
79 #if defined (__TARGET_FPU_VFP)
80 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
81 #define __FPU_USED 1U
82 #else
83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
84 #define __FPU_USED 0U
85 #endif
86 #else
87 #define __FPU_USED 0U
88 #endif
89
90 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
91 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
92 #define __DSP_USED 1U
93 #else
94 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
95 #define __DSP_USED 0U
96 #endif
97 #else
98 #define __DSP_USED 0U
99 #endif
100
101#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
102 #if defined (__ARM_FP)
103 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
104 #define __FPU_USED 1U
105 #else
106 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
107 #define __FPU_USED 0U
108 #endif
109 #else
110 #define __FPU_USED 0U
111 #endif
112
113 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
114 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
115 #define __DSP_USED 1U
116 #else
117 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
118 #define __DSP_USED 0U
119 #endif
120 #else
121 #define __DSP_USED 0U
122 #endif
123
124#elif defined (__ti__)
125 #if defined (__ARM_FP)
126 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
127 #define __FPU_USED 1U
128 #else
129 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
130 #define __FPU_USED 0U
131 #endif
132 #else
133 #define __FPU_USED 0U
134 #endif
135
136 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
137 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
138 #define __DSP_USED 1U
139 #else
140 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
141 #define __DSP_USED 0U
142 #endif
143 #else
144 #define __DSP_USED 0U
145 #endif
146
147#elif defined ( __GNUC__ )
148 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
149 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
150 #define __FPU_USED 1U
151 #else
152 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
153 #define __FPU_USED 0U
154 #endif
155 #else
156 #define __FPU_USED 0U
157 #endif
158
159 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
160 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
161 #define __DSP_USED 1U
162 #else
163 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
164 #define __DSP_USED 0U
165 #endif
166 #else
167 #define __DSP_USED 0U
168 #endif
169
170#elif defined ( __ICCARM__ )
171 #if defined (__ARMVFP__)
172 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
173 #define __FPU_USED 1U
174 #else
175 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
176 #define __FPU_USED 0U
177 #endif
178 #else
179 #define __FPU_USED 0U
180 #endif
181
182 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
183 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
184 #define __DSP_USED 1U
185 #else
186 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
187 #define __DSP_USED 0U
188 #endif
189 #else
190 #define __DSP_USED 0U
191 #endif
192
193#elif defined ( __TI_ARM__ )
194 #if defined (__TI_VFP_SUPPORT__)
195 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
196 #define __FPU_USED 1U
197 #else
198 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
199 #define __FPU_USED 0U
200 #endif
201 #else
202 #define __FPU_USED 0U
203 #endif
204
205#elif defined ( __TASKING__ )
206 #if defined (__FPU_VFP__)
207 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
208 #define __FPU_USED 1U
209 #else
210 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
211 #define __FPU_USED 0U
212 #endif
213 #else
214 #define __FPU_USED 0U
215 #endif
216
217#elif defined ( __CSMC__ )
218 #if ( __CSMC__ & 0x400U)
219 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
220 #define __FPU_USED 1U
221 #else
222 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
223 #define __FPU_USED 0U
224 #endif
225 #else
226 #define __FPU_USED 0U
227 #endif
228
229#endif
230
231#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
232
233
234#ifdef __cplusplus
235}
236#endif
237
238#endif /* __CORE_CM35P_H_GENERIC */
239
240#ifndef __CMSIS_GENERIC
241
242#ifndef __CORE_CM35P_H_DEPENDANT
243#define __CORE_CM35P_H_DEPENDANT
244
245#ifdef __cplusplus
246 extern "C" {
247#endif
248
249/* check device defines and use defaults */
250#if defined __CHECK_DEVICE_DEFINES
251 #ifndef __CM35P_REV
252 #define __CM35P_REV 0x0000U
253 #warning "__CM35P_REV not defined in device header file; using default!"
254 #endif
255
256 #ifndef __FPU_PRESENT
257 #define __FPU_PRESENT 0U
258 #warning "__FPU_PRESENT not defined in device header file; using default!"
259 #endif
260
261 #ifndef __MPU_PRESENT
262 #define __MPU_PRESENT 0U
263 #warning "__MPU_PRESENT not defined in device header file; using default!"
264 #endif
265
266 #ifndef __SAUREGION_PRESENT
267 #define __SAUREGION_PRESENT 0U
268 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
269 #endif
270
271 #ifndef __DSP_PRESENT
272 #define __DSP_PRESENT 0U
273 #warning "__DSP_PRESENT not defined in device header file; using default!"
274 #endif
275
276 #ifndef __VTOR_PRESENT
277 #define __VTOR_PRESENT 1U
278 #warning "__VTOR_PRESENT not defined in device header file; using default!"
279 #endif
280
281 #ifndef __NVIC_PRIO_BITS
282 #define __NVIC_PRIO_BITS 3U
283 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
284 #endif
285
286 #ifndef __Vendor_SysTickConfig
287 #define __Vendor_SysTickConfig 0U
288 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
289 #endif
290#endif
291
292/* IO definitions (access restrictions to peripheral registers) */
300#ifdef __cplusplus
301 #define __I volatile
302#else
303 #define __I volatile const
304#endif
305#define __O volatile
306#define __IO volatile
308/* following defines should be used for structure members */
309#define __IM volatile const
310#define __OM volatile
311#define __IOM volatile
317/*******************************************************************************
318 * Register Abstraction
319 Core Register contain:
320 - Core Register
321 - Core NVIC Register
322 - Core SCB Register
323 - Core SysTick Register
324 - Core Debug Register
325 - Core MPU Register
326 - Core SAU Register
327 - Core FPU Register
328 ******************************************************************************/
344typedef union
345{
346 struct
347 {
348 uint32_t _reserved0:16;
349 uint32_t GE:4;
350 uint32_t _reserved1:7;
351 uint32_t Q:1;
352 uint32_t V:1;
353 uint32_t C:1;
354 uint32_t Z:1;
355 uint32_t N:1;
356 } b;
357 uint32_t w;
358} APSR_Type;
359
360/* APSR Register Definitions */
361#define APSR_N_Pos 31U
362#define APSR_N_Msk (1UL << APSR_N_Pos)
364#define APSR_Z_Pos 30U
365#define APSR_Z_Msk (1UL << APSR_Z_Pos)
367#define APSR_C_Pos 29U
368#define APSR_C_Msk (1UL << APSR_C_Pos)
370#define APSR_V_Pos 28U
371#define APSR_V_Msk (1UL << APSR_V_Pos)
373#define APSR_Q_Pos 27U
374#define APSR_Q_Msk (1UL << APSR_Q_Pos)
376#define APSR_GE_Pos 16U
377#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)
383typedef union
384{
385 struct
386 {
387 uint32_t ISR:9;
388 uint32_t _reserved0:23;
389 } b;
390 uint32_t w;
391} IPSR_Type;
392
393/* IPSR Register Definitions */
394#define IPSR_ISR_Pos 0U
395#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
401typedef union
402{
403 struct
404 {
405 uint32_t ISR:9;
406 uint32_t _reserved0:7;
407 uint32_t GE:4;
408 uint32_t _reserved1:4;
409 uint32_t T:1;
410 uint32_t IT:2;
411 uint32_t Q:1;
412 uint32_t V:1;
413 uint32_t C:1;
414 uint32_t Z:1;
415 uint32_t N:1;
416 } b;
417 uint32_t w;
418} xPSR_Type;
419
420/* xPSR Register Definitions */
421#define xPSR_N_Pos 31U
422#define xPSR_N_Msk (1UL << xPSR_N_Pos)
424#define xPSR_Z_Pos 30U
425#define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
427#define xPSR_C_Pos 29U
428#define xPSR_C_Msk (1UL << xPSR_C_Pos)
430#define xPSR_V_Pos 28U
431#define xPSR_V_Msk (1UL << xPSR_V_Pos)
433#define xPSR_Q_Pos 27U
434#define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
436#define xPSR_IT_Pos 25U
437#define xPSR_IT_Msk (3UL << xPSR_IT_Pos)
439#define xPSR_T_Pos 24U
440#define xPSR_T_Msk (1UL << xPSR_T_Pos)
442#define xPSR_GE_Pos 16U
443#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
445#define xPSR_ISR_Pos 0U
446#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
452typedef union
453{
454 struct
455 {
456 uint32_t nPRIV:1;
457 uint32_t SPSEL:1;
458 uint32_t FPCA:1;
459 uint32_t SFPA:1;
460 uint32_t _reserved1:28;
461 } b;
462 uint32_t w;
463} CONTROL_Type;
464
465/* CONTROL Register Definitions */
466#define CONTROL_SFPA_Pos 3U
467#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)
469#define CONTROL_FPCA_Pos 2U
470#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
472#define CONTROL_SPSEL_Pos 1U
473#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
475#define CONTROL_nPRIV_Pos 0U
476#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
491typedef struct
492{
493 __IOM uint32_t ISER[16U];
494 uint32_t RESERVED0[16U];
495 __IOM uint32_t ICER[16U];
496 uint32_t RSERVED1[16U];
497 __IOM uint32_t ISPR[16U];
498 uint32_t RESERVED2[16U];
499 __IOM uint32_t ICPR[16U];
500 uint32_t RESERVED3[16U];
501 __IOM uint32_t IABR[16U];
502 uint32_t RESERVED4[16U];
503 __IOM uint32_t ITNS[16U];
504 uint32_t RESERVED5[16U];
505 __IOM uint8_t IPR[496U];
506 uint32_t RESERVED6[580U];
507 __OM uint32_t STIR;
508} NVIC_Type;
509
510/* Software Triggered Interrupt Register Definitions */
511#define NVIC_STIR_INTID_Pos 0U
512#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
527typedef struct
528{
529 __IM uint32_t CPUID;
530 __IOM uint32_t ICSR;
531 __IOM uint32_t VTOR;
532 __IOM uint32_t AIRCR;
533 __IOM uint32_t SCR;
534 __IOM uint32_t CCR;
535 __IOM uint8_t SHPR[12U];
536 __IOM uint32_t SHCSR;
537 __IOM uint32_t CFSR;
538 __IOM uint32_t HFSR;
539 __IOM uint32_t DFSR;
540 __IOM uint32_t MMFAR;
541 __IOM uint32_t BFAR;
542 __IOM uint32_t AFSR;
543 __IM uint32_t ID_PFR[2U];
544 __IM uint32_t ID_DFR;
545 __IM uint32_t ID_AFR;
546 __IM uint32_t ID_MMFR[4U];
547 __IM uint32_t ID_ISAR[6U];
548 __IM uint32_t CLIDR;
549 __IM uint32_t CTR;
550 __IM uint32_t CCSIDR;
551 __IOM uint32_t CSSELR;
552 __IOM uint32_t CPACR;
553 __IOM uint32_t NSACR;
554 uint32_t RESERVED7[21U];
555 __IOM uint32_t SFSR;
556 __IOM uint32_t SFAR;
557 uint32_t RESERVED3[69U];
558 __OM uint32_t STIR;
559 uint32_t RESERVED4[15U];
560 __IM uint32_t MVFR0;
561 __IM uint32_t MVFR1;
562 __IM uint32_t MVFR2;
563 uint32_t RESERVED5[1U];
564 __OM uint32_t ICIALLU;
565 uint32_t RESERVED6[1U];
566 __OM uint32_t ICIMVAU;
567 __OM uint32_t DCIMVAC;
568 __OM uint32_t DCISW;
569 __OM uint32_t DCCMVAU;
570 __OM uint32_t DCCMVAC;
571 __OM uint32_t DCCSW;
572 __OM uint32_t DCCIMVAC;
573 __OM uint32_t DCCISW;
574 __OM uint32_t BPIALL;
575} SCB_Type;
576
577/* SCB CPUID Register Definitions */
578#define SCB_CPUID_IMPLEMENTER_Pos 24U
579#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
581#define SCB_CPUID_VARIANT_Pos 20U
582#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
584#define SCB_CPUID_ARCHITECTURE_Pos 16U
585#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
587#define SCB_CPUID_PARTNO_Pos 4U
588#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
590#define SCB_CPUID_REVISION_Pos 0U
591#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
593/* SCB Interrupt Control State Register Definitions */
594#define SCB_ICSR_PENDNMISET_Pos 31U
595#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)
597#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos
598#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk
600#define SCB_ICSR_PENDNMICLR_Pos 30U
601#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)
603#define SCB_ICSR_PENDSVSET_Pos 28U
604#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
606#define SCB_ICSR_PENDSVCLR_Pos 27U
607#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
609#define SCB_ICSR_PENDSTSET_Pos 26U
610#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
612#define SCB_ICSR_PENDSTCLR_Pos 25U
613#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
615#define SCB_ICSR_STTNS_Pos 24U
616#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)
618#define SCB_ICSR_ISRPREEMPT_Pos 23U
619#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
621#define SCB_ICSR_ISRPENDING_Pos 22U
622#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
624#define SCB_ICSR_VECTPENDING_Pos 12U
625#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
627#define SCB_ICSR_RETTOBASE_Pos 11U
628#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
630#define SCB_ICSR_VECTACTIVE_Pos 0U
631#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
633/* SCB Vector Table Offset Register Definitions */
634#define SCB_VTOR_TBLOFF_Pos 7U
635#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
637/* SCB Application Interrupt and Reset Control Register Definitions */
638#define SCB_AIRCR_VECTKEY_Pos 16U
639#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
641#define SCB_AIRCR_VECTKEYSTAT_Pos 16U
642#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
644#define SCB_AIRCR_ENDIANESS_Pos 15U
645#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
647#define SCB_AIRCR_PRIS_Pos 14U
648#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)
650#define SCB_AIRCR_BFHFNMINS_Pos 13U
651#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)
653#define SCB_AIRCR_PRIGROUP_Pos 8U
654#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
656#define SCB_AIRCR_SYSRESETREQS_Pos 3U
657#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
659#define SCB_AIRCR_SYSRESETREQ_Pos 2U
660#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
662#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
663#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
665/* SCB System Control Register Definitions */
666#define SCB_SCR_SEVONPEND_Pos 4U
667#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
669#define SCB_SCR_SLEEPDEEPS_Pos 3U
670#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)
672#define SCB_SCR_SLEEPDEEP_Pos 2U
673#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
675#define SCB_SCR_SLEEPONEXIT_Pos 1U
676#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
678/* SCB Configuration Control Register Definitions */
679#define SCB_CCR_BP_Pos 18U
680#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
682#define SCB_CCR_IC_Pos 17U
683#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
685#define SCB_CCR_DC_Pos 16U
686#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
688#define SCB_CCR_STKOFHFNMIGN_Pos 10U
689#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
691#define SCB_CCR_BFHFNMIGN_Pos 8U
692#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
694#define SCB_CCR_DIV_0_TRP_Pos 4U
695#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
697#define SCB_CCR_UNALIGN_TRP_Pos 3U
698#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
700#define SCB_CCR_USERSETMPEND_Pos 1U
701#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
703/* SCB System Handler Control and State Register Definitions */
704#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U
705#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
707#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U
708#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
710#define SCB_SHCSR_SECUREFAULTENA_Pos 19U
711#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
713#define SCB_SHCSR_USGFAULTENA_Pos 18U
714#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
716#define SCB_SHCSR_BUSFAULTENA_Pos 17U
717#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
719#define SCB_SHCSR_MEMFAULTENA_Pos 16U
720#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
722#define SCB_SHCSR_SVCALLPENDED_Pos 15U
723#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
725#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
726#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
728#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
729#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
731#define SCB_SHCSR_USGFAULTPENDED_Pos 12U
732#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
734#define SCB_SHCSR_SYSTICKACT_Pos 11U
735#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
737#define SCB_SHCSR_PENDSVACT_Pos 10U
738#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
740#define SCB_SHCSR_MONITORACT_Pos 8U
741#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
743#define SCB_SHCSR_SVCALLACT_Pos 7U
744#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
746#define SCB_SHCSR_NMIACT_Pos 5U
747#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)
749#define SCB_SHCSR_SECUREFAULTACT_Pos 4U
750#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
752#define SCB_SHCSR_USGFAULTACT_Pos 3U
753#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
755#define SCB_SHCSR_HARDFAULTACT_Pos 2U
756#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
758#define SCB_SHCSR_BUSFAULTACT_Pos 1U
759#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
761#define SCB_SHCSR_MEMFAULTACT_Pos 0U
762#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
764/* SCB Configurable Fault Status Register Definitions */
765#define SCB_CFSR_USGFAULTSR_Pos 16U
766#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
768#define SCB_CFSR_BUSFAULTSR_Pos 8U
769#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
771#define SCB_CFSR_MEMFAULTSR_Pos 0U
772#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
774/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
775#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U)
776#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
778#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U)
779#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)
781#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U)
782#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
784#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U)
785#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
787#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U)
788#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
790#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U)
791#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
793/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
794#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
795#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
797#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)
798#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)
800#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
801#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
803#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
804#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
806#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
807#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
809#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
810#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
812#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
813#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
815/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
816#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
817#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
819#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
820#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
822#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)
823#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)
825#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
826#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
828#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
829#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
831#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
832#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
834#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
835#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
837/* SCB Hard Fault Status Register Definitions */
838#define SCB_HFSR_DEBUGEVT_Pos 31U
839#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
841#define SCB_HFSR_FORCED_Pos 30U
842#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
844#define SCB_HFSR_VECTTBL_Pos 1U
845#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
847/* SCB Debug Fault Status Register Definitions */
848#define SCB_DFSR_EXTERNAL_Pos 4U
849#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
851#define SCB_DFSR_VCATCH_Pos 3U
852#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
854#define SCB_DFSR_DWTTRAP_Pos 2U
855#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
857#define SCB_DFSR_BKPT_Pos 1U
858#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
860#define SCB_DFSR_HALTED_Pos 0U
861#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
863/* SCB Non-Secure Access Control Register Definitions */
864#define SCB_NSACR_CP11_Pos 11U
865#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)
867#define SCB_NSACR_CP10_Pos 10U
868#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)
870#define SCB_NSACR_CPn_Pos 0U
871#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/)
873/* SCB Cache Level ID Register Definitions */
874#define SCB_CLIDR_LOUU_Pos 27U
875#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)
877#define SCB_CLIDR_LOC_Pos 24U
878#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)
880/* SCB Cache Type Register Definitions */
881#define SCB_CTR_FORMAT_Pos 29U
882#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)
884#define SCB_CTR_CWG_Pos 24U
885#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
887#define SCB_CTR_ERG_Pos 20U
888#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)
890#define SCB_CTR_DMINLINE_Pos 16U
891#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)
893#define SCB_CTR_IMINLINE_Pos 0U
894#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
896/* SCB Cache Size ID Register Definitions */
897#define SCB_CCSIDR_WT_Pos 31U
898#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)
900#define SCB_CCSIDR_WB_Pos 30U
901#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)
903#define SCB_CCSIDR_RA_Pos 29U
904#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)
906#define SCB_CCSIDR_WA_Pos 28U
907#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)
909#define SCB_CCSIDR_NUMSETS_Pos 13U
910#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
912#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U
913#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
915#define SCB_CCSIDR_LINESIZE_Pos 0U
916#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
918/* SCB Cache Size Selection Register Definitions */
919#define SCB_CSSELR_LEVEL_Pos 1U
920#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)
922#define SCB_CSSELR_IND_Pos 0U
923#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)
925/* SCB Software Triggered Interrupt Register Definitions */
926#define SCB_STIR_INTID_Pos 0U
927#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
929/* SCB D-Cache Invalidate by Set-way Register Definitions */
930#define SCB_DCISW_WAY_Pos 30U
931#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)
933#define SCB_DCISW_SET_Pos 5U
934#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)
936/* SCB D-Cache Clean by Set-way Register Definitions */
937#define SCB_DCCSW_WAY_Pos 30U
938#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)
940#define SCB_DCCSW_SET_Pos 5U
941#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)
943/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
944#define SCB_DCCISW_WAY_Pos 30U
945#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)
947#define SCB_DCCISW_SET_Pos 5U
948#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)
963typedef struct
964{
965 uint32_t RESERVED0[1U];
966 __IM uint32_t ICTR;
967 __IOM uint32_t ACTLR;
968 __IOM uint32_t CPPWR;
969} SCnSCB_Type;
970
971/* Interrupt Controller Type Register Definitions */
972#define SCnSCB_ICTR_INTLINESNUM_Pos 0U
973#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
988typedef struct
989{
990 __IOM uint32_t CTRL;
991 __IOM uint32_t LOAD;
992 __IOM uint32_t VAL;
993 __IM uint32_t CALIB;
994} SysTick_Type;
995
996/* SysTick Control / Status Register Definitions */
997#define SysTick_CTRL_COUNTFLAG_Pos 16U
998#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
1000#define SysTick_CTRL_CLKSOURCE_Pos 2U
1001#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
1003#define SysTick_CTRL_TICKINT_Pos 1U
1004#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
1006#define SysTick_CTRL_ENABLE_Pos 0U
1007#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
1009/* SysTick Reload Register Definitions */
1010#define SysTick_LOAD_RELOAD_Pos 0U
1011#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
1013/* SysTick Current Register Definitions */
1014#define SysTick_VAL_CURRENT_Pos 0U
1015#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
1017/* SysTick Calibration Register Definitions */
1018#define SysTick_CALIB_NOREF_Pos 31U
1019#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
1021#define SysTick_CALIB_SKEW_Pos 30U
1022#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
1024#define SysTick_CALIB_TENMS_Pos 0U
1025#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
1040typedef struct
1041{
1042 __OM union
1043 {
1044 __OM uint8_t u8;
1045 __OM uint16_t u16;
1046 __OM uint32_t u32;
1047 } PORT [32U];
1048 uint32_t RESERVED0[864U];
1049 __IOM uint32_t TER;
1050 uint32_t RESERVED1[15U];
1051 __IOM uint32_t TPR;
1052 uint32_t RESERVED2[15U];
1053 __IOM uint32_t TCR;
1054 uint32_t RESERVED3[32U];
1055 uint32_t RESERVED4[43U];
1056 __OM uint32_t LAR;
1057 __IM uint32_t LSR;
1058 uint32_t RESERVED5[1U];
1059 __IM uint32_t DEVARCH;
1060 uint32_t RESERVED6[4U];
1061 __IM uint32_t PID4;
1062 __IM uint32_t PID5;
1063 __IM uint32_t PID6;
1064 __IM uint32_t PID7;
1065 __IM uint32_t PID0;
1066 __IM uint32_t PID1;
1067 __IM uint32_t PID2;
1068 __IM uint32_t PID3;
1069 __IM uint32_t CID0;
1070 __IM uint32_t CID1;
1071 __IM uint32_t CID2;
1072 __IM uint32_t CID3;
1073} ITM_Type;
1074
1075/* ITM Stimulus Port Register Definitions */
1076#define ITM_STIM_DISABLED_Pos 1U
1077#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)
1079#define ITM_STIM_FIFOREADY_Pos 0U
1080#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
1082/* ITM Trace Privilege Register Definitions */
1083#define ITM_TPR_PRIVMASK_Pos 0U
1084#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
1086/* ITM Trace Control Register Definitions */
1087#define ITM_TCR_BUSY_Pos 23U
1088#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
1090#define ITM_TCR_TRACEBUSID_Pos 16U
1091#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
1093#define ITM_TCR_GTSFREQ_Pos 10U
1094#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
1096#define ITM_TCR_TSPRESCALE_Pos 8U
1097#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)
1099#define ITM_TCR_STALLENA_Pos 5U
1100#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)
1102#define ITM_TCR_SWOENA_Pos 4U
1103#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
1105#define ITM_TCR_DWTENA_Pos 3U
1106#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
1108#define ITM_TCR_SYNCENA_Pos 2U
1109#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
1111#define ITM_TCR_TSENA_Pos 1U
1112#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
1114#define ITM_TCR_ITMENA_Pos 0U
1115#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
1117/* ITM Lock Status Register Definitions */
1118#define ITM_LSR_ByteAcc_Pos 2U
1119#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
1121#define ITM_LSR_Access_Pos 1U
1122#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
1124#define ITM_LSR_Present_Pos 0U
1125#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /* end of group CMSIS_ITM */
1128
1129
1140typedef struct
1141{
1142 __IOM uint32_t CTRL;
1143 __IOM uint32_t CYCCNT;
1144 __IOM uint32_t CPICNT;
1145 __IOM uint32_t EXCCNT;
1146 __IOM uint32_t SLEEPCNT;
1147 __IOM uint32_t LSUCNT;
1148 __IOM uint32_t FOLDCNT;
1149 __IM uint32_t PCSR;
1150 __IOM uint32_t COMP0;
1151 uint32_t RESERVED1[1U];
1152 __IOM uint32_t FUNCTION0;
1153 uint32_t RESERVED2[1U];
1154 __IOM uint32_t COMP1;
1155 uint32_t RESERVED3[1U];
1156 __IOM uint32_t FUNCTION1;
1157 uint32_t RESERVED4[1U];
1158 __IOM uint32_t COMP2;
1159 uint32_t RESERVED5[1U];
1160 __IOM uint32_t FUNCTION2;
1161 uint32_t RESERVED6[1U];
1162 __IOM uint32_t COMP3;
1163 uint32_t RESERVED7[1U];
1164 __IOM uint32_t FUNCTION3;
1165 uint32_t RESERVED8[1U];
1166 __IOM uint32_t COMP4;
1167 uint32_t RESERVED9[1U];
1168 __IOM uint32_t FUNCTION4;
1169 uint32_t RESERVED10[1U];
1170 __IOM uint32_t COMP5;
1171 uint32_t RESERVED11[1U];
1172 __IOM uint32_t FUNCTION5;
1173 uint32_t RESERVED12[1U];
1174 __IOM uint32_t COMP6;
1175 uint32_t RESERVED13[1U];
1176 __IOM uint32_t FUNCTION6;
1177 uint32_t RESERVED14[1U];
1178 __IOM uint32_t COMP7;
1179 uint32_t RESERVED15[1U];
1180 __IOM uint32_t FUNCTION7;
1181 uint32_t RESERVED16[1U];
1182 __IOM uint32_t COMP8;
1183 uint32_t RESERVED17[1U];
1184 __IOM uint32_t FUNCTION8;
1185 uint32_t RESERVED18[1U];
1186 __IOM uint32_t COMP9;
1187 uint32_t RESERVED19[1U];
1188 __IOM uint32_t FUNCTION9;
1189 uint32_t RESERVED20[1U];
1190 __IOM uint32_t COMP10;
1191 uint32_t RESERVED21[1U];
1192 __IOM uint32_t FUNCTION10;
1193 uint32_t RESERVED22[1U];
1194 __IOM uint32_t COMP11;
1195 uint32_t RESERVED23[1U];
1196 __IOM uint32_t FUNCTION11;
1197 uint32_t RESERVED24[1U];
1198 __IOM uint32_t COMP12;
1199 uint32_t RESERVED25[1U];
1200 __IOM uint32_t FUNCTION12;
1201 uint32_t RESERVED26[1U];
1202 __IOM uint32_t COMP13;
1203 uint32_t RESERVED27[1U];
1204 __IOM uint32_t FUNCTION13;
1205 uint32_t RESERVED28[1U];
1206 __IOM uint32_t COMP14;
1207 uint32_t RESERVED29[1U];
1208 __IOM uint32_t FUNCTION14;
1209 uint32_t RESERVED30[1U];
1210 __IOM uint32_t COMP15;
1211 uint32_t RESERVED31[1U];
1212 __IOM uint32_t FUNCTION15;
1213 uint32_t RESERVED32[934U];
1214 __IM uint32_t LSR;
1215 uint32_t RESERVED33[1U];
1216 __IM uint32_t DEVARCH;
1217} DWT_Type;
1218
1219/* DWT Control Register Definitions */
1220#define DWT_CTRL_NUMCOMP_Pos 28U
1221#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
1223#define DWT_CTRL_NOTRCPKT_Pos 27U
1224#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
1226#define DWT_CTRL_NOEXTTRIG_Pos 26U
1227#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
1229#define DWT_CTRL_NOCYCCNT_Pos 25U
1230#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
1232#define DWT_CTRL_NOPRFCNT_Pos 24U
1233#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
1235#define DWT_CTRL_CYCDISS_Pos 23U
1236#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos)
1238#define DWT_CTRL_CYCEVTENA_Pos 22U
1239#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
1241#define DWT_CTRL_FOLDEVTENA_Pos 21U
1242#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
1244#define DWT_CTRL_LSUEVTENA_Pos 20U
1245#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
1247#define DWT_CTRL_SLEEPEVTENA_Pos 19U
1248#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
1250#define DWT_CTRL_EXCEVTENA_Pos 18U
1251#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
1253#define DWT_CTRL_CPIEVTENA_Pos 17U
1254#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
1256#define DWT_CTRL_EXCTRCENA_Pos 16U
1257#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
1259#define DWT_CTRL_PCSAMPLENA_Pos 12U
1260#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
1262#define DWT_CTRL_SYNCTAP_Pos 10U
1263#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
1265#define DWT_CTRL_CYCTAP_Pos 9U
1266#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
1268#define DWT_CTRL_POSTINIT_Pos 5U
1269#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
1271#define DWT_CTRL_POSTPRESET_Pos 1U
1272#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
1274#define DWT_CTRL_CYCCNTENA_Pos 0U
1275#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
1277/* DWT CPI Count Register Definitions */
1278#define DWT_CPICNT_CPICNT_Pos 0U
1279#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
1281/* DWT Exception Overhead Count Register Definitions */
1282#define DWT_EXCCNT_EXCCNT_Pos 0U
1283#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
1285/* DWT Sleep Count Register Definitions */
1286#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
1287#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
1289/* DWT LSU Count Register Definitions */
1290#define DWT_LSUCNT_LSUCNT_Pos 0U
1291#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
1293/* DWT Folded-instruction Count Register Definitions */
1294#define DWT_FOLDCNT_FOLDCNT_Pos 0U
1295#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
1297/* DWT Comparator Function Register Definitions */
1298#define DWT_FUNCTION_ID_Pos 27U
1299#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)
1301#define DWT_FUNCTION_MATCHED_Pos 24U
1302#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
1304#define DWT_FUNCTION_DATAVSIZE_Pos 10U
1305#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
1307#define DWT_FUNCTION_ACTION_Pos 4U
1308#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos)
1310#define DWT_FUNCTION_MATCH_Pos 0U
1311#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /* end of group CMSIS_DWT */
1314
1315
1326typedef struct
1327{
1328 __IM uint32_t SSPSR;
1329 __IOM uint32_t CSPSR;
1330 uint32_t RESERVED0[2U];
1331 __IOM uint32_t ACPR;
1332 uint32_t RESERVED1[55U];
1333 __IOM uint32_t SPPR;
1334 uint32_t RESERVED2[131U];
1335 __IM uint32_t FFSR;
1336 __IOM uint32_t FFCR;
1337 __IOM uint32_t PSCR;
1338 uint32_t RESERVED3[759U];
1339 __IM uint32_t TRIGGER;
1340 __IM uint32_t ITFTTD0;
1341 __IOM uint32_t ITATBCTR2;
1342 uint32_t RESERVED4[1U];
1343 __IM uint32_t ITATBCTR0;
1344 __IM uint32_t ITFTTD1;
1345 __IOM uint32_t ITCTRL;
1346 uint32_t RESERVED5[39U];
1347 __IOM uint32_t CLAIMSET;
1348 __IOM uint32_t CLAIMCLR;
1349 uint32_t RESERVED7[8U];
1350 __IM uint32_t DEVID;
1351 __IM uint32_t DEVTYPE;
1352} TPI_Type;
1353
1354/* TPI Asynchronous Clock Prescaler Register Definitions */
1355#define TPI_ACPR_PRESCALER_Pos 0U
1356#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
1358/* TPI Selected Pin Protocol Register Definitions */
1359#define TPI_SPPR_TXMODE_Pos 0U
1360#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
1362/* TPI Formatter and Flush Status Register Definitions */
1363#define TPI_FFSR_FtNonStop_Pos 3U
1364#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1366#define TPI_FFSR_TCPresent_Pos 2U
1367#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1369#define TPI_FFSR_FtStopped_Pos 1U
1370#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1372#define TPI_FFSR_FlInProg_Pos 0U
1373#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
1375/* TPI Formatter and Flush Control Register Definitions */
1376#define TPI_FFCR_TrigIn_Pos 8U
1377#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1379#define TPI_FFCR_FOnMan_Pos 6U
1380#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
1382#define TPI_FFCR_EnFCont_Pos 1U
1383#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1385/* TPI TRIGGER Register Definitions */
1386#define TPI_TRIGGER_TRIGGER_Pos 0U
1387#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
1389/* TPI Integration Test FIFO Test Data 0 Register Definitions */
1390#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U
1391#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)
1393#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U
1394#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)
1396#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U
1397#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)
1399#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U
1400#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)
1402#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U
1403#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
1405#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U
1406#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
1408#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U
1409#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/)
1411/* TPI Integration Test ATB Control Register 2 Register Definitions */
1412#define TPI_ITATBCTR2_AFVALID2S_Pos 1U
1413#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)
1415#define TPI_ITATBCTR2_AFVALID1S_Pos 1U
1416#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)
1418#define TPI_ITATBCTR2_ATREADY2S_Pos 0U
1419#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)
1421#define TPI_ITATBCTR2_ATREADY1S_Pos 0U
1422#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)
1424/* TPI Integration Test FIFO Test Data 1 Register Definitions */
1425#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U
1426#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)
1428#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U
1429#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)
1431#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U
1432#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)
1434#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U
1435#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)
1437#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U
1438#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
1440#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U
1441#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
1443#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U
1444#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/)
1446/* TPI Integration Test ATB Control Register 0 Definitions */
1447#define TPI_ITATBCTR0_AFVALID2S_Pos 1U
1448#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)
1450#define TPI_ITATBCTR0_AFVALID1S_Pos 1U
1451#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)
1453#define TPI_ITATBCTR0_ATREADY2S_Pos 0U
1454#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)
1456#define TPI_ITATBCTR0_ATREADY1S_Pos 0U
1457#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)
1459/* TPI Integration Mode Control Register Definitions */
1460#define TPI_ITCTRL_Mode_Pos 0U
1461#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
1463/* TPI DEVID Register Definitions */
1464#define TPI_DEVID_NRZVALID_Pos 11U
1465#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1467#define TPI_DEVID_MANCVALID_Pos 10U
1468#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1470#define TPI_DEVID_PTINVALID_Pos 9U
1471#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1473#define TPI_DEVID_FIFOSZ_Pos 6U
1474#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
1476#define TPI_DEVID_NrTraceInput_Pos 0U
1477#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
1479/* TPI DEVTYPE Register Definitions */
1480#define TPI_DEVTYPE_SubType_Pos 4U
1481#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
1483#define TPI_DEVTYPE_MajorType_Pos 0U
1484#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /* end of group CMSIS_TPI */
1487
1488
1489#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1500typedef struct
1501{
1502 __IM uint32_t TYPE;
1503 __IOM uint32_t CTRL;
1504 __IOM uint32_t RNR;
1505 __IOM uint32_t RBAR;
1506 __IOM uint32_t RLAR;
1507 __IOM uint32_t RBAR_A1;
1508 __IOM uint32_t RLAR_A1;
1509 __IOM uint32_t RBAR_A2;
1510 __IOM uint32_t RLAR_A2;
1511 __IOM uint32_t RBAR_A3;
1512 __IOM uint32_t RLAR_A3;
1513 uint32_t RESERVED0[1];
1514 union {
1515 __IOM uint32_t MAIR[2];
1516 struct {
1517 __IOM uint32_t MAIR0;
1518 __IOM uint32_t MAIR1;
1519 };
1520 };
1521} MPU_Type;
1522
1523#define MPU_TYPE_RALIASES 4U
1524
1525/* MPU Type Register Definitions */
1526#define MPU_TYPE_IREGION_Pos 16U
1527#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1529#define MPU_TYPE_DREGION_Pos 8U
1530#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1532#define MPU_TYPE_SEPARATE_Pos 0U
1533#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
1535/* MPU Control Register Definitions */
1536#define MPU_CTRL_PRIVDEFENA_Pos 2U
1537#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1539#define MPU_CTRL_HFNMIENA_Pos 1U
1540#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1542#define MPU_CTRL_ENABLE_Pos 0U
1543#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
1545/* MPU Region Number Register Definitions */
1546#define MPU_RNR_REGION_Pos 0U
1547#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
1549/* MPU Region Base Address Register Definitions */
1550#define MPU_RBAR_BASE_Pos 5U
1551#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
1553#define MPU_RBAR_SH_Pos 3U
1554#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
1556#define MPU_RBAR_AP_Pos 1U
1557#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
1559#define MPU_RBAR_XN_Pos 0U
1560#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/)
1562/* MPU Region Limit Address Register Definitions */
1563#define MPU_RLAR_LIMIT_Pos 5U
1564#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
1566#define MPU_RLAR_AttrIndx_Pos 1U
1567#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
1569#define MPU_RLAR_EN_Pos 0U
1570#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/)
1572/* MPU Memory Attribute Indirection Register 0 Definitions */
1573#define MPU_MAIR0_Attr3_Pos 24U
1574#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
1576#define MPU_MAIR0_Attr2_Pos 16U
1577#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
1579#define MPU_MAIR0_Attr1_Pos 8U
1580#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
1582#define MPU_MAIR0_Attr0_Pos 0U
1583#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)
1585/* MPU Memory Attribute Indirection Register 1 Definitions */
1586#define MPU_MAIR1_Attr7_Pos 24U
1587#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
1589#define MPU_MAIR1_Attr6_Pos 16U
1590#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
1592#define MPU_MAIR1_Attr5_Pos 8U
1593#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
1595#define MPU_MAIR1_Attr4_Pos 0U
1596#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)
1599#endif
1600
1601
1602#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1613typedef struct
1614{
1615 __IOM uint32_t CTRL;
1616 __IM uint32_t TYPE;
1617#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1618 __IOM uint32_t RNR;
1619 __IOM uint32_t RBAR;
1620 __IOM uint32_t RLAR;
1621#else
1622 uint32_t RESERVED0[3];
1623#endif
1624 __IOM uint32_t SFSR;
1625 __IOM uint32_t SFAR;
1626} SAU_Type;
1627
1628/* SAU Control Register Definitions */
1629#define SAU_CTRL_ALLNS_Pos 1U
1630#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos)
1632#define SAU_CTRL_ENABLE_Pos 0U
1633#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/)
1635/* SAU Type Register Definitions */
1636#define SAU_TYPE_SREGION_Pos 0U
1637#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)
1639#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1640/* SAU Region Number Register Definitions */
1641#define SAU_RNR_REGION_Pos 0U
1642#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/)
1644/* SAU Region Base Address Register Definitions */
1645#define SAU_RBAR_BADDR_Pos 5U
1646#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)
1648/* SAU Region Limit Address Register Definitions */
1649#define SAU_RLAR_LADDR_Pos 5U
1650#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)
1652#define SAU_RLAR_NSC_Pos 1U
1653#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos)
1655#define SAU_RLAR_ENABLE_Pos 0U
1656#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/)
1658#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1659
1660/* Secure Fault Status Register Definitions */
1661#define SAU_SFSR_LSERR_Pos 7U
1662#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos)
1664#define SAU_SFSR_SFARVALID_Pos 6U
1665#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos)
1667#define SAU_SFSR_LSPERR_Pos 5U
1668#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos)
1670#define SAU_SFSR_INVTRAN_Pos 4U
1671#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos)
1673#define SAU_SFSR_AUVIOL_Pos 3U
1674#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos)
1676#define SAU_SFSR_INVER_Pos 2U
1677#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos)
1679#define SAU_SFSR_INVIS_Pos 1U
1680#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos)
1682#define SAU_SFSR_INVEP_Pos 0U
1683#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/)
1686#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1687
1688
1699typedef struct
1700{
1701 uint32_t RESERVED0[1U];
1702 __IOM uint32_t FPCCR;
1703 __IOM uint32_t FPCAR;
1704 __IOM uint32_t FPDSCR;
1705 __IM uint32_t MVFR0;
1706 __IM uint32_t MVFR1;
1707 __IM uint32_t MVFR2;
1708} FPU_Type;
1709
1710/* Floating-Point Context Control Register Definitions */
1711#define FPU_FPCCR_ASPEN_Pos 31U
1712#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
1714#define FPU_FPCCR_LSPEN_Pos 30U
1715#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
1717#define FPU_FPCCR_LSPENS_Pos 29U
1718#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)
1720#define FPU_FPCCR_CLRONRET_Pos 28U
1721#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)
1723#define FPU_FPCCR_CLRONRETS_Pos 27U
1724#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)
1726#define FPU_FPCCR_TS_Pos 26U
1727#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)
1729#define FPU_FPCCR_UFRDY_Pos 10U
1730#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)
1732#define FPU_FPCCR_SPLIMVIOL_Pos 9U
1733#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
1735#define FPU_FPCCR_MONRDY_Pos 8U
1736#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
1738#define FPU_FPCCR_SFRDY_Pos 7U
1739#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)
1741#define FPU_FPCCR_BFRDY_Pos 6U
1742#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
1744#define FPU_FPCCR_MMRDY_Pos 5U
1745#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
1747#define FPU_FPCCR_HFRDY_Pos 4U
1748#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
1750#define FPU_FPCCR_THREAD_Pos 3U
1751#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
1753#define FPU_FPCCR_S_Pos 2U
1754#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)
1756#define FPU_FPCCR_USER_Pos 1U
1757#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
1759#define FPU_FPCCR_LSPACT_Pos 0U
1760#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
1762/* Floating-Point Context Address Register Definitions */
1763#define FPU_FPCAR_ADDRESS_Pos 3U
1764#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
1766/* Floating-Point Default Status Control Register Definitions */
1767#define FPU_FPDSCR_AHP_Pos 26U
1768#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
1770#define FPU_FPDSCR_DN_Pos 25U
1771#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
1773#define FPU_FPDSCR_FZ_Pos 24U
1774#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
1776#define FPU_FPDSCR_RMode_Pos 22U
1777#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
1779/* Media and VFP Feature Register 0 Definitions */
1780#define FPU_MVFR0_FP_rounding_modes_Pos 28U
1781#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
1783#define FPU_MVFR0_Short_vectors_Pos 24U
1784#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
1786#define FPU_MVFR0_Square_root_Pos 20U
1787#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
1789#define FPU_MVFR0_Divide_Pos 16U
1790#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
1792#define FPU_MVFR0_FP_excep_trapping_Pos 12U
1793#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
1795#define FPU_MVFR0_Double_precision_Pos 8U
1796#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
1798#define FPU_MVFR0_Single_precision_Pos 4U
1799#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
1801#define FPU_MVFR0_A_SIMD_registers_Pos 0U
1802#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
1804/* Media and VFP Feature Register 1 Definitions */
1805#define FPU_MVFR1_FP_fused_MAC_Pos 28U
1806#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
1808#define FPU_MVFR1_FP_HPFP_Pos 24U
1809#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
1811#define FPU_MVFR1_D_NaN_mode_Pos 4U
1812#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
1814#define FPU_MVFR1_FtZ_mode_Pos 0U
1815#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
1817/* Media and VFP Feature Register 2 Definitions */
1818#define FPU_MVFR2_FPMisc_Pos 4U
1819#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos)
1823/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
1834typedef struct
1835{
1836 __IOM uint32_t DHCSR;
1837 __OM uint32_t DCRSR;
1838 __IOM uint32_t DCRDR;
1839 __IOM uint32_t DEMCR;
1840 uint32_t RESERVED0[1U];
1841 __IOM uint32_t DAUTHCTRL;
1842 __IOM uint32_t DSCSR;
1843} CoreDebug_Type;
1844
1845/* Debug Halting Control and Status Register Definitions */
1846#define CoreDebug_DHCSR_DBGKEY_Pos 16U
1847#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1849#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U
1850#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
1852#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1853#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1855#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1856#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1858#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1859#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1861#define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1862#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1864#define CoreDebug_DHCSR_S_HALT_Pos 17U
1865#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1867#define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1868#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1870#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
1871#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1873#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1874#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1876#define CoreDebug_DHCSR_C_STEP_Pos 2U
1877#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1879#define CoreDebug_DHCSR_C_HALT_Pos 1U
1880#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1882#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1883#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
1885/* Debug Core Register Selector Register Definitions */
1886#define CoreDebug_DCRSR_REGWnR_Pos 16U
1887#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1889#define CoreDebug_DCRSR_REGSEL_Pos 0U
1890#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
1892/* Debug Exception and Monitor Control Register Definitions */
1893#define CoreDebug_DEMCR_TRCENA_Pos 24U
1894#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1896#define CoreDebug_DEMCR_MON_REQ_Pos 19U
1897#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1899#define CoreDebug_DEMCR_MON_STEP_Pos 18U
1900#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1902#define CoreDebug_DEMCR_MON_PEND_Pos 17U
1903#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1905#define CoreDebug_DEMCR_MON_EN_Pos 16U
1906#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1908#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1909#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1911#define CoreDebug_DEMCR_VC_INTERR_Pos 9U
1912#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1914#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
1915#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1917#define CoreDebug_DEMCR_VC_STATERR_Pos 7U
1918#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1920#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
1921#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1923#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
1924#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1926#define CoreDebug_DEMCR_VC_MMERR_Pos 4U
1927#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1929#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1930#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
1932/* Debug Authentication Control Register Definitions */
1933#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U
1934#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
1936#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U
1937#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
1939#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U
1940#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
1942#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U
1943#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
1945/* Debug Security Control and Status Register Definitions */
1946#define CoreDebug_DSCSR_CDS_Pos 16U
1947#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)
1949#define CoreDebug_DSCSR_SBRSEL_Pos 1U
1950#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
1952#define CoreDebug_DSCSR_SBRSELEN_Pos 0U
1953#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
1968typedef struct
1969{
1970 __IOM uint32_t DHCSR;
1971 __OM uint32_t DCRSR;
1972 __IOM uint32_t DCRDR;
1973 __IOM uint32_t DEMCR;
1974 uint32_t RESERVED0[1U];
1975 __IOM uint32_t DAUTHCTRL;
1976 __IOM uint32_t DSCSR;
1977} DCB_Type;
1978
1979/* DHCSR, Debug Halting Control and Status Register Definitions */
1980#define DCB_DHCSR_DBGKEY_Pos 16U
1981#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
1983#define DCB_DHCSR_S_RESTART_ST_Pos 26U
1984#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
1986#define DCB_DHCSR_S_RESET_ST_Pos 25U
1987#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
1989#define DCB_DHCSR_S_RETIRE_ST_Pos 24U
1990#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
1992#define DCB_DHCSR_S_SDE_Pos 20U
1993#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)
1995#define DCB_DHCSR_S_LOCKUP_Pos 19U
1996#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
1998#define DCB_DHCSR_S_SLEEP_Pos 18U
1999#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
2001#define DCB_DHCSR_S_HALT_Pos 17U
2002#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)
2004#define DCB_DHCSR_S_REGRDY_Pos 16U
2005#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
2007#define DCB_DHCSR_C_SNAPSTALL_Pos 5U
2008#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
2010#define DCB_DHCSR_C_MASKINTS_Pos 3U
2011#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
2013#define DCB_DHCSR_C_STEP_Pos 2U
2014#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)
2016#define DCB_DHCSR_C_HALT_Pos 1U
2017#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)
2019#define DCB_DHCSR_C_DEBUGEN_Pos 0U
2020#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)
2022/* DCRSR, Debug Core Register Select Register Definitions */
2023#define DCB_DCRSR_REGWnR_Pos 16U
2024#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)
2026#define DCB_DCRSR_REGSEL_Pos 0U
2027#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)
2029/* DCRDR, Debug Core Register Data Register Definitions */
2030#define DCB_DCRDR_DBGTMP_Pos 0U
2031#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)
2033/* DEMCR, Debug Exception and Monitor Control Register Definitions */
2034#define DCB_DEMCR_TRCENA_Pos 24U
2035#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)
2037#define DCB_DEMCR_MONPRKEY_Pos 23U
2038#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
2040#define DCB_DEMCR_UMON_EN_Pos 21U
2041#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos)
2043#define DCB_DEMCR_SDME_Pos 20U
2044#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos)
2046#define DCB_DEMCR_MON_REQ_Pos 19U
2047#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos)
2049#define DCB_DEMCR_MON_STEP_Pos 18U
2050#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos)
2052#define DCB_DEMCR_MON_PEND_Pos 17U
2053#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos)
2055#define DCB_DEMCR_MON_EN_Pos 16U
2056#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos)
2058#define DCB_DEMCR_VC_SFERR_Pos 11U
2059#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
2061#define DCB_DEMCR_VC_HARDERR_Pos 10U
2062#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
2064#define DCB_DEMCR_VC_INTERR_Pos 9U
2065#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
2067#define DCB_DEMCR_VC_BUSERR_Pos 8U
2068#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
2070#define DCB_DEMCR_VC_STATERR_Pos 7U
2071#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
2073#define DCB_DEMCR_VC_CHKERR_Pos 6U
2074#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
2076#define DCB_DEMCR_VC_NOCPERR_Pos 5U
2077#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
2079#define DCB_DEMCR_VC_MMERR_Pos 4U
2080#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
2082#define DCB_DEMCR_VC_CORERESET_Pos 0U
2083#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)
2085/* DAUTHCTRL, Debug Authentication Control Register Definitions */
2086#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U
2087#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
2089#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U
2090#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
2092#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U
2093#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
2095#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U
2096#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)
2098/* DSCSR, Debug Security Control and Status Register Definitions */
2099#define DCB_DSCSR_CDSKEY_Pos 17U
2100#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)
2102#define DCB_DSCSR_CDS_Pos 16U
2103#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)
2105#define DCB_DSCSR_SBRSEL_Pos 1U
2106#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)
2108#define DCB_DSCSR_SBRSELEN_Pos 0U
2109#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)
2125typedef struct
2126{
2127 __OM uint32_t DLAR;
2128 __IM uint32_t DLSR;
2129 __IM uint32_t DAUTHSTATUS;
2130 __IM uint32_t DDEVARCH;
2131 __IM uint32_t DDEVTYPE;
2132} DIB_Type;
2133
2134/* DLAR, SCS Software Lock Access Register Definitions */
2135#define DIB_DLAR_KEY_Pos 0U
2136#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */)
2138/* DLSR, SCS Software Lock Status Register Definitions */
2139#define DIB_DLSR_nTT_Pos 2U
2140#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos )
2142#define DIB_DLSR_SLK_Pos 1U
2143#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos )
2145#define DIB_DLSR_SLI_Pos 0U
2146#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/)
2148/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
2149#define DIB_DAUTHSTATUS_SNID_Pos 6U
2150#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )
2152#define DIB_DAUTHSTATUS_SID_Pos 4U
2153#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos )
2155#define DIB_DAUTHSTATUS_NSNID_Pos 2U
2156#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )
2158#define DIB_DAUTHSTATUS_NSID_Pos 0U
2159#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/)
2161/* DDEVARCH, SCS Device Architecture Register Definitions */
2162#define DIB_DDEVARCH_ARCHITECT_Pos 21U
2163#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )
2165#define DIB_DDEVARCH_PRESENT_Pos 20U
2166#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )
2168#define DIB_DDEVARCH_REVISION_Pos 16U
2169#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos )
2171#define DIB_DDEVARCH_ARCHVER_Pos 12U
2172#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )
2174#define DIB_DDEVARCH_ARCHPART_Pos 0U
2175#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/)
2177/* DDEVTYPE, SCS Device Type Register Definitions */
2178#define DIB_DDEVTYPE_SUB_Pos 4U
2179#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos )
2181#define DIB_DDEVTYPE_MAJOR_Pos 0U
2182#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/)
2201#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
2202
2209#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
2210
2221/* Memory mapping of Core Hardware */
2222 #define SCS_BASE (0xE000E000UL)
2223 #define ITM_BASE (0xE0000000UL)
2224 #define DWT_BASE (0xE0001000UL)
2225 #define TPI_BASE (0xE0040000UL)
2226 #define CoreDebug_BASE (0xE000EDF0UL)
2227 #define DCB_BASE (0xE000EDF0UL)
2228 #define DIB_BASE (0xE000EFB0UL)
2229 #define SysTick_BASE (SCS_BASE + 0x0010UL)
2230 #define NVIC_BASE (SCS_BASE + 0x0100UL)
2231 #define SCB_BASE (SCS_BASE + 0x0D00UL)
2233 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
2234 #define SCB ((SCB_Type *) SCB_BASE )
2235 #define SysTick ((SysTick_Type *) SysTick_BASE )
2236 #define NVIC ((NVIC_Type *) NVIC_BASE )
2237 #define ITM ((ITM_Type *) ITM_BASE )
2238 #define DWT ((DWT_Type *) DWT_BASE )
2239 #define TPI ((TPI_Type *) TPI_BASE )
2240 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )
2241 #define DCB ((DCB_Type *) DCB_BASE )
2242 #define DIB ((DIB_Type *) DIB_BASE )
2244 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2245 #define MPU_BASE (SCS_BASE + 0x0D90UL)
2246 #define MPU ((MPU_Type *) MPU_BASE )
2247 #endif
2248
2249 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2250 #define SAU_BASE (SCS_BASE + 0x0DD0UL)
2251 #define SAU ((SAU_Type *) SAU_BASE )
2252 #endif
2253
2254 #define FPU_BASE (SCS_BASE + 0x0F30UL)
2255 #define FPU ((FPU_Type *) FPU_BASE )
2257#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2258 #define SCS_BASE_NS (0xE002E000UL)
2259 #define CoreDebug_BASE_NS (0xE002EDF0UL)
2260 #define DCB_BASE_NS (0xE002EDF0UL)
2261 #define DIB_BASE_NS (0xE002EFB0UL)
2262 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL)
2263 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL)
2264 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL)
2266 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS )
2267 #define SCB_NS ((SCB_Type *) SCB_BASE_NS )
2268 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS )
2269 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS )
2270 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS)
2271 #define DCB_NS ((DCB_Type *) DCB_BASE_NS )
2272 #define DIB_NS ((DIB_Type *) DIB_BASE_NS )
2274 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2275 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL)
2276 #define MPU_NS ((MPU_Type *) MPU_BASE_NS )
2277 #endif
2278
2279 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL)
2280 #define FPU_NS ((FPU_Type *) FPU_BASE_NS )
2282#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2292#define ID_ADR (ID_AFR)
2296/*******************************************************************************
2297 * Hardware Abstraction Layer
2298 Core Function Interface contains:
2299 - Core NVIC Functions
2300 - Core SysTick Functions
2301 - Core Debug Functions
2302 - Core Register Access Functions
2303 ******************************************************************************/
2310/* ########################## NVIC functions #################################### */
2318#ifdef CMSIS_NVIC_VIRTUAL
2319 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
2320 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
2321 #endif
2322 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
2323#else
2324 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
2325 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
2326 #define NVIC_EnableIRQ __NVIC_EnableIRQ
2327 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
2328 #define NVIC_DisableIRQ __NVIC_DisableIRQ
2329 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
2330 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
2331 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
2332 #define NVIC_GetActive __NVIC_GetActive
2333 #define NVIC_SetPriority __NVIC_SetPriority
2334 #define NVIC_GetPriority __NVIC_GetPriority
2335 #define NVIC_SystemReset __NVIC_SystemReset
2336#endif /* CMSIS_NVIC_VIRTUAL */
2337
2338#ifdef CMSIS_VECTAB_VIRTUAL
2339 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2340 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
2341 #endif
2342 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2343#else
2344 #define NVIC_SetVector __NVIC_SetVector
2345 #define NVIC_GetVector __NVIC_GetVector
2346#endif /* (CMSIS_VECTAB_VIRTUAL) */
2347
2348#define NVIC_USER_IRQ_OFFSET 16
2349
2350
2351/* Special LR values for Secure/Non-Secure call handling and exception handling */
2352
2353/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
2354#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
2355
2356/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
2357#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
2358#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
2359#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
2360#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
2361#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
2362#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
2363#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
2364
2365/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
2366#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
2367#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
2368#else
2369#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
2370#endif
2371
2372
2382__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
2383{
2384 uint32_t reg_value;
2385 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2386
2387 reg_value = SCB->AIRCR; /* read old register configuration */
2388 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2389 reg_value = (reg_value |
2390 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2391 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2392 SCB->AIRCR = reg_value;
2393}
2394
2395
2401__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
2402{
2403 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2404}
2405
2406
2413__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
2414{
2415 if ((int32_t)(IRQn) >= 0)
2416 {
2417 __COMPILER_BARRIER();
2418 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2419 __COMPILER_BARRIER();
2420 }
2421}
2422
2423
2432__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
2433{
2434 if ((int32_t)(IRQn) >= 0)
2435 {
2436 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2437 }
2438 else
2439 {
2440 return(0U);
2441 }
2442}
2443
2444
2451__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
2452{
2453 if ((int32_t)(IRQn) >= 0)
2454 {
2455 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2456 __DSB();
2457 __ISB();
2458 }
2459}
2460
2461
2470__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2471{
2472 if ((int32_t)(IRQn) >= 0)
2473 {
2474 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2475 }
2476 else
2477 {
2478 return(0U);
2479 }
2480}
2481
2482
2489__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2490{
2491 if ((int32_t)(IRQn) >= 0)
2492 {
2493 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2494 }
2495}
2496
2497
2504__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2505{
2506 if ((int32_t)(IRQn) >= 0)
2507 {
2508 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2509 }
2510}
2511
2512
2521__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2522{
2523 if ((int32_t)(IRQn) >= 0)
2524 {
2525 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2526 }
2527 else
2528 {
2529 return(0U);
2530 }
2531}
2532
2533
2534#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2543__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
2544{
2545 if ((int32_t)(IRQn) >= 0)
2546 {
2547 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2548 }
2549 else
2550 {
2551 return(0U);
2552 }
2553}
2554
2555
2564__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
2565{
2566 if ((int32_t)(IRQn) >= 0)
2567 {
2568 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2569 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2570 }
2571 else
2572 {
2573 return(0U);
2574 }
2575}
2576
2577
2586__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
2587{
2588 if ((int32_t)(IRQn) >= 0)
2589 {
2590 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2591 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2592 }
2593 else
2594 {
2595 return(0U);
2596 }
2597}
2598#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2599
2600
2610__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2611{
2612 if ((int32_t)(IRQn) >= 0)
2613 {
2614 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2615 }
2616 else
2617 {
2618 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2619 }
2620}
2621
2622
2632__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2633{
2634
2635 if ((int32_t)(IRQn) >= 0)
2636 {
2637 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2638 }
2639 else
2640 {
2641 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2642 }
2643}
2644
2645
2657__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2658{
2659 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2660 uint32_t PreemptPriorityBits;
2661 uint32_t SubPriorityBits;
2662
2663 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2664 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2665
2666 return (
2667 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2668 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2669 );
2670}
2671
2672
2684__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2685{
2686 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2687 uint32_t PreemptPriorityBits;
2688 uint32_t SubPriorityBits;
2689
2690 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2691 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2692
2693 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2694 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2695}
2696
2697
2707__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2708{
2709 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2710 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2711 __DSB();
2712}
2713
2714
2723__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2724{
2725 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2726 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2727}
2728
2729
2734__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2735{
2736 __DSB(); /* Ensure all outstanding memory accesses included
2737 buffered write are completed before reset */
2738 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2739 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2740 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2741 __DSB(); /* Ensure completion of memory access */
2742
2743 for(;;) /* wait until reset */
2744 {
2745 __NOP();
2746 }
2747}
2748
2749#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2759__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
2760{
2761 uint32_t reg_value;
2762 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2763
2764 reg_value = SCB_NS->AIRCR; /* read old register configuration */
2765 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2766 reg_value = (reg_value |
2767 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2768 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2769 SCB_NS->AIRCR = reg_value;
2770}
2771
2772
2778__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
2779{
2780 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2781}
2782
2783
2790__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
2791{
2792 if ((int32_t)(IRQn) >= 0)
2793 {
2794 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2795 }
2796}
2797
2798
2807__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
2808{
2809 if ((int32_t)(IRQn) >= 0)
2810 {
2811 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2812 }
2813 else
2814 {
2815 return(0U);
2816 }
2817}
2818
2819
2826__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
2827{
2828 if ((int32_t)(IRQn) >= 0)
2829 {
2830 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2831 }
2832}
2833
2834
2843__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
2844{
2845 if ((int32_t)(IRQn) >= 0)
2846 {
2847 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2848 }
2849 else
2850 {
2851 return(0U);
2852 }
2853}
2854
2855
2862__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
2863{
2864 if ((int32_t)(IRQn) >= 0)
2865 {
2866 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2867 }
2868}
2869
2870
2877__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
2878{
2879 if ((int32_t)(IRQn) >= 0)
2880 {
2881 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2882 }
2883}
2884
2885
2894__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
2895{
2896 if ((int32_t)(IRQn) >= 0)
2897 {
2898 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2899 }
2900 else
2901 {
2902 return(0U);
2903 }
2904}
2905
2906
2916__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
2917{
2918 if ((int32_t)(IRQn) >= 0)
2919 {
2920 NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2921 }
2922 else
2923 {
2924 SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2925 }
2926}
2927
2928
2937__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
2938{
2939
2940 if ((int32_t)(IRQn) >= 0)
2941 {
2942 return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2943 }
2944 else
2945 {
2946 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2947 }
2948}
2949#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
2950
2953/* ########################## MPU functions #################################### */
2954
2955#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2956
2957#include "mpu_armv8.h"
2958
2959#endif
2960
2961/* ########################## FPU functions #################################### */
2977__STATIC_INLINE uint32_t SCB_GetFPUType(void)
2978{
2979 uint32_t mvfr0;
2980
2981 mvfr0 = FPU->MVFR0;
2982 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
2983 {
2984 return 2U; /* Double + Single precision FPU */
2985 }
2986 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2987 {
2988 return 1U; /* Single precision FPU */
2989 }
2990 else
2991 {
2992 return 0U; /* No FPU */
2993 }
2994}
2995
2996
3001/* ########################## SAU functions #################################### */
3009#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3010
3015__STATIC_INLINE void TZ_SAU_Enable(void)
3016{
3017 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
3018}
3019
3020
3021
3026__STATIC_INLINE void TZ_SAU_Disable(void)
3027{
3028 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
3029}
3030
3031#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3032
3038/* ################################## Debug Control function ############################################ */
3052__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
3053{
3054 __DSB();
3055 __ISB();
3056 DCB->DAUTHCTRL = value;
3057 __DSB();
3058 __ISB();
3059}
3060
3061
3067__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
3068{
3069 return (DCB->DAUTHCTRL);
3070}
3071
3072
3073#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3079__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
3080{
3081 __DSB();
3082 __ISB();
3083 DCB_NS->DAUTHCTRL = value;
3084 __DSB();
3085 __ISB();
3086}
3087
3088
3094__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
3095{
3096 return (DCB_NS->DAUTHCTRL);
3097}
3098#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3099
3105/* ################################## Debug Identification function ############################################ */
3119__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
3120{
3121 return (DIB->DAUTHSTATUS);
3122}
3123
3124
3125#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3131__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
3132{
3133 return (DIB_NS->DAUTHSTATUS);
3134}
3135#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3136
3142/* ################################## SysTick function ############################################ */
3150#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
3151
3163__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
3164{
3165 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
3166 {
3167 return (1UL); /* Reload value impossible */
3168 }
3169
3170 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
3171 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
3172 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
3173 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
3174 SysTick_CTRL_TICKINT_Msk |
3175 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
3176 return (0UL); /* Function successful */
3177}
3178
3179#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3192__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
3193{
3194 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
3195 {
3196 return (1UL); /* Reload value impossible */
3197 }
3198
3199 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
3200 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
3201 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
3202 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
3203 SysTick_CTRL_TICKINT_Msk |
3204 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
3205 return (0UL); /* Function successful */
3206}
3207#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3208
3209#endif
3210
3215/* ##################################### Debug In/Output function ########################################### */
3223extern volatile int32_t ITM_RxBuffer;
3224#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
3235__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
3236{
3237 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
3238 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
3239 {
3240 while (ITM->PORT[0U].u32 == 0UL)
3241 {
3242 __NOP();
3243 }
3244 ITM->PORT[0U].u8 = (uint8_t)ch;
3245 }
3246 return (ch);
3247}
3248
3249
3256__STATIC_INLINE int32_t ITM_ReceiveChar (void)
3257{
3258 int32_t ch = -1; /* no character available */
3259
3260 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
3261 {
3262 ch = ITM_RxBuffer;
3263 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
3264 }
3265
3266 return (ch);
3267}
3268
3269
3276__STATIC_INLINE int32_t ITM_CheckChar (void)
3277{
3278
3279 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
3280 {
3281 return (0); /* no character available */
3282 }
3283 else
3284 {
3285 return (1); /* character available */
3286 }
3287}
3288
3294#ifdef __cplusplus
3295}
3296#endif
3297
3298#endif /* __CORE_CM35P_H_DEPENDANT */
3299
3300#endif /* __CMSIS_GENERIC */
cmsis_compiler.h
CMSIS compiler generic header file.
cmsis_version.h
CMSIS Core(M) Version definitions.
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition core_cm35p.h:1007
DCB
#define DCB
Definition core_cm35p.h:2241
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition core_cm35p.h:1011
FPU_MVFR0_Double_precision_Msk
#define FPU_MVFR0_Double_precision_Msk
Definition core_cm35p.h:1796
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition core_cm35p.h:1115
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition core_cm35p.h:654
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition core_cm35p.h:639
FPU_MVFR0_Single_precision_Msk
#define FPU_MVFR0_Single_precision_Msk
Definition core_cm35p.h:1799
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition core_cm35p.h:1004
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition core_cm35p.h:1001
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition core_cm35p.h:638
SCB
#define SCB
Definition core_cm35p.h:2234
DIB
#define DIB
Definition core_cm35p.h:2242
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition core_cm35p.h:660
ITM
#define ITM
Definition core_cm35p.h:2237
FPU
#define FPU
Definition core_cm35p.h:2255
NVIC
#define NVIC
Definition core_cm35p.h:2236
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition core_cm35p.h:653
SysTick
#define SysTick
Definition core_cm35p.h:2235
__ISB
#define __ISB()
Instruction Synchronization Barrier.
Definition cmsis_armcc.h:181
__DSB
#define __DSB()
Data Synchronization Barrier.
Definition cmsis_armcc.h:188
__NOP
#define __NOP
No Operation.
Definition cmsis_armcc.h:150
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition core_armv81mml.h:3634
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition core_armv81mml.h:3607
DIB_GetAuthStatus
__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
Get Debug Authentication Status Register.
Definition core_armv81mml.h:4070
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition core_armv81mml.h:3584
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition core_armv81mml.h:3623
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition core_armv81mml.h:3510
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition core_armv81mml.h:3404
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition core_armv81mml.h:3370
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition core_armv81mml.h:3885
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition core_armv81mml.h:3313
DCB_SetAuthCtrl
__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
Set Debug Authentication Control Register.
Definition core_armv81mml.h:4003
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition core_armv81mml.h:3421
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition core_armv81mml.h:3389
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition core_armv81mml.h:3332
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition core_armv81mml.h:3557
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition core_armv81mml.h:3351
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition core_armv81mml.h:3532
DCB_GetAuthCtrl
__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
Get Debug Authentication Control Register.
Definition core_armv81mml.h:4018
__NVIC_GetPriorityGrouping
#define __NVIC_GetPriorityGrouping()
Get Priority Grouping.
Definition core_armv8mbl.h:1446
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
ITM_Type::@44::u16
__OM uint16_t u16
Definition core_cm35p.h:1045
xPSR_Type::@42::T
uint32_t T
Definition core_cm35p.h:409
xPSR_Type::@42::V
uint32_t V
Definition core_cm35p.h:412
APSR_Type::@40::V
uint32_t V
Definition core_cm35p.h:352
ITM_Type::@44::u32
__OM uint32_t u32
Definition core_cm35p.h:1046
CONTROL_Type::@43::SPSEL
uint32_t SPSEL
Definition core_cm35p.h:457
CONTROL_Type::@43::nPRIV
uint32_t nPRIV
Definition core_cm35p.h:456
xPSR_Type::@42::Z
uint32_t Z
Definition core_cm35p.h:414
APSR_Type::@40::_reserved1
uint32_t _reserved1
Definition core_cm35p.h:350
xPSR_Type::@42::Q
uint32_t Q
Definition core_cm35p.h:411
APSR_Type::@40::_reserved0
uint32_t _reserved0
Definition core_cm35p.h:348
APSR_Type::@40::C
uint32_t C
Definition core_cm35p.h:353
xPSR_Type::@42::_reserved0
uint32_t _reserved0
Definition core_cm35p.h:406
CONTROL_Type::@43::SFPA
uint32_t SFPA
Definition core_cm35p.h:459
APSR_Type::@40::N
uint32_t N
Definition core_cm35p.h:355
ITM_Type::@44::u8
__OM uint8_t u8
Definition core_cm35p.h:1044
IPSR_Type::@41::_reserved0
uint32_t _reserved0
Definition core_cm35p.h:388
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition core_cm35p.h:3224
xPSR_Type::@42::ISR
uint32_t ISR
Definition core_cm35p.h:405
APSR_Type::@40::Z
uint32_t Z
Definition core_cm35p.h:354
xPSR_Type::@42::GE
uint32_t GE
Definition core_cm35p.h:407
xPSR_Type::@42::N
uint32_t N
Definition core_cm35p.h:415
IPSR_Type::@41::ISR
uint32_t ISR
Definition core_cm35p.h:387
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition core_armv81mml.h:4207
APSR_Type::@40::GE
uint32_t GE
Definition core_cm35p.h:349
ITM_SendChar
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
ITM Send Character.
Definition core_armv81mml.h:4186
xPSR_Type::@42::IT
uint32_t IT
Definition core_cm35p.h:410
CONTROL_Type::@43::_reserved1
uint32_t _reserved1
Definition core_cm35p.h:460
CONTROL_Type::@43::FPCA
uint32_t FPCA
Definition core_cm35p.h:458
xPSR_Type::@42::C
uint32_t C
Definition core_cm35p.h:413
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition core_armv81mml.h:4227
xPSR_Type::@42::_reserved1
uint32_t _reserved1
Definition core_cm35p.h:408
APSR_Type::@40::Q
uint32_t Q
Definition core_cm35p.h:351
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition core_armv81mml.h:2647
DCB_Type
Structure type to access the Debug Control Block Registers (DCB).
Definition core_armv81mml.h:2818
DIB_Type
Structure type to access the Debug Identification Block Registers (DIB).
Definition core_armv81mml.h:3009
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition core_armv81mml.h:1203
FPU_Type
Structure type to access the Floating Point Unit (FPU).
Definition core_armv81mml.h:2506
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition core_armv81mml.h:1102
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition core_armv81mml.h:499
SCB_Type
Structure type to access the System Control Block (SCB).
Definition core_armv81mml.h:535
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition core_armv81mml.h:1025
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition core_armv81mml.h:1050
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition core_armv81mml.h:1389
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition core_armv81mml.h:352
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition core_armv81mml.h:460
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition core_armv81mml.h:391
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition core_armv81mml.h:409
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