Functions that access the ITM debug interface. More...
Detailed Description
Functions that access the ITM debug interface.
Macro Definition Documentation
◆ ITM_RXBUFFER_EMPTY [1/15]
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 4175 of file core_armv81mml.h.
◆ ITM_RXBUFFER_EMPTY [2/15]
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 3156 of file core_armv8mml.h.
◆ ITM_RXBUFFER_EMPTY [3/15]
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 1901 of file core_cm3.h.
◆ ITM_RXBUFFER_EMPTY [4/15]
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 3224 of file core_cm33.h.
◆ ITM_RXBUFFER_EMPTY [5/15]
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 3224 of file core_cm35p.h.
◆ ITM_RXBUFFER_EMPTY [6/15]
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 2094 of file core_cm4.h.
◆ ITM_RXBUFFER_EMPTY [7/15]
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 4835 of file core_cm55.h.
◆ ITM_RXBUFFER_EMPTY [8/15]
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 2331 of file core_cm7.h.
◆ ITM_RXBUFFER_EMPTY [9/15]
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 4701 of file core_cm85.h.
◆ ITM_RXBUFFER_EMPTY [10/15]
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 1875 of file core_sc300.h.
◆ ITM_RXBUFFER_EMPTY [11/15]
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 3539 of file core_starmc1.h.
◆ ITM_RXBUFFER_EMPTY [12/15]
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 4175 of file core_armv81mml.h.
◆ ITM_RXBUFFER_EMPTY [13/15]
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 3156 of file core_armv8mml.h.
◆ ITM_RXBUFFER_EMPTY [14/15]
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 3224 of file core_cm33.h.
◆ ITM_RXBUFFER_EMPTY [15/15]
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
Definition at line 2094 of file core_cm4.h.
Function Documentation
◆ ITM_CheckChar()
| __STATIC_INLINE int32_t ITM_CheckChar | ( | void | ) |
ITM Check Character.
Checks whether a character is pending for reading in the variable ITM_RxBuffer.
- Returns
- 0 No character available.
- 1 Character available.
Definition at line 4227 of file core_armv81mml.h.
◆ ITM_ReceiveChar()
| __STATIC_INLINE int32_t ITM_ReceiveChar | ( | void | ) |
ITM Receive Character.
Inputs a character via the external variable ITM_RxBuffer.
- Returns
- Received character.
- -1 No character pending.
Definition at line 4207 of file core_armv81mml.h.
◆ ITM_SendChar()
| __STATIC_INLINE uint32_t ITM_SendChar | ( | uint32_t | ch | ) |
ITM Send Character.
Transmits a character via the ITM channel 0, and
- Just returns when no debugger is connected that has booked the output.
- Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
- Parameters
-
[in] ch Character to transmit.
- Returns
- Character to transmit.
Definition at line 4186 of file core_armv81mml.h.
Variable Documentation
◆ [] [1/45]
| uint32_t { ... } ::_reserved0 |
bit: 0..15 Reserved
Definition at line 355 of file core_armv81mml.h.
◆ [] [2/45]
| uint32_t { ... } ::_reserved0 |
bit: 0..15 Reserved
Definition at line 348 of file core_cm33.h.
◆ [] [3/45]
| uint32_t { ... } ::_reserved0 |
bit: 0..15 Reserved
Definition at line 280 of file core_cm4.h.
◆ [] [4/45]
| uint32_t { ... } ::_reserved0 |
bit: 0..26 Reserved
Definition at line 220 of file core_cm3.h.
◆ [] [5/45]
| uint32_t { ... } ::_reserved0 |
bit: 0..15 Reserved
Definition at line 348 of file core_cm33.h.
◆ [] [6/45]
| uint32_t { ... } ::_reserved0 |
bit: 0..15 Reserved
Definition at line 348 of file core_cm35p.h.
◆ [] [7/45]
| uint32_t { ... } ::_reserved0 |
bit: 0..15 Reserved
Definition at line 280 of file core_cm4.h.
◆ [] [8/45]
| uint32_t { ... } ::_reserved0 |
bit: 0..15 Reserved
Definition at line 358 of file core_cm55.h.
◆ [] [9/45]
| uint32_t { ... } ::_reserved0 |
bit: 0..15 Reserved
Definition at line 295 of file core_cm7.h.
◆ [] [10/45]
| uint32_t { ... } ::_reserved0 |
bit: 0..15 Reserved
Definition at line 354 of file core_cm85.h.
◆ [] [11/45]
| uint32_t { ... } ::_reserved0 |
bit: 0..26 Reserved
Definition at line 220 of file core_sc300.h.
◆ [] [12/45]
| uint32_t { ... } ::_reserved0 |
bit: 0..15 Reserved
Definition at line 354 of file core_starmc1.h.
◆ [] [13/45]
| uint32_t { ... } ::_reserved0 |
bit: 0..15 Reserved
Definition at line 355 of file core_armv81mml.h.
◆ _reserved0 [14/45]
| uint32_t APSR_Type::_reserved0 |
bit: 0..15 Reserved
bit: 0..27 Reserved
bit: 0..26 Reserved
Definition at line 355 of file core_armv81mml.h.
◆ [] [15/45]
| uint32_t { ... } ::_reserved0 |
bit: 3..31 Reserved
Definition at line 395 of file core_cm4.h.
◆ [] [16/45]
| uint32_t { ... } ::_reserved0 |
bit: 3..31 Reserved
Definition at line 395 of file core_cm4.h.
◆ [] [17/45]
| uint32_t { ... } ::_reserved0 |
bit: 3..31 Reserved
Definition at line 410 of file core_cm7.h.
◆ [] [18/45]
| uint32_t { ... } ::_reserved0 |
bit: 9..31 Reserved
Definition at line 388 of file core_cm33.h.
◆ [] [19/45]
| uint32_t { ... } ::_reserved0 |
bit: 9..31 Reserved
Definition at line 320 of file core_cm4.h.
◆ [] [20/45]
| uint32_t { ... } ::_reserved0 |
bit: 9..31 Reserved
Definition at line 395 of file core_armv81mml.h.
◆ [] [21/45]
| uint32_t { ... } ::_reserved0 |
bit: 9..31 Reserved
Definition at line 255 of file core_cm3.h.
◆ [] [22/45]
| uint32_t { ... } ::_reserved0 |
bit: 9..31 Reserved
Definition at line 388 of file core_cm33.h.
◆ [] [23/45]
| uint32_t { ... } ::_reserved0 |
bit: 9..31 Reserved
Definition at line 388 of file core_cm35p.h.
◆ [] [24/45]
| uint32_t { ... } ::_reserved0 |
bit: 9..31 Reserved
Definition at line 320 of file core_cm4.h.
◆ [] [25/45]
| uint32_t { ... } ::_reserved0 |
bit: 9..31 Reserved
Definition at line 398 of file core_cm55.h.
◆ [] [26/45]
| uint32_t { ... } ::_reserved0 |
bit: 9..31 Reserved
Definition at line 335 of file core_cm7.h.
◆ [] [27/45]
| uint32_t { ... } ::_reserved0 |
bit: 9..31 Reserved
Definition at line 394 of file core_cm85.h.
◆ [] [28/45]
| uint32_t { ... } ::_reserved0 |
bit: 9..31 Reserved
Definition at line 255 of file core_sc300.h.
◆ [] [29/45]
| uint32_t { ... } ::_reserved0 |
bit: 9..31 Reserved
Definition at line 394 of file core_starmc1.h.
◆ [] [30/45]
| uint32_t { ... } ::_reserved0 |
bit: 9..31 Reserved
Definition at line 395 of file core_armv81mml.h.
◆ _reserved0 [31/45]
| uint32_t IPSR_Type::_reserved0 |
bit: 9..31 Reserved
Definition at line 395 of file core_armv81mml.h.
◆ [] [32/45]
| uint32_t { ... } ::_reserved0 |
bit: 9..15 Reserved
Definition at line 406 of file core_cm33.h.
◆ [] [33/45]
| uint32_t { ... } ::_reserved0 |
bit: 9 Reserved
Definition at line 338 of file core_cm4.h.
◆ [] [34/45]
| uint32_t { ... } ::_reserved0 |
bit: 9..15 Reserved
Definition at line 413 of file core_armv81mml.h.
◆ [] [35/45]
| uint32_t { ... } ::_reserved0 |
bit: 9 Reserved
Definition at line 273 of file core_cm3.h.
◆ [] [36/45]
| uint32_t { ... } ::_reserved0 |
bit: 9..15 Reserved
Definition at line 406 of file core_cm33.h.
◆ [] [37/45]
| uint32_t { ... } ::_reserved0 |
bit: 9..15 Reserved
Definition at line 406 of file core_cm35p.h.
◆ [] [38/45]
| uint32_t { ... } ::_reserved0 |
bit: 9 Reserved
Definition at line 338 of file core_cm4.h.
◆ [] [39/45]
| uint32_t { ... } ::_reserved0 |
bit: 9..15 Reserved
Definition at line 416 of file core_cm55.h.
◆ [] [40/45]
| uint32_t { ... } ::_reserved0 |
bit: 9 Reserved
Definition at line 353 of file core_cm7.h.
◆ [] [41/45]
| uint32_t { ... } ::_reserved0 |
bit: 9..15 Reserved
Definition at line 412 of file core_cm85.h.
◆ [] [42/45]
| uint32_t { ... } ::_reserved0 |
bit: 9 Reserved
Definition at line 273 of file core_sc300.h.
◆ [] [43/45]
| uint32_t { ... } ::_reserved0 |
bit: 9..15 Reserved
Definition at line 412 of file core_starmc1.h.
◆ [] [44/45]
| uint32_t { ... } ::_reserved0 |
bit: 9..15 Reserved
Definition at line 413 of file core_armv81mml.h.
◆ _reserved0 [45/45]
| uint32_t xPSR_Type::_reserved0 |
bit: 9..15 Reserved
bit: 9..23 Reserved
bit: 9 Reserved
Definition at line 413 of file core_armv81mml.h.
◆ [] [1/37]
| uint32_t { ... } ::_reserved1 |
bit: 20..26 Reserved
Definition at line 357 of file core_armv81mml.h.
◆ [] [2/37]
| uint32_t { ... } ::_reserved1 |
bit: 20..26 Reserved
Definition at line 350 of file core_cm33.h.
◆ [] [3/37]
| uint32_t { ... } ::_reserved1 |
bit: 20..26 Reserved
Definition at line 282 of file core_cm4.h.
◆ [] [4/37]
| uint32_t { ... } ::_reserved1 |
bit: 20..26 Reserved
Definition at line 350 of file core_cm33.h.
◆ [] [5/37]
| uint32_t { ... } ::_reserved1 |
bit: 20..26 Reserved
Definition at line 350 of file core_cm35p.h.
◆ [] [6/37]
| uint32_t { ... } ::_reserved1 |
bit: 20..26 Reserved
Definition at line 282 of file core_cm4.h.
◆ [] [7/37]
| uint32_t { ... } ::_reserved1 |
bit: 20..26 Reserved
Definition at line 360 of file core_cm55.h.
◆ [] [8/37]
| uint32_t { ... } ::_reserved1 |
bit: 20..26 Reserved
Definition at line 297 of file core_cm7.h.
◆ [] [9/37]
| uint32_t { ... } ::_reserved1 |
bit: 20..26 Reserved
Definition at line 356 of file core_cm85.h.
◆ [] [10/37]
| uint32_t { ... } ::_reserved1 |
bit: 20..26 Reserved
Definition at line 356 of file core_starmc1.h.
◆ [] [11/37]
| uint32_t { ... } ::_reserved1 |
bit: 20..26 Reserved
Definition at line 357 of file core_armv81mml.h.
◆ _reserved1 [12/37]
| uint32_t APSR_Type::_reserved1 |
bit: 20..26 Reserved
Definition at line 357 of file core_armv81mml.h.
◆ [] [13/37]
| uint32_t { ... } ::_reserved1 |
bit: 4..31 Reserved
Definition at line 460 of file core_cm33.h.
◆ [] [14/37]
| uint32_t { ... } ::_reserved1 |
bit: 2..31 Reserved
Definition at line 325 of file core_cm3.h.
◆ [] [15/37]
| uint32_t { ... } ::_reserved1 |
bit: 4..31 Reserved
Definition at line 460 of file core_cm33.h.
◆ [] [16/37]
| uint32_t { ... } ::_reserved1 |
bit: 4..31 Reserved
Definition at line 467 of file core_armv81mml.h.
◆ [] [17/37]
| uint32_t { ... } ::_reserved1 |
bit: 4..31 Reserved
Definition at line 460 of file core_cm35p.h.
◆ [] [18/37]
| uint32_t { ... } ::_reserved1 |
bit: 4..31 Reserved
Definition at line 470 of file core_cm55.h.
◆ [] [19/37]
| uint32_t { ... } ::_reserved1 |
bit: 8..31 Reserved
Definition at line 475 of file core_cm85.h.
◆ [] [20/37]
| uint32_t { ... } ::_reserved1 |
bit: 2..31 Reserved
Definition at line 325 of file core_sc300.h.
◆ [] [21/37]
| uint32_t { ... } ::_reserved1 |
bit: 4..31 Reserved
Definition at line 466 of file core_starmc1.h.
◆ [] [22/37]
| uint32_t { ... } ::_reserved1 |
bit: 4..31 Reserved
Definition at line 467 of file core_armv81mml.h.
◆ _reserved1 [23/37]
| uint32_t CONTROL_Type::_reserved1 |
bit: 4..31 Reserved
bit: 2..31 Reserved
bit: 8..31 Reserved
Definition at line 467 of file core_armv81mml.h.
◆ [] [24/37]
| uint32_t { ... } ::_reserved1 |
bit: 20..23 Reserved
Definition at line 408 of file core_cm33.h.
◆ [] [25/37]
| uint32_t { ... } ::_reserved1 |
bit: 20..23 Reserved
Definition at line 341 of file core_cm4.h.
◆ [] [26/37]
| uint32_t { ... } ::_reserved1 |
bit: 20..23 Reserved
Definition at line 415 of file core_armv81mml.h.
◆ [] [27/37]
| uint32_t { ... } ::_reserved1 |
bit: 16..23 Reserved
Definition at line 275 of file core_cm3.h.
◆ [] [28/37]
| uint32_t { ... } ::_reserved1 |
bit: 20..23 Reserved
Definition at line 408 of file core_cm33.h.
◆ [] [29/37]
| uint32_t { ... } ::_reserved1 |
bit: 20..23 Reserved
Definition at line 408 of file core_cm35p.h.
◆ [] [30/37]
| uint32_t { ... } ::_reserved1 |
bit: 20..23 Reserved
Definition at line 341 of file core_cm4.h.
◆ [] [31/37]
| uint32_t { ... } ::_reserved1 |
bit: 20..23 Reserved
Definition at line 418 of file core_cm55.h.
◆ [] [32/37]
| uint32_t { ... } ::_reserved1 |
bit: 20..23 Reserved
Definition at line 356 of file core_cm7.h.
◆ [] [33/37]
| uint32_t { ... } ::_reserved1 |
bit: 20 Reserved
Definition at line 414 of file core_cm85.h.
◆ [] [34/37]
| uint32_t { ... } ::_reserved1 |
bit: 16..23 Reserved
Definition at line 275 of file core_sc300.h.
◆ [] [35/37]
| uint32_t { ... } ::_reserved1 |
bit: 20..23 Reserved
Definition at line 414 of file core_starmc1.h.
◆ [] [36/37]
| uint32_t { ... } ::_reserved1 |
bit: 20..23 Reserved
Definition at line 415 of file core_armv81mml.h.
◆ _reserved1 [37/37]
| uint32_t xPSR_Type::_reserved1 |
bit: 20..23 Reserved
bit: 25..27 Reserved
bit: 16..23 Reserved
bit: 20 Reserved
Definition at line 415 of file core_armv81mml.h.
◆ [] [1/2]
| uint32_t { ... } ::_reserved2 |
bit: 22..23 Reserved
Definition at line 416 of file core_cm85.h.
◆ _reserved2 [2/2]
| uint32_t xPSR_Type::_reserved2 |
bit: 22..23 Reserved
Definition at line 416 of file core_cm85.h.
◆ ABFSR
| __IOM uint32_t SCB_Type::ABFSR |
Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register
Definition at line 524 of file core_cm7.h.
◆ ACPR
| __IOM uint32_t TPI_Type::ACPR |
Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register
Definition at line 1393 of file core_armv81mml.h.
◆ ACTLR [1/2]
| __IOM uint32_t ICB_Type::ACTLR |
Offset: 0x008 (R/W) Auxiliary Control Register
Definition at line 1031 of file core_cm55.h.
◆ ACTLR [2/2]
| __IOM uint32_t SCnSCB_Type::ACTLR |
Offset: 0x008 (R/W) Auxiliary Control Register
Definition at line 1028 of file core_armv81mml.h.
◆ ADR
| __IM uint32_t SCB_Type::ADR |
Offset: 0x04C (R/ ) Auxiliary Feature Register
Definition at line 402 of file core_cm3.h.
◆ AFSR
| __IOM uint32_t SCB_Type::AFSR |
Offset: 0x03C (R/W) Auxiliary Fault Status Register
Definition at line 549 of file core_armv81mml.h.
◆ AHBPCR
| __IOM uint32_t SCB_Type::AHBPCR |
Offset: 0x298 (R/W) AHBP Control Register
Definition at line 520 of file core_cm7.h.
◆ AHBSCR
| __IOM uint32_t SCB_Type::AHBSCR |
Offset: 0x2A0 (R/W) AHB Slave Control Register
Definition at line 522 of file core_cm7.h.
◆ AIRCR
| __IOM uint32_t SCB_Type::AIRCR |
Offset: 0x00C (R/W) Application Interrupt and Reset Control Register
Definition at line 539 of file core_armv81mml.h.
◆ [] [1/2]
| uint32_t { ... } ::B |
bit: 21 BTI active (read 0)
Definition at line 415 of file core_cm85.h.
◆ B [2/2]
| uint32_t xPSR_Type::B |
bit: 21 BTI active (read 0)
Definition at line 415 of file core_cm85.h.
◆ [struct] [1/52]
| struct { ... } APSR_Type::b |
Structure used for bit access
◆ [struct] [2/52]
| struct { ... } APSR_Type::b |
Structure used for bit access
◆ [struct] [3/52]
| struct { ... } APSR_Type::b |
Structure used for bit access
◆ [struct] [4/52]
| struct { ... } APSR_Type::b |
Structure used for bit access
◆ [struct] [5/52]
| struct { ... } APSR_Type::b |
Structure used for bit access
◆ [struct] [6/52]
| struct { ... } APSR_Type::b |
Structure used for bit access
◆ [struct] [7/52]
| struct { ... } APSR_Type::b |
Structure used for bit access
◆ [struct] [8/52]
| struct { ... } APSR_Type::b |
Structure used for bit access
◆ [struct] [9/52]
| struct { ... } APSR_Type::b |
Structure used for bit access
◆ [struct] [10/52]
| struct { ... } APSR_Type::b |
Structure used for bit access
◆ [struct] [11/52]
| struct { ... } APSR_Type::b |
Structure used for bit access
◆ [struct] [12/52]
| struct { ... } APSR_Type::b |
Structure used for bit access
◆ [struct] [13/52]
| struct { ... } APSR_Type::b |
Structure used for bit access
◆ [struct] [14/52]
| struct { ... } CONTROL_Type::b |
Structure used for bit access
◆ [struct] [15/52]
| struct { ... } CONTROL_Type::b |
Structure used for bit access
◆ [struct] [16/52]
| struct { ... } CONTROL_Type::b |
Structure used for bit access
◆ [struct] [17/52]
| struct { ... } CONTROL_Type::b |
Structure used for bit access
◆ [struct] [18/52]
| struct { ... } CONTROL_Type::b |
Structure used for bit access
◆ [struct] [19/52]
| struct { ... } CONTROL_Type::b |
Structure used for bit access
◆ [struct] [20/52]
| struct { ... } CONTROL_Type::b |
Structure used for bit access
◆ [struct] [21/52]
| struct { ... } CONTROL_Type::b |
Structure used for bit access
◆ [struct] [22/52]
| struct { ... } CONTROL_Type::b |
Structure used for bit access
◆ [struct] [23/52]
| struct { ... } CONTROL_Type::b |
Structure used for bit access
◆ [struct] [24/52]
| struct { ... } CONTROL_Type::b |
Structure used for bit access
◆ [struct] [25/52]
| struct { ... } CONTROL_Type::b |
Structure used for bit access
◆ [struct] [26/52]
| struct { ... } CONTROL_Type::b |
Structure used for bit access
◆ [struct] [27/52]
| struct { ... } IPSR_Type::b |
Structure used for bit access
◆ [struct] [28/52]
| struct { ... } IPSR_Type::b |
Structure used for bit access
◆ [struct] [29/52]
| struct { ... } IPSR_Type::b |
Structure used for bit access
◆ [struct] [30/52]
| struct { ... } IPSR_Type::b |
Structure used for bit access
◆ [struct] [31/52]
| struct { ... } IPSR_Type::b |
Structure used for bit access
◆ [struct] [32/52]
| struct { ... } IPSR_Type::b |
Structure used for bit access
◆ [struct] [33/52]
| struct { ... } IPSR_Type::b |
Structure used for bit access
◆ [struct] [34/52]
| struct { ... } IPSR_Type::b |
Structure used for bit access
◆ [struct] [35/52]
| struct { ... } IPSR_Type::b |
Structure used for bit access
◆ [struct] [36/52]
| struct { ... } IPSR_Type::b |
Structure used for bit access
◆ [struct] [37/52]
| struct { ... } IPSR_Type::b |
Structure used for bit access
◆ [struct] [38/52]
| struct { ... } IPSR_Type::b |
Structure used for bit access
◆ [struct] [39/52]
| struct { ... } IPSR_Type::b |
Structure used for bit access
◆ [struct] [40/52]
| struct { ... } xPSR_Type::b |
Structure used for bit access
◆ [struct] [41/52]
| struct { ... } xPSR_Type::b |
Structure used for bit access
◆ [struct] [42/52]
| struct { ... } xPSR_Type::b |
Structure used for bit access
◆ [struct] [43/52]
| struct { ... } xPSR_Type::b |
Structure used for bit access
◆ [struct] [44/52]
| struct { ... } xPSR_Type::b |
Structure used for bit access
◆ [struct] [45/52]
| struct { ... } xPSR_Type::b |
Structure used for bit access
◆ [struct] [46/52]
| struct { ... } xPSR_Type::b |
Structure used for bit access
◆ [struct] [47/52]
| struct { ... } xPSR_Type::b |
Structure used for bit access
◆ [struct] [48/52]
| struct { ... } xPSR_Type::b |
Structure used for bit access
◆ [struct] [49/52]
| struct { ... } xPSR_Type::b |
Structure used for bit access
◆ [struct] [50/52]
| struct { ... } xPSR_Type::b |
Structure used for bit access
◆ [struct] [51/52]
| struct { ... } xPSR_Type::b |
Structure used for bit access
◆ [struct] [52/52]
| struct { ... } xPSR_Type::b |
Structure used for bit access
◆ BFAR
| __IOM uint32_t SCB_Type::BFAR |
Offset: 0x038 (R/W) BusFault Address Register
Definition at line 548 of file core_armv81mml.h.
◆ BPIALL
| __OM uint32_t SCB_Type::BPIALL |
Offset: 0x278 ( /W) Branch Predictor Invalidate All
Definition at line 582 of file core_armv81mml.h.
◆ [] [1/2]
| uint32_t { ... } ::BTI_EN |
bit: 4 Privileged branch target identification enable
Definition at line 471 of file core_cm85.h.
◆ BTI_EN [2/2]
| uint32_t CONTROL_Type::BTI_EN |
bit: 4 Privileged branch target identification enable
Definition at line 471 of file core_cm85.h.
◆ [] [1/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 360 of file core_armv81mml.h.
◆ [] [2/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 353 of file core_cm33.h.
◆ [] [3/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 285 of file core_cm4.h.
◆ [] [4/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 223 of file core_cm3.h.
◆ [] [5/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 353 of file core_cm33.h.
◆ [] [6/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 353 of file core_cm35p.h.
◆ [] [7/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 285 of file core_cm4.h.
◆ [] [8/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 363 of file core_cm55.h.
◆ [] [9/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 300 of file core_cm7.h.
◆ [] [10/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 359 of file core_cm85.h.
◆ [] [11/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 223 of file core_sc300.h.
◆ [] [12/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 359 of file core_starmc1.h.
◆ [] [13/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 360 of file core_armv81mml.h.
◆ C [14/28]
| uint32_t APSR_Type::C |
bit: 29 Carry condition code flag
Definition at line 360 of file core_armv81mml.h.
◆ [] [15/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 413 of file core_cm33.h.
◆ [] [16/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 346 of file core_cm4.h.
◆ [] [17/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 420 of file core_armv81mml.h.
◆ [] [18/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 280 of file core_cm3.h.
◆ [] [19/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 413 of file core_cm33.h.
◆ [] [20/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 413 of file core_cm35p.h.
◆ [] [21/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 346 of file core_cm4.h.
◆ [] [22/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 423 of file core_cm55.h.
◆ [] [23/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 361 of file core_cm7.h.
◆ [] [24/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 421 of file core_cm85.h.
◆ [] [25/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 280 of file core_sc300.h.
◆ [] [26/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 419 of file core_starmc1.h.
◆ [] [27/28]
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
Definition at line 420 of file core_armv81mml.h.
◆ C [28/28]
| uint32_t xPSR_Type::C |
bit: 29 Carry condition code flag
Definition at line 420 of file core_armv81mml.h.
◆ CACR [1/2]
| __IOM uint32_t EMSS_Type::CACR |
Offset: 0x0 (R/W) L1 Cache Control Register
Definition at line 585 of file core_starmc1.h.
◆ CACR [2/2]
| __IOM uint32_t SCB_Type::CACR |
Offset: 0x29C (R/W) L1 Cache Control Register
Definition at line 521 of file core_cm7.h.
◆ CALIB
| __IM uint32_t SysTick_Type::CALIB |
Offset: 0x00C (R/ ) SysTick Calibration Register
Definition at line 1054 of file core_armv81mml.h.
◆ CCR
| __IOM uint32_t SCB_Type::CCR |
Offset: 0x014 (R/W) Configuration Control Register
Definition at line 541 of file core_armv81mml.h.
◆ CCSIDR
| __IM uint32_t SCB_Type::CCSIDR |
Offset: 0x080 (R/ ) Cache Size ID Register
Definition at line 557 of file core_armv81mml.h.
◆ CFGINFORD
| __IM uint32_t PrcCfgInf_Type::CFGINFORD |
Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register
Definition at line 1839 of file core_cm55.h.
◆ CFGINFOSEL
| __OM uint32_t PrcCfgInf_Type::CFGINFOSEL |
Offset: 0x000 ( /W) Processor Configuration Information Selection Register
Definition at line 1838 of file core_cm55.h.
◆ CFSR
| __IOM uint32_t SCB_Type::CFSR |
Offset: 0x028 (R/W) Configurable Fault Status Register
Definition at line 544 of file core_armv81mml.h.
◆ CID0
| __IM uint32_t ITM_Type::CID0 |
Offset: 0xFF0 (R/ ) ITM Component Identification Register #0
Definition at line 1131 of file core_armv81mml.h.
◆ CID1
| __IM uint32_t ITM_Type::CID1 |
Offset: 0xFF4 (R/ ) ITM Component Identification Register #1
Definition at line 1132 of file core_armv81mml.h.
◆ CID2
| __IM uint32_t ITM_Type::CID2 |
Offset: 0xFF8 (R/ ) ITM Component Identification Register #2
Definition at line 1133 of file core_armv81mml.h.
◆ CID3
| __IM uint32_t ITM_Type::CID3 |
Offset: 0xFFC (R/ ) ITM Component Identification Register #3
Definition at line 1134 of file core_armv81mml.h.
◆ CLIDR
| __IM uint32_t SCB_Type::CLIDR |
Offset: 0x078 (R/ ) Cache Level ID register
Definition at line 555 of file core_armv81mml.h.
◆ COMP0
| __IOM uint32_t DWT_Type::COMP0 |
Offset: 0x020 (R/W) Comparator Register 0
Definition at line 1212 of file core_armv81mml.h.
◆ COMP1
| __IOM uint32_t DWT_Type::COMP1 |
Offset: 0x030 (R/W) Comparator Register 1
Definition at line 1216 of file core_armv81mml.h.
◆ COMP10
| __IOM uint32_t DWT_Type::COMP10 |
Offset: 0x0C0 (R/W) Comparator Register 10
Definition at line 1252 of file core_armv81mml.h.
◆ COMP11
| __IOM uint32_t DWT_Type::COMP11 |
Offset: 0x0D0 (R/W) Comparator Register 11
Definition at line 1256 of file core_armv81mml.h.
◆ COMP12
| __IOM uint32_t DWT_Type::COMP12 |
Offset: 0x0E0 (R/W) Comparator Register 12
Definition at line 1260 of file core_armv81mml.h.
◆ COMP13
| __IOM uint32_t DWT_Type::COMP13 |
Offset: 0x0F0 (R/W) Comparator Register 13
Definition at line 1264 of file core_armv81mml.h.
◆ COMP14
| __IOM uint32_t DWT_Type::COMP14 |
Offset: 0x100 (R/W) Comparator Register 14
Definition at line 1268 of file core_armv81mml.h.
◆ COMP15
| __IOM uint32_t DWT_Type::COMP15 |
Offset: 0x110 (R/W) Comparator Register 15
Definition at line 1272 of file core_armv81mml.h.
◆ COMP2
| __IOM uint32_t DWT_Type::COMP2 |
Offset: 0x040 (R/W) Comparator Register 2
Definition at line 1220 of file core_armv81mml.h.
◆ COMP3
| __IOM uint32_t DWT_Type::COMP3 |
Offset: 0x050 (R/W) Comparator Register 3
Definition at line 1224 of file core_armv81mml.h.
◆ COMP4
| __IOM uint32_t DWT_Type::COMP4 |
Offset: 0x060 (R/W) Comparator Register 4
Definition at line 1228 of file core_armv81mml.h.
◆ COMP5
| __IOM uint32_t DWT_Type::COMP5 |
Offset: 0x070 (R/W) Comparator Register 5
Definition at line 1232 of file core_armv81mml.h.
◆ COMP6
| __IOM uint32_t DWT_Type::COMP6 |
Offset: 0x080 (R/W) Comparator Register 6
Definition at line 1236 of file core_armv81mml.h.
◆ COMP7
| __IOM uint32_t DWT_Type::COMP7 |
Offset: 0x090 (R/W) Comparator Register 7
Definition at line 1240 of file core_armv81mml.h.
◆ COMP8
| __IOM uint32_t DWT_Type::COMP8 |
Offset: 0x0A0 (R/W) Comparator Register 8
Definition at line 1244 of file core_armv81mml.h.
◆ COMP9
| __IOM uint32_t DWT_Type::COMP9 |
Offset: 0x0B0 (R/W) Comparator Register 9
Definition at line 1248 of file core_armv81mml.h.
◆ CPACR
| __IOM uint32_t SCB_Type::CPACR |
Offset: 0x088 (R/W) Coprocessor Access Control Register
Definition at line 559 of file core_armv81mml.h.
◆ CPDLPSTATE
| __IOM uint32_t PwrModCtl_Type::CPDLPSTATE |
Offset: 0x000 (R/W) Core Power Domain Low Power State Register
Definition at line 1541 of file core_cm55.h.
◆ CPICNT
| __IOM uint32_t DWT_Type::CPICNT |
Offset: 0x008 (R/W) CPI Count Register
Definition at line 1206 of file core_armv81mml.h.
◆ CPPWR [1/2]
| __IOM uint32_t ICB_Type::CPPWR |
Offset: 0x00C (R/W) Coprocessor Power Control Register
Definition at line 1032 of file core_cm55.h.
◆ CPPWR [2/2]
| __IOM uint32_t SCnSCB_Type::CPPWR |
Offset: 0x00C (R/W) Coprocessor Power Control Register
Definition at line 1029 of file core_armv81mml.h.
◆ CPUID
| __IM uint32_t SCB_Type::CPUID |
Offset: 0x000 (R/ ) CPUID Base Register
Definition at line 536 of file core_armv81mml.h.
◆ CSPSR
| __IOM uint32_t TPI_Type::CSPSR |
Offset: 0x004 (R/W) Current Parallel Port Sizes Register
Offset: 0x004 (R/W) Current Parallel Port Size Register
Definition at line 1391 of file core_armv81mml.h.
◆ CSSELR
| __IOM uint32_t SCB_Type::CSSELR |
Offset: 0x084 (R/W) Cache Size Selection Register
Definition at line 558 of file core_armv81mml.h.
◆ CTR
| __IM uint32_t SCB_Type::CTR |
Offset: 0x07C (R/ ) Cache Type register
Definition at line 556 of file core_armv81mml.h.
◆ CTRL [1/2]
| __IOM uint32_t DWT_Type::CTRL |
Offset: 0x000 (R/W) Control Register
Definition at line 1204 of file core_armv81mml.h.
◆ CTRL [2/2]
| __IOM uint32_t SysTick_Type::CTRL |
Offset: 0x000 (R/W) SysTick Control and Status Register
Definition at line 1051 of file core_armv81mml.h.
◆ CYCCNT
| __IOM uint32_t DWT_Type::CYCCNT |
Offset: 0x004 (R/W) Cycle Count Register
Definition at line 1205 of file core_armv81mml.h.
◆ DAUTHCTRL [1/2]
| __IOM uint32_t CoreDebug_Type::DAUTHCTRL |
Offset: 0x014 (R/W) Debug Authentication Control Register
Definition at line 2653 of file core_armv81mml.h.
◆ DAUTHCTRL [2/2]
| __IOM uint32_t DCB_Type::DAUTHCTRL |
Offset: 0x014 (R/W) Debug Authentication Control Register
Definition at line 2824 of file core_armv81mml.h.
◆ DAUTHSTATUS
| __IM uint32_t DIB_Type::DAUTHSTATUS |
Offset: 0x008 (R/ ) Debug Authentication Status Register
Definition at line 3012 of file core_armv81mml.h.
◆ DCCIMVAC
| __OM uint32_t SCB_Type::DCCIMVAC |
Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC
Definition at line 580 of file core_armv81mml.h.
◆ DCCISW
| __OM uint32_t SCB_Type::DCCISW |
Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way
Definition at line 581 of file core_armv81mml.h.
◆ DCCMVAC
| __OM uint32_t SCB_Type::DCCMVAC |
Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC
Definition at line 578 of file core_armv81mml.h.
◆ DCCMVAU
| __OM uint32_t SCB_Type::DCCMVAU |
Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU
Definition at line 577 of file core_armv81mml.h.
◆ DCCSW
| __OM uint32_t SCB_Type::DCCSW |
Offset: 0x26C ( /W) D-Cache Clean by Set-way
Definition at line 579 of file core_armv81mml.h.
◆ DCIMVAC
| __OM uint32_t SCB_Type::DCIMVAC |
Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC
Definition at line 575 of file core_armv81mml.h.
◆ DCISW
| __OM uint32_t SCB_Type::DCISW |
Offset: 0x260 ( /W) D-Cache Invalidate by Set-way
Definition at line 576 of file core_armv81mml.h.
◆ DCRDR [1/2]
| __IOM uint32_t CoreDebug_Type::DCRDR |
Offset: 0x008 (R/W) Debug Core Register Data Register
Definition at line 2650 of file core_armv81mml.h.
◆ DCRDR [2/2]
| __IOM uint32_t DCB_Type::DCRDR |
Offset: 0x008 (R/W) Debug Core Register Data Register
Definition at line 2821 of file core_armv81mml.h.
◆ DCRSR [1/2]
| __OM uint32_t CoreDebug_Type::DCRSR |
Offset: 0x004 ( /W) Debug Core Register Selector Register
Definition at line 2649 of file core_armv81mml.h.
◆ DCRSR [2/2]
| __OM uint32_t DCB_Type::DCRSR |
Offset: 0x004 ( /W) Debug Core Register Selector Register
Definition at line 2820 of file core_armv81mml.h.
◆ DDEVARCH
| __IM uint32_t DIB_Type::DDEVARCH |
Offset: 0x00C (R/ ) SCS Device Architecture Register
Definition at line 3013 of file core_armv81mml.h.
◆ DDEVTYPE
| __IM uint32_t DIB_Type::DDEVTYPE |
Offset: 0x010 (R/ ) SCS Device Type Register
Offset: 0x01C (R/ ) SCS Device Type Register
Definition at line 3014 of file core_armv81mml.h.
◆ DEBR0
| __IOM uint32_t ErrBnk_Type::DEBR0 |
Offset: 0x010 (R/W) Data Cache Error Bank Register 0
Definition at line 1701 of file core_cm55.h.
◆ DEBR1
| __IOM uint32_t ErrBnk_Type::DEBR1 |
Offset: 0x014 (R/W) Data Cache Error Bank Register 1
Definition at line 1702 of file core_cm55.h.
◆ DEMCR [1/2]
| __IOM uint32_t CoreDebug_Type::DEMCR |
Offset: 0x00C (R/W) Debug Exception and Monitor Control Register
Definition at line 2651 of file core_armv81mml.h.
◆ DEMCR [2/2]
| __IOM uint32_t DCB_Type::DEMCR |
Offset: 0x00C (R/W) Debug Exception and Monitor Control Register
Definition at line 2822 of file core_armv81mml.h.
◆ DEVARCH [1/2]
| __IM uint32_t DWT_Type::DEVARCH |
Offset: 0xFBC (R/ ) Device Architecture Register
Offset: 0xFBC (R/ ) Device Type Architecture Register
Definition at line 1278 of file core_armv81mml.h.
◆ DEVARCH [2/2]
| __IM uint32_t ITM_Type::DEVARCH |
Offset: 0xFBC (R/ ) ITM Device Architecture Register
Definition at line 1120 of file core_armv81mml.h.
◆ DEVTYPE [1/3]
| __IM uint32_t DWT_Type::DEVTYPE |
Offset: 0xFCC (R/ ) Device Type Identifier Register
Definition at line 1302 of file core_cm55.h.
◆ DEVTYPE [2/3]
| __IM uint32_t ITM_Type::DEVTYPE |
Offset: 0xFCC (R/ ) ITM Device Type Register
Definition at line 1122 of file core_armv81mml.h.
◆ DEVTYPE [3/3]
| __IM uint32_t TPI_Type::DEVTYPE |
Offset: 0xFCC (R/ ) Device Type Register
Offset: 0xFCC (R/ ) Device Type Identifier Register
Offset: 0xFCC (R/ ) TPIU_DEVTYPE
Definition at line 1405 of file core_armv81mml.h.
◆ DFR
| __IM uint32_t SCB_Type::DFR |
Offset: 0x048 (R/ ) Debug Feature Register
Definition at line 401 of file core_cm3.h.
◆ DFSR
| __IOM uint32_t SCB_Type::DFSR |
Offset: 0x030 (R/W) Debug Fault Status Register
Definition at line 546 of file core_armv81mml.h.
◆ DHCSR [1/2]
| __IOM uint32_t CoreDebug_Type::DHCSR |
Offset: 0x000 (R/W) Debug Halting Control and Status Register
Definition at line 2648 of file core_armv81mml.h.
◆ DHCSR [2/2]
| __IOM uint32_t DCB_Type::DHCSR |
Offset: 0x000 (R/W) Debug Halting Control and Status Register
Definition at line 2819 of file core_armv81mml.h.
◆ DLAR
| __OM uint32_t DIB_Type::DLAR |
Offset: 0x000 ( /W) SCS Software Lock Access Register
Definition at line 3010 of file core_armv81mml.h.
◆ DLSR
| __IM uint32_t DIB_Type::DLSR |
Offset: 0x004 (R/ ) SCS Software Lock Status Register
Definition at line 3011 of file core_armv81mml.h.
◆ DPDLPSTATE
| __IOM uint32_t PwrModCtl_Type::DPDLPSTATE |
Offset: 0x004 (R/W) Debug Power Domain Low Power State Register
Definition at line 1542 of file core_cm55.h.
◆ DSCEMCR [1/2]
| __OM uint32_t CoreDebug_Type::DSCEMCR |
Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register
Definition at line 2652 of file core_armv81mml.h.
◆ DSCEMCR [2/2]
| __OM uint32_t DCB_Type::DSCEMCR |
Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register
Definition at line 2823 of file core_armv81mml.h.
◆ DSCSR [1/2]
| __IOM uint32_t CoreDebug_Type::DSCSR |
Offset: 0x018 (R/W) Debug Security Control and Status Register
Definition at line 2654 of file core_armv81mml.h.
◆ DSCSR [2/2]
| __IOM uint32_t DCB_Type::DSCSR |
Offset: 0x018 (R/W) Debug Security Control and Status Register
Definition at line 2825 of file core_armv81mml.h.
◆ DTCMCR [1/3]
| __IOM uint32_t EMSS_Type::DTCMCR |
Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers
Definition at line 587 of file core_starmc1.h.
◆ DTCMCR [2/3]
| __IOM uint32_t MemSysCtl_Type::DTCMCR |
Offset: 0x014 (R/W) DTCM Control Register
Definition at line 1418 of file core_cm55.h.
◆ DTCMCR [3/3]
| __IOM uint32_t SCB_Type::DTCMCR |
Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers
Definition at line 519 of file core_cm7.h.
◆ DTGU_CFG
| __IOM uint32_t MemSysCtl_Type::DTGU_CFG |
Offset: 0x604 (R/W) DTGU Configuration Register
Definition at line 1427 of file core_cm55.h.
◆ DTGU_CTRL
| __IOM uint32_t MemSysCtl_Type::DTGU_CTRL |
Offset: 0x600 (R/W) DTGU Control Registers
Definition at line 1426 of file core_cm55.h.
◆ DTGU_LUT
| __IOM uint32_t MemSysCtl_Type::DTGU_LUT |
Offset: 0x610 (R/W) DTGU Look Up Table Register
Definition at line 1429 of file core_cm55.h.
◆ EVENTMASKA
| __IM uint32_t EWIC_ISA_Type::EVENTMASKA |
Offset: 0x080 (R/ ) Event Mask A Register
Definition at line 1655 of file core_cm55.h.
◆ EVENTMASKn
| __IM uint32_t EWIC_ISA_Type::EVENTMASKn |
Offset: 0x084 (R/ ) Event Mask Register
Definition at line 1656 of file core_cm55.h.
◆ EVENTSPR
| __OM uint32_t EWIC_ISA_Type::EVENTSPR |
Offset: 0x000 ( /W) Event Set Pending Register
Definition at line 1653 of file core_cm55.h.
◆ EWIC_ASCR
| __IOM uint32_t EWIC_Type::EWIC_ASCR |
Offset: 0x004 (R/W) EWIC Automatic Sequence Control Register
Definition at line 1575 of file core_cm55.h.
◆ EWIC_CLRMASK
| __OM uint32_t EWIC_Type::EWIC_CLRMASK |
Offset: 0x008 ( /W) EWIC Clear Mask Register
Definition at line 1576 of file core_cm55.h.
◆ EWIC_CR
| __IOM uint32_t EWIC_Type::EWIC_CR |
Offset: 0x000 (R/W) EWIC Control Register
Definition at line 1574 of file core_cm55.h.
◆ EWIC_MASKA
| __IOM uint32_t EWIC_Type::EWIC_MASKA |
Offset: 0x200 (R/W) EWIC MaskA Register
Definition at line 1579 of file core_cm55.h.
◆ EWIC_MASKn
| __IOM uint32_t EWIC_Type::EWIC_MASKn |
Offset: 0x204 (R/W) EWIC Maskn Registers
Definition at line 1580 of file core_cm55.h.
◆ EWIC_NUMID
| __IM uint32_t EWIC_Type::EWIC_NUMID |
Offset: 0x00C (R/ ) EWIC Event Number ID Register
Definition at line 1577 of file core_cm55.h.
◆ EWIC_PENDA
| __IM uint32_t EWIC_Type::EWIC_PENDA |
Offset: 0x400 (R/ ) EWIC PendA Event Register
Definition at line 1582 of file core_cm55.h.
◆ EWIC_PENDn
| __IOM uint32_t EWIC_Type::EWIC_PENDn |
Offset: 0x404 (R/W) EWIC Pendn Event Registers
Definition at line 1583 of file core_cm55.h.
◆ EWIC_PSR
| __IM uint32_t EWIC_Type::EWIC_PSR |
Offset: 0x600 (R/ ) EWIC Pend Summary Register
Definition at line 1585 of file core_cm55.h.
◆ EXCCNT
| __IOM uint32_t DWT_Type::EXCCNT |
Offset: 0x00C (R/W) Exception Overhead Count Register
Definition at line 1207 of file core_armv81mml.h.
◆ FFCR
| __IOM uint32_t TPI_Type::FFCR |
Offset: 0x304 (R/W) Formatter and Flush Control Register
Definition at line 1398 of file core_armv81mml.h.
◆ FFSR
| __IM uint32_t TPI_Type::FFSR |
Offset: 0x300 (R/ ) Formatter and Flush Status Register
Definition at line 1397 of file core_armv81mml.h.
◆ FIFO0
| __IM uint32_t TPI_Type::FIFO0 |
Offset: 0xEEC (R/ ) Integration ETM Data
Definition at line 1012 of file core_cm3.h.
◆ FIFO1
| __IM uint32_t TPI_Type::FIFO1 |
Offset: 0xEFC (R/ ) Integration ITM Data
Definition at line 1016 of file core_cm3.h.
◆ FOLDCNT
| __IOM uint32_t DWT_Type::FOLDCNT |
Offset: 0x018 (R/W) Folded-instruction Count Register
Definition at line 1210 of file core_armv81mml.h.
◆ [] [1/12]
| uint32_t { ... } ::FPCA |
bit: 2 Floating-point context active
Definition at line 458 of file core_cm33.h.
◆ [] [2/12]
| uint32_t { ... } ::FPCA |
bit: 2 FP extension active flag
Definition at line 394 of file core_cm4.h.
◆ [] [3/12]
| uint32_t { ... } ::FPCA |
bit: 2 Floating-point context active
Definition at line 458 of file core_cm33.h.
◆ [] [4/12]
| uint32_t { ... } ::FPCA |
bit: 2 Floating-point context active
Definition at line 465 of file core_armv81mml.h.
◆ [] [5/12]
| uint32_t { ... } ::FPCA |
bit: 2 Floating-point context active
Definition at line 458 of file core_cm35p.h.
◆ [] [6/12]
| uint32_t { ... } ::FPCA |
bit: 2 FP extension active flag
Definition at line 394 of file core_cm4.h.
◆ [] [7/12]
| uint32_t { ... } ::FPCA |
bit: 2 Floating-point context active
Definition at line 468 of file core_cm55.h.
◆ [] [8/12]
| uint32_t { ... } ::FPCA |
bit: 2 FP extension active flag
Definition at line 409 of file core_cm7.h.
◆ [] [9/12]
| uint32_t { ... } ::FPCA |
bit: 2 Floating-point context active
Definition at line 469 of file core_cm85.h.
◆ [] [10/12]
| uint32_t { ... } ::FPCA |
bit: 2 Floating-point context active
Definition at line 464 of file core_starmc1.h.
◆ [] [11/12]
| uint32_t { ... } ::FPCA |
bit: 2 Floating-point context active
Definition at line 465 of file core_armv81mml.h.
◆ FPCA [12/12]
| uint32_t CONTROL_Type::FPCA |
bit: 2 Floating-point context active
bit: 2 FP extension active flag
Definition at line 465 of file core_armv81mml.h.
◆ FPCAR
| __IOM uint32_t FPU_Type::FPCAR |
Offset: 0x008 (R/W) Floating-Point Context Address Register
Definition at line 2509 of file core_armv81mml.h.
◆ FPCCR
| __IOM uint32_t FPU_Type::FPCCR |
Offset: 0x004 (R/W) Floating-Point Context Control Register
Definition at line 2508 of file core_armv81mml.h.
◆ FPDSCR
| __IOM uint32_t FPU_Type::FPDSCR |
Offset: 0x00C (R/W) Floating-Point Default Status Control Register
Definition at line 2510 of file core_armv81mml.h.
◆ FSCR
| __IM uint32_t TPI_Type::FSCR |
Offset: 0x308 (R/ ) Formatter Synchronization Counter Register
Definition at line 1009 of file core_cm3.h.
◆ FUNCTION0
| __IOM uint32_t DWT_Type::FUNCTION0 |
Offset: 0x028 (R/W) Function Register 0
Definition at line 1214 of file core_armv81mml.h.
◆ FUNCTION1
| __IOM uint32_t DWT_Type::FUNCTION1 |
Offset: 0x038 (R/W) Function Register 1
Definition at line 1218 of file core_armv81mml.h.
◆ FUNCTION10
| __IOM uint32_t DWT_Type::FUNCTION10 |
Offset: 0x0C8 (R/W) Function Register 10
Definition at line 1254 of file core_armv81mml.h.
◆ FUNCTION11
| __IOM uint32_t DWT_Type::FUNCTION11 |
Offset: 0x0D8 (R/W) Function Register 11
Definition at line 1258 of file core_armv81mml.h.
◆ FUNCTION12
| __IOM uint32_t DWT_Type::FUNCTION12 |
Offset: 0x0E8 (R/W) Function Register 12
Definition at line 1262 of file core_armv81mml.h.
◆ FUNCTION13
| __IOM uint32_t DWT_Type::FUNCTION13 |
Offset: 0x0F8 (R/W) Function Register 13
Definition at line 1266 of file core_armv81mml.h.
◆ FUNCTION14
| __IOM uint32_t DWT_Type::FUNCTION14 |
Offset: 0x108 (R/W) Function Register 14
Definition at line 1270 of file core_armv81mml.h.
◆ FUNCTION15
| __IOM uint32_t DWT_Type::FUNCTION15 |
Offset: 0x118 (R/W) Function Register 15
Definition at line 1274 of file core_armv81mml.h.
◆ FUNCTION2
| __IOM uint32_t DWT_Type::FUNCTION2 |
Offset: 0x048 (R/W) Function Register 2
Definition at line 1222 of file core_armv81mml.h.
◆ FUNCTION3
| __IOM uint32_t DWT_Type::FUNCTION3 |
Offset: 0x058 (R/W) Function Register 3
Definition at line 1226 of file core_armv81mml.h.
◆ FUNCTION4
| __IOM uint32_t DWT_Type::FUNCTION4 |
Offset: 0x068 (R/W) Function Register 4
Definition at line 1230 of file core_armv81mml.h.
◆ FUNCTION5
| __IOM uint32_t DWT_Type::FUNCTION5 |
Offset: 0x078 (R/W) Function Register 5
Definition at line 1234 of file core_armv81mml.h.
◆ FUNCTION6
| __IOM uint32_t DWT_Type::FUNCTION6 |
Offset: 0x088 (R/W) Function Register 6
Definition at line 1238 of file core_armv81mml.h.
◆ FUNCTION7
| __IOM uint32_t DWT_Type::FUNCTION7 |
Offset: 0x098 (R/W) Function Register 7
Definition at line 1242 of file core_armv81mml.h.
◆ FUNCTION8
| __IOM uint32_t DWT_Type::FUNCTION8 |
Offset: 0x0A8 (R/W) Function Register 8
Definition at line 1246 of file core_armv81mml.h.
◆ FUNCTION9
| __IOM uint32_t DWT_Type::FUNCTION9 |
Offset: 0x0B8 (R/W) Function Register 9
Definition at line 1250 of file core_armv81mml.h.
◆ [] [1/24]
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 356 of file core_armv81mml.h.
◆ [] [2/24]
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 349 of file core_cm33.h.
◆ [] [3/24]
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 281 of file core_cm4.h.
◆ [] [4/24]
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 349 of file core_cm33.h.
◆ [] [5/24]
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 349 of file core_cm35p.h.
◆ [] [6/24]
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 281 of file core_cm4.h.
◆ [] [7/24]
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 359 of file core_cm55.h.
◆ [] [8/24]
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 296 of file core_cm7.h.
◆ [] [9/24]
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 355 of file core_cm85.h.
◆ [] [10/24]
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 355 of file core_starmc1.h.
◆ [] [11/24]
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 356 of file core_armv81mml.h.
◆ GE [12/24]
| uint32_t APSR_Type::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 356 of file core_armv81mml.h.
◆ [] [13/24]
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 407 of file core_cm33.h.
◆ [] [14/24]
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 340 of file core_cm4.h.
◆ [] [15/24]
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 414 of file core_armv81mml.h.
◆ [] [16/24]
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 407 of file core_cm33.h.
◆ [] [17/24]
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 407 of file core_cm35p.h.
◆ [] [18/24]
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 340 of file core_cm4.h.
◆ [] [19/24]
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 417 of file core_cm55.h.
◆ [] [20/24]
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 355 of file core_cm7.h.
◆ [] [21/24]
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 413 of file core_cm85.h.
◆ [] [22/24]
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 413 of file core_starmc1.h.
◆ [] [23/24]
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 414 of file core_armv81mml.h.
◆ GE [24/24]
| uint32_t xPSR_Type::GE |
bit: 16..19 Greater than or Equal flags
Definition at line 414 of file core_armv81mml.h.
◆ HFSR
| __IOM uint32_t SCB_Type::HFSR |
Offset: 0x02C (R/W) HardFault Status Register
Definition at line 545 of file core_armv81mml.h.
◆ IABR
| __IOM uint32_t NVIC_Type::IABR |
Offset: 0x200 (R/W) Interrupt Active bit Register
Definition at line 508 of file core_armv81mml.h.
◆ ICER
| __IOM uint32_t NVIC_Type::ICER |
Offset: 0x080 (R/W) Interrupt Clear Enable Register
Definition at line 502 of file core_armv81mml.h.
◆ [] [1/6]
| uint32_t { ... } ::ICI_IT_1 |
bit: 10..15 ICI/IT part 1
Definition at line 339 of file core_cm4.h.
◆ [] [2/6]
| uint32_t { ... } ::ICI_IT_1 |
bit: 10..15 ICI/IT part 1
Definition at line 274 of file core_cm3.h.
◆ [] [3/6]
| uint32_t { ... } ::ICI_IT_1 |
bit: 10..15 ICI/IT part 1
Definition at line 339 of file core_cm4.h.
◆ [] [4/6]
| uint32_t { ... } ::ICI_IT_1 |
bit: 10..15 ICI/IT part 1
Definition at line 354 of file core_cm7.h.
◆ [] [5/6]
| uint32_t { ... } ::ICI_IT_1 |
bit: 10..15 ICI/IT part 1
Definition at line 274 of file core_sc300.h.
◆ ICI_IT_1 [6/6]
| uint32_t xPSR_Type::ICI_IT_1 |
bit: 10..15 ICI/IT part 1
Definition at line 274 of file core_cm3.h.
◆ [] [1/6]
| uint32_t { ... } ::ICI_IT_2 |
bit: 25..26 ICI/IT part 2
Definition at line 343 of file core_cm4.h.
◆ [] [2/6]
| uint32_t { ... } ::ICI_IT_2 |
bit: 25..26 ICI/IT part 2
Definition at line 277 of file core_cm3.h.
◆ [] [3/6]
| uint32_t { ... } ::ICI_IT_2 |
bit: 25..26 ICI/IT part 2
Definition at line 343 of file core_cm4.h.
◆ [] [4/6]
| uint32_t { ... } ::ICI_IT_2 |
bit: 25..26 ICI/IT part 2
Definition at line 358 of file core_cm7.h.
◆ [] [5/6]
| uint32_t { ... } ::ICI_IT_2 |
bit: 25..26 ICI/IT part 2
Definition at line 277 of file core_sc300.h.
◆ ICI_IT_2 [6/6]
| uint32_t xPSR_Type::ICI_IT_2 |
bit: 25..26 ICI/IT part 2
Definition at line 277 of file core_cm3.h.
◆ ICIALLU
| __OM uint32_t SCB_Type::ICIALLU |
Offset: 0x250 ( /W) I-Cache Invalidate All to PoU
Definition at line 572 of file core_armv81mml.h.
◆ ICIMVAU
| __OM uint32_t SCB_Type::ICIMVAU |
Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU
Definition at line 574 of file core_armv81mml.h.
◆ ICPR
| __IOM uint32_t NVIC_Type::ICPR |
Offset: 0x180 (R/W) Interrupt Clear Pending Register
Definition at line 506 of file core_armv81mml.h.
◆ ICSR
| __IOM uint32_t SCB_Type::ICSR |
Offset: 0x004 (R/W) Interrupt Control and State Register
Definition at line 537 of file core_armv81mml.h.
◆ ICTR [1/2]
| __IM uint32_t ICB_Type::ICTR |
Offset: 0x004 (R/ ) Interrupt Controller Type Register
Definition at line 1030 of file core_cm55.h.
◆ ICTR [2/2]
| __IM uint32_t SCnSCB_Type::ICTR |
Offset: 0x004 (R/ ) Interrupt Controller Type Register
Definition at line 1027 of file core_armv81mml.h.
◆ ID_AFR
| __IM uint32_t SCB_Type::ID_AFR |
Offset: 0x04C (R/ ) Auxiliary Feature Register
Definition at line 552 of file core_armv81mml.h.
◆ ID_DFR
| __IM uint32_t SCB_Type::ID_DFR |
Offset: 0x048 (R/ ) Debug Feature Register
Definition at line 551 of file core_armv81mml.h.
◆ ID_ISAR
| __IM uint32_t SCB_Type::ID_ISAR |
Offset: 0x060 (R/ ) Instruction Set Attributes Register
Definition at line 554 of file core_armv81mml.h.
◆ ID_MFR
| __IM uint32_t SCB_Type::ID_MFR[4U] |
Offset: 0x050 (R/ ) Memory Model Feature Register
Definition at line 491 of file core_cm7.h.
◆ ID_MMFR
| __IM uint32_t SCB_Type::ID_MMFR |
Offset: 0x050 (R/ ) Memory Model Feature Register
Definition at line 553 of file core_armv81mml.h.
◆ ID_PFR
| __IM uint32_t SCB_Type::ID_PFR |
Offset: 0x040 (R/ ) Processor Feature Register
Definition at line 550 of file core_armv81mml.h.
◆ IEBR0
| __IOM uint32_t ErrBnk_Type::IEBR0 |
Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0
Definition at line 1698 of file core_cm55.h.
◆ IEBR1
| __IOM uint32_t ErrBnk_Type::IEBR1 |
Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1
Definition at line 1699 of file core_cm55.h.
◆ IP
| __IOM uint8_t NVIC_Type::IP[240U] |
Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)
Definition at line 362 of file core_cm3.h.
◆ IPR
| __IOM uint8_t NVIC_Type::IPR |
Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)
Offset: 0x300 (R/W) Interrupt Priority Register
Definition at line 512 of file core_armv81mml.h.
◆ ISAR
| __IM uint32_t SCB_Type::ISAR |
Offset: 0x060 (R/ ) Instruction Set Attributes Register
Definition at line 404 of file core_cm3.h.
◆ ISER
| __IOM uint32_t NVIC_Type::ISER |
Offset: 0x000 (R/W) Interrupt Set Enable Register
Definition at line 500 of file core_armv81mml.h.
◆ ISPR
| __IOM uint32_t NVIC_Type::ISPR |
Offset: 0x100 (R/W) Interrupt Set Pending Register
Definition at line 504 of file core_armv81mml.h.
◆ [] [1/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 387 of file core_cm33.h.
◆ [] [2/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 319 of file core_cm4.h.
◆ [] [3/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 394 of file core_armv81mml.h.
◆ [] [4/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 254 of file core_cm3.h.
◆ [] [5/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 387 of file core_cm33.h.
◆ [] [6/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 387 of file core_cm35p.h.
◆ [] [7/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 319 of file core_cm4.h.
◆ [] [8/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 397 of file core_cm55.h.
◆ [] [9/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 334 of file core_cm7.h.
◆ [] [10/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 393 of file core_cm85.h.
◆ [] [11/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 254 of file core_sc300.h.
◆ [] [12/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 393 of file core_starmc1.h.
◆ [] [13/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 394 of file core_armv81mml.h.
◆ ISR [14/28]
| uint32_t IPSR_Type::ISR |
bit: 0.. 8 Exception number
Definition at line 394 of file core_armv81mml.h.
◆ [] [15/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 405 of file core_cm33.h.
◆ [] [16/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 337 of file core_cm4.h.
◆ [] [17/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 412 of file core_armv81mml.h.
◆ [] [18/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 272 of file core_cm3.h.
◆ [] [19/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 405 of file core_cm33.h.
◆ [] [20/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 405 of file core_cm35p.h.
◆ [] [21/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 337 of file core_cm4.h.
◆ [] [22/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 415 of file core_cm55.h.
◆ [] [23/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 352 of file core_cm7.h.
◆ [] [24/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 411 of file core_cm85.h.
◆ [] [25/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 272 of file core_sc300.h.
◆ [] [26/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 411 of file core_starmc1.h.
◆ [] [27/28]
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
Definition at line 412 of file core_armv81mml.h.
◆ ISR [28/28]
| uint32_t xPSR_Type::ISR |
bit: 0.. 8 Exception number
Definition at line 412 of file core_armv81mml.h.
◆ [] [1/9]
| uint32_t { ... } ::IT |
bit: 25..26 saved IT state (read 0)
Definition at line 410 of file core_cm33.h.
◆ [] [2/9]
| uint32_t { ... } ::IT |
bit: 25..26 saved IT state (read 0)
Definition at line 417 of file core_armv81mml.h.
◆ [] [3/9]
| uint32_t { ... } ::IT |
bit: 25..26 saved IT state (read 0)
Definition at line 410 of file core_cm33.h.
◆ [] [4/9]
| uint32_t { ... } ::IT |
bit: 25..26 saved IT state (read 0)
Definition at line 410 of file core_cm35p.h.
◆ [] [5/9]
| uint32_t { ... } ::IT |
bit: 25..26 saved IT state (read 0)
Definition at line 420 of file core_cm55.h.
◆ [] [6/9]
| uint32_t { ... } ::IT |
bit: 25..26 saved IT state (read 0)
Definition at line 418 of file core_cm85.h.
◆ [] [7/9]
| uint32_t { ... } ::IT |
bit: 25..26 saved IT state (read 0)
Definition at line 416 of file core_starmc1.h.
◆ [] [8/9]
| uint32_t { ... } ::IT |
bit: 25..26 saved IT state (read 0)
Definition at line 417 of file core_armv81mml.h.
◆ IT [9/9]
| uint32_t xPSR_Type::IT |
bit: 25..26 saved IT state (read 0)
Definition at line 417 of file core_armv81mml.h.
◆ ITATBCTR2
| __IM uint32_t TPI_Type::ITATBCTR2 |
Offset: 0xEF0 (R/ ) ITATBCTR2
Definition at line 1013 of file core_cm3.h.
◆ ITCMCR [1/3]
| __IOM uint32_t EMSS_Type::ITCMCR |
Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register
Definition at line 586 of file core_starmc1.h.
◆ ITCMCR [2/3]
| __IOM uint32_t MemSysCtl_Type::ITCMCR |
Offset: 0x010 (R/W) ITCM Control Register
Definition at line 1417 of file core_cm55.h.
◆ ITCMCR [3/3]
| __IOM uint32_t SCB_Type::ITCMCR |
Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register
Definition at line 518 of file core_cm7.h.
◆ ITCTRL
| __IOM uint32_t ITM_Type::ITCTRL |
Offset: 0xF00 (R/W) ITM Integration Mode Control Register
Definition at line 1166 of file core_cm55.h.
◆ ITGU_CFG
| __IOM uint32_t MemSysCtl_Type::ITGU_CFG |
Offset: 0x504 (R/W) ITGU Configuration Register
Definition at line 1422 of file core_cm55.h.
◆ ITGU_CTRL
| __IOM uint32_t MemSysCtl_Type::ITGU_CTRL |
Offset: 0x500 (R/W) ITGU Control Register
Definition at line 1421 of file core_cm55.h.
◆ ITGU_LUT
| __IOM uint32_t MemSysCtl_Type::ITGU_LUT |
Offset: 0x510 (R/W) ITGU Look Up Table Register
Definition at line 1424 of file core_cm55.h.
◆ ITM_RxBuffer [1/15]
|
extern |
External variable to receive characters.
◆ ITM_RxBuffer [2/15]
|
extern |
External variable to receive characters.
◆ ITM_RxBuffer [3/15]
|
extern |
External variable to receive characters.
◆ ITM_RxBuffer [4/15]
|
extern |
External variable to receive characters.
◆ ITM_RxBuffer [5/15]
|
extern |
External variable to receive characters.
◆ ITM_RxBuffer [6/15]
|
extern |
External variable to receive characters.
◆ ITM_RxBuffer [7/15]
|
extern |
External variable to receive characters.
◆ ITM_RxBuffer [8/15]
|
extern |
External variable to receive characters.
◆ ITM_RxBuffer [9/15]
|
extern |
External variable to receive characters.
◆ ITM_RxBuffer [10/15]
|
extern |
External variable to receive characters.
◆ ITM_RxBuffer [11/15]
|
extern |
External variable to receive characters.
◆ ITM_RxBuffer [12/15]
|
extern |
External variable to receive characters.
◆ ITM_RxBuffer [13/15]
|
extern |
External variable to receive characters.
◆ ITM_RxBuffer [14/15]
|
extern |
External variable to receive characters.
◆ ITM_RxBuffer [15/15]
|
extern |
External variable to receive characters.
◆ ITNS
| __IOM uint32_t NVIC_Type::ITNS |
Offset: 0x280 (R/W) Interrupt Non-Secure State Register
Definition at line 510 of file core_armv81mml.h.
◆ ITREAD
| __IM uint32_t ITM_Type::ITREAD |
Offset: 0xEF0 (R/ ) ITM Integration Read Register
Definition at line 1162 of file core_cm55.h.
◆ ITWRITE
| __OM uint32_t ITM_Type::ITWRITE |
Offset: 0xEF8 ( /W) ITM Integration Write Register
Definition at line 1164 of file core_cm55.h.
◆ LAR [1/3]
| __OM uint32_t DWT_Type::LAR |
Offset: 0xFB0 ( W) Lock Access Register
Definition at line 1166 of file core_cm7.h.
◆ LAR [2/3]
| __OM uint32_t ITM_Type::LAR |
Offset: 0xFB0 ( /W) ITM Lock Access Register
Definition at line 1117 of file core_armv81mml.h.
◆ LAR [3/3]
| __OM uint32_t TPI_Type::LAR |
Offset: 0xFB0 ( /W) Software Lock Access Register
Definition at line 1401 of file core_armv81mml.h.
◆ LOAD
| __IOM uint32_t SysTick_Type::LOAD |
Offset: 0x004 (R/W) SysTick Reload Value Register
Definition at line 1052 of file core_armv81mml.h.
◆ LSR [1/3]
| __IM uint32_t DWT_Type::LSR |
Offset: 0xFB4 (R ) Lock Status Register
Definition at line 1276 of file core_armv81mml.h.
◆ LSR [2/3]
| __IM uint32_t ITM_Type::LSR |
Offset: 0xFB4 (R/ ) ITM Lock Status Register
Definition at line 1118 of file core_armv81mml.h.
◆ LSR [3/3]
| __IM uint32_t TPI_Type::LSR |
Offset: 0xFB4 (R/ ) Software Lock Status Register
Definition at line 1402 of file core_armv81mml.h.
◆ LSUCNT
| __IOM uint32_t DWT_Type::LSUCNT |
Offset: 0x014 (R/W) LSU Count Register
Definition at line 1209 of file core_armv81mml.h.
◆ MASK0
| __IOM uint32_t DWT_Type::MASK0 |
Offset: 0x024 (R/W) Mask Register 0
Definition at line 862 of file core_cm3.h.
◆ MASK1
| __IOM uint32_t DWT_Type::MASK1 |
Offset: 0x034 (R/W) Mask Register 1
Definition at line 866 of file core_cm3.h.
◆ MASK2
| __IOM uint32_t DWT_Type::MASK2 |
Offset: 0x044 (R/W) Mask Register 2
Definition at line 870 of file core_cm3.h.
◆ MASK3
| __IOM uint32_t DWT_Type::MASK3 |
Offset: 0x054 (R/W) Mask Register 3
Definition at line 874 of file core_cm3.h.
◆ MMFAR
| __IOM uint32_t SCB_Type::MMFAR |
Offset: 0x034 (R/W) MemManage Fault Address Register
Definition at line 547 of file core_armv81mml.h.
◆ MMFR
| __IM uint32_t SCB_Type::MMFR |
Offset: 0x050 (R/ ) Memory Model Feature Register
Definition at line 403 of file core_cm3.h.
◆ MSCR
| __IOM uint32_t MemSysCtl_Type::MSCR |
Offset: 0x000 (R/W) Memory System Control Register
Definition at line 1414 of file core_cm55.h.
◆ MVFR0 [1/2]
| __IM uint32_t FPU_Type::MVFR0 |
Offset: 0x010 (R/ ) Media and VFP Feature Register 0
Offset: 0x010 (R/ ) Media and FP Feature Register 0
Definition at line 2511 of file core_armv81mml.h.
◆ MVFR0 [2/2]
| __IM uint32_t SCB_Type::MVFR0 |
Offset: 0x240 (R/ ) Media and VFP Feature Register 0
Definition at line 568 of file core_armv81mml.h.
◆ MVFR1 [1/2]
| __IM uint32_t FPU_Type::MVFR1 |
Offset: 0x014 (R/ ) Media and VFP Feature Register 1
Offset: 0x014 (R/ ) Media and FP Feature Register 1
Definition at line 2512 of file core_armv81mml.h.
◆ MVFR1 [2/2]
| __IM uint32_t SCB_Type::MVFR1 |
Offset: 0x244 (R/ ) Media and VFP Feature Register 1
Definition at line 569 of file core_armv81mml.h.
◆ MVFR2 [1/2]
| __IM uint32_t FPU_Type::MVFR2 |
Offset: 0x018 (R/ ) Media and VFP Feature Register 2
Offset: 0x018 (R/ ) Media and FP Feature Register 2
Definition at line 2513 of file core_armv81mml.h.
◆ MVFR2 [2/2]
| __IM uint32_t SCB_Type::MVFR2 |
Offset: 0x248 (R/ ) Media and VFP Feature Register 2
Definition at line 570 of file core_armv81mml.h.
◆ [] [1/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 362 of file core_armv81mml.h.
◆ [] [2/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 355 of file core_cm33.h.
◆ [] [3/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 287 of file core_cm4.h.
◆ [] [4/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 225 of file core_cm3.h.
◆ [] [5/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 355 of file core_cm33.h.
◆ [] [6/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 355 of file core_cm35p.h.
◆ [] [7/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 287 of file core_cm4.h.
◆ [] [8/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 365 of file core_cm55.h.
◆ [] [9/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 302 of file core_cm7.h.
◆ [] [10/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 361 of file core_cm85.h.
◆ [] [11/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 225 of file core_sc300.h.
◆ [] [12/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 361 of file core_starmc1.h.
◆ [] [13/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 362 of file core_armv81mml.h.
◆ N [14/28]
| uint32_t APSR_Type::N |
bit: 31 Negative condition code flag
Definition at line 362 of file core_armv81mml.h.
◆ [] [15/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 415 of file core_cm33.h.
◆ [] [16/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 348 of file core_cm4.h.
◆ [] [17/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 422 of file core_armv81mml.h.
◆ [] [18/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 282 of file core_cm3.h.
◆ [] [19/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 415 of file core_cm33.h.
◆ [] [20/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 415 of file core_cm35p.h.
◆ [] [21/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 348 of file core_cm4.h.
◆ [] [22/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 425 of file core_cm55.h.
◆ [] [23/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 363 of file core_cm7.h.
◆ [] [24/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 423 of file core_cm85.h.
◆ [] [25/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 282 of file core_sc300.h.
◆ [] [26/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 421 of file core_starmc1.h.
◆ [] [27/28]
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
Definition at line 422 of file core_armv81mml.h.
◆ N [28/28]
| uint32_t xPSR_Type::N |
bit: 31 Negative condition code flag
Definition at line 422 of file core_armv81mml.h.
◆ [] [1/14]
| uint32_t { ... } ::nPRIV |
bit: 0 Execution privilege in Thread mode
Definition at line 456 of file core_cm33.h.
◆ [] [2/14]
| uint32_t { ... } ::nPRIV |
bit: 0 Execution privilege in Thread mode
Definition at line 392 of file core_cm4.h.
◆ [] [3/14]
| uint32_t { ... } ::nPRIV |
bit: 0 Execution privilege in Thread mode
Definition at line 323 of file core_cm3.h.
◆ [] [4/14]
| uint32_t { ... } ::nPRIV |
bit: 0 Execution privilege in Thread mode
Definition at line 456 of file core_cm33.h.
◆ [] [5/14]
| uint32_t { ... } ::nPRIV |
bit: 0 Execution privilege in Thread mode
Definition at line 463 of file core_armv81mml.h.
◆ [] [6/14]
| uint32_t { ... } ::nPRIV |
bit: 0 Execution privilege in Thread mode
Definition at line 456 of file core_cm35p.h.
◆ [] [7/14]
| uint32_t { ... } ::nPRIV |
bit: 0 Execution privilege in Thread mode
Definition at line 392 of file core_cm4.h.
◆ [] [8/14]
| uint32_t { ... } ::nPRIV |
bit: 0 Execution privilege in Thread mode
Definition at line 466 of file core_cm55.h.
◆ [] [9/14]
| uint32_t { ... } ::nPRIV |
bit: 0 Execution privilege in Thread mode
Definition at line 407 of file core_cm7.h.
◆ [] [10/14]
| uint32_t { ... } ::nPRIV |
bit: 0 Execution privilege in Thread mode
Definition at line 467 of file core_cm85.h.
◆ [] [11/14]
| uint32_t { ... } ::nPRIV |
bit: 0 Execution privilege in Thread mode
Definition at line 323 of file core_sc300.h.
◆ [] [12/14]
| uint32_t { ... } ::nPRIV |
bit: 0 Execution privilege in Thread mode
Definition at line 462 of file core_starmc1.h.
◆ [] [13/14]
| uint32_t { ... } ::nPRIV |
bit: 0 Execution privilege in Thread mode
Definition at line 463 of file core_armv81mml.h.
◆ nPRIV [14/14]
| uint32_t CONTROL_Type::nPRIV |
bit: 0 Execution privilege in Thread mode
Definition at line 463 of file core_armv81mml.h.
◆ NSACR
| __IOM uint32_t SCB_Type::NSACR |
Offset: 0x08C (R/W) Non-Secure Access Control Register
Definition at line 560 of file core_armv81mml.h.
◆ [] [1/2]
| uint32_t { ... } ::PAC_EN |
bit: 6 Privileged pointer authentication enable
Definition at line 473 of file core_cm85.h.
◆ PAC_EN [2/2]
| uint32_t CONTROL_Type::PAC_EN |
bit: 6 Privileged pointer authentication enable
Definition at line 473 of file core_cm85.h.
◆ PAHBCR
| __IOM uint32_t MemSysCtl_Type::PAHBCR |
Offset: 0x018 (R/W) P-AHB Control Register
Definition at line 1419 of file core_cm55.h.
◆ PCSR
| __IM uint32_t DWT_Type::PCSR |
Offset: 0x01C (R/ ) Program Counter Sample Register
Definition at line 1211 of file core_armv81mml.h.
◆ PFCR
| __IOM uint32_t MemSysCtl_Type::PFCR |
Offset: 0x004 (R/W) Prefetcher Control Register
Definition at line 1415 of file core_cm55.h.
◆ PFR
| __IM uint32_t SCB_Type::PFR |
Offset: 0x040 (R/ ) Processor Feature Register
Definition at line 400 of file core_cm3.h.
◆ PID0
| __IM uint32_t ITM_Type::PID0 |
Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0
Definition at line 1127 of file core_armv81mml.h.
◆ PID1
| __IM uint32_t ITM_Type::PID1 |
Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1
Definition at line 1128 of file core_armv81mml.h.
◆ PID2
| __IM uint32_t ITM_Type::PID2 |
Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2
Definition at line 1129 of file core_armv81mml.h.
◆ PID3
| __IM uint32_t ITM_Type::PID3 |
Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3
Definition at line 1130 of file core_armv81mml.h.
◆ PID4
| __IM uint32_t ITM_Type::PID4 |
Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4
Definition at line 1123 of file core_armv81mml.h.
◆ PID5
| __IM uint32_t ITM_Type::PID5 |
Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5
Definition at line 1124 of file core_armv81mml.h.
◆ PID6
| __IM uint32_t ITM_Type::PID6 |
Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6
Definition at line 1125 of file core_armv81mml.h.
◆ PID7
| __IM uint32_t ITM_Type::PID7 |
Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7
Definition at line 1126 of file core_armv81mml.h.
◆ [union] [1/13]
| __OM union { ... } ITM_Type::PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
◆ [union] [2/13]
| __OM union { ... } ITM_Type::PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
◆ [union] [3/13]
| __OM union { ... } ITM_Type::PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
◆ [union] [4/13]
| __OM union { ... } ITM_Type::PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
◆ [union] [5/13]
| __OM union { ... } ITM_Type::PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
◆ [union] [6/13]
| __OM union { ... } ITM_Type::PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
◆ [union] [7/13]
| __OM union { ... } ITM_Type::PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
◆ [union] [8/13]
| __OM union { ... } ITM_Type::PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
◆ [union] [9/13]
| __OM union { ... } ITM_Type::PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
◆ [union] [10/13]
| __OM union { ... } ITM_Type::PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
◆ [union] [11/13]
| __OM union { ... } ITM_Type::PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
◆ [union] [12/13]
| __OM union { ... } ITM_Type::PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
◆ [union] [13/13]
| __OM union { ... } ITM_Type::PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
◆ PSCR
| __IOM uint32_t TPI_Type::PSCR |
Offset: 0x308 (R/W) Periodic Synchronization Control Register
Definition at line 1399 of file core_armv81mml.h.
◆ [] [1/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 358 of file core_armv81mml.h.
◆ [] [2/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 351 of file core_cm33.h.
◆ [] [3/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 283 of file core_cm4.h.
◆ [] [4/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 221 of file core_cm3.h.
◆ [] [5/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 351 of file core_cm33.h.
◆ [] [6/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 351 of file core_cm35p.h.
◆ [] [7/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 283 of file core_cm4.h.
◆ [] [8/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 361 of file core_cm55.h.
◆ [] [9/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 298 of file core_cm7.h.
◆ [] [10/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 357 of file core_cm85.h.
◆ [] [11/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 221 of file core_sc300.h.
◆ [] [12/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 357 of file core_starmc1.h.
◆ [] [13/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 358 of file core_armv81mml.h.
◆ Q [14/28]
| uint32_t APSR_Type::Q |
bit: 27 Saturation condition flag
Definition at line 358 of file core_armv81mml.h.
◆ [] [15/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 411 of file core_cm33.h.
◆ [] [16/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 344 of file core_cm4.h.
◆ [] [17/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 418 of file core_armv81mml.h.
◆ [] [18/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 278 of file core_cm3.h.
◆ [] [19/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 411 of file core_cm33.h.
◆ [] [20/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 411 of file core_cm35p.h.
◆ [] [21/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 344 of file core_cm4.h.
◆ [] [22/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 421 of file core_cm55.h.
◆ [] [23/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 359 of file core_cm7.h.
◆ [] [24/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 419 of file core_cm85.h.
◆ [] [25/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 278 of file core_sc300.h.
◆ [] [26/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 417 of file core_starmc1.h.
◆ [] [27/28]
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
Definition at line 418 of file core_armv81mml.h.
◆ Q [28/28]
| uint32_t xPSR_Type::Q |
bit: 27 Saturation condition flag
Definition at line 418 of file core_armv81mml.h.
◆ RESERVED0 [1/11]
| uint32_t DIB_Type::RESERVED0 |
Definition at line 3564 of file core_cm55.h.
◆ RESERVED0 [2/11]
| uint32_t ErrBnk_Type::RESERVED0 |
Definition at line 1700 of file core_cm55.h.
◆ RESERVED0 [3/11]
| uint32_t EWIC_ISA_Type::RESERVED0 |
Definition at line 1654 of file core_cm55.h.
◆ RESERVED0 [4/11]
| uint32_t EWIC_Type::RESERVED0 |
Definition at line 1578 of file core_cm55.h.
◆ RESERVED0 [5/11]
| uint32_t FPU_Type::RESERVED0 |
Definition at line 2507 of file core_armv81mml.h.
◆ RESERVED0 [6/11]
| uint32_t ICB_Type::RESERVED0 |
Definition at line 1029 of file core_cm55.h.
◆ RESERVED0 [7/11]
| uint32_t ITM_Type::RESERVED0 |
Definition at line 1109 of file core_armv81mml.h.
◆ RESERVED0 [8/11]
| uint32_t NVIC_Type::RESERVED0 |
Definition at line 501 of file core_armv81mml.h.
◆ RESERVED0 [9/11]
| uint32_t SCnSCB_Type::RESERVED0 |
Definition at line 1026 of file core_armv81mml.h.
◆ RESERVED0 [10/11]
| uint32_t STL_Type::RESERVED0[2U] |
Definition at line 1863 of file core_cm55.h.
◆ RESERVED0 [11/11]
| uint32_t TPI_Type::RESERVED0 |
Definition at line 1392 of file core_armv81mml.h.
◆ RESERVED1 [1/8]
| uint32_t DIB_Type::RESERVED1 |
Definition at line 3567 of file core_cm55.h.
◆ RESERVED1 [2/8]
| uint32_t DWT_Type::RESERVED1 |
Definition at line 1213 of file core_armv81mml.h.
◆ RESERVED1 [3/8]
| uint32_t ErrBnk_Type::RESERVED1 |
Definition at line 1703 of file core_cm55.h.
◆ RESERVED1 [4/8]
| uint32_t EWIC_Type::RESERVED1 |
Definition at line 1581 of file core_cm55.h.
◆ RESERVED1 [5/8]
| uint32_t ITM_Type::RESERVED1 |
Definition at line 1111 of file core_armv81mml.h.
◆ RESERVED1 [6/8]
| uint32_t MemSysCtl_Type::RESERVED1 |
Definition at line 1416 of file core_cm55.h.
◆ RESERVED1 [7/8]
| uint32_t SCnSCB_Type::RESERVED1[1U] |
Definition at line 672 of file core_cm3.h.
◆ RESERVED1 [8/8]
| uint32_t TPI_Type::RESERVED1 |
Definition at line 1394 of file core_armv81mml.h.
◆ RESERVED10
| uint32_t DWT_Type::RESERVED10 |
Definition at line 1231 of file core_armv81mml.h.
◆ RESERVED11
| uint32_t DWT_Type::RESERVED11 |
Definition at line 1233 of file core_armv81mml.h.
◆ RESERVED12
| uint32_t DWT_Type::RESERVED12 |
Definition at line 1235 of file core_armv81mml.h.
◆ RESERVED13
| uint32_t DWT_Type::RESERVED13 |
Definition at line 1237 of file core_armv81mml.h.
◆ RESERVED14
| uint32_t DWT_Type::RESERVED14 |
Definition at line 1239 of file core_armv81mml.h.
◆ RESERVED15
| uint32_t DWT_Type::RESERVED15 |
Definition at line 1241 of file core_armv81mml.h.
◆ RESERVED16
| uint32_t DWT_Type::RESERVED16 |
Definition at line 1243 of file core_armv81mml.h.
◆ RESERVED17
| uint32_t DWT_Type::RESERVED17 |
Definition at line 1245 of file core_armv81mml.h.
◆ RESERVED18
| uint32_t DWT_Type::RESERVED18 |
Definition at line 1247 of file core_armv81mml.h.
◆ RESERVED19
| uint32_t DWT_Type::RESERVED19 |
Definition at line 1249 of file core_armv81mml.h.
◆ RESERVED2 [1/7]
| uint32_t DWT_Type::RESERVED2 |
Definition at line 1215 of file core_armv81mml.h.
◆ RESERVED2 [2/7]
| uint32_t ErrBnk_Type::RESERVED2 |
Definition at line 1705 of file core_cm55.h.
◆ RESERVED2 [3/7]
| uint32_t EWIC_Type::RESERVED2 |
Definition at line 1584 of file core_cm55.h.
◆ RESERVED2 [4/7]
| uint32_t ITM_Type::RESERVED2 |
Definition at line 1113 of file core_armv81mml.h.
◆ RESERVED2 [5/7]
| uint32_t MemSysCtl_Type::RESERVED2 |
Definition at line 1420 of file core_cm55.h.
◆ RESERVED2 [6/7]
| uint32_t NVIC_Type::RESERVED2 |
Definition at line 505 of file core_armv81mml.h.
◆ RESERVED2 [7/7]
| uint32_t TPI_Type::RESERVED2 |
Definition at line 1396 of file core_armv81mml.h.
◆ RESERVED20
| uint32_t DWT_Type::RESERVED20 |
Definition at line 1251 of file core_armv81mml.h.
◆ RESERVED21
| uint32_t DWT_Type::RESERVED21 |
Definition at line 1253 of file core_armv81mml.h.
◆ RESERVED22
| uint32_t DWT_Type::RESERVED22 |
Definition at line 1255 of file core_armv81mml.h.
◆ RESERVED23
| uint32_t DWT_Type::RESERVED23 |
Definition at line 1257 of file core_armv81mml.h.
◆ RESERVED24
| uint32_t DWT_Type::RESERVED24 |
Definition at line 1259 of file core_armv81mml.h.
◆ RESERVED25
| uint32_t DWT_Type::RESERVED25 |
Definition at line 1261 of file core_armv81mml.h.
◆ RESERVED26
| uint32_t DWT_Type::RESERVED26 |
Definition at line 1263 of file core_armv81mml.h.
◆ RESERVED27
| uint32_t DWT_Type::RESERVED27 |
Definition at line 1265 of file core_armv81mml.h.
◆ RESERVED28
| uint32_t DWT_Type::RESERVED28 |
Definition at line 1267 of file core_armv81mml.h.
◆ RESERVED29
| uint32_t DWT_Type::RESERVED29 |
Definition at line 1269 of file core_armv81mml.h.
◆ RESERVED3 [1/6]
| uint32_t DWT_Type::RESERVED3 |
Definition at line 1217 of file core_armv81mml.h.
◆ RESERVED3 [2/6]
| uint32_t ITM_Type::RESERVED3 |
Definition at line 1115 of file core_armv81mml.h.
◆ RESERVED3 [3/6]
| uint32_t MemSysCtl_Type::RESERVED3 |
Definition at line 1423 of file core_cm55.h.
◆ RESERVED3 [4/6]
| uint32_t NVIC_Type::RESERVED3 |
Definition at line 507 of file core_armv81mml.h.
◆ RESERVED3 [5/6]
| uint32_t SCB_Type::RESERVED3 |
Definition at line 564 of file core_armv81mml.h.
◆ RESERVED3 [6/6]
| uint32_t TPI_Type::RESERVED3 |
Definition at line 1400 of file core_armv81mml.h.
◆ RESERVED30
| uint32_t DWT_Type::RESERVED30 |
Definition at line 1271 of file core_armv81mml.h.
◆ RESERVED31
| uint32_t DWT_Type::RESERVED31 |
Definition at line 1273 of file core_armv81mml.h.
◆ RESERVED32
| uint32_t DWT_Type::RESERVED32 |
Definition at line 1275 of file core_armv81mml.h.
◆ RESERVED33
| uint32_t DWT_Type::RESERVED33 |
Definition at line 1277 of file core_armv81mml.h.
◆ RESERVED4 [1/6]
| uint32_t DWT_Type::RESERVED4 |
Definition at line 1219 of file core_armv81mml.h.
◆ RESERVED4 [2/6]
| uint32_t ITM_Type::RESERVED4 |
Definition at line 1116 of file core_armv81mml.h.
◆ RESERVED4 [3/6]
| uint32_t MemSysCtl_Type::RESERVED4 |
Definition at line 1425 of file core_cm55.h.
◆ RESERVED4 [4/6]
| uint32_t NVIC_Type::RESERVED4 |
Definition at line 509 of file core_armv81mml.h.
◆ RESERVED4 [5/6]
| uint32_t SCB_Type::RESERVED4 |
Definition at line 567 of file core_armv81mml.h.
◆ RESERVED4 [6/6]
| uint32_t TPI_Type::RESERVED4 |
Definition at line 1403 of file core_armv81mml.h.
◆ RESERVED5 [1/5]
| uint32_t DWT_Type::RESERVED5 |
Definition at line 1221 of file core_armv81mml.h.
◆ RESERVED5 [2/5]
| uint32_t ITM_Type::RESERVED5 |
Definition at line 1119 of file core_armv81mml.h.
◆ RESERVED5 [3/5]
| uint32_t MemSysCtl_Type::RESERVED5 |
Definition at line 1428 of file core_cm55.h.
◆ RESERVED5 [4/5]
| uint32_t NVIC_Type::RESERVED5 |
Definition at line 511 of file core_armv81mml.h.
◆ RESERVED5 [5/5]
| uint32_t SCB_Type::RESERVED5 |
Definition at line 571 of file core_armv81mml.h.
◆ RESERVED6 [1/4]
| uint32_t DWT_Type::RESERVED6 |
Definition at line 1223 of file core_armv81mml.h.
◆ RESERVED6 [2/4]
| uint32_t ITM_Type::RESERVED6 |
Definition at line 1121 of file core_armv81mml.h.
◆ RESERVED6 [3/4]
| uint32_t NVIC_Type::RESERVED6 |
Definition at line 513 of file core_armv81mml.h.
◆ RESERVED6 [4/4]
| uint32_t SCB_Type::RESERVED6 |
Definition at line 573 of file core_armv81mml.h.
◆ RESERVED7 [1/3]
| uint32_t DWT_Type::RESERVED7 |
Definition at line 1225 of file core_armv81mml.h.
◆ RESERVED7 [2/3]
| uint32_t ITM_Type::RESERVED7 |
Definition at line 1169 of file core_cm55.h.
◆ RESERVED7 [3/3]
| uint32_t SCB_Type::RESERVED7 |
Definition at line 561 of file core_armv81mml.h.
◆ RESERVED8 [1/2]
| uint32_t DWT_Type::RESERVED8 |
Definition at line 1227 of file core_armv81mml.h.
◆ RESERVED8 [2/2]
| uint32_t SCB_Type::RESERVED8[1U] |
Definition at line 523 of file core_cm7.h.
◆ RESERVED9
| uint32_t DWT_Type::RESERVED9 |
Definition at line 1229 of file core_armv81mml.h.
◆ RESERVED_ADD1
| uint32_t SCB_Type::RESERVED_ADD1[21U] |
Definition at line 561 of file core_starmc1.h.
◆ RFSR
| __IOM uint32_t SCB_Type::RFSR |
Offset: 0x204 (R/W) RAS Fault Status Register
Definition at line 566 of file core_armv81mml.h.
◆ RSERVED1
| uint32_t NVIC_Type::RSERVED1 |
Definition at line 503 of file core_armv81mml.h.
◆ SCR
| __IOM uint32_t SCB_Type::SCR |
Offset: 0x010 (R/W) System Control Register
Definition at line 540 of file core_armv81mml.h.
◆ SFAR
| __IOM uint32_t SCB_Type::SFAR |
Offset: 0x0E8 (R/W) Secure Fault Address Register
Definition at line 563 of file core_armv81mml.h.
◆ [] [1/9]
| uint32_t { ... } ::SFPA |
bit: 3 Secure floating-point active
Definition at line 459 of file core_cm33.h.
◆ [] [2/9]
| uint32_t { ... } ::SFPA |
bit: 3 Secure floating-point active
Definition at line 459 of file core_cm33.h.
◆ [] [3/9]
| uint32_t { ... } ::SFPA |
bit: 3 Secure floating-point active
Definition at line 466 of file core_armv81mml.h.
◆ [] [4/9]
| uint32_t { ... } ::SFPA |
bit: 3 Secure floating-point active
Definition at line 459 of file core_cm35p.h.
◆ [] [5/9]
| uint32_t { ... } ::SFPA |
bit: 3 Secure floating-point active
Definition at line 469 of file core_cm55.h.
◆ [] [6/9]
| uint32_t { ... } ::SFPA |
bit: 3 Secure floating-point active
Definition at line 470 of file core_cm85.h.
◆ [] [7/9]
| uint32_t { ... } ::SFPA |
bit: 3 Secure floating-point active
Definition at line 465 of file core_starmc1.h.
◆ [] [8/9]
| uint32_t { ... } ::SFPA |
bit: 3 Secure floating-point active
Definition at line 466 of file core_armv81mml.h.
◆ SFPA [9/9]
| uint32_t CONTROL_Type::SFPA |
bit: 3 Secure floating-point active
Definition at line 466 of file core_armv81mml.h.
◆ SFSR
| __IOM uint32_t SCB_Type::SFSR |
Offset: 0x0E4 (R/W) Secure Fault Status Register
Definition at line 562 of file core_armv81mml.h.
◆ SHCSR
| __IOM uint32_t SCB_Type::SHCSR |
Offset: 0x024 (R/W) System Handler Control and State Register
Definition at line 543 of file core_armv81mml.h.
◆ SHP
| __IOM uint8_t SCB_Type::SHP[12U] |
Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)
Definition at line 392 of file core_cm3.h.
◆ SHPR
| __IOM uint8_t SCB_Type::SHPR |
Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)
Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED
Definition at line 542 of file core_armv81mml.h.
◆ SLEEPCNT
| __IOM uint32_t DWT_Type::SLEEPCNT |
Offset: 0x010 (R/W) Sleep Count Register
Definition at line 1208 of file core_armv81mml.h.
◆ SPPR
| __IOM uint32_t TPI_Type::SPPR |
Offset: 0x0F0 (R/W) Selected Pin Protocol Register
Definition at line 1395 of file core_armv81mml.h.
◆ [] [1/14]
| uint32_t { ... } ::SPSEL |
bit: 1 Stack-pointer select
Definition at line 457 of file core_cm33.h.
◆ [] [2/14]
| uint32_t { ... } ::SPSEL |
bit: 1 Stack to be used
Definition at line 393 of file core_cm4.h.
◆ [] [3/14]
| uint32_t { ... } ::SPSEL |
bit: 1 Stack to be used
Definition at line 324 of file core_cm3.h.
◆ [] [4/14]
| uint32_t { ... } ::SPSEL |
bit: 1 Stack-pointer select
Definition at line 457 of file core_cm33.h.
◆ [] [5/14]
| uint32_t { ... } ::SPSEL |
bit: 1 Stack-pointer select
Definition at line 464 of file core_armv81mml.h.
◆ [] [6/14]
| uint32_t { ... } ::SPSEL |
bit: 1 Stack-pointer select
Definition at line 457 of file core_cm35p.h.
◆ [] [7/14]
| uint32_t { ... } ::SPSEL |
bit: 1 Stack to be used
Definition at line 393 of file core_cm4.h.
◆ [] [8/14]
| uint32_t { ... } ::SPSEL |
bit: 1 Stack-pointer select
Definition at line 467 of file core_cm55.h.
◆ [] [9/14]
| uint32_t { ... } ::SPSEL |
bit: 1 Stack to be used
Definition at line 408 of file core_cm7.h.
◆ [] [10/14]
| uint32_t { ... } ::SPSEL |
bit: 1 Stack-pointer select
Definition at line 468 of file core_cm85.h.
◆ [] [11/14]
| uint32_t { ... } ::SPSEL |
bit: 1 Stack to be used
Definition at line 324 of file core_sc300.h.
◆ [] [12/14]
| uint32_t { ... } ::SPSEL |
bit: 1 Stack-pointer select
Definition at line 463 of file core_starmc1.h.
◆ [] [13/14]
| uint32_t { ... } ::SPSEL |
bit: 1 Stack-pointer select
Definition at line 464 of file core_armv81mml.h.
◆ SPSEL [14/14]
| uint32_t CONTROL_Type::SPSEL |
bit: 1 Stack-pointer select
bit: 1 Stack to be used
Definition at line 464 of file core_armv81mml.h.
◆ SSPSR
| __IM uint32_t TPI_Type::SSPSR |
Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register
Offset: 0x000 (R/ ) Supported Parallel Port Size Register
Definition at line 1390 of file core_armv81mml.h.
◆ STIR [1/2]
| __OM uint32_t NVIC_Type::STIR |
Offset: 0xE00 ( /W) Software Trigger Interrupt Register
Definition at line 514 of file core_armv81mml.h.
◆ STIR [2/2]
| __OM uint32_t SCB_Type::STIR |
Offset: 0x200 ( /W) Software Triggered Interrupt Register
Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register
Definition at line 565 of file core_armv81mml.h.
◆ STLD0MPUOR
| __IM uint32_t STL_Type::STLD0MPUOR |
Offset: 0x018 (R/ ) MPU Memory Attributes Register 0
Definition at line 1866 of file core_cm55.h.
◆ STLD1MPUOR
| __IM uint32_t STL_Type::STLD1MPUOR |
Offset: 0x01C (R/ ) MPU Memory Attributes Register 1
Definition at line 1867 of file core_cm55.h.
◆ STLIDMPUSR
| __OM uint32_t STL_Type::STLIDMPUSR |
Offset: 0x010 ( /W) MPU Sample Register
Definition at line 1864 of file core_cm55.h.
◆ STLIMPUOR
| __IM uint32_t STL_Type::STLIMPUOR |
Offset: 0x014 (R/ ) MPU Region Hit Register
Definition at line 1865 of file core_cm55.h.
◆ STLNVICACTVOR
| __IM uint32_t STL_Type::STLNVICACTVOR |
Offset: 0x004 (R/ ) NVIC Active Priority Tree Register
Definition at line 1862 of file core_cm55.h.
◆ STLNVICPENDOR
| __IM uint32_t STL_Type::STLNVICPENDOR |
Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register
Definition at line 1861 of file core_cm55.h.
◆ [] [1/14]
| uint32_t { ... } ::T |
bit: 24 Thumb bit (read 0)
Definition at line 409 of file core_cm33.h.
◆ [] [2/14]
| uint32_t { ... } ::T |
bit: 24 Thumb bit
Definition at line 342 of file core_cm4.h.
◆ [] [3/14]
| uint32_t { ... } ::T |
bit: 24 Thumb bit (read 0)
Definition at line 416 of file core_armv81mml.h.
◆ [] [4/14]
| uint32_t { ... } ::T |
bit: 24 Thumb bit
Definition at line 276 of file core_cm3.h.
◆ [] [5/14]
| uint32_t { ... } ::T |
bit: 24 Thumb bit (read 0)
Definition at line 409 of file core_cm33.h.
◆ [] [6/14]
| uint32_t { ... } ::T |
bit: 24 Thumb bit (read 0)
Definition at line 409 of file core_cm35p.h.
◆ [] [7/14]
| uint32_t { ... } ::T |
bit: 24 Thumb bit
Definition at line 342 of file core_cm4.h.
◆ [] [8/14]
| uint32_t { ... } ::T |
bit: 24 Thumb bit (read 0)
Definition at line 419 of file core_cm55.h.
◆ [] [9/14]
| uint32_t { ... } ::T |
bit: 24 Thumb bit
Definition at line 357 of file core_cm7.h.
◆ [] [10/14]
| uint32_t { ... } ::T |
bit: 24 Thumb bit (read 0)
Definition at line 417 of file core_cm85.h.
◆ [] [11/14]
| uint32_t { ... } ::T |
bit: 24 Thumb bit
Definition at line 276 of file core_sc300.h.
◆ [] [12/14]
| uint32_t { ... } ::T |
bit: 24 Thumb bit (read 0)
Definition at line 415 of file core_starmc1.h.
◆ [] [13/14]
| uint32_t { ... } ::T |
bit: 24 Thumb bit (read 0)
Definition at line 416 of file core_armv81mml.h.
◆ T [14/14]
| uint32_t xPSR_Type::T |
◆ TCR
| __IOM uint32_t ITM_Type::TCR |
Offset: 0xE80 (R/W) ITM Trace Control Register
Definition at line 1114 of file core_armv81mml.h.
◆ TEBR0
| __IOM uint32_t ErrBnk_Type::TEBR0 |
Offset: 0x020 (R/W) TCM Error Bank Register 0
Definition at line 1704 of file core_cm55.h.
◆ TEBR1
| __IOM uint32_t ErrBnk_Type::TEBR1 |
Offset: 0x028 (R/W) TCM Error Bank Register 1
Definition at line 1706 of file core_cm55.h.
◆ TER
| __IOM uint32_t ITM_Type::TER |
Offset: 0xE00 (R/W) ITM Trace Enable Register
Definition at line 1110 of file core_armv81mml.h.
◆ TPR
| __IOM uint32_t ITM_Type::TPR |
Offset: 0xE40 (R/W) ITM Trace Privilege Register
Definition at line 1112 of file core_armv81mml.h.
◆ TYPE
| __IM uint32_t TPI_Type::TYPE |
Offset: 0xFC8 (R/ ) Device Identifier Register
Definition at line 1404 of file core_armv81mml.h.
◆ [] [1/14]
| __OM uint16_t { ... } ::u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
Definition at line 1045 of file core_cm33.h.
◆ [] [2/14]
| __OM uint16_t { ... } ::u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
Definition at line 833 of file core_cm4.h.
◆ [] [3/14]
| __OM uint16_t { ... } ::u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
Definition at line 768 of file core_cm3.h.
◆ [] [4/14]
| __OM uint16_t { ... } ::u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
Definition at line 1045 of file core_cm33.h.
◆ [] [5/14]
| __OM uint16_t { ... } ::u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
Definition at line 1045 of file core_cm35p.h.
◆ [] [6/14]
| __OM uint16_t { ... } ::u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
Definition at line 833 of file core_cm4.h.
◆ [] [7/14]
| __OM uint16_t { ... } ::u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
Definition at line 1106 of file core_armv81mml.h.
◆ [] [8/14]
| __OM uint16_t { ... } ::u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
Definition at line 1152 of file core_cm55.h.
◆ [] [9/14]
| __OM uint16_t { ... } ::u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
Definition at line 1057 of file core_cm7.h.
◆ [] [10/14]
| __OM uint16_t { ... } ::u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
Definition at line 1148 of file core_cm85.h.
◆ [] [11/14]
| __OM uint16_t { ... } ::u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
Definition at line 753 of file core_sc300.h.
◆ [] [12/14]
| __OM uint16_t { ... } ::u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
Definition at line 1103 of file core_starmc1.h.
◆ [] [13/14]
| __OM uint16_t { ... } ::u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
Definition at line 1106 of file core_armv81mml.h.
◆ u16 [14/14]
| __OM uint16_t ITM_Type::u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
Definition at line 1106 of file core_armv81mml.h.
◆ [] [1/14]
| __OM uint32_t { ... } ::u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
Definition at line 1046 of file core_cm33.h.
◆ [] [2/14]
| __OM uint32_t { ... } ::u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
Definition at line 834 of file core_cm4.h.
◆ [] [3/14]
| __OM uint32_t { ... } ::u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
Definition at line 769 of file core_cm3.h.
◆ [] [4/14]
| __OM uint32_t { ... } ::u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
Definition at line 1046 of file core_cm33.h.
◆ [] [5/14]
| __OM uint32_t { ... } ::u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
Definition at line 1046 of file core_cm35p.h.
◆ [] [6/14]
| __OM uint32_t { ... } ::u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
Definition at line 834 of file core_cm4.h.
◆ [] [7/14]
| __OM uint32_t { ... } ::u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
Definition at line 1107 of file core_armv81mml.h.
◆ [] [8/14]
| __OM uint32_t { ... } ::u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
Definition at line 1153 of file core_cm55.h.
◆ [] [9/14]
| __OM uint32_t { ... } ::u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
Definition at line 1058 of file core_cm7.h.
◆ [] [10/14]
| __OM uint32_t { ... } ::u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
Definition at line 1149 of file core_cm85.h.
◆ [] [11/14]
| __OM uint32_t { ... } ::u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
Definition at line 754 of file core_sc300.h.
◆ [] [12/14]
| __OM uint32_t { ... } ::u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
Definition at line 1104 of file core_starmc1.h.
◆ [] [13/14]
| __OM uint32_t { ... } ::u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
Definition at line 1107 of file core_armv81mml.h.
◆ u32 [14/14]
| __OM uint32_t ITM_Type::u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
Definition at line 1107 of file core_armv81mml.h.
◆ [] [1/14]
| __OM uint8_t { ... } ::u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
Definition at line 1044 of file core_cm33.h.
◆ [] [2/14]
| __OM uint8_t { ... } ::u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
Definition at line 832 of file core_cm4.h.
◆ [] [3/14]
| __OM uint8_t { ... } ::u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
Definition at line 767 of file core_cm3.h.
◆ [] [4/14]
| __OM uint8_t { ... } ::u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
Definition at line 1044 of file core_cm33.h.
◆ [] [5/14]
| __OM uint8_t { ... } ::u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
Definition at line 1044 of file core_cm35p.h.
◆ [] [6/14]
| __OM uint8_t { ... } ::u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
Definition at line 832 of file core_cm4.h.
◆ [] [7/14]
| __OM uint8_t { ... } ::u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
Definition at line 1105 of file core_armv81mml.h.
◆ [] [8/14]
| __OM uint8_t { ... } ::u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
Definition at line 1151 of file core_cm55.h.
◆ [] [9/14]
| __OM uint8_t { ... } ::u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
Definition at line 1056 of file core_cm7.h.
◆ [] [10/14]
| __OM uint8_t { ... } ::u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
Definition at line 1147 of file core_cm85.h.
◆ [] [11/14]
| __OM uint8_t { ... } ::u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
Definition at line 752 of file core_sc300.h.
◆ [] [12/14]
| __OM uint8_t { ... } ::u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
Definition at line 1102 of file core_starmc1.h.
◆ [] [13/14]
| __OM uint8_t { ... } ::u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
Definition at line 1105 of file core_armv81mml.h.
◆ u8 [14/14]
| __OM uint8_t ITM_Type::u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
Definition at line 1105 of file core_armv81mml.h.
◆ [] [1/2]
| uint32_t { ... } ::UBTI_EN |
bit: 5 Unprivileged branch target identification enable
Definition at line 472 of file core_cm85.h.
◆ UBTI_EN [2/2]
| uint32_t CONTROL_Type::UBTI_EN |
bit: 5 Unprivileged branch target identification enable
Definition at line 472 of file core_cm85.h.
◆ [] [1/2]
| uint32_t { ... } ::UPAC_EN |
bit: 7 Unprivileged pointer authentication enable
Definition at line 474 of file core_cm85.h.
◆ UPAC_EN [2/2]
| uint32_t CONTROL_Type::UPAC_EN |
bit: 7 Unprivileged pointer authentication enable
Definition at line 474 of file core_cm85.h.
◆ [] [1/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 359 of file core_armv81mml.h.
◆ [] [2/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 352 of file core_cm33.h.
◆ [] [3/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 284 of file core_cm4.h.
◆ [] [4/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 222 of file core_cm3.h.
◆ [] [5/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 352 of file core_cm33.h.
◆ [] [6/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 352 of file core_cm35p.h.
◆ [] [7/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 284 of file core_cm4.h.
◆ [] [8/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 362 of file core_cm55.h.
◆ [] [9/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 299 of file core_cm7.h.
◆ [] [10/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 358 of file core_cm85.h.
◆ [] [11/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 222 of file core_sc300.h.
◆ [] [12/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 358 of file core_starmc1.h.
◆ [] [13/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 359 of file core_armv81mml.h.
◆ V [14/28]
| uint32_t APSR_Type::V |
bit: 28 Overflow condition code flag
Definition at line 359 of file core_armv81mml.h.
◆ [] [15/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 412 of file core_cm33.h.
◆ [] [16/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 345 of file core_cm4.h.
◆ [] [17/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 419 of file core_armv81mml.h.
◆ [] [18/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 279 of file core_cm3.h.
◆ [] [19/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 412 of file core_cm33.h.
◆ [] [20/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 412 of file core_cm35p.h.
◆ [] [21/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 345 of file core_cm4.h.
◆ [] [22/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 422 of file core_cm55.h.
◆ [] [23/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 360 of file core_cm7.h.
◆ [] [24/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 420 of file core_cm85.h.
◆ [] [25/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 279 of file core_sc300.h.
◆ [] [26/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 418 of file core_starmc1.h.
◆ [] [27/28]
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
Definition at line 419 of file core_armv81mml.h.
◆ V [28/28]
| uint32_t xPSR_Type::V |
bit: 28 Overflow condition code flag
Definition at line 419 of file core_armv81mml.h.
◆ VAL
| __IOM uint32_t SysTick_Type::VAL |
Offset: 0x008 (R/W) SysTick Current Value Register
Definition at line 1053 of file core_armv81mml.h.
◆ VMASK1
| __IOM uint32_t DWT_Type::VMASK1 |
Offset: 0x03C (R/W) Comparator Value Mask 1
Definition at line 1275 of file core_cm55.h.
◆ VMASK3
| __IOM uint32_t DWT_Type::VMASK3 |
Offset: 0x05C (R/W) Comparator Value Mask 3
Definition at line 1283 of file core_cm55.h.
◆ VTOR
| __IOM uint32_t SCB_Type::VTOR |
Offset: 0x008 (R/W) Vector Table Offset Register
Definition at line 538 of file core_armv81mml.h.
◆ w [1/4]
| uint32_t APSR_Type::w |
Type used for word access
Definition at line 364 of file core_armv81mml.h.
◆ w [2/4]
| uint32_t CONTROL_Type::w |
Type used for word access
Definition at line 469 of file core_armv81mml.h.
◆ w [3/4]
| uint32_t IPSR_Type::w |
Type used for word access
Definition at line 397 of file core_armv81mml.h.
◆ w [4/4]
| uint32_t xPSR_Type::w |
Type used for word access
Definition at line 424 of file core_armv81mml.h.
◆ [] [1/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 361 of file core_armv81mml.h.
◆ [] [2/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 354 of file core_cm33.h.
◆ [] [3/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 286 of file core_cm4.h.
◆ [] [4/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 224 of file core_cm3.h.
◆ [] [5/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 354 of file core_cm33.h.
◆ [] [6/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 354 of file core_cm35p.h.
◆ [] [7/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 286 of file core_cm4.h.
◆ [] [8/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 364 of file core_cm55.h.
◆ [] [9/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 301 of file core_cm7.h.
◆ [] [10/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 360 of file core_cm85.h.
◆ [] [11/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 224 of file core_sc300.h.
◆ [] [12/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 360 of file core_starmc1.h.
◆ [] [13/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 361 of file core_armv81mml.h.
◆ Z [14/28]
| uint32_t APSR_Type::Z |
bit: 30 Zero condition code flag
Definition at line 361 of file core_armv81mml.h.
◆ [] [15/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 414 of file core_cm33.h.
◆ [] [16/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 347 of file core_cm4.h.
◆ [] [17/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 421 of file core_armv81mml.h.
◆ [] [18/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 281 of file core_cm3.h.
◆ [] [19/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 414 of file core_cm33.h.
◆ [] [20/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 414 of file core_cm35p.h.
◆ [] [21/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 347 of file core_cm4.h.
◆ [] [22/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 424 of file core_cm55.h.
◆ [] [23/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 362 of file core_cm7.h.
◆ [] [24/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 422 of file core_cm85.h.
◆ [] [25/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 281 of file core_sc300.h.
◆ [] [26/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 420 of file core_starmc1.h.
◆ [] [27/28]
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
Definition at line 421 of file core_armv81mml.h.
◆ Z [28/28]
| uint32_t xPSR_Type::Z |
bit: 30 Zero condition code flag
Definition at line 421 of file core_armv81mml.h.
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