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Yet Another Hardware Abstraction Library
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Instrumentation Trace Macrocell (ITM)
Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » Implementation Control Block register (ICB) » System Tick Timer (SysTick)

Type definitions for the Instrumentation Trace Macrocell (ITM) More...

Topics

 Data Watchpoint and Trace (DWT)
 Type definitions for the Data Watchpoint and Trace (DWT)
 

Classes

struct  ITM_Type
 Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...
 
#define ITM_STIM_DISABLED_Pos   1U
 
#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)
 
#define ITM_STIM_FIFOREADY_Pos   0U
 
#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
 
#define ITM_TCR_STALLENA_Pos   5U
 
#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)
 
#define ITM_LSR_ByteAcc_Pos   2U
 
#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
 
#define ITM_LSR_Access_Pos   1U
 
#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
 
#define ITM_LSR_Present_Pos   0U
 
#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
 
#define ITM_STIM_DISABLED_Pos   1U
 
#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)
 
#define ITM_STIM_FIFOREADY_Pos   0U
 
#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
 
#define ITM_TCR_STALLENA_Pos   5U
 
#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)
 
#define ITM_LSR_ByteAcc_Pos   2U
 
#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
 
#define ITM_LSR_Access_Pos   1U
 
#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
 
#define ITM_LSR_Present_Pos   0U
 
#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
 
#define ITM_STIM_DISABLED_Pos   1U
 
#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)
 
#define ITM_STIM_FIFOREADY_Pos   0U
 
#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
 
#define ITM_TCR_STALLENA_Pos   5U
 
#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)
 
#define ITM_LSR_ByteAcc_Pos   2U
 
#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
 
#define ITM_LSR_Access_Pos   1U
 
#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
 
#define ITM_LSR_Present_Pos   0U
 
#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
 
#define ITM_STIM_DISABLED_Pos   1U
 
#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)
 
#define ITM_STIM_FIFOREADY_Pos   0U
 
#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
 
#define ITM_TCR_STALLENA_Pos   5U
 
#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)
 
#define ITM_LSR_ByteAcc_Pos   2U
 
#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
 
#define ITM_LSR_Access_Pos   1U
 
#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
 
#define ITM_LSR_Present_Pos   0U
 
#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
 
#define ITM_STIM_DISABLED_Pos   1U
 
#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)
 
#define ITM_STIM_FIFOREADY_Pos   0U
 
#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
 
#define ITM_TCR_STALLENA_Pos   5U
 
#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)
 
#define ITM_STIM_DISABLED_Pos   1U
 
#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)
 
#define ITM_STIM_FIFOREADY_Pos   0U
 
#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
 
#define ITM_TCR_STALLENA_Pos   5U
 
#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)
 
#define ITM_STIM_DISABLED_Pos   1U
 
#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)
 
#define ITM_STIM_FIFOREADY_Pos   0U
 
#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
 
#define ITM_TCR_STALLENA_Pos   5U
 
#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)
 
#define ITM_LSR_ByteAcc_Pos   2U
 
#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
 
#define ITM_LSR_Access_Pos   1U
 
#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
 
#define ITM_LSR_Present_Pos   0U
 
#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
 
#define ITM_STIM_DISABLED_Pos   1U
 
#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)
 
#define ITM_STIM_FIFOREADY_Pos   0U
 
#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
 
#define ITM_TCR_STALLENA_Pos   5U
 
#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)
 
#define ITM_LSR_ByteAcc_Pos   2U
 
#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
 
#define ITM_LSR_Access_Pos   1U
 
#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
 
#define ITM_LSR_Present_Pos   0U
 
#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
 
#define ITM_STIM_DISABLED_Pos   1U
 
#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)
 
#define ITM_STIM_FIFOREADY_Pos   0U
 
#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
 
#define ITM_TCR_STALLENA_Pos   5U
 
#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)
 
#define ITM_LSR_ByteAcc_Pos   2U
 
#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
 
#define ITM_LSR_Access_Pos   1U
 
#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
 
#define ITM_LSR_Present_Pos   0U
 
#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
 
#define ITM_STIM_DISABLED_Pos   1U
 
#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)
 
#define ITM_STIM_FIFOREADY_Pos   0U
 
#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
 
#define ITM_TCR_STALLENA_Pos   5U
 
#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)
 
#define ITM_LSR_ByteAcc_Pos   2U
 
#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
 
#define ITM_LSR_Access_Pos   1U
 
#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
 
#define ITM_LSR_Present_Pos   0U
 
#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
 
#define ITM_TPR_PRIVMASK_Pos   0U
 
#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
 
#define ITM_TCR_BUSY_Pos   23U
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TRACEBUSID_Pos   16U
 
#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10U
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPRESCALE_Pos   8U
 
#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
 
#define ITM_TCR_SWOENA_Pos   4U
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3U
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2U
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1U
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0U
 
#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
 
#define ITM_TPR_PRIVMASK_Pos   0U
 
#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
 
#define ITM_TCR_BUSY_Pos   23U
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TRACEBUSID_Pos   16U
 
#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10U
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPRESCALE_Pos   8U
 
#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
 
#define ITM_TCR_SWOENA_Pos   4U
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3U
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2U
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1U
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0U
 
#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
 
#define ITM_TPR_PRIVMASK_Pos   0U
 
#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
 
#define ITM_TCR_BUSY_Pos   23U
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TRACEBUSID_Pos   16U
 
#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10U
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPRESCALE_Pos   8U
 
#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
 
#define ITM_TCR_SWOENA_Pos   4U
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3U
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2U
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1U
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0U
 
#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
 
#define ITM_LSR_BYTEACC_Pos   2U
 
#define ITM_LSR_BYTEACC_Msk   (1UL << ITM_LSR_BYTEACC_Pos)
 
#define ITM_LSR_ACCESS_Pos   1U
 
#define ITM_LSR_ACCESS_Msk   (1UL << ITM_LSR_ACCESS_Pos)
 
#define ITM_LSR_PRESENT_Pos   0U
 
#define ITM_LSR_PRESENT_Msk   (1UL /*<< ITM_LSR_PRESENT_Pos*/)
 
#define ITM_TPR_PRIVMASK_Pos   0U
 
#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
 
#define ITM_TCR_BUSY_Pos   23U
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TRACEBUSID_Pos   16U
 
#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10U
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPRESCALE_Pos   8U
 
#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
 
#define ITM_TCR_SWOENA_Pos   4U
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3U
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2U
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1U
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0U
 
#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
 
#define ITM_TPR_PRIVMASK_Pos   0U
 
#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
 
#define ITM_TCR_BUSY_Pos   23U
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TRACEBUSID_Pos   16U
 
#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10U
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPRESCALE_Pos   8U
 
#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
 
#define ITM_TCR_SWOENA_Pos   4U
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3U
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2U
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1U
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0U
 
#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
 
#define ITM_TPR_PRIVMASK_Pos   0U
 
#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
 
#define ITM_TCR_BUSY_Pos   23U
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TRACEBUSID_Pos   16U
 
#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10U
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPRESCALE_Pos   8U
 
#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
 
#define ITM_TCR_SWOENA_Pos   4U
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3U
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2U
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1U
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0U
 
#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
 
#define ITM_LSR_BYTEACC_Pos   2U
 
#define ITM_LSR_BYTEACC_Msk   (1UL << ITM_LSR_BYTEACC_Pos)
 
#define ITM_LSR_ACCESS_Pos   1U
 
#define ITM_LSR_ACCESS_Msk   (1UL << ITM_LSR_ACCESS_Pos)
 
#define ITM_LSR_PRESENT_Pos   0U
 
#define ITM_LSR_PRESENT_Msk   (1UL /*<< ITM_LSR_PRESENT_Pos*/)
 
#define ITM_TPR_PRIVMASK_Pos   0U
 
#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
 
#define ITM_TCR_BUSY_Pos   23U
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TRACEBUSID_Pos   16U
 
#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10U
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPRESCALE_Pos   8U
 
#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
 
#define ITM_TCR_SWOENA_Pos   4U
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3U
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2U
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1U
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0U
 
#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
 
#define ITM_TPR_PRIVMASK_Pos   0U
 
#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
 
#define ITM_TCR_BUSY_Pos   23U
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TRACEBUSID_Pos   16U
 
#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10U
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPRESCALE_Pos   8U
 
#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
 
#define ITM_TCR_SWOENA_Pos   4U
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3U
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2U
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1U
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0U
 
#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
 
#define ITM_LSR_BYTEACC_Pos   2U
 
#define ITM_LSR_BYTEACC_Msk   (1UL << ITM_LSR_BYTEACC_Pos)
 
#define ITM_LSR_ACCESS_Pos   1U
 
#define ITM_LSR_ACCESS_Msk   (1UL << ITM_LSR_ACCESS_Pos)
 
#define ITM_LSR_PRESENT_Pos   0U
 
#define ITM_LSR_PRESENT_Msk   (1UL /*<< ITM_LSR_PRESENT_Pos*/)
 
#define ITM_TPR_PRIVMASK_Pos   0U
 
#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
 
#define ITM_TCR_BUSY_Pos   23U
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TRACEBUSID_Pos   16U
 
#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10U
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPRESCALE_Pos   8U
 
#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
 
#define ITM_TCR_SWOENA_Pos   4U
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3U
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2U
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1U
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0U
 
#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
 
#define ITM_TPR_PRIVMASK_Pos   0U
 
#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
 
#define ITM_TCR_BUSY_Pos   23U
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TRACEBUSID_Pos   16U
 
#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10U
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPRESCALE_Pos   8U
 
#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
 
#define ITM_TCR_SWOENA_Pos   4U
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3U
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2U
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1U
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0U
 
#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
 
#define ITM_LSR_BYTEACC_Pos   2U
 
#define ITM_LSR_BYTEACC_Msk   (1UL << ITM_LSR_BYTEACC_Pos)
 
#define ITM_LSR_ACCESS_Pos   1U
 
#define ITM_LSR_ACCESS_Msk   (1UL << ITM_LSR_ACCESS_Pos)
 
#define ITM_LSR_PRESENT_Pos   0U
 
#define ITM_LSR_PRESENT_Msk   (1UL /*<< ITM_LSR_PRESENT_Pos*/)
 
#define ITM_TPR_PRIVMASK_Pos   0U
 
#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
 
#define ITM_TCR_BUSY_Pos   23U
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TRACEBUSID_Pos   16U
 
#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10U
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPRESCALE_Pos   8U
 
#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
 
#define ITM_TCR_SWOENA_Pos   4U
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3U
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2U
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1U
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0U
 
#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
 
#define ITM_TPR_PRIVMASK_Pos   0U
 
#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
 
#define ITM_TCR_BUSY_Pos   23U
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TRACEBUSID_Pos   16U
 
#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10U
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPRESCALE_Pos   8U
 
#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
 
#define ITM_TCR_SWOENA_Pos   4U
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3U
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2U
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1U
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0U
 
#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
 
#define ITM_TPR_PRIVMASK_Pos   0U
 
#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
 
#define ITM_TCR_BUSY_Pos   23U
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TRACEBUSID_Pos   16U
 
#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10U
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPRESCALE_Pos   8U
 
#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
 
#define ITM_TCR_SWOENA_Pos   4U
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3U
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2U
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1U
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0U
 
#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
 
#define ITM_TPR_PRIVMASK_Pos   0U
 
#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
 
#define ITM_TCR_BUSY_Pos   23U
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TRACEBUSID_Pos   16U
 
#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10U
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPRESCALE_Pos   8U
 
#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
 
#define ITM_TCR_SWOENA_Pos   4U
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3U
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2U
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1U
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0U
 
#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
 
#define ITM_TPR_PRIVMASK_Pos   0U
 
#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
 
#define ITM_TCR_BUSY_Pos   23U
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TRACEBUSID_Pos   16U
 
#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10U
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPRESCALE_Pos   8U
 
#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
 
#define ITM_TCR_SWOENA_Pos   4U
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3U
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2U
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1U
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0U
 
#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
 
#define ITM_LSR_BYTEACC_Pos   2U
 
#define ITM_LSR_BYTEACC_Msk   (1UL << ITM_LSR_BYTEACC_Pos)
 
#define ITM_LSR_ACCESS_Pos   1U
 
#define ITM_LSR_ACCESS_Msk   (1UL << ITM_LSR_ACCESS_Pos)
 
#define ITM_LSR_PRESENT_Pos   0U
 
#define ITM_LSR_PRESENT_Msk   (1UL /*<< ITM_LSR_PRESENT_Pos*/)
 
#define ITM_ITREAD_AFVALID_Pos   1U
 
#define ITM_ITREAD_AFVALID_Msk   (0x1UL << ITM_ITREAD_AFVALID_Pos)
 
#define ITM_ITREAD_ATREADY_Pos   0U
 
#define ITM_ITREAD_ATREADY_Msk   (0x1UL /*<< ITM_ITREAD_ATREADY_Pos*/)
 
#define ITM_ITWRITE_AFVALID_Pos   1U
 
#define ITM_ITWRITE_AFVALID_Msk   (0x1UL << ITM_ITWRITE_AFVALID_Pos)
 
#define ITM_ITWRITE_ATREADY_Pos   0U
 
#define ITM_ITWRITE_ATREADY_Msk   (0x1UL /*<< ITM_ITWRITE_ATREADY_Pos*/)
 
#define ITM_ITCTRL_IME_Pos   0U
 
#define ITM_ITCTRL_IME_Msk   (0x1UL /*<< ITM_ITCTRL_IME_Pos*/)
 
#define ITM_ITREAD_AFVALID_Pos   1U
 
#define ITM_ITREAD_AFVALID_Msk   (0x1UL << ITM_ITREAD_AFVALID_Pos)
 
#define ITM_ITREAD_ATREADY_Pos   0U
 
#define ITM_ITREAD_ATREADY_Msk   (0x1UL /*<< ITM_ITREAD_ATREADY_Pos*/)
 
#define ITM_ITWRITE_AFVALID_Pos   1U
 
#define ITM_ITWRITE_AFVALID_Msk   (0x1UL << ITM_ITWRITE_AFVALID_Pos)
 
#define ITM_ITWRITE_ATREADY_Pos   0U
 
#define ITM_ITWRITE_ATREADY_Msk   (0x1UL /*<< ITM_ITWRITE_ATREADY_Pos*/)
 
#define ITM_ITCTRL_IME_Pos   0U
 
#define ITM_ITCTRL_IME_Msk   (0x1UL /*<< ITM_ITCTRL_IME_Pos*/)
 

Detailed Description

Type definitions for the Instrumentation Trace Macrocell (ITM)

Macro Definition Documentation

◆ ITM_ITCTRL_IME_Msk [1/2]

#define ITM_ITCTRL_IME_Msk   (0x1UL /*<< ITM_ITCTRL_IME_Pos*/)

ITM ITCTRL: IME Mask

Definition at line 1243 of file core_cm55.h.

◆ ITM_ITCTRL_IME_Msk [2/2]

#define ITM_ITCTRL_IME_Msk   (0x1UL /*<< ITM_ITCTRL_IME_Pos*/)

ITM ITCTRL: IME Mask

Definition at line 1239 of file core_cm85.h.

◆ ITM_ITCTRL_IME_Pos [1/2]

#define ITM_ITCTRL_IME_Pos   0U

ITM ITCTRL: IME Position

Definition at line 1242 of file core_cm55.h.

◆ ITM_ITCTRL_IME_Pos [2/2]

#define ITM_ITCTRL_IME_Pos   0U

ITM ITCTRL: IME Position

Definition at line 1238 of file core_cm85.h.

◆ ITM_ITREAD_AFVALID_Msk [1/2]

#define ITM_ITREAD_AFVALID_Msk   (0x1UL << ITM_ITREAD_AFVALID_Pos)

ITM ITREAD: AFVALID Mask

Definition at line 1229 of file core_cm55.h.

◆ ITM_ITREAD_AFVALID_Msk [2/2]

#define ITM_ITREAD_AFVALID_Msk   (0x1UL << ITM_ITREAD_AFVALID_Pos)

ITM ITREAD: AFVALID Mask

Definition at line 1225 of file core_cm85.h.

◆ ITM_ITREAD_AFVALID_Pos [1/2]

#define ITM_ITREAD_AFVALID_Pos   1U

ITM ITREAD: AFVALID Position

Definition at line 1228 of file core_cm55.h.

◆ ITM_ITREAD_AFVALID_Pos [2/2]

#define ITM_ITREAD_AFVALID_Pos   1U

ITM ITREAD: AFVALID Position

Definition at line 1224 of file core_cm85.h.

◆ ITM_ITREAD_ATREADY_Msk [1/2]

#define ITM_ITREAD_ATREADY_Msk   (0x1UL /*<< ITM_ITREAD_ATREADY_Pos*/)

ITM ITREAD: ATREADY Mask

Definition at line 1232 of file core_cm55.h.

◆ ITM_ITREAD_ATREADY_Msk [2/2]

#define ITM_ITREAD_ATREADY_Msk   (0x1UL /*<< ITM_ITREAD_ATREADY_Pos*/)

ITM ITREAD: ATREADY Mask

Definition at line 1228 of file core_cm85.h.

◆ ITM_ITREAD_ATREADY_Pos [1/2]

#define ITM_ITREAD_ATREADY_Pos   0U

ITM ITREAD: ATREADY Position

Definition at line 1231 of file core_cm55.h.

◆ ITM_ITREAD_ATREADY_Pos [2/2]

#define ITM_ITREAD_ATREADY_Pos   0U

ITM ITREAD: ATREADY Position

Definition at line 1227 of file core_cm85.h.

◆ ITM_ITWRITE_AFVALID_Msk [1/2]

#define ITM_ITWRITE_AFVALID_Msk   (0x1UL << ITM_ITWRITE_AFVALID_Pos)

ITM ITWRITE: AFVALID Mask

Definition at line 1236 of file core_cm55.h.

◆ ITM_ITWRITE_AFVALID_Msk [2/2]

#define ITM_ITWRITE_AFVALID_Msk   (0x1UL << ITM_ITWRITE_AFVALID_Pos)

ITM ITWRITE: AFVALID Mask

Definition at line 1232 of file core_cm85.h.

◆ ITM_ITWRITE_AFVALID_Pos [1/2]

#define ITM_ITWRITE_AFVALID_Pos   1U

ITM ITWRITE: AFVALID Position

Definition at line 1235 of file core_cm55.h.

◆ ITM_ITWRITE_AFVALID_Pos [2/2]

#define ITM_ITWRITE_AFVALID_Pos   1U

ITM ITWRITE: AFVALID Position

Definition at line 1231 of file core_cm85.h.

◆ ITM_ITWRITE_ATREADY_Msk [1/2]

#define ITM_ITWRITE_ATREADY_Msk   (0x1UL /*<< ITM_ITWRITE_ATREADY_Pos*/)

ITM ITWRITE: ATREADY Mask

Definition at line 1239 of file core_cm55.h.

◆ ITM_ITWRITE_ATREADY_Msk [2/2]

#define ITM_ITWRITE_ATREADY_Msk   (0x1UL /*<< ITM_ITWRITE_ATREADY_Pos*/)

ITM ITWRITE: ATREADY Mask

Definition at line 1235 of file core_cm85.h.

◆ ITM_ITWRITE_ATREADY_Pos [1/2]

#define ITM_ITWRITE_ATREADY_Pos   0U

ITM ITWRITE: ATREADY Position

Definition at line 1238 of file core_cm55.h.

◆ ITM_ITWRITE_ATREADY_Pos [2/2]

#define ITM_ITWRITE_ATREADY_Pos   0U

ITM ITWRITE: ATREADY Position

Definition at line 1234 of file core_cm85.h.

◆ ITM_LSR_ACCESS_Msk [1/5]

#define ITM_LSR_ACCESS_Msk   (1UL << ITM_LSR_ACCESS_Pos)

ITM LSR: Access Mask

Definition at line 833 of file core_cm3.h.

◆ ITM_LSR_ACCESS_Msk [2/5]

#define ITM_LSR_ACCESS_Msk   (1UL << ITM_LSR_ACCESS_Pos)

ITM LSR: Access Mask

Definition at line 898 of file core_cm4.h.

◆ ITM_LSR_ACCESS_Msk [3/5]

#define ITM_LSR_ACCESS_Msk   (1UL << ITM_LSR_ACCESS_Pos)

ITM LSR: Access Mask

Definition at line 1122 of file core_cm7.h.

◆ ITM_LSR_ACCESS_Msk [4/5]

#define ITM_LSR_ACCESS_Msk   (1UL << ITM_LSR_ACCESS_Pos)

ITM LSR: Access Mask

Definition at line 818 of file core_sc300.h.

◆ ITM_LSR_ACCESS_Msk [5/5]

#define ITM_LSR_ACCESS_Msk   (1UL << ITM_LSR_ACCESS_Pos)

ITM LSR: Access Mask

Definition at line 898 of file core_cm4.h.

◆ ITM_LSR_Access_Msk [1/8]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1184 of file core_armv81mml.h.

◆ ITM_LSR_Access_Msk [2/8]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1122 of file core_armv8mml.h.

◆ ITM_LSR_Access_Msk [3/8]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1122 of file core_cm33.h.

◆ ITM_LSR_Access_Msk [4/8]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1122 of file core_cm35p.h.

◆ ITM_LSR_Access_Msk [5/8]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1180 of file core_starmc1.h.

◆ ITM_LSR_Access_Msk [6/8]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1184 of file core_armv81mml.h.

◆ ITM_LSR_Access_Msk [7/8]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1122 of file core_armv8mml.h.

◆ ITM_LSR_Access_Msk [8/8]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1122 of file core_cm33.h.

◆ ITM_LSR_ACCESS_Pos [1/5]

#define ITM_LSR_ACCESS_Pos   1U

ITM LSR: Access Position

Definition at line 832 of file core_cm3.h.

◆ ITM_LSR_ACCESS_Pos [2/5]

#define ITM_LSR_ACCESS_Pos   1U

ITM LSR: Access Position

Definition at line 897 of file core_cm4.h.

◆ ITM_LSR_ACCESS_Pos [3/5]

#define ITM_LSR_ACCESS_Pos   1U

ITM LSR: Access Position

Definition at line 1121 of file core_cm7.h.

◆ ITM_LSR_ACCESS_Pos [4/5]

#define ITM_LSR_ACCESS_Pos   1U

ITM LSR: Access Position

Definition at line 817 of file core_sc300.h.

◆ ITM_LSR_ACCESS_Pos [5/5]

#define ITM_LSR_ACCESS_Pos   1U

ITM LSR: Access Position

Definition at line 897 of file core_cm4.h.

◆ ITM_LSR_Access_Pos [1/8]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position

Definition at line 1183 of file core_armv81mml.h.

◆ ITM_LSR_Access_Pos [2/8]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position

Definition at line 1121 of file core_armv8mml.h.

◆ ITM_LSR_Access_Pos [3/8]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position

Definition at line 1121 of file core_cm33.h.

◆ ITM_LSR_Access_Pos [4/8]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position

Definition at line 1121 of file core_cm35p.h.

◆ ITM_LSR_Access_Pos [5/8]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position

Definition at line 1179 of file core_starmc1.h.

◆ ITM_LSR_Access_Pos [6/8]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position

Definition at line 1183 of file core_armv81mml.h.

◆ ITM_LSR_Access_Pos [7/8]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position

Definition at line 1121 of file core_armv8mml.h.

◆ ITM_LSR_Access_Pos [8/8]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position

Definition at line 1121 of file core_cm33.h.

◆ ITM_LSR_BYTEACC_Msk [1/5]

#define ITM_LSR_BYTEACC_Msk   (1UL << ITM_LSR_BYTEACC_Pos)

ITM LSR: ByteAcc Mask

Definition at line 830 of file core_cm3.h.

◆ ITM_LSR_BYTEACC_Msk [2/5]

#define ITM_LSR_BYTEACC_Msk   (1UL << ITM_LSR_BYTEACC_Pos)

ITM LSR: ByteAcc Mask

Definition at line 895 of file core_cm4.h.

◆ ITM_LSR_BYTEACC_Msk [3/5]

#define ITM_LSR_BYTEACC_Msk   (1UL << ITM_LSR_BYTEACC_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1119 of file core_cm7.h.

◆ ITM_LSR_BYTEACC_Msk [4/5]

#define ITM_LSR_BYTEACC_Msk   (1UL << ITM_LSR_BYTEACC_Pos)

ITM LSR: ByteAcc Mask

Definition at line 815 of file core_sc300.h.

◆ ITM_LSR_BYTEACC_Msk [5/5]

#define ITM_LSR_BYTEACC_Msk   (1UL << ITM_LSR_BYTEACC_Pos)

ITM LSR: ByteAcc Mask

Definition at line 895 of file core_cm4.h.

◆ ITM_LSR_ByteAcc_Msk [1/8]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1181 of file core_armv81mml.h.

◆ ITM_LSR_ByteAcc_Msk [2/8]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1119 of file core_armv8mml.h.

◆ ITM_LSR_ByteAcc_Msk [3/8]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1119 of file core_cm33.h.

◆ ITM_LSR_ByteAcc_Msk [4/8]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1119 of file core_cm35p.h.

◆ ITM_LSR_ByteAcc_Msk [5/8]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1177 of file core_starmc1.h.

◆ ITM_LSR_ByteAcc_Msk [6/8]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1181 of file core_armv81mml.h.

◆ ITM_LSR_ByteAcc_Msk [7/8]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1119 of file core_armv8mml.h.

◆ ITM_LSR_ByteAcc_Msk [8/8]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1119 of file core_cm33.h.

◆ ITM_LSR_BYTEACC_Pos [1/5]

#define ITM_LSR_BYTEACC_Pos   2U

ITM LSR: ByteAcc Position

Definition at line 829 of file core_cm3.h.

◆ ITM_LSR_BYTEACC_Pos [2/5]

#define ITM_LSR_BYTEACC_Pos   2U

ITM LSR: ByteAcc Position

Definition at line 894 of file core_cm4.h.

◆ ITM_LSR_BYTEACC_Pos [3/5]

#define ITM_LSR_BYTEACC_Pos   2U

ITM LSR: ByteAcc Position

Definition at line 1118 of file core_cm7.h.

◆ ITM_LSR_BYTEACC_Pos [4/5]

#define ITM_LSR_BYTEACC_Pos   2U

ITM LSR: ByteAcc Position

Definition at line 814 of file core_sc300.h.

◆ ITM_LSR_BYTEACC_Pos [5/5]

#define ITM_LSR_BYTEACC_Pos   2U

ITM LSR: ByteAcc Position

Definition at line 894 of file core_cm4.h.

◆ ITM_LSR_ByteAcc_Pos [1/8]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position

Definition at line 1180 of file core_armv81mml.h.

◆ ITM_LSR_ByteAcc_Pos [2/8]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position

Definition at line 1118 of file core_armv8mml.h.

◆ ITM_LSR_ByteAcc_Pos [3/8]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position

Definition at line 1118 of file core_cm33.h.

◆ ITM_LSR_ByteAcc_Pos [4/8]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position

Definition at line 1118 of file core_cm35p.h.

◆ ITM_LSR_ByteAcc_Pos [5/8]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position

Definition at line 1176 of file core_starmc1.h.

◆ ITM_LSR_ByteAcc_Pos [6/8]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position

Definition at line 1180 of file core_armv81mml.h.

◆ ITM_LSR_ByteAcc_Pos [7/8]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position

Definition at line 1118 of file core_armv8mml.h.

◆ ITM_LSR_ByteAcc_Pos [8/8]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position

Definition at line 1118 of file core_cm33.h.

◆ ITM_LSR_PRESENT_Msk [1/5]

#define ITM_LSR_PRESENT_Msk   (1UL /*<< ITM_LSR_PRESENT_Pos*/)

ITM LSR: Present Mask

Definition at line 836 of file core_cm3.h.

◆ ITM_LSR_PRESENT_Msk [2/5]

#define ITM_LSR_PRESENT_Msk   (1UL /*<< ITM_LSR_PRESENT_Pos*/)

ITM LSR: Present Mask

Definition at line 901 of file core_cm4.h.

◆ ITM_LSR_PRESENT_Msk [3/5]

#define ITM_LSR_PRESENT_Msk   (1UL /*<< ITM_LSR_PRESENT_Pos*/)

ITM LSR: Present Mask

Definition at line 1125 of file core_cm7.h.

◆ ITM_LSR_PRESENT_Msk [4/5]

#define ITM_LSR_PRESENT_Msk   (1UL /*<< ITM_LSR_PRESENT_Pos*/)

ITM LSR: Present Mask

Definition at line 821 of file core_sc300.h.

◆ ITM_LSR_PRESENT_Msk [5/5]

#define ITM_LSR_PRESENT_Msk   (1UL /*<< ITM_LSR_PRESENT_Pos*/)

ITM LSR: Present Mask

Definition at line 901 of file core_cm4.h.

◆ ITM_LSR_Present_Msk [1/8]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1187 of file core_armv81mml.h.

◆ ITM_LSR_Present_Msk [2/8]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1125 of file core_armv8mml.h.

◆ ITM_LSR_Present_Msk [3/8]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1125 of file core_cm33.h.

◆ ITM_LSR_Present_Msk [4/8]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1125 of file core_cm35p.h.

◆ ITM_LSR_Present_Msk [5/8]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1183 of file core_starmc1.h.

◆ ITM_LSR_Present_Msk [6/8]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1187 of file core_armv81mml.h.

◆ ITM_LSR_Present_Msk [7/8]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1125 of file core_armv8mml.h.

◆ ITM_LSR_Present_Msk [8/8]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1125 of file core_cm33.h.

◆ ITM_LSR_PRESENT_Pos [1/5]

#define ITM_LSR_PRESENT_Pos   0U

ITM LSR: Present Position

Definition at line 835 of file core_cm3.h.

◆ ITM_LSR_PRESENT_Pos [2/5]

#define ITM_LSR_PRESENT_Pos   0U

ITM LSR: Present Position

Definition at line 900 of file core_cm4.h.

◆ ITM_LSR_PRESENT_Pos [3/5]

#define ITM_LSR_PRESENT_Pos   0U

ITM LSR: Present Position

Definition at line 1124 of file core_cm7.h.

◆ ITM_LSR_PRESENT_Pos [4/5]

#define ITM_LSR_PRESENT_Pos   0U

ITM LSR: Present Position

Definition at line 820 of file core_sc300.h.

◆ ITM_LSR_PRESENT_Pos [5/5]

#define ITM_LSR_PRESENT_Pos   0U

ITM LSR: Present Position

Definition at line 900 of file core_cm4.h.

◆ ITM_LSR_Present_Pos [1/8]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position

Definition at line 1186 of file core_armv81mml.h.

◆ ITM_LSR_Present_Pos [2/8]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position

Definition at line 1124 of file core_armv8mml.h.

◆ ITM_LSR_Present_Pos [3/8]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position

Definition at line 1124 of file core_cm33.h.

◆ ITM_LSR_Present_Pos [4/8]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position

Definition at line 1124 of file core_cm35p.h.

◆ ITM_LSR_Present_Pos [5/8]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position

Definition at line 1182 of file core_starmc1.h.

◆ ITM_LSR_Present_Pos [6/8]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position

Definition at line 1186 of file core_armv81mml.h.

◆ ITM_LSR_Present_Pos [7/8]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position

Definition at line 1124 of file core_armv8mml.h.

◆ ITM_LSR_Present_Pos [8/8]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position

Definition at line 1124 of file core_cm33.h.

◆ ITM_STIM_DISABLED_Msk [1/10]

#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1139 of file core_armv81mml.h.

◆ ITM_STIM_DISABLED_Msk [2/10]

#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1077 of file core_armv8mml.h.

◆ ITM_STIM_DISABLED_Msk [3/10]

#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1077 of file core_cm33.h.

◆ ITM_STIM_DISABLED_Msk [4/10]

#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1077 of file core_cm35p.h.

◆ ITM_STIM_DISABLED_Msk [5/10]

#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1187 of file core_cm55.h.

◆ ITM_STIM_DISABLED_Msk [6/10]

#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1183 of file core_cm85.h.

◆ ITM_STIM_DISABLED_Msk [7/10]

#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1135 of file core_starmc1.h.

◆ ITM_STIM_DISABLED_Msk [8/10]

#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1139 of file core_armv81mml.h.

◆ ITM_STIM_DISABLED_Msk [9/10]

#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1077 of file core_armv8mml.h.

◆ ITM_STIM_DISABLED_Msk [10/10]

#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1077 of file core_cm33.h.

◆ ITM_STIM_DISABLED_Pos [1/10]

#define ITM_STIM_DISABLED_Pos   1U

ITM STIM: DISABLED Position

Definition at line 1138 of file core_armv81mml.h.

◆ ITM_STIM_DISABLED_Pos [2/10]

#define ITM_STIM_DISABLED_Pos   1U

ITM STIM: DISABLED Position

Definition at line 1076 of file core_armv8mml.h.

◆ ITM_STIM_DISABLED_Pos [3/10]

#define ITM_STIM_DISABLED_Pos   1U

ITM STIM: DISABLED Position

Definition at line 1076 of file core_cm33.h.

◆ ITM_STIM_DISABLED_Pos [4/10]

#define ITM_STIM_DISABLED_Pos   1U

ITM STIM: DISABLED Position

Definition at line 1076 of file core_cm35p.h.

◆ ITM_STIM_DISABLED_Pos [5/10]

#define ITM_STIM_DISABLED_Pos   1U

ITM STIM: DISABLED Position

Definition at line 1186 of file core_cm55.h.

◆ ITM_STIM_DISABLED_Pos [6/10]

#define ITM_STIM_DISABLED_Pos   1U

ITM STIM: DISABLED Position

Definition at line 1182 of file core_cm85.h.

◆ ITM_STIM_DISABLED_Pos [7/10]

#define ITM_STIM_DISABLED_Pos   1U

ITM STIM: DISABLED Position

Definition at line 1134 of file core_starmc1.h.

◆ ITM_STIM_DISABLED_Pos [8/10]

#define ITM_STIM_DISABLED_Pos   1U

ITM STIM: DISABLED Position

Definition at line 1138 of file core_armv81mml.h.

◆ ITM_STIM_DISABLED_Pos [9/10]

#define ITM_STIM_DISABLED_Pos   1U

ITM STIM: DISABLED Position

Definition at line 1076 of file core_armv8mml.h.

◆ ITM_STIM_DISABLED_Pos [10/10]

#define ITM_STIM_DISABLED_Pos   1U

ITM STIM: DISABLED Position

Definition at line 1076 of file core_cm33.h.

◆ ITM_STIM_FIFOREADY_Msk [1/10]

#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1142 of file core_armv81mml.h.

◆ ITM_STIM_FIFOREADY_Msk [2/10]

#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1080 of file core_armv8mml.h.

◆ ITM_STIM_FIFOREADY_Msk [3/10]

#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1080 of file core_cm33.h.

◆ ITM_STIM_FIFOREADY_Msk [4/10]

#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1080 of file core_cm35p.h.

◆ ITM_STIM_FIFOREADY_Msk [5/10]

#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1190 of file core_cm55.h.

◆ ITM_STIM_FIFOREADY_Msk [6/10]

#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1186 of file core_cm85.h.

◆ ITM_STIM_FIFOREADY_Msk [7/10]

#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1138 of file core_starmc1.h.

◆ ITM_STIM_FIFOREADY_Msk [8/10]

#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1142 of file core_armv81mml.h.

◆ ITM_STIM_FIFOREADY_Msk [9/10]

#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1080 of file core_armv8mml.h.

◆ ITM_STIM_FIFOREADY_Msk [10/10]

#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1080 of file core_cm33.h.

◆ ITM_STIM_FIFOREADY_Pos [1/10]

#define ITM_STIM_FIFOREADY_Pos   0U

ITM STIM: FIFOREADY Position

Definition at line 1141 of file core_armv81mml.h.

◆ ITM_STIM_FIFOREADY_Pos [2/10]

#define ITM_STIM_FIFOREADY_Pos   0U

ITM STIM: FIFOREADY Position

Definition at line 1079 of file core_armv8mml.h.

◆ ITM_STIM_FIFOREADY_Pos [3/10]

#define ITM_STIM_FIFOREADY_Pos   0U

ITM STIM: FIFOREADY Position

Definition at line 1079 of file core_cm33.h.

◆ ITM_STIM_FIFOREADY_Pos [4/10]

#define ITM_STIM_FIFOREADY_Pos   0U

ITM STIM: FIFOREADY Position

Definition at line 1079 of file core_cm35p.h.

◆ ITM_STIM_FIFOREADY_Pos [5/10]

#define ITM_STIM_FIFOREADY_Pos   0U

ITM STIM: FIFOREADY Position

Definition at line 1189 of file core_cm55.h.

◆ ITM_STIM_FIFOREADY_Pos [6/10]

#define ITM_STIM_FIFOREADY_Pos   0U

ITM STIM: FIFOREADY Position

Definition at line 1185 of file core_cm85.h.

◆ ITM_STIM_FIFOREADY_Pos [7/10]

#define ITM_STIM_FIFOREADY_Pos   0U

ITM STIM: FIFOREADY Position

Definition at line 1137 of file core_starmc1.h.

◆ ITM_STIM_FIFOREADY_Pos [8/10]

#define ITM_STIM_FIFOREADY_Pos   0U

ITM STIM: FIFOREADY Position

Definition at line 1141 of file core_armv81mml.h.

◆ ITM_STIM_FIFOREADY_Pos [9/10]

#define ITM_STIM_FIFOREADY_Pos   0U

ITM STIM: FIFOREADY Position

Definition at line 1079 of file core_armv8mml.h.

◆ ITM_STIM_FIFOREADY_Pos [10/10]

#define ITM_STIM_FIFOREADY_Pos   0U

ITM STIM: FIFOREADY Position

Definition at line 1079 of file core_cm33.h.

◆ ITM_TCR_BUSY_Msk [1/15]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1150 of file core_armv81mml.h.

◆ ITM_TCR_BUSY_Msk [2/15]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1088 of file core_armv8mml.h.

◆ ITM_TCR_BUSY_Msk [3/15]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 802 of file core_cm3.h.

◆ ITM_TCR_BUSY_Msk [4/15]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1088 of file core_cm33.h.

◆ ITM_TCR_BUSY_Msk [5/15]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1088 of file core_cm35p.h.

◆ ITM_TCR_BUSY_Msk [6/15]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 867 of file core_cm4.h.

◆ ITM_TCR_BUSY_Msk [7/15]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1198 of file core_cm55.h.

◆ ITM_TCR_BUSY_Msk [8/15]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1091 of file core_cm7.h.

◆ ITM_TCR_BUSY_Msk [9/15]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1194 of file core_cm85.h.

◆ ITM_TCR_BUSY_Msk [10/15]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 787 of file core_sc300.h.

◆ ITM_TCR_BUSY_Msk [11/15]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1146 of file core_starmc1.h.

◆ ITM_TCR_BUSY_Msk [12/15]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1150 of file core_armv81mml.h.

◆ ITM_TCR_BUSY_Msk [13/15]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1088 of file core_armv8mml.h.

◆ ITM_TCR_BUSY_Msk [14/15]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1088 of file core_cm33.h.

◆ ITM_TCR_BUSY_Msk [15/15]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 867 of file core_cm4.h.

◆ ITM_TCR_BUSY_Pos [1/15]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

Definition at line 1149 of file core_armv81mml.h.

◆ ITM_TCR_BUSY_Pos [2/15]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

Definition at line 1087 of file core_armv8mml.h.

◆ ITM_TCR_BUSY_Pos [3/15]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

Definition at line 801 of file core_cm3.h.

◆ ITM_TCR_BUSY_Pos [4/15]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

Definition at line 1087 of file core_cm33.h.

◆ ITM_TCR_BUSY_Pos [5/15]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

Definition at line 1087 of file core_cm35p.h.

◆ ITM_TCR_BUSY_Pos [6/15]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

Definition at line 866 of file core_cm4.h.

◆ ITM_TCR_BUSY_Pos [7/15]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

Definition at line 1197 of file core_cm55.h.

◆ ITM_TCR_BUSY_Pos [8/15]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

Definition at line 1090 of file core_cm7.h.

◆ ITM_TCR_BUSY_Pos [9/15]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

Definition at line 1193 of file core_cm85.h.

◆ ITM_TCR_BUSY_Pos [10/15]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

Definition at line 786 of file core_sc300.h.

◆ ITM_TCR_BUSY_Pos [11/15]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

Definition at line 1145 of file core_starmc1.h.

◆ ITM_TCR_BUSY_Pos [12/15]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

Definition at line 1149 of file core_armv81mml.h.

◆ ITM_TCR_BUSY_Pos [13/15]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

Definition at line 1087 of file core_armv8mml.h.

◆ ITM_TCR_BUSY_Pos [14/15]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

Definition at line 1087 of file core_cm33.h.

◆ ITM_TCR_BUSY_Pos [15/15]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

Definition at line 866 of file core_cm4.h.

◆ ITM_TCR_DWTENA_Msk [1/15]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1168 of file core_armv81mml.h.

◆ ITM_TCR_DWTENA_Msk [2/15]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1106 of file core_armv8mml.h.

◆ ITM_TCR_DWTENA_Msk [3/15]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 817 of file core_cm3.h.

◆ ITM_TCR_DWTENA_Msk [4/15]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1106 of file core_cm33.h.

◆ ITM_TCR_DWTENA_Msk [5/15]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1106 of file core_cm35p.h.

◆ ITM_TCR_DWTENA_Msk [6/15]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 882 of file core_cm4.h.

◆ ITM_TCR_DWTENA_Msk [7/15]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1216 of file core_cm55.h.

◆ ITM_TCR_DWTENA_Msk [8/15]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1106 of file core_cm7.h.

◆ ITM_TCR_DWTENA_Msk [9/15]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1212 of file core_cm85.h.

◆ ITM_TCR_DWTENA_Msk [10/15]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 802 of file core_sc300.h.

◆ ITM_TCR_DWTENA_Msk [11/15]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1164 of file core_starmc1.h.

◆ ITM_TCR_DWTENA_Msk [12/15]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1168 of file core_armv81mml.h.

◆ ITM_TCR_DWTENA_Msk [13/15]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1106 of file core_armv8mml.h.

◆ ITM_TCR_DWTENA_Msk [14/15]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1106 of file core_cm33.h.

◆ ITM_TCR_DWTENA_Msk [15/15]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 882 of file core_cm4.h.

◆ ITM_TCR_DWTENA_Pos [1/15]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

Definition at line 1167 of file core_armv81mml.h.

◆ ITM_TCR_DWTENA_Pos [2/15]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

Definition at line 1105 of file core_armv8mml.h.

◆ ITM_TCR_DWTENA_Pos [3/15]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

Definition at line 816 of file core_cm3.h.

◆ ITM_TCR_DWTENA_Pos [4/15]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

Definition at line 1105 of file core_cm33.h.

◆ ITM_TCR_DWTENA_Pos [5/15]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

Definition at line 1105 of file core_cm35p.h.

◆ ITM_TCR_DWTENA_Pos [6/15]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

Definition at line 881 of file core_cm4.h.

◆ ITM_TCR_DWTENA_Pos [7/15]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

Definition at line 1215 of file core_cm55.h.

◆ ITM_TCR_DWTENA_Pos [8/15]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

Definition at line 1105 of file core_cm7.h.

◆ ITM_TCR_DWTENA_Pos [9/15]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

Definition at line 1211 of file core_cm85.h.

◆ ITM_TCR_DWTENA_Pos [10/15]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

Definition at line 801 of file core_sc300.h.

◆ ITM_TCR_DWTENA_Pos [11/15]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

Definition at line 1163 of file core_starmc1.h.

◆ ITM_TCR_DWTENA_Pos [12/15]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

Definition at line 1167 of file core_armv81mml.h.

◆ ITM_TCR_DWTENA_Pos [13/15]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

Definition at line 1105 of file core_armv8mml.h.

◆ ITM_TCR_DWTENA_Pos [14/15]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

Definition at line 1105 of file core_cm33.h.

◆ ITM_TCR_DWTENA_Pos [15/15]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

Definition at line 881 of file core_cm4.h.

◆ ITM_TCR_GTSFREQ_Msk [1/15]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1156 of file core_armv81mml.h.

◆ ITM_TCR_GTSFREQ_Msk [2/15]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1094 of file core_armv8mml.h.

◆ ITM_TCR_GTSFREQ_Msk [3/15]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 808 of file core_cm3.h.

◆ ITM_TCR_GTSFREQ_Msk [4/15]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1094 of file core_cm33.h.

◆ ITM_TCR_GTSFREQ_Msk [5/15]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1094 of file core_cm35p.h.

◆ ITM_TCR_GTSFREQ_Msk [6/15]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 873 of file core_cm4.h.

◆ ITM_TCR_GTSFREQ_Msk [7/15]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1204 of file core_cm55.h.

◆ ITM_TCR_GTSFREQ_Msk [8/15]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1097 of file core_cm7.h.

◆ ITM_TCR_GTSFREQ_Msk [9/15]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1200 of file core_cm85.h.

◆ ITM_TCR_GTSFREQ_Msk [10/15]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 793 of file core_sc300.h.

◆ ITM_TCR_GTSFREQ_Msk [11/15]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1152 of file core_starmc1.h.

◆ ITM_TCR_GTSFREQ_Msk [12/15]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1156 of file core_armv81mml.h.

◆ ITM_TCR_GTSFREQ_Msk [13/15]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1094 of file core_armv8mml.h.

◆ ITM_TCR_GTSFREQ_Msk [14/15]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1094 of file core_cm33.h.

◆ ITM_TCR_GTSFREQ_Msk [15/15]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 873 of file core_cm4.h.

◆ ITM_TCR_GTSFREQ_Pos [1/15]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

Definition at line 1155 of file core_armv81mml.h.

◆ ITM_TCR_GTSFREQ_Pos [2/15]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

Definition at line 1093 of file core_armv8mml.h.

◆ ITM_TCR_GTSFREQ_Pos [3/15]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

Definition at line 807 of file core_cm3.h.

◆ ITM_TCR_GTSFREQ_Pos [4/15]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

Definition at line 1093 of file core_cm33.h.

◆ ITM_TCR_GTSFREQ_Pos [5/15]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

Definition at line 1093 of file core_cm35p.h.

◆ ITM_TCR_GTSFREQ_Pos [6/15]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

Definition at line 872 of file core_cm4.h.

◆ ITM_TCR_GTSFREQ_Pos [7/15]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

Definition at line 1203 of file core_cm55.h.

◆ ITM_TCR_GTSFREQ_Pos [8/15]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

Definition at line 1096 of file core_cm7.h.

◆ ITM_TCR_GTSFREQ_Pos [9/15]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

Definition at line 1199 of file core_cm85.h.

◆ ITM_TCR_GTSFREQ_Pos [10/15]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

Definition at line 792 of file core_sc300.h.

◆ ITM_TCR_GTSFREQ_Pos [11/15]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

Definition at line 1151 of file core_starmc1.h.

◆ ITM_TCR_GTSFREQ_Pos [12/15]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

Definition at line 1155 of file core_armv81mml.h.

◆ ITM_TCR_GTSFREQ_Pos [13/15]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

Definition at line 1093 of file core_armv8mml.h.

◆ ITM_TCR_GTSFREQ_Pos [14/15]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

Definition at line 1093 of file core_cm33.h.

◆ ITM_TCR_GTSFREQ_Pos [15/15]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

Definition at line 872 of file core_cm4.h.

◆ ITM_TCR_ITMENA_Msk [1/15]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1177 of file core_armv81mml.h.

◆ ITM_TCR_ITMENA_Msk [2/15]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1115 of file core_armv8mml.h.

◆ ITM_TCR_ITMENA_Msk [3/15]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 826 of file core_cm3.h.

◆ ITM_TCR_ITMENA_Msk [4/15]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1115 of file core_cm33.h.

◆ ITM_TCR_ITMENA_Msk [5/15]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1115 of file core_cm35p.h.

◆ ITM_TCR_ITMENA_Msk [6/15]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 891 of file core_cm4.h.

◆ ITM_TCR_ITMENA_Msk [7/15]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1225 of file core_cm55.h.

◆ ITM_TCR_ITMENA_Msk [8/15]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1115 of file core_cm7.h.

◆ ITM_TCR_ITMENA_Msk [9/15]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1221 of file core_cm85.h.

◆ ITM_TCR_ITMENA_Msk [10/15]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 811 of file core_sc300.h.

◆ ITM_TCR_ITMENA_Msk [11/15]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1173 of file core_starmc1.h.

◆ ITM_TCR_ITMENA_Msk [12/15]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1177 of file core_armv81mml.h.

◆ ITM_TCR_ITMENA_Msk [13/15]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1115 of file core_armv8mml.h.

◆ ITM_TCR_ITMENA_Msk [14/15]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1115 of file core_cm33.h.

◆ ITM_TCR_ITMENA_Msk [15/15]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 891 of file core_cm4.h.

◆ ITM_TCR_ITMENA_Pos [1/15]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

Definition at line 1176 of file core_armv81mml.h.

◆ ITM_TCR_ITMENA_Pos [2/15]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

Definition at line 1114 of file core_armv8mml.h.

◆ ITM_TCR_ITMENA_Pos [3/15]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

Definition at line 825 of file core_cm3.h.

◆ ITM_TCR_ITMENA_Pos [4/15]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

Definition at line 1114 of file core_cm33.h.

◆ ITM_TCR_ITMENA_Pos [5/15]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

Definition at line 1114 of file core_cm35p.h.

◆ ITM_TCR_ITMENA_Pos [6/15]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

Definition at line 890 of file core_cm4.h.

◆ ITM_TCR_ITMENA_Pos [7/15]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

Definition at line 1224 of file core_cm55.h.

◆ ITM_TCR_ITMENA_Pos [8/15]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

Definition at line 1114 of file core_cm7.h.

◆ ITM_TCR_ITMENA_Pos [9/15]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

Definition at line 1220 of file core_cm85.h.

◆ ITM_TCR_ITMENA_Pos [10/15]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

Definition at line 810 of file core_sc300.h.

◆ ITM_TCR_ITMENA_Pos [11/15]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

Definition at line 1172 of file core_starmc1.h.

◆ ITM_TCR_ITMENA_Pos [12/15]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

Definition at line 1176 of file core_armv81mml.h.

◆ ITM_TCR_ITMENA_Pos [13/15]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

Definition at line 1114 of file core_armv8mml.h.

◆ ITM_TCR_ITMENA_Pos [14/15]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

Definition at line 1114 of file core_cm33.h.

◆ ITM_TCR_ITMENA_Pos [15/15]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

Definition at line 890 of file core_cm4.h.

◆ ITM_TCR_STALLENA_Msk [1/10]

#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1162 of file core_armv81mml.h.

◆ ITM_TCR_STALLENA_Msk [2/10]

#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1100 of file core_armv8mml.h.

◆ ITM_TCR_STALLENA_Msk [3/10]

#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1100 of file core_cm33.h.

◆ ITM_TCR_STALLENA_Msk [4/10]

#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1100 of file core_cm35p.h.

◆ ITM_TCR_STALLENA_Msk [5/10]

#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1210 of file core_cm55.h.

◆ ITM_TCR_STALLENA_Msk [6/10]

#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1206 of file core_cm85.h.

◆ ITM_TCR_STALLENA_Msk [7/10]

#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1158 of file core_starmc1.h.

◆ ITM_TCR_STALLENA_Msk [8/10]

#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1162 of file core_armv81mml.h.

◆ ITM_TCR_STALLENA_Msk [9/10]

#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1100 of file core_armv8mml.h.

◆ ITM_TCR_STALLENA_Msk [10/10]

#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1100 of file core_cm33.h.

◆ ITM_TCR_STALLENA_Pos [1/10]

#define ITM_TCR_STALLENA_Pos   5U

ITM TCR: STALLENA Position

Definition at line 1161 of file core_armv81mml.h.

◆ ITM_TCR_STALLENA_Pos [2/10]

#define ITM_TCR_STALLENA_Pos   5U

ITM TCR: STALLENA Position

Definition at line 1099 of file core_armv8mml.h.

◆ ITM_TCR_STALLENA_Pos [3/10]

#define ITM_TCR_STALLENA_Pos   5U

ITM TCR: STALLENA Position

Definition at line 1099 of file core_cm33.h.

◆ ITM_TCR_STALLENA_Pos [4/10]

#define ITM_TCR_STALLENA_Pos   5U

ITM TCR: STALLENA Position

Definition at line 1099 of file core_cm35p.h.

◆ ITM_TCR_STALLENA_Pos [5/10]

#define ITM_TCR_STALLENA_Pos   5U

ITM TCR: STALLENA Position

Definition at line 1209 of file core_cm55.h.

◆ ITM_TCR_STALLENA_Pos [6/10]

#define ITM_TCR_STALLENA_Pos   5U

ITM TCR: STALLENA Position

Definition at line 1205 of file core_cm85.h.

◆ ITM_TCR_STALLENA_Pos [7/10]

#define ITM_TCR_STALLENA_Pos   5U

ITM TCR: STALLENA Position

Definition at line 1157 of file core_starmc1.h.

◆ ITM_TCR_STALLENA_Pos [8/10]

#define ITM_TCR_STALLENA_Pos   5U

ITM TCR: STALLENA Position

Definition at line 1161 of file core_armv81mml.h.

◆ ITM_TCR_STALLENA_Pos [9/10]

#define ITM_TCR_STALLENA_Pos   5U

ITM TCR: STALLENA Position

Definition at line 1099 of file core_armv8mml.h.

◆ ITM_TCR_STALLENA_Pos [10/10]

#define ITM_TCR_STALLENA_Pos   5U

ITM TCR: STALLENA Position

Definition at line 1099 of file core_cm33.h.

◆ ITM_TCR_SWOENA_Msk [1/15]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1165 of file core_armv81mml.h.

◆ ITM_TCR_SWOENA_Msk [2/15]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1103 of file core_armv8mml.h.

◆ ITM_TCR_SWOENA_Msk [3/15]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 814 of file core_cm3.h.

◆ ITM_TCR_SWOENA_Msk [4/15]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1103 of file core_cm33.h.

◆ ITM_TCR_SWOENA_Msk [5/15]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1103 of file core_cm35p.h.

◆ ITM_TCR_SWOENA_Msk [6/15]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 879 of file core_cm4.h.

◆ ITM_TCR_SWOENA_Msk [7/15]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1213 of file core_cm55.h.

◆ ITM_TCR_SWOENA_Msk [8/15]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1103 of file core_cm7.h.

◆ ITM_TCR_SWOENA_Msk [9/15]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1209 of file core_cm85.h.

◆ ITM_TCR_SWOENA_Msk [10/15]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 799 of file core_sc300.h.

◆ ITM_TCR_SWOENA_Msk [11/15]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1161 of file core_starmc1.h.

◆ ITM_TCR_SWOENA_Msk [12/15]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1165 of file core_armv81mml.h.

◆ ITM_TCR_SWOENA_Msk [13/15]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1103 of file core_armv8mml.h.

◆ ITM_TCR_SWOENA_Msk [14/15]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1103 of file core_cm33.h.

◆ ITM_TCR_SWOENA_Msk [15/15]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 879 of file core_cm4.h.

◆ ITM_TCR_SWOENA_Pos [1/15]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

Definition at line 1164 of file core_armv81mml.h.

◆ ITM_TCR_SWOENA_Pos [2/15]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

Definition at line 1102 of file core_armv8mml.h.

◆ ITM_TCR_SWOENA_Pos [3/15]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

Definition at line 813 of file core_cm3.h.

◆ ITM_TCR_SWOENA_Pos [4/15]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

Definition at line 1102 of file core_cm33.h.

◆ ITM_TCR_SWOENA_Pos [5/15]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

Definition at line 1102 of file core_cm35p.h.

◆ ITM_TCR_SWOENA_Pos [6/15]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

Definition at line 878 of file core_cm4.h.

◆ ITM_TCR_SWOENA_Pos [7/15]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

Definition at line 1212 of file core_cm55.h.

◆ ITM_TCR_SWOENA_Pos [8/15]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

Definition at line 1102 of file core_cm7.h.

◆ ITM_TCR_SWOENA_Pos [9/15]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

Definition at line 1208 of file core_cm85.h.

◆ ITM_TCR_SWOENA_Pos [10/15]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

Definition at line 798 of file core_sc300.h.

◆ ITM_TCR_SWOENA_Pos [11/15]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

Definition at line 1160 of file core_starmc1.h.

◆ ITM_TCR_SWOENA_Pos [12/15]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

Definition at line 1164 of file core_armv81mml.h.

◆ ITM_TCR_SWOENA_Pos [13/15]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

Definition at line 1102 of file core_armv8mml.h.

◆ ITM_TCR_SWOENA_Pos [14/15]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

Definition at line 1102 of file core_cm33.h.

◆ ITM_TCR_SWOENA_Pos [15/15]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

Definition at line 878 of file core_cm4.h.

◆ ITM_TCR_SYNCENA_Msk [1/15]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1171 of file core_armv81mml.h.

◆ ITM_TCR_SYNCENA_Msk [2/15]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1109 of file core_armv8mml.h.

◆ ITM_TCR_SYNCENA_Msk [3/15]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 820 of file core_cm3.h.

◆ ITM_TCR_SYNCENA_Msk [4/15]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1109 of file core_cm33.h.

◆ ITM_TCR_SYNCENA_Msk [5/15]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1109 of file core_cm35p.h.

◆ ITM_TCR_SYNCENA_Msk [6/15]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 885 of file core_cm4.h.

◆ ITM_TCR_SYNCENA_Msk [7/15]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1219 of file core_cm55.h.

◆ ITM_TCR_SYNCENA_Msk [8/15]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1109 of file core_cm7.h.

◆ ITM_TCR_SYNCENA_Msk [9/15]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1215 of file core_cm85.h.

◆ ITM_TCR_SYNCENA_Msk [10/15]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 805 of file core_sc300.h.

◆ ITM_TCR_SYNCENA_Msk [11/15]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1167 of file core_starmc1.h.

◆ ITM_TCR_SYNCENA_Msk [12/15]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1171 of file core_armv81mml.h.

◆ ITM_TCR_SYNCENA_Msk [13/15]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1109 of file core_armv8mml.h.

◆ ITM_TCR_SYNCENA_Msk [14/15]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1109 of file core_cm33.h.

◆ ITM_TCR_SYNCENA_Msk [15/15]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 885 of file core_cm4.h.

◆ ITM_TCR_SYNCENA_Pos [1/15]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

Definition at line 1170 of file core_armv81mml.h.

◆ ITM_TCR_SYNCENA_Pos [2/15]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

Definition at line 1108 of file core_armv8mml.h.

◆ ITM_TCR_SYNCENA_Pos [3/15]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

Definition at line 819 of file core_cm3.h.

◆ ITM_TCR_SYNCENA_Pos [4/15]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

Definition at line 1108 of file core_cm33.h.

◆ ITM_TCR_SYNCENA_Pos [5/15]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

Definition at line 1108 of file core_cm35p.h.

◆ ITM_TCR_SYNCENA_Pos [6/15]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

Definition at line 884 of file core_cm4.h.

◆ ITM_TCR_SYNCENA_Pos [7/15]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

Definition at line 1218 of file core_cm55.h.

◆ ITM_TCR_SYNCENA_Pos [8/15]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

Definition at line 1108 of file core_cm7.h.

◆ ITM_TCR_SYNCENA_Pos [9/15]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

Definition at line 1214 of file core_cm85.h.

◆ ITM_TCR_SYNCENA_Pos [10/15]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

Definition at line 804 of file core_sc300.h.

◆ ITM_TCR_SYNCENA_Pos [11/15]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

Definition at line 1166 of file core_starmc1.h.

◆ ITM_TCR_SYNCENA_Pos [12/15]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

Definition at line 1170 of file core_armv81mml.h.

◆ ITM_TCR_SYNCENA_Pos [13/15]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

Definition at line 1108 of file core_armv8mml.h.

◆ ITM_TCR_SYNCENA_Pos [14/15]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

Definition at line 1108 of file core_cm33.h.

◆ ITM_TCR_SYNCENA_Pos [15/15]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

Definition at line 884 of file core_cm4.h.

◆ ITM_TCR_TRACEBUSID_Msk [1/15]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1153 of file core_armv81mml.h.

◆ ITM_TCR_TRACEBUSID_Msk [2/15]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1091 of file core_armv8mml.h.

◆ ITM_TCR_TRACEBUSID_Msk [3/15]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 805 of file core_cm3.h.

◆ ITM_TCR_TRACEBUSID_Msk [4/15]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1091 of file core_cm33.h.

◆ ITM_TCR_TRACEBUSID_Msk [5/15]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1091 of file core_cm35p.h.

◆ ITM_TCR_TRACEBUSID_Msk [6/15]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 870 of file core_cm4.h.

◆ ITM_TCR_TRACEBUSID_Msk [7/15]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1201 of file core_cm55.h.

◆ ITM_TCR_TRACEBUSID_Msk [8/15]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1094 of file core_cm7.h.

◆ ITM_TCR_TRACEBUSID_Msk [9/15]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1197 of file core_cm85.h.

◆ ITM_TCR_TRACEBUSID_Msk [10/15]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 790 of file core_sc300.h.

◆ ITM_TCR_TRACEBUSID_Msk [11/15]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1149 of file core_starmc1.h.

◆ ITM_TCR_TRACEBUSID_Msk [12/15]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1153 of file core_armv81mml.h.

◆ ITM_TCR_TRACEBUSID_Msk [13/15]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1091 of file core_armv8mml.h.

◆ ITM_TCR_TRACEBUSID_Msk [14/15]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1091 of file core_cm33.h.

◆ ITM_TCR_TRACEBUSID_Msk [15/15]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 870 of file core_cm4.h.

◆ ITM_TCR_TRACEBUSID_Pos [1/15]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position

Definition at line 1152 of file core_armv81mml.h.

◆ ITM_TCR_TRACEBUSID_Pos [2/15]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position

Definition at line 1090 of file core_armv8mml.h.

◆ ITM_TCR_TRACEBUSID_Pos [3/15]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position

Definition at line 804 of file core_cm3.h.

◆ ITM_TCR_TRACEBUSID_Pos [4/15]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position

Definition at line 1090 of file core_cm33.h.

◆ ITM_TCR_TRACEBUSID_Pos [5/15]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position

Definition at line 1090 of file core_cm35p.h.

◆ ITM_TCR_TRACEBUSID_Pos [6/15]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position

Definition at line 869 of file core_cm4.h.

◆ ITM_TCR_TRACEBUSID_Pos [7/15]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position

Definition at line 1200 of file core_cm55.h.

◆ ITM_TCR_TRACEBUSID_Pos [8/15]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position

Definition at line 1093 of file core_cm7.h.

◆ ITM_TCR_TRACEBUSID_Pos [9/15]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position

Definition at line 1196 of file core_cm85.h.

◆ ITM_TCR_TRACEBUSID_Pos [10/15]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position

Definition at line 789 of file core_sc300.h.

◆ ITM_TCR_TRACEBUSID_Pos [11/15]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position

Definition at line 1148 of file core_starmc1.h.

◆ ITM_TCR_TRACEBUSID_Pos [12/15]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position

Definition at line 1152 of file core_armv81mml.h.

◆ ITM_TCR_TRACEBUSID_Pos [13/15]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position

Definition at line 1090 of file core_armv8mml.h.

◆ ITM_TCR_TRACEBUSID_Pos [14/15]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position

Definition at line 1090 of file core_cm33.h.

◆ ITM_TCR_TRACEBUSID_Pos [15/15]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position

Definition at line 869 of file core_cm4.h.

◆ ITM_TCR_TSENA_Msk [1/15]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1174 of file core_armv81mml.h.

◆ ITM_TCR_TSENA_Msk [2/15]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1112 of file core_armv8mml.h.

◆ ITM_TCR_TSENA_Msk [3/15]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 823 of file core_cm3.h.

◆ ITM_TCR_TSENA_Msk [4/15]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1112 of file core_cm33.h.

◆ ITM_TCR_TSENA_Msk [5/15]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1112 of file core_cm35p.h.

◆ ITM_TCR_TSENA_Msk [6/15]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 888 of file core_cm4.h.

◆ ITM_TCR_TSENA_Msk [7/15]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1222 of file core_cm55.h.

◆ ITM_TCR_TSENA_Msk [8/15]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1112 of file core_cm7.h.

◆ ITM_TCR_TSENA_Msk [9/15]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1218 of file core_cm85.h.

◆ ITM_TCR_TSENA_Msk [10/15]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 808 of file core_sc300.h.

◆ ITM_TCR_TSENA_Msk [11/15]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1170 of file core_starmc1.h.

◆ ITM_TCR_TSENA_Msk [12/15]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1174 of file core_armv81mml.h.

◆ ITM_TCR_TSENA_Msk [13/15]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1112 of file core_armv8mml.h.

◆ ITM_TCR_TSENA_Msk [14/15]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1112 of file core_cm33.h.

◆ ITM_TCR_TSENA_Msk [15/15]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 888 of file core_cm4.h.

◆ ITM_TCR_TSENA_Pos [1/15]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

Definition at line 1173 of file core_armv81mml.h.

◆ ITM_TCR_TSENA_Pos [2/15]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

Definition at line 1111 of file core_armv8mml.h.

◆ ITM_TCR_TSENA_Pos [3/15]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

Definition at line 822 of file core_cm3.h.

◆ ITM_TCR_TSENA_Pos [4/15]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

Definition at line 1111 of file core_cm33.h.

◆ ITM_TCR_TSENA_Pos [5/15]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

Definition at line 1111 of file core_cm35p.h.

◆ ITM_TCR_TSENA_Pos [6/15]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

Definition at line 887 of file core_cm4.h.

◆ ITM_TCR_TSENA_Pos [7/15]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

Definition at line 1221 of file core_cm55.h.

◆ ITM_TCR_TSENA_Pos [8/15]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

Definition at line 1111 of file core_cm7.h.

◆ ITM_TCR_TSENA_Pos [9/15]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

Definition at line 1217 of file core_cm85.h.

◆ ITM_TCR_TSENA_Pos [10/15]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

Definition at line 807 of file core_sc300.h.

◆ ITM_TCR_TSENA_Pos [11/15]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

Definition at line 1169 of file core_starmc1.h.

◆ ITM_TCR_TSENA_Pos [12/15]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

Definition at line 1173 of file core_armv81mml.h.

◆ ITM_TCR_TSENA_Pos [13/15]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

Definition at line 1111 of file core_armv8mml.h.

◆ ITM_TCR_TSENA_Pos [14/15]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

Definition at line 1111 of file core_cm33.h.

◆ ITM_TCR_TSENA_Pos [15/15]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

Definition at line 887 of file core_cm4.h.

◆ ITM_TCR_TSPRESCALE_Msk [1/15]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

ITM TCR: TSPrescale Mask

Definition at line 1159 of file core_armv81mml.h.

◆ ITM_TCR_TSPRESCALE_Msk [2/15]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

ITM TCR: TSPrescale Mask

Definition at line 1097 of file core_armv8mml.h.

◆ ITM_TCR_TSPRESCALE_Msk [3/15]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPrescale Mask

ITM TCR: TSPRESCALE Mask

Definition at line 811 of file core_cm3.h.

◆ ITM_TCR_TSPRESCALE_Msk [4/15]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

ITM TCR: TSPrescale Mask

Definition at line 1097 of file core_cm33.h.

◆ ITM_TCR_TSPRESCALE_Msk [5/15]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

ITM TCR: TSPrescale Mask

Definition at line 1097 of file core_cm35p.h.

◆ ITM_TCR_TSPRESCALE_Msk [6/15]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPrescale Mask

ITM TCR: TSPRESCALE Mask

Definition at line 876 of file core_cm4.h.

◆ ITM_TCR_TSPRESCALE_Msk [7/15]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

ITM TCR: TSPrescale Mask

Definition at line 1207 of file core_cm55.h.

◆ ITM_TCR_TSPRESCALE_Msk [8/15]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPrescale Mask

ITM TCR: TSPRESCALE Mask

Definition at line 1100 of file core_cm7.h.

◆ ITM_TCR_TSPRESCALE_Msk [9/15]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

ITM TCR: TSPrescale Mask

Definition at line 1203 of file core_cm85.h.

◆ ITM_TCR_TSPRESCALE_Msk [10/15]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPrescale Mask

ITM TCR: TSPRESCALE Mask

Definition at line 796 of file core_sc300.h.

◆ ITM_TCR_TSPRESCALE_Msk [11/15]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

ITM TCR: TSPrescale Mask

Definition at line 1155 of file core_starmc1.h.

◆ ITM_TCR_TSPRESCALE_Msk [12/15]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

ITM TCR: TSPrescale Mask

Definition at line 1159 of file core_armv81mml.h.

◆ ITM_TCR_TSPRESCALE_Msk [13/15]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

ITM TCR: TSPrescale Mask

Definition at line 1097 of file core_armv8mml.h.

◆ ITM_TCR_TSPRESCALE_Msk [14/15]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

ITM TCR: TSPrescale Mask

Definition at line 1097 of file core_cm33.h.

◆ ITM_TCR_TSPRESCALE_Msk [15/15]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPrescale Mask

Definition at line 876 of file core_cm4.h.

◆ ITM_TCR_TSPRESCALE_Pos [1/15]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPRESCALE Position

ITM TCR: TSPrescale Position

Definition at line 1158 of file core_armv81mml.h.

◆ ITM_TCR_TSPRESCALE_Pos [2/15]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPRESCALE Position

ITM TCR: TSPrescale Position

Definition at line 1096 of file core_armv8mml.h.

◆ ITM_TCR_TSPRESCALE_Pos [3/15]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPrescale Position

ITM TCR: TSPRESCALE Position

Definition at line 810 of file core_cm3.h.

◆ ITM_TCR_TSPRESCALE_Pos [4/15]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPRESCALE Position

ITM TCR: TSPrescale Position

Definition at line 1096 of file core_cm33.h.

◆ ITM_TCR_TSPRESCALE_Pos [5/15]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPRESCALE Position

ITM TCR: TSPrescale Position

Definition at line 1096 of file core_cm35p.h.

◆ ITM_TCR_TSPRESCALE_Pos [6/15]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPrescale Position

ITM TCR: TSPRESCALE Position

Definition at line 875 of file core_cm4.h.

◆ ITM_TCR_TSPRESCALE_Pos [7/15]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPRESCALE Position

ITM TCR: TSPrescale Position

Definition at line 1206 of file core_cm55.h.

◆ ITM_TCR_TSPRESCALE_Pos [8/15]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPrescale Position

ITM TCR: TSPRESCALE Position

Definition at line 1099 of file core_cm7.h.

◆ ITM_TCR_TSPRESCALE_Pos [9/15]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPRESCALE Position

ITM TCR: TSPrescale Position

Definition at line 1202 of file core_cm85.h.

◆ ITM_TCR_TSPRESCALE_Pos [10/15]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPrescale Position

ITM TCR: TSPRESCALE Position

Definition at line 795 of file core_sc300.h.

◆ ITM_TCR_TSPRESCALE_Pos [11/15]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPRESCALE Position

ITM TCR: TSPrescale Position

Definition at line 1154 of file core_starmc1.h.

◆ ITM_TCR_TSPRESCALE_Pos [12/15]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPRESCALE Position

ITM TCR: TSPrescale Position

Definition at line 1158 of file core_armv81mml.h.

◆ ITM_TCR_TSPRESCALE_Pos [13/15]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPRESCALE Position

ITM TCR: TSPrescale Position

Definition at line 1096 of file core_armv8mml.h.

◆ ITM_TCR_TSPRESCALE_Pos [14/15]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPRESCALE Position

ITM TCR: TSPrescale Position

Definition at line 1096 of file core_cm33.h.

◆ ITM_TCR_TSPRESCALE_Pos [15/15]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPrescale Position

Definition at line 875 of file core_cm4.h.

◆ ITM_TPR_PRIVMASK_Msk [1/15]

#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1146 of file core_armv81mml.h.

◆ ITM_TPR_PRIVMASK_Msk [2/15]

#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1084 of file core_armv8mml.h.

◆ ITM_TPR_PRIVMASK_Msk [3/15]

#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 798 of file core_cm3.h.

◆ ITM_TPR_PRIVMASK_Msk [4/15]

#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1084 of file core_cm33.h.

◆ ITM_TPR_PRIVMASK_Msk [5/15]

#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1084 of file core_cm35p.h.

◆ ITM_TPR_PRIVMASK_Msk [6/15]

#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 863 of file core_cm4.h.

◆ ITM_TPR_PRIVMASK_Msk [7/15]

#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1194 of file core_cm55.h.

◆ ITM_TPR_PRIVMASK_Msk [8/15]

#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1087 of file core_cm7.h.

◆ ITM_TPR_PRIVMASK_Msk [9/15]

#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1190 of file core_cm85.h.

◆ ITM_TPR_PRIVMASK_Msk [10/15]

#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 783 of file core_sc300.h.

◆ ITM_TPR_PRIVMASK_Msk [11/15]

#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1142 of file core_starmc1.h.

◆ ITM_TPR_PRIVMASK_Msk [12/15]

#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1146 of file core_armv81mml.h.

◆ ITM_TPR_PRIVMASK_Msk [13/15]

#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1084 of file core_armv8mml.h.

◆ ITM_TPR_PRIVMASK_Msk [14/15]

#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1084 of file core_cm33.h.

◆ ITM_TPR_PRIVMASK_Msk [15/15]

#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 863 of file core_cm4.h.

◆ ITM_TPR_PRIVMASK_Pos [1/15]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

Definition at line 1145 of file core_armv81mml.h.

◆ ITM_TPR_PRIVMASK_Pos [2/15]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

Definition at line 1083 of file core_armv8mml.h.

◆ ITM_TPR_PRIVMASK_Pos [3/15]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

Definition at line 797 of file core_cm3.h.

◆ ITM_TPR_PRIVMASK_Pos [4/15]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

Definition at line 1083 of file core_cm33.h.

◆ ITM_TPR_PRIVMASK_Pos [5/15]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

Definition at line 1083 of file core_cm35p.h.

◆ ITM_TPR_PRIVMASK_Pos [6/15]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

Definition at line 862 of file core_cm4.h.

◆ ITM_TPR_PRIVMASK_Pos [7/15]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

Definition at line 1193 of file core_cm55.h.

◆ ITM_TPR_PRIVMASK_Pos [8/15]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

Definition at line 1086 of file core_cm7.h.

◆ ITM_TPR_PRIVMASK_Pos [9/15]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

Definition at line 1189 of file core_cm85.h.

◆ ITM_TPR_PRIVMASK_Pos [10/15]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

Definition at line 782 of file core_sc300.h.

◆ ITM_TPR_PRIVMASK_Pos [11/15]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

Definition at line 1141 of file core_starmc1.h.

◆ ITM_TPR_PRIVMASK_Pos [12/15]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

Definition at line 1145 of file core_armv81mml.h.

◆ ITM_TPR_PRIVMASK_Pos [13/15]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

Definition at line 1083 of file core_armv8mml.h.

◆ ITM_TPR_PRIVMASK_Pos [14/15]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

Definition at line 1083 of file core_cm33.h.

◆ ITM_TPR_PRIVMASK_Pos [15/15]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

Definition at line 862 of file core_cm4.h.

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