YAHAL
Yet Another Hardware Abstraction Library
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core_starmc1.h
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1/**************************************************************************/
7/*
8 * Copyright (c) 2009-2013 Arm Limited.
9 * Copyright (c) 2018-2022 Arm China.
10 * All rights reserved.
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the License); you may
14 * not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 */
25
26#if defined ( __ICCARM__ )
27 #pragma system_include /* treat file as system include file for MISRA check */
28#elif defined (__clang__)
29 #pragma clang system_header /* treat file as system include file */
30#elif defined ( __GNUC__ )
31 #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
32#endif
33
34#ifndef __CORE_STAR_H_GENERIC
35#define __CORE_STAR_H_GENERIC
36
37#include <stdint.h>
38
39#ifdef __cplusplus
40 extern "C" {
41#endif
42
58/*******************************************************************************
59 * CMSIS definitions
60 ******************************************************************************/
66#include "cmsis_version.h"
67
68/* Macro Define for STAR-MC1 */
69#define __STAR_MC (1U)
74#if defined ( __CC_ARM )
75 #if defined (__TARGET_FPU_VFP)
76 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
77 #define __FPU_USED 1U
78 #else
79 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
80 #define __FPU_USED 0U
81 #endif
82 #else
83 #define __FPU_USED 0U
84 #endif
85
86 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
87 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
88 #define __DSP_USED 1U
89 #else
90 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
91 #define __DSP_USED 0U
92 #endif
93 #else
94 #define __DSP_USED 0U
95 #endif
96
97#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
98 #if defined (__ARM_FP)
99 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
100 #define __FPU_USED 1U
101 #else
102 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
103 #define __FPU_USED 0U
104 #endif
105 #else
106 #define __FPU_USED 0U
107 #endif
108
109 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
110 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
111 #define __DSP_USED 1U
112 #else
113 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
114 #define __DSP_USED 0U
115 #endif
116 #else
117 #define __DSP_USED 0U
118 #endif
119
120#elif defined (__ti__)
121 #if defined (__ARM_FP)
122 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
123 #define __FPU_USED 1U
124 #else
125 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
126 #define __FPU_USED 0U
127 #endif
128 #else
129 #define __FPU_USED 0U
130 #endif
131
132 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
133 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
134 #define __DSP_USED 1U
135 #else
136 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
137 #define __DSP_USED 0U
138 #endif
139 #else
140 #define __DSP_USED 0U
141 #endif
142
143#elif defined ( __GNUC__ )
144 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
145 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
146 #define __FPU_USED 1U
147 #else
148 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
149 #define __FPU_USED 0U
150 #endif
151 #else
152 #define __FPU_USED 0U
153 #endif
154
155 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
156 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
157 #define __DSP_USED 1U
158 #else
159 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
160 #define __DSP_USED 0U
161 #endif
162 #else
163 #define __DSP_USED 0U
164 #endif
165
166#elif defined ( __ICCARM__ )
167 #if defined (__ARMVFP__)
168 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
169 #define __FPU_USED 1U
170 #else
171 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
172 #define __FPU_USED 0U
173 #endif
174 #else
175 #define __FPU_USED 0U
176 #endif
177
178 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
179 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
180 #define __DSP_USED 1U
181 #else
182 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
183 #define __DSP_USED 0U
184 #endif
185 #else
186 #define __DSP_USED 0U
187 #endif
188
189#elif defined ( __TI_ARM__ )
190 #if defined (__TI_VFP_SUPPORT__)
191 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
192 #define __FPU_USED 1U
193 #else
194 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
195 #define __FPU_USED 0U
196 #endif
197 #else
198 #define __FPU_USED 0U
199 #endif
200
201#elif defined ( __TASKING__ )
202 #if defined (__FPU_VFP__)
203 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
204 #define __FPU_USED 1U
205 #else
206 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
207 #define __FPU_USED 0U
208 #endif
209 #else
210 #define __FPU_USED 0U
211 #endif
212
213#elif defined ( __CSMC__ )
214 #if ( __CSMC__ & 0x400U)
215 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
216 #define __FPU_USED 1U
217 #else
218 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
219 #define __FPU_USED 0U
220 #endif
221 #else
222 #define __FPU_USED 0U
223 #endif
224
225#endif
226
227#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
228
229
230#ifdef __cplusplus
231}
232#endif
233
234#endif /* __CORE_STAR_H_GENERIC */
235
236#ifndef __CMSIS_GENERIC
237
238#ifndef __CORE_STAR_H_DEPENDANT
239#define __CORE_STAR_H_DEPENDANT
240
241#ifdef __cplusplus
242 extern "C" {
243#endif
244
245/* check device defines and use defaults */
246#if defined __CHECK_DEVICE_DEFINES
247 #ifndef __STAR_REV
248 #define __STAR_REV 0x0000U
249 #warning "__STAR_REV not defined in device header file; using default!"
250 #endif
251
252 #ifndef __FPU_PRESENT
253 #define __FPU_PRESENT 0U
254 #warning "__FPU_PRESENT not defined in device header file; using default!"
255 #endif
256
257 #ifndef __MPU_PRESENT
258 #define __MPU_PRESENT 0U
259 #warning "__MPU_PRESENT not defined in device header file; using default!"
260 #endif
261
262 #ifndef __SAUREGION_PRESENT
263 #define __SAUREGION_PRESENT 0U
264 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
265 #endif
266
267 #ifndef __DSP_PRESENT
268 #define __DSP_PRESENT 0U
269 #warning "__DSP_PRESENT not defined in device header file; using default!"
270 #endif
271
272 #ifndef __ICACHE_PRESENT
273 #define __ICACHE_PRESENT 0U
274 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
275 #endif
276
277 #ifndef __DCACHE_PRESENT
278 #define __DCACHE_PRESENT 0U
279 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
280 #endif
281
282 #ifndef __DTCM_PRESENT
283 #define __DTCM_PRESENT 0U
284 #warning "__DTCM_PRESENT not defined in device header file; using default!"
285 #endif
286
287 #ifndef __NVIC_PRIO_BITS
288 #define __NVIC_PRIO_BITS 3U
289 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
290 #endif
291
292 #ifndef __Vendor_SysTickConfig
293 #define __Vendor_SysTickConfig 0U
294 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
295 #endif
296#endif
297
298/* IO definitions (access restrictions to peripheral registers) */
306#ifdef __cplusplus
307 #define __I volatile
308#else
309 #define __I volatile const
310#endif
311#define __O volatile
312#define __IO volatile
314/* following defines should be used for structure members */
315#define __IM volatile const
316#define __OM volatile
317#define __IOM volatile
323/*******************************************************************************
324 * Register Abstraction
325 Core Register contain:
326 - Core Register
327 - Core NVIC Register
328 - Core SCB Register
329 - Core SysTick Register
330 - Core Debug Register
331 - Core MPU Register
332 - Core SAU Register
333 - Core FPU Register
334 ******************************************************************************/
350typedef union
351{
352 struct
353 {
354 uint32_t _reserved0:16;
355 uint32_t GE:4;
356 uint32_t _reserved1:7;
357 uint32_t Q:1;
358 uint32_t V:1;
359 uint32_t C:1;
360 uint32_t Z:1;
361 uint32_t N:1;
362 } b;
363 uint32_t w;
364} APSR_Type;
365
366/* APSR Register Definitions */
367#define APSR_N_Pos 31U
368#define APSR_N_Msk (1UL << APSR_N_Pos)
370#define APSR_Z_Pos 30U
371#define APSR_Z_Msk (1UL << APSR_Z_Pos)
373#define APSR_C_Pos 29U
374#define APSR_C_Msk (1UL << APSR_C_Pos)
376#define APSR_V_Pos 28U
377#define APSR_V_Msk (1UL << APSR_V_Pos)
379#define APSR_Q_Pos 27U
380#define APSR_Q_Msk (1UL << APSR_Q_Pos)
382#define APSR_GE_Pos 16U
383#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)
389typedef union
390{
391 struct
392 {
393 uint32_t ISR:9;
394 uint32_t _reserved0:23;
395 } b;
396 uint32_t w;
397} IPSR_Type;
398
399/* IPSR Register Definitions */
400#define IPSR_ISR_Pos 0U
401#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
407typedef union
408{
409 struct
410 {
411 uint32_t ISR:9;
412 uint32_t _reserved0:7;
413 uint32_t GE:4;
414 uint32_t _reserved1:4;
415 uint32_t T:1;
416 uint32_t IT:2;
417 uint32_t Q:1;
418 uint32_t V:1;
419 uint32_t C:1;
420 uint32_t Z:1;
421 uint32_t N:1;
422 } b;
423 uint32_t w;
424} xPSR_Type;
425
426/* xPSR Register Definitions */
427#define xPSR_N_Pos 31U
428#define xPSR_N_Msk (1UL << xPSR_N_Pos)
430#define xPSR_Z_Pos 30U
431#define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
433#define xPSR_C_Pos 29U
434#define xPSR_C_Msk (1UL << xPSR_C_Pos)
436#define xPSR_V_Pos 28U
437#define xPSR_V_Msk (1UL << xPSR_V_Pos)
439#define xPSR_Q_Pos 27U
440#define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
442#define xPSR_IT_Pos 25U
443#define xPSR_IT_Msk (3UL << xPSR_IT_Pos)
445#define xPSR_T_Pos 24U
446#define xPSR_T_Msk (1UL << xPSR_T_Pos)
448#define xPSR_GE_Pos 16U
449#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
451#define xPSR_ISR_Pos 0U
452#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
458typedef union
459{
460 struct
461 {
462 uint32_t nPRIV:1;
463 uint32_t SPSEL:1;
464 uint32_t FPCA:1;
465 uint32_t SFPA:1;
466 uint32_t _reserved1:28;
467 } b;
468 uint32_t w;
469} CONTROL_Type;
470
471/* CONTROL Register Definitions */
472#define CONTROL_SFPA_Pos 3U
473#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)
475#define CONTROL_FPCA_Pos 2U
476#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
478#define CONTROL_SPSEL_Pos 1U
479#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
481#define CONTROL_nPRIV_Pos 0U
482#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
497typedef struct
498{
499 __IOM uint32_t ISER[16U];
500 uint32_t RESERVED0[16U];
501 __IOM uint32_t ICER[16U];
502 uint32_t RSERVED1[16U];
503 __IOM uint32_t ISPR[16U];
504 uint32_t RESERVED2[16U];
505 __IOM uint32_t ICPR[16U];
506 uint32_t RESERVED3[16U];
507 __IOM uint32_t IABR[16U];
508 uint32_t RESERVED4[16U];
509 __IOM uint32_t ITNS[16U];
510 uint32_t RESERVED5[16U];
511 __IOM uint8_t IPR[496U];
512 uint32_t RESERVED6[580U];
513 __OM uint32_t STIR;
514} NVIC_Type;
515
516/* Software Triggered Interrupt Register Definitions */
517#define NVIC_STIR_INTID_Pos 0U
518#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
533typedef struct
534{
535 __IM uint32_t CPUID;
536 __IOM uint32_t ICSR;
537 __IOM uint32_t VTOR;
538 __IOM uint32_t AIRCR;
539 __IOM uint32_t SCR;
540 __IOM uint32_t CCR;
541 __IOM uint8_t SHPR[12U];
542 __IOM uint32_t SHCSR;
543 __IOM uint32_t CFSR;
544 __IOM uint32_t HFSR;
545 __IOM uint32_t DFSR;
546 __IOM uint32_t MMFAR;
547 __IOM uint32_t BFAR;
548 __IOM uint32_t AFSR;
549 __IM uint32_t ID_PFR[2U];
550 __IM uint32_t ID_DFR;
551 __IM uint32_t ID_AFR;
552 __IM uint32_t ID_MMFR[4U];
553 __IM uint32_t ID_ISAR[5U];
554 uint32_t RESERVED0[1U];
555 __IM uint32_t CLIDR;
556 __IM uint32_t CTR;
557 __IM uint32_t CCSIDR;
558 __IOM uint32_t CSSELR;
559 __IOM uint32_t CPACR;
560 __IOM uint32_t NSACR;
561 uint32_t RESERVED_ADD1[21U];
562 __IOM uint32_t SFSR;
563 __IOM uint32_t SFAR;
564 uint32_t RESERVED3[69U];
565 __OM uint32_t STIR;
566 uint32_t RESERVED4[15U];
567 __IM uint32_t MVFR0;
568 __IM uint32_t MVFR1;
569 __IM uint32_t MVFR2;
570 uint32_t RESERVED5[1U];
571 __OM uint32_t ICIALLU;
572 uint32_t RESERVED6[1U];
573 __OM uint32_t ICIMVAU;
574 __OM uint32_t DCIMVAC;
575 __OM uint32_t DCISW;
576 __OM uint32_t DCCMVAU;
577 __OM uint32_t DCCMVAC;
578 __OM uint32_t DCCSW;
579 __OM uint32_t DCCIMVAC;
580 __OM uint32_t DCCISW;
581} SCB_Type;
582
583typedef struct
584{
585 __IOM uint32_t CACR;
586 __IOM uint32_t ITCMCR;
587 __IOM uint32_t DTCMCR;
588}EMSS_Type;
589
590/* SCB CPUID Register Definitions */
591#define SCB_CPUID_IMPLEMENTER_Pos 24U
592#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
594#define SCB_CPUID_VARIANT_Pos 20U
595#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
597#define SCB_CPUID_ARCHITECTURE_Pos 16U
598#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
600#define SCB_CPUID_PARTNO_Pos 4U
601#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
603#define SCB_CPUID_REVISION_Pos 0U
604#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
606/* SCB Interrupt Control State Register Definitions */
607#define SCB_ICSR_PENDNMISET_Pos 31U
608#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)
610#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos
611#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk
613#define SCB_ICSR_PENDNMICLR_Pos 30U
614#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)
616#define SCB_ICSR_PENDSVSET_Pos 28U
617#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
619#define SCB_ICSR_PENDSVCLR_Pos 27U
620#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
622#define SCB_ICSR_PENDSTSET_Pos 26U
623#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
625#define SCB_ICSR_PENDSTCLR_Pos 25U
626#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
628#define SCB_ICSR_STTNS_Pos 24U
629#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)
631#define SCB_ICSR_ISRPREEMPT_Pos 23U
632#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
634#define SCB_ICSR_ISRPENDING_Pos 22U
635#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
637#define SCB_ICSR_VECTPENDING_Pos 12U
638#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
640#define SCB_ICSR_RETTOBASE_Pos 11U
641#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
643#define SCB_ICSR_VECTACTIVE_Pos 0U
644#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
646/* SCB Vector Table Offset Register Definitions */
647#define SCB_VTOR_TBLOFF_Pos 7U
648#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
650/* SCB Application Interrupt and Reset Control Register Definitions */
651#define SCB_AIRCR_VECTKEY_Pos 16U
652#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
654#define SCB_AIRCR_VECTKEYSTAT_Pos 16U
655#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
657#define SCB_AIRCR_ENDIANESS_Pos 15U
658#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
660#define SCB_AIRCR_PRIS_Pos 14U
661#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)
663#define SCB_AIRCR_BFHFNMINS_Pos 13U
664#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)
666#define SCB_AIRCR_PRIGROUP_Pos 8U
667#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
669#define SCB_AIRCR_SYSRESETREQS_Pos 3U
670#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
672#define SCB_AIRCR_SYSRESETREQ_Pos 2U
673#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
675#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
676#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
678/* SCB System Control Register Definitions */
679#define SCB_SCR_SEVONPEND_Pos 4U
680#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
682#define SCB_SCR_SLEEPDEEPS_Pos 3U
683#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)
685#define SCB_SCR_SLEEPDEEP_Pos 2U
686#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
688#define SCB_SCR_SLEEPONEXIT_Pos 1U
689#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
691/* SCB Configuration Control Register Definitions */
692#define SCB_CCR_BP_Pos 18U
693#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
695#define SCB_CCR_IC_Pos 17U
696#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
698#define SCB_CCR_DC_Pos 16U
699#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
701#define SCB_CCR_STKOFHFNMIGN_Pos 10U
702#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
704#define SCB_CCR_BFHFNMIGN_Pos 8U
705#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
707#define SCB_CCR_DIV_0_TRP_Pos 4U
708#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
710#define SCB_CCR_UNALIGN_TRP_Pos 3U
711#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
713#define SCB_CCR_USERSETMPEND_Pos 1U
714#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
716/* SCB System Handler Control and State Register Definitions */
717#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U
718#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
720#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U
721#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
723#define SCB_SHCSR_SECUREFAULTENA_Pos 19U
724#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
726#define SCB_SHCSR_USGFAULTENA_Pos 18U
727#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
729#define SCB_SHCSR_BUSFAULTENA_Pos 17U
730#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
732#define SCB_SHCSR_MEMFAULTENA_Pos 16U
733#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
735#define SCB_SHCSR_SVCALLPENDED_Pos 15U
736#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
738#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
739#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
741#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
742#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
744#define SCB_SHCSR_USGFAULTPENDED_Pos 12U
745#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
747#define SCB_SHCSR_SYSTICKACT_Pos 11U
748#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
750#define SCB_SHCSR_PENDSVACT_Pos 10U
751#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
753#define SCB_SHCSR_MONITORACT_Pos 8U
754#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
756#define SCB_SHCSR_SVCALLACT_Pos 7U
757#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
759#define SCB_SHCSR_NMIACT_Pos 5U
760#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)
762#define SCB_SHCSR_SECUREFAULTACT_Pos 4U
763#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
765#define SCB_SHCSR_USGFAULTACT_Pos 3U
766#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
768#define SCB_SHCSR_HARDFAULTACT_Pos 2U
769#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
771#define SCB_SHCSR_BUSFAULTACT_Pos 1U
772#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
774#define SCB_SHCSR_MEMFAULTACT_Pos 0U
775#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
777/* SCB Configurable Fault Status Register Definitions */
778#define SCB_CFSR_USGFAULTSR_Pos 16U
779#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
781#define SCB_CFSR_BUSFAULTSR_Pos 8U
782#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
784#define SCB_CFSR_MEMFAULTSR_Pos 0U
785#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
787/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
788#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U)
789#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
791#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U)
792#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)
794#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U)
795#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
797#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U)
798#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
800#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U)
801#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
803#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U)
804#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
806/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
807#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
808#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
810#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)
811#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)
813#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
814#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
816#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
817#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
819#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
820#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
822#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
823#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
825#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
826#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
828/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
829#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
830#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
832#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
833#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
835#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)
836#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)
838#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
839#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
841#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
842#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
844#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
845#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
847#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
848#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
850/* SCB Hard Fault Status Register Definitions */
851#define SCB_HFSR_DEBUGEVT_Pos 31U
852#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
854#define SCB_HFSR_FORCED_Pos 30U
855#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
857#define SCB_HFSR_VECTTBL_Pos 1U
858#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
860/* SCB Debug Fault Status Register Definitions */
861#define SCB_DFSR_EXTERNAL_Pos 4U
862#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
864#define SCB_DFSR_VCATCH_Pos 3U
865#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
867#define SCB_DFSR_DWTTRAP_Pos 2U
868#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
870#define SCB_DFSR_BKPT_Pos 1U
871#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
873#define SCB_DFSR_HALTED_Pos 0U
874#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
876/* SCB Non-Secure Access Control Register Definitions */
877#define SCB_NSACR_CP11_Pos 11U
878#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)
880#define SCB_NSACR_CP10_Pos 10U
881#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)
883#define SCB_NSACR_CPn_Pos 0U
884#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/)
886/* SCB Cache Level ID Register Definitions */
887#define SCB_CLIDR_LOUU_Pos 27U
888#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)
890#define SCB_CLIDR_LOC_Pos 24U
891#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)
893#define SCB_CLIDR_IC_Pos 0U
894#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos)
896#define SCB_CLIDR_DC_Pos 1U
897#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos)
901/* SCB Cache Type Register Definitions */
902#define SCB_CTR_FORMAT_Pos 29U
903#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)
905#define SCB_CTR_CWG_Pos 24U
906#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
908#define SCB_CTR_ERG_Pos 20U
909#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)
911#define SCB_CTR_DMINLINE_Pos 16U
912#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)
914#define SCB_CTR_IMINLINE_Pos 0U
915#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
917/* SCB Cache Size ID Register Definitions */
918#define SCB_CCSIDR_WT_Pos 31U
919#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)
921#define SCB_CCSIDR_WB_Pos 30U
922#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)
924#define SCB_CCSIDR_RA_Pos 29U
925#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)
927#define SCB_CCSIDR_WA_Pos 28U
928#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)
930#define SCB_CCSIDR_NUMSETS_Pos 13U
931#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
933#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U
934#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
936#define SCB_CCSIDR_LINESIZE_Pos 0U
937#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
939/* SCB Cache Size Selection Register Definitions */
940#define SCB_CSSELR_LEVEL_Pos 1U
941#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)
943#define SCB_CSSELR_IND_Pos 0U
944#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)
946/* SCB Software Triggered Interrupt Register Definitions */
947#define SCB_STIR_INTID_Pos 0U
948#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
950/* SCB D-Cache line Invalidate by Set-way Register Definitions */
951#define SCB_DCISW_LEVEL_Pos 1U
952#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos)
954#define SCB_DCISW_WAY_Pos 30U
955#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)
957#define SCB_DCISW_SET_Pos 5U
958#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos)
960/* SCB D-Cache Clean line by Set-way Register Definitions */
961#define SCB_DCCSW_LEVEL_Pos 1U
962#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos)
964#define SCB_DCCSW_WAY_Pos 30U
965#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)
967#define SCB_DCCSW_SET_Pos 5U
968#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos)
970/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
971#define SCB_DCCISW_LEVEL_Pos 1U
972#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos)
974#define SCB_DCCISW_WAY_Pos 30U
975#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)
977#define SCB_DCCISW_SET_Pos 5U
978#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos)
980/* ArmChina: Implementation Defined */
981/* Instruction Tightly-Coupled Memory Control Register Definitions */
982#define SCB_ITCMCR_SZ_Pos 3U
983#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)
985#define SCB_ITCMCR_EN_Pos 0U
986#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/)
988/* Data Tightly-Coupled Memory Control Register Definitions */
989#define SCB_DTCMCR_SZ_Pos 3U
990#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)
992#define SCB_DTCMCR_EN_Pos 0U
993#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/)
995/* L1 Cache Control Register Definitions */
996#define SCB_CACR_DCCLEAN_Pos 16U
997#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos)
999#define SCB_CACR_ICACTIVE_Pos 13U
1000#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos)
1002#define SCB_CACR_DCACTIVE_Pos 12U
1003#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos)
1005#define SCB_CACR_FORCEWT_Pos 2U
1006#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)
1021typedef struct
1022{
1023 uint32_t RESERVED0[1U];
1024 __IM uint32_t ICTR;
1025 __IOM uint32_t ACTLR;
1026 __IOM uint32_t CPPWR;
1027} SCnSCB_Type;
1028
1029/* Interrupt Controller Type Register Definitions */
1030#define SCnSCB_ICTR_INTLINESNUM_Pos 0U
1031#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
1046typedef struct
1047{
1048 __IOM uint32_t CTRL;
1049 __IOM uint32_t LOAD;
1050 __IOM uint32_t VAL;
1051 __IM uint32_t CALIB;
1052} SysTick_Type;
1053
1054/* SysTick Control / Status Register Definitions */
1055#define SysTick_CTRL_COUNTFLAG_Pos 16U
1056#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
1058#define SysTick_CTRL_CLKSOURCE_Pos 2U
1059#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
1061#define SysTick_CTRL_TICKINT_Pos 1U
1062#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
1064#define SysTick_CTRL_ENABLE_Pos 0U
1065#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
1067/* SysTick Reload Register Definitions */
1068#define SysTick_LOAD_RELOAD_Pos 0U
1069#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
1071/* SysTick Current Register Definitions */
1072#define SysTick_VAL_CURRENT_Pos 0U
1073#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
1075/* SysTick Calibration Register Definitions */
1076#define SysTick_CALIB_NOREF_Pos 31U
1077#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
1079#define SysTick_CALIB_SKEW_Pos 30U
1080#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
1082#define SysTick_CALIB_TENMS_Pos 0U
1083#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
1098typedef struct
1099{
1100 __OM union
1101 {
1102 __OM uint8_t u8;
1103 __OM uint16_t u16;
1104 __OM uint32_t u32;
1105 } PORT [32U];
1106 uint32_t RESERVED0[864U];
1107 __IOM uint32_t TER;
1108 uint32_t RESERVED1[15U];
1109 __IOM uint32_t TPR;
1110 uint32_t RESERVED2[15U];
1111 __IOM uint32_t TCR;
1112 uint32_t RESERVED3[32U];
1113 uint32_t RESERVED4[43U];
1114 __OM uint32_t LAR;
1115 __IM uint32_t LSR;
1116 uint32_t RESERVED5[1U];
1117 __IM uint32_t DEVARCH;
1118 uint32_t RESERVED6[4U];
1119 __IM uint32_t PID4;
1120 __IM uint32_t PID5;
1121 __IM uint32_t PID6;
1122 __IM uint32_t PID7;
1123 __IM uint32_t PID0;
1124 __IM uint32_t PID1;
1125 __IM uint32_t PID2;
1126 __IM uint32_t PID3;
1127 __IM uint32_t CID0;
1128 __IM uint32_t CID1;
1129 __IM uint32_t CID2;
1130 __IM uint32_t CID3;
1131} ITM_Type;
1132
1133/* ITM Stimulus Port Register Definitions */
1134#define ITM_STIM_DISABLED_Pos 1U
1135#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)
1137#define ITM_STIM_FIFOREADY_Pos 0U
1138#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
1140/* ITM Trace Privilege Register Definitions */
1141#define ITM_TPR_PRIVMASK_Pos 0U
1142#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
1144/* ITM Trace Control Register Definitions */
1145#define ITM_TCR_BUSY_Pos 23U
1146#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
1148#define ITM_TCR_TRACEBUSID_Pos 16U
1149#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
1151#define ITM_TCR_GTSFREQ_Pos 10U
1152#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
1154#define ITM_TCR_TSPRESCALE_Pos 8U
1155#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)
1157#define ITM_TCR_STALLENA_Pos 5U
1158#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)
1160#define ITM_TCR_SWOENA_Pos 4U
1161#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
1163#define ITM_TCR_DWTENA_Pos 3U
1164#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
1166#define ITM_TCR_SYNCENA_Pos 2U
1167#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
1169#define ITM_TCR_TSENA_Pos 1U
1170#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
1172#define ITM_TCR_ITMENA_Pos 0U
1173#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
1175/* ITM Lock Status Register Definitions */
1176#define ITM_LSR_ByteAcc_Pos 2U
1177#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
1179#define ITM_LSR_Access_Pos 1U
1180#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
1182#define ITM_LSR_Present_Pos 0U
1183#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /* end of group CMSIS_ITM */
1186
1187
1198typedef struct
1199{
1200 __IOM uint32_t CTRL;
1201 __IOM uint32_t CYCCNT;
1202 __IOM uint32_t CPICNT;
1203 __IOM uint32_t EXCCNT;
1204 __IOM uint32_t SLEEPCNT;
1205 __IOM uint32_t LSUCNT;
1206 __IOM uint32_t FOLDCNT;
1207 __IM uint32_t PCSR;
1208 __IOM uint32_t COMP0;
1209 uint32_t RESERVED1[1U];
1210 __IOM uint32_t FUNCTION0;
1211 uint32_t RESERVED2[1U];
1212 __IOM uint32_t COMP1;
1213 uint32_t RESERVED3[1U];
1214 __IOM uint32_t FUNCTION1;
1215 uint32_t RESERVED4[1U];
1216 __IOM uint32_t COMP2;
1217 uint32_t RESERVED5[1U];
1218 __IOM uint32_t FUNCTION2;
1219 uint32_t RESERVED6[1U];
1220 __IOM uint32_t COMP3;
1221 uint32_t RESERVED7[1U];
1222 __IOM uint32_t FUNCTION3;
1223 uint32_t RESERVED8[1U];
1224 __IOM uint32_t COMP4;
1225 uint32_t RESERVED9[1U];
1226 __IOM uint32_t FUNCTION4;
1227 uint32_t RESERVED10[1U];
1228 __IOM uint32_t COMP5;
1229 uint32_t RESERVED11[1U];
1230 __IOM uint32_t FUNCTION5;
1231 uint32_t RESERVED12[1U];
1232 __IOM uint32_t COMP6;
1233 uint32_t RESERVED13[1U];
1234 __IOM uint32_t FUNCTION6;
1235 uint32_t RESERVED14[1U];
1236 __IOM uint32_t COMP7;
1237 uint32_t RESERVED15[1U];
1238 __IOM uint32_t FUNCTION7;
1239 uint32_t RESERVED16[1U];
1240 __IOM uint32_t COMP8;
1241 uint32_t RESERVED17[1U];
1242 __IOM uint32_t FUNCTION8;
1243 uint32_t RESERVED18[1U];
1244 __IOM uint32_t COMP9;
1245 uint32_t RESERVED19[1U];
1246 __IOM uint32_t FUNCTION9;
1247 uint32_t RESERVED20[1U];
1248 __IOM uint32_t COMP10;
1249 uint32_t RESERVED21[1U];
1250 __IOM uint32_t FUNCTION10;
1251 uint32_t RESERVED22[1U];
1252 __IOM uint32_t COMP11;
1253 uint32_t RESERVED23[1U];
1254 __IOM uint32_t FUNCTION11;
1255 uint32_t RESERVED24[1U];
1256 __IOM uint32_t COMP12;
1257 uint32_t RESERVED25[1U];
1258 __IOM uint32_t FUNCTION12;
1259 uint32_t RESERVED26[1U];
1260 __IOM uint32_t COMP13;
1261 uint32_t RESERVED27[1U];
1262 __IOM uint32_t FUNCTION13;
1263 uint32_t RESERVED28[1U];
1264 __IOM uint32_t COMP14;
1265 uint32_t RESERVED29[1U];
1266 __IOM uint32_t FUNCTION14;
1267 uint32_t RESERVED30[1U];
1268 __IOM uint32_t COMP15;
1269 uint32_t RESERVED31[1U];
1270 __IOM uint32_t FUNCTION15;
1271 uint32_t RESERVED32[934U];
1272 __IM uint32_t LSR;
1273 uint32_t RESERVED33[1U];
1274 __IM uint32_t DEVARCH;
1275} DWT_Type;
1276
1277/* DWT Control Register Definitions */
1278#define DWT_CTRL_NUMCOMP_Pos 28U
1279#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
1281#define DWT_CTRL_NOTRCPKT_Pos 27U
1282#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
1284#define DWT_CTRL_NOEXTTRIG_Pos 26U
1285#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
1287#define DWT_CTRL_NOCYCCNT_Pos 25U
1288#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
1290#define DWT_CTRL_NOPRFCNT_Pos 24U
1291#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
1293#define DWT_CTRL_CYCDISS_Pos 23U
1294#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos)
1296#define DWT_CTRL_CYCEVTENA_Pos 22U
1297#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
1299#define DWT_CTRL_FOLDEVTENA_Pos 21U
1300#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
1302#define DWT_CTRL_LSUEVTENA_Pos 20U
1303#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
1305#define DWT_CTRL_SLEEPEVTENA_Pos 19U
1306#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
1308#define DWT_CTRL_EXCEVTENA_Pos 18U
1309#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
1311#define DWT_CTRL_CPIEVTENA_Pos 17U
1312#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
1314#define DWT_CTRL_EXCTRCENA_Pos 16U
1315#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
1317#define DWT_CTRL_PCSAMPLENA_Pos 12U
1318#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
1320#define DWT_CTRL_SYNCTAP_Pos 10U
1321#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
1323#define DWT_CTRL_CYCTAP_Pos 9U
1324#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
1326#define DWT_CTRL_POSTINIT_Pos 5U
1327#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
1329#define DWT_CTRL_POSTPRESET_Pos 1U
1330#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
1332#define DWT_CTRL_CYCCNTENA_Pos 0U
1333#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
1335/* DWT CPI Count Register Definitions */
1336#define DWT_CPICNT_CPICNT_Pos 0U
1337#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
1339/* DWT Exception Overhead Count Register Definitions */
1340#define DWT_EXCCNT_EXCCNT_Pos 0U
1341#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
1343/* DWT Sleep Count Register Definitions */
1344#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
1345#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
1347/* DWT LSU Count Register Definitions */
1348#define DWT_LSUCNT_LSUCNT_Pos 0U
1349#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
1351/* DWT Folded-instruction Count Register Definitions */
1352#define DWT_FOLDCNT_FOLDCNT_Pos 0U
1353#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
1355/* DWT Comparator Function Register Definitions */
1356#define DWT_FUNCTION_ID_Pos 27U
1357#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)
1359#define DWT_FUNCTION_MATCHED_Pos 24U
1360#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
1362#define DWT_FUNCTION_DATAVSIZE_Pos 10U
1363#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
1365#define DWT_FUNCTION_ACTION_Pos 4U
1366#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos)
1368#define DWT_FUNCTION_MATCH_Pos 0U
1369#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /* end of group CMSIS_DWT */
1372
1373
1384typedef struct
1385{
1386 __IM uint32_t SSPSR;
1387 __IOM uint32_t CSPSR;
1388 uint32_t RESERVED0[2U];
1389 __IOM uint32_t ACPR;
1390 uint32_t RESERVED1[55U];
1391 __IOM uint32_t SPPR;
1392 uint32_t RESERVED2[131U];
1393 __IM uint32_t FFSR;
1394 __IOM uint32_t FFCR;
1395 __IOM uint32_t PSCR;
1396 uint32_t RESERVED3[759U];
1397 __IM uint32_t TRIGGER;
1398 __IM uint32_t ITFTTD0;
1399 __IOM uint32_t ITATBCTR2;
1400 uint32_t RESERVED4[1U];
1401 __IM uint32_t ITATBCTR0;
1402 __IM uint32_t ITFTTD1;
1403 __IOM uint32_t ITCTRL;
1404 uint32_t RESERVED5[39U];
1405 __IOM uint32_t CLAIMSET;
1406 __IOM uint32_t CLAIMCLR;
1407 uint32_t RESERVED7[8U];
1408 __IM uint32_t DEVID;
1409 __IM uint32_t DEVTYPE;
1410} TPI_Type;
1411
1412/* TPI Asynchronous Clock Prescaler Register Definitions */
1413#define TPI_ACPR_PRESCALER_Pos 0U
1414#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
1416/* TPI Selected Pin Protocol Register Definitions */
1417#define TPI_SPPR_TXMODE_Pos 0U
1418#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
1420/* TPI Formatter and Flush Status Register Definitions */
1421#define TPI_FFSR_FtNonStop_Pos 3U
1422#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1424#define TPI_FFSR_TCPresent_Pos 2U
1425#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1427#define TPI_FFSR_FtStopped_Pos 1U
1428#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1430#define TPI_FFSR_FlInProg_Pos 0U
1431#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
1433/* TPI Formatter and Flush Control Register Definitions */
1434#define TPI_FFCR_TrigIn_Pos 8U
1435#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1437#define TPI_FFCR_FOnMan_Pos 6U
1438#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
1440#define TPI_FFCR_EnFCont_Pos 1U
1441#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1443/* TPI TRIGGER Register Definitions */
1444#define TPI_TRIGGER_TRIGGER_Pos 0U
1445#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
1447/* TPI Integration Test FIFO Test Data 0 Register Definitions */
1448#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U
1449#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)
1451#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U
1452#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)
1454#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U
1455#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)
1457#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U
1458#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)
1460#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U
1461#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
1463#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U
1464#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
1466#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U
1467#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/)
1469/* TPI Integration Test ATB Control Register 2 Register Definitions */
1470#define TPI_ITATBCTR2_AFVALID2S_Pos 1U
1471#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)
1473#define TPI_ITATBCTR2_AFVALID1S_Pos 1U
1474#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)
1476#define TPI_ITATBCTR2_ATREADY2S_Pos 0U
1477#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)
1479#define TPI_ITATBCTR2_ATREADY1S_Pos 0U
1480#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)
1482/* TPI Integration Test FIFO Test Data 1 Register Definitions */
1483#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U
1484#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)
1486#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U
1487#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)
1489#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U
1490#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)
1492#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U
1493#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)
1495#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U
1496#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
1498#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U
1499#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
1501#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U
1502#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/)
1504/* TPI Integration Test ATB Control Register 0 Definitions */
1505#define TPI_ITATBCTR0_AFVALID2S_Pos 1U
1506#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)
1508#define TPI_ITATBCTR0_AFVALID1S_Pos 1U
1509#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)
1511#define TPI_ITATBCTR0_ATREADY2S_Pos 0U
1512#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)
1514#define TPI_ITATBCTR0_ATREADY1S_Pos 0U
1515#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)
1517/* TPI Integration Mode Control Register Definitions */
1518#define TPI_ITCTRL_Mode_Pos 0U
1519#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
1521/* TPI DEVID Register Definitions */
1522#define TPI_DEVID_NRZVALID_Pos 11U
1523#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1525#define TPI_DEVID_MANCVALID_Pos 10U
1526#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1528#define TPI_DEVID_PTINVALID_Pos 9U
1529#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1531#define TPI_DEVID_FIFOSZ_Pos 6U
1532#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
1534#define TPI_DEVID_NrTraceInput_Pos 0U
1535#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
1537/* TPI DEVTYPE Register Definitions */
1538#define TPI_DEVTYPE_SubType_Pos 4U
1539#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
1541#define TPI_DEVTYPE_MajorType_Pos 0U
1542#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /* end of group CMSIS_TPI */
1545
1546
1547#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1558typedef struct
1559{
1560 __IM uint32_t TYPE;
1561 __IOM uint32_t CTRL;
1562 __IOM uint32_t RNR;
1563 __IOM uint32_t RBAR;
1564 __IOM uint32_t RLAR;
1565 __IOM uint32_t RBAR_A1;
1566 __IOM uint32_t RLAR_A1;
1567 __IOM uint32_t RBAR_A2;
1568 __IOM uint32_t RLAR_A2;
1569 __IOM uint32_t RBAR_A3;
1570 __IOM uint32_t RLAR_A3;
1571 uint32_t RESERVED0[1];
1572 union {
1573 __IOM uint32_t MAIR[2];
1574 struct {
1575 __IOM uint32_t MAIR0;
1576 __IOM uint32_t MAIR1;
1577 };
1578 };
1579} MPU_Type;
1580
1581#define MPU_TYPE_RALIASES 4U
1582
1583/* MPU Type Register Definitions */
1584#define MPU_TYPE_IREGION_Pos 16U
1585#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1587#define MPU_TYPE_DREGION_Pos 8U
1588#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1590#define MPU_TYPE_SEPARATE_Pos 0U
1591#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
1593/* MPU Control Register Definitions */
1594#define MPU_CTRL_PRIVDEFENA_Pos 2U
1595#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1597#define MPU_CTRL_HFNMIENA_Pos 1U
1598#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1600#define MPU_CTRL_ENABLE_Pos 0U
1601#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
1603/* MPU Region Number Register Definitions */
1604#define MPU_RNR_REGION_Pos 0U
1605#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
1607/* MPU Region Base Address Register Definitions */
1608#define MPU_RBAR_BASE_Pos 5U
1609#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
1611#define MPU_RBAR_SH_Pos 3U
1612#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
1614#define MPU_RBAR_AP_Pos 1U
1615#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
1617#define MPU_RBAR_XN_Pos 0U
1618#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/)
1620/* MPU Region Limit Address Register Definitions */
1621#define MPU_RLAR_LIMIT_Pos 5U
1622#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
1624#define MPU_RLAR_AttrIndx_Pos 1U
1625#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
1627#define MPU_RLAR_EN_Pos 0U
1628#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/)
1630/* MPU Memory Attribute Indirection Register 0 Definitions */
1631#define MPU_MAIR0_Attr3_Pos 24U
1632#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
1634#define MPU_MAIR0_Attr2_Pos 16U
1635#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
1637#define MPU_MAIR0_Attr1_Pos 8U
1638#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
1640#define MPU_MAIR0_Attr0_Pos 0U
1641#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)
1643/* MPU Memory Attribute Indirection Register 1 Definitions */
1644#define MPU_MAIR1_Attr7_Pos 24U
1645#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
1647#define MPU_MAIR1_Attr6_Pos 16U
1648#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
1650#define MPU_MAIR1_Attr5_Pos 8U
1651#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
1653#define MPU_MAIR1_Attr4_Pos 0U
1654#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)
1657#endif
1658
1659
1660#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1671typedef struct
1672{
1673 __IOM uint32_t CTRL;
1674 __IM uint32_t TYPE;
1675#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1676 __IOM uint32_t RNR;
1677 __IOM uint32_t RBAR;
1678 __IOM uint32_t RLAR;
1679#else
1680 uint32_t RESERVED0[3];
1681#endif
1682 __IOM uint32_t SFSR;
1683 __IOM uint32_t SFAR;
1684} SAU_Type;
1685
1686/* SAU Control Register Definitions */
1687#define SAU_CTRL_ALLNS_Pos 1U
1688#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos)
1690#define SAU_CTRL_ENABLE_Pos 0U
1691#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/)
1693/* SAU Type Register Definitions */
1694#define SAU_TYPE_SREGION_Pos 0U
1695#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)
1697#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1698/* SAU Region Number Register Definitions */
1699#define SAU_RNR_REGION_Pos 0U
1700#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/)
1702/* SAU Region Base Address Register Definitions */
1703#define SAU_RBAR_BADDR_Pos 5U
1704#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)
1706/* SAU Region Limit Address Register Definitions */
1707#define SAU_RLAR_LADDR_Pos 5U
1708#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)
1710#define SAU_RLAR_NSC_Pos 1U
1711#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos)
1713#define SAU_RLAR_ENABLE_Pos 0U
1714#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/)
1716#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1717
1718/* Secure Fault Status Register Definitions */
1719#define SAU_SFSR_LSERR_Pos 7U
1720#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos)
1722#define SAU_SFSR_SFARVALID_Pos 6U
1723#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos)
1725#define SAU_SFSR_LSPERR_Pos 5U
1726#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos)
1728#define SAU_SFSR_INVTRAN_Pos 4U
1729#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos)
1731#define SAU_SFSR_AUVIOL_Pos 3U
1732#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos)
1734#define SAU_SFSR_INVER_Pos 2U
1735#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos)
1737#define SAU_SFSR_INVIS_Pos 1U
1738#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos)
1740#define SAU_SFSR_INVEP_Pos 0U
1741#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/)
1744#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1745
1746
1757typedef struct
1758{
1759 uint32_t RESERVED0[1U];
1760 __IOM uint32_t FPCCR;
1761 __IOM uint32_t FPCAR;
1762 __IOM uint32_t FPDSCR;
1763 __IM uint32_t MVFR0;
1764 __IM uint32_t MVFR1;
1765 __IM uint32_t MVFR2;
1766} FPU_Type;
1767
1768/* Floating-Point Context Control Register Definitions */
1769#define FPU_FPCCR_ASPEN_Pos 31U
1770#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
1772#define FPU_FPCCR_LSPEN_Pos 30U
1773#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
1775#define FPU_FPCCR_LSPENS_Pos 29U
1776#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)
1778#define FPU_FPCCR_CLRONRET_Pos 28U
1779#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)
1781#define FPU_FPCCR_CLRONRETS_Pos 27U
1782#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)
1784#define FPU_FPCCR_TS_Pos 26U
1785#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)
1787#define FPU_FPCCR_UFRDY_Pos 10U
1788#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)
1790#define FPU_FPCCR_SPLIMVIOL_Pos 9U
1791#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
1793#define FPU_FPCCR_MONRDY_Pos 8U
1794#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
1796#define FPU_FPCCR_SFRDY_Pos 7U
1797#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)
1799#define FPU_FPCCR_BFRDY_Pos 6U
1800#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
1802#define FPU_FPCCR_MMRDY_Pos 5U
1803#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
1805#define FPU_FPCCR_HFRDY_Pos 4U
1806#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
1808#define FPU_FPCCR_THREAD_Pos 3U
1809#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
1811#define FPU_FPCCR_S_Pos 2U
1812#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)
1814#define FPU_FPCCR_USER_Pos 1U
1815#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
1817#define FPU_FPCCR_LSPACT_Pos 0U
1818#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
1820/* Floating-Point Context Address Register Definitions */
1821#define FPU_FPCAR_ADDRESS_Pos 3U
1822#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
1824/* Floating-Point Default Status Control Register Definitions */
1825#define FPU_FPDSCR_AHP_Pos 26U
1826#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
1828#define FPU_FPDSCR_DN_Pos 25U
1829#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
1831#define FPU_FPDSCR_FZ_Pos 24U
1832#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
1834#define FPU_FPDSCR_RMode_Pos 22U
1835#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
1837/* Media and VFP Feature Register 0 Definitions */
1838#define FPU_MVFR0_FP_rounding_modes_Pos 28U
1839#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
1841#define FPU_MVFR0_Short_vectors_Pos 24U
1842#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
1844#define FPU_MVFR0_Square_root_Pos 20U
1845#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
1847#define FPU_MVFR0_Divide_Pos 16U
1848#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
1850#define FPU_MVFR0_FP_excep_trapping_Pos 12U
1851#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
1853#define FPU_MVFR0_Double_precision_Pos 8U
1854#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
1856#define FPU_MVFR0_Single_precision_Pos 4U
1857#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
1859#define FPU_MVFR0_A_SIMD_registers_Pos 0U
1860#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
1862/* Media and VFP Feature Register 1 Definitions */
1863#define FPU_MVFR1_FP_fused_MAC_Pos 28U
1864#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
1866#define FPU_MVFR1_FP_HPFP_Pos 24U
1867#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
1869#define FPU_MVFR1_D_NaN_mode_Pos 4U
1870#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
1872#define FPU_MVFR1_FtZ_mode_Pos 0U
1873#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
1875/* Media and VFP Feature Register 2 Definitions */
1876#define FPU_MVFR2_FPMisc_Pos 4U
1877#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos)
1895typedef struct
1896{
1897 __IOM uint32_t DHCSR;
1898 __OM uint32_t DCRSR;
1899 __IOM uint32_t DCRDR;
1900 __IOM uint32_t DEMCR;
1901 uint32_t RESERVED0[1U];
1902 __IOM uint32_t DAUTHCTRL;
1903 __IOM uint32_t DSCSR;
1904} DCB_Type;
1905
1906/* DHCSR, Debug Halting Control and Status Register Definitions */
1907#define DCB_DHCSR_DBGKEY_Pos 16U
1908#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
1910#define DCB_DHCSR_S_RESTART_ST_Pos 26U
1911#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
1913#define DCB_DHCSR_S_RESET_ST_Pos 25U
1914#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
1916#define DCB_DHCSR_S_RETIRE_ST_Pos 24U
1917#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
1919#define DCB_DHCSR_S_SDE_Pos 20U
1920#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)
1922#define DCB_DHCSR_S_LOCKUP_Pos 19U
1923#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
1925#define DCB_DHCSR_S_SLEEP_Pos 18U
1926#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
1928#define DCB_DHCSR_S_HALT_Pos 17U
1929#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)
1931#define DCB_DHCSR_S_REGRDY_Pos 16U
1932#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
1934#define DCB_DHCSR_C_SNAPSTALL_Pos 5U
1935#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
1937#define DCB_DHCSR_C_MASKINTS_Pos 3U
1938#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
1940#define DCB_DHCSR_C_STEP_Pos 2U
1941#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)
1943#define DCB_DHCSR_C_HALT_Pos 1U
1944#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)
1946#define DCB_DHCSR_C_DEBUGEN_Pos 0U
1947#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)
1949/* DCRSR, Debug Core Register Select Register Definitions */
1950#define DCB_DCRSR_REGWnR_Pos 16U
1951#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)
1953#define DCB_DCRSR_REGSEL_Pos 0U
1954#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)
1956/* DCRDR, Debug Core Register Data Register Definitions */
1957#define DCB_DCRDR_DBGTMP_Pos 0U
1958#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)
1960/* DEMCR, Debug Exception and Monitor Control Register Definitions */
1961#define DCB_DEMCR_TRCENA_Pos 24U
1962#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)
1964#define DCB_DEMCR_MONPRKEY_Pos 23U
1965#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
1967#define DCB_DEMCR_UMON_EN_Pos 21U
1968#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos)
1970#define DCB_DEMCR_SDME_Pos 20U
1971#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos)
1973#define DCB_DEMCR_MON_REQ_Pos 19U
1974#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos)
1976#define DCB_DEMCR_MON_STEP_Pos 18U
1977#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos)
1979#define DCB_DEMCR_MON_PEND_Pos 17U
1980#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos)
1982#define DCB_DEMCR_MON_EN_Pos 16U
1983#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos)
1985#define DCB_DEMCR_VC_SFERR_Pos 11U
1986#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
1988#define DCB_DEMCR_VC_HARDERR_Pos 10U
1989#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
1991#define DCB_DEMCR_VC_INTERR_Pos 9U
1992#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
1994#define DCB_DEMCR_VC_BUSERR_Pos 8U
1995#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
1997#define DCB_DEMCR_VC_STATERR_Pos 7U
1998#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
2000#define DCB_DEMCR_VC_CHKERR_Pos 6U
2001#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
2003#define DCB_DEMCR_VC_NOCPERR_Pos 5U
2004#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
2006#define DCB_DEMCR_VC_MMERR_Pos 4U
2007#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
2009#define DCB_DEMCR_VC_CORERESET_Pos 0U
2010#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)
2012/* DAUTHCTRL, Debug Authentication Control Register Definitions */
2013#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U
2014#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
2016#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U
2017#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
2019#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U
2020#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
2022#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U
2023#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)
2025/* DSCSR, Debug Security Control and Status Register Definitions */
2026#define DCB_DSCSR_CDSKEY_Pos 17U
2027#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)
2029#define DCB_DSCSR_CDS_Pos 16U
2030#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)
2032#define DCB_DSCSR_SBRSEL_Pos 1U
2033#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)
2035#define DCB_DSCSR_SBRSELEN_Pos 0U
2036#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)
2052typedef struct
2053{
2054 __OM uint32_t DLAR;
2055 __IM uint32_t DLSR;
2056 __IM uint32_t DAUTHSTATUS;
2057 __IM uint32_t DDEVARCH;
2058 __IM uint32_t DDEVTYPE;
2059} DIB_Type;
2060
2061/* DLAR, SCS Software Lock Access Register Definitions */
2062#define DIB_DLAR_KEY_Pos 0U
2063#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */)
2065/* DLSR, SCS Software Lock Status Register Definitions */
2066#define DIB_DLSR_nTT_Pos 2U
2067#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos )
2069#define DIB_DLSR_SLK_Pos 1U
2070#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos )
2072#define DIB_DLSR_SLI_Pos 0U
2073#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/)
2075/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
2076#define DIB_DAUTHSTATUS_SNID_Pos 6U
2077#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )
2079#define DIB_DAUTHSTATUS_SID_Pos 4U
2080#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos )
2082#define DIB_DAUTHSTATUS_NSNID_Pos 2U
2083#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )
2085#define DIB_DAUTHSTATUS_NSID_Pos 0U
2086#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/)
2088/* DDEVARCH, SCS Device Architecture Register Definitions */
2089#define DIB_DDEVARCH_ARCHITECT_Pos 21U
2090#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )
2092#define DIB_DDEVARCH_PRESENT_Pos 20U
2093#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )
2095#define DIB_DDEVARCH_REVISION_Pos 16U
2096#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos )
2098#define DIB_DDEVARCH_ARCHVER_Pos 12U
2099#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )
2101#define DIB_DDEVARCH_ARCHPART_Pos 0U
2102#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/)
2104/* DDEVTYPE, SCS Device Type Register Definitions */
2105#define DIB_DDEVTYPE_SUB_Pos 4U
2106#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos )
2108#define DIB_DDEVTYPE_MAJOR_Pos 0U
2109#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/)
2128#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
2129
2136#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
2137
2148/* Memory mapping of Core Hardware */
2149 #define SCS_BASE (0xE000E000UL)
2150 #define ITM_BASE (0xE0000000UL)
2151 #define DWT_BASE (0xE0001000UL)
2152 #define TPI_BASE (0xE0040000UL)
2153 #define DCB_BASE (0xE000EDF0UL)
2154 #define DIB_BASE (0xE000EFB0UL)
2155 #define EMSS_BASE (0xE001E000UL)
2157 #define SysTick_BASE (SCS_BASE + 0x0010UL)
2158 #define NVIC_BASE (SCS_BASE + 0x0100UL)
2159 #define SCB_BASE (SCS_BASE + 0x0D00UL)
2161 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
2162 #define SCB ((SCB_Type *) SCB_BASE )
2163 #define SysTick ((SysTick_Type *) SysTick_BASE )
2164 #define NVIC ((NVIC_Type *) NVIC_BASE )
2165 #define ITM ((ITM_Type *) ITM_BASE )
2166 #define DWT ((DWT_Type *) DWT_BASE )
2167 #define TPI ((TPI_Type *) TPI_BASE )
2168 #define DCB ((DCB_Type *) DCB_BASE )
2169 #define DIB ((DIB_Type *) DIB_BASE )
2170 #define EMSS ((EMSS_Type *) EMSS_BASE )
2172 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2173 #define MPU_BASE (SCS_BASE + 0x0D90UL)
2174 #define MPU ((MPU_Type *) MPU_BASE )
2175 #endif
2176
2177 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2178 #define SAU_BASE (SCS_BASE + 0x0DD0UL)
2179 #define SAU ((SAU_Type *) SAU_BASE )
2180 #endif
2181
2182 #define FPU_BASE (SCS_BASE + 0x0F30UL)
2183 #define FPU ((FPU_Type *) FPU_BASE )
2185#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2186 #define SCS_BASE_NS (0xE002E000UL)
2188 #define DCB_BASE_NS (0xE002EDF0UL)
2189 #define DIB_BASE_NS (0xE002EFB0UL)
2190 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL)
2191 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL)
2192 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL)
2194 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS )
2195 #define SCB_NS ((SCB_Type *) SCB_BASE_NS )
2196 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS )
2197 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS )
2198 #define DCB_NS ((DCB_Type *) DCB_BASE_NS )
2199 #define DIB_NS ((DIB_Type *) DIB_BASE_NS )
2201 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2202 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL)
2203 #define MPU_NS ((MPU_Type *) MPU_BASE_NS )
2204 #endif
2205
2206 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL)
2207 #define FPU_NS ((FPU_Type *) FPU_BASE_NS )
2209#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2214/*******************************************************************************
2215 * Hardware Abstraction Layer
2216 Core Function Interface contains:
2217 - Core NVIC Functions
2218 - Core SysTick Functions
2219 - Core Debug Functions
2220 - Core Register Access Functions
2221 ******************************************************************************/
2228/* ########################## NVIC functions #################################### */
2236#ifdef CMSIS_NVIC_VIRTUAL
2237 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
2238 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
2239 #endif
2240 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
2241#else
2242 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
2243 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
2244 #define NVIC_EnableIRQ __NVIC_EnableIRQ
2245 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
2246 #define NVIC_DisableIRQ __NVIC_DisableIRQ
2247 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
2248 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
2249 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
2250 #define NVIC_GetActive __NVIC_GetActive
2251 #define NVIC_SetPriority __NVIC_SetPriority
2252 #define NVIC_GetPriority __NVIC_GetPriority
2253 #define NVIC_SystemReset __NVIC_SystemReset
2254 #define SW_SystemReset __SW_SystemReset
2255#endif /* CMSIS_NVIC_VIRTUAL */
2256
2257#ifdef CMSIS_VECTAB_VIRTUAL
2258 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2259 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
2260 #endif
2261 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2262#else
2263 #define NVIC_SetVector __NVIC_SetVector
2264 #define NVIC_GetVector __NVIC_GetVector
2265#endif /* (CMSIS_VECTAB_VIRTUAL) */
2266
2267#define NVIC_USER_IRQ_OFFSET 16
2268
2269
2270/* Special LR values for Secure/Non-Secure call handling and exception handling */
2271
2272/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
2273#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
2274
2275/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
2276#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
2277#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
2278#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
2279#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
2280#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
2281#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
2282#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
2283
2284/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
2285#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
2286#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
2287#else
2288#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
2289#endif
2290
2291
2301__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
2302{
2303 uint32_t reg_value;
2304 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2305
2306 reg_value = SCB->AIRCR; /* read old register configuration */
2307 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2308 reg_value = (reg_value |
2309 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2310 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2311 SCB->AIRCR = reg_value;
2312}
2313
2314
2320__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
2321{
2322 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2323}
2324
2325
2332__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
2333{
2334 if ((int32_t)(IRQn) >= 0)
2335 {
2336 __COMPILER_BARRIER();
2337 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2338 __COMPILER_BARRIER();
2339 }
2340}
2341
2342
2351__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
2352{
2353 if ((int32_t)(IRQn) >= 0)
2354 {
2355 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2356 }
2357 else
2358 {
2359 return(0U);
2360 }
2361}
2362
2363
2370__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
2371{
2372 if ((int32_t)(IRQn) >= 0)
2373 {
2374 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2375 __DSB();
2376 __ISB();
2377 }
2378}
2379
2380
2389__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2390{
2391 if ((int32_t)(IRQn) >= 0)
2392 {
2393 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2394 }
2395 else
2396 {
2397 return(0U);
2398 }
2399}
2400
2401
2408__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2409{
2410 if ((int32_t)(IRQn) >= 0)
2411 {
2412 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2413 }
2414}
2415
2416
2423__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2424{
2425 if ((int32_t)(IRQn) >= 0)
2426 {
2427 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2428 }
2429}
2430
2431
2440__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2441{
2442 if ((int32_t)(IRQn) >= 0)
2443 {
2444 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2445 }
2446 else
2447 {
2448 return(0U);
2449 }
2450}
2451
2452
2453#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2462__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
2463{
2464 if ((int32_t)(IRQn) >= 0)
2465 {
2466 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2467 }
2468 else
2469 {
2470 return(0U);
2471 }
2472}
2473
2474
2483__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
2484{
2485 if ((int32_t)(IRQn) >= 0)
2486 {
2487 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2488 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2489 }
2490 else
2491 {
2492 return(0U);
2493 }
2494}
2495
2496
2505__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
2506{
2507 if ((int32_t)(IRQn) >= 0)
2508 {
2509 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2510 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2511 }
2512 else
2513 {
2514 return(0U);
2515 }
2516}
2517#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2518
2519
2529__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2530{
2531 if ((int32_t)(IRQn) >= 0)
2532 {
2533 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2534 }
2535 else
2536 {
2537 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2538 }
2539}
2540
2541
2551__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2552{
2553
2554 if ((int32_t)(IRQn) >= 0)
2555 {
2556 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2557 }
2558 else
2559 {
2560 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2561 }
2562}
2563
2564
2576__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2577{
2578 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2579 uint32_t PreemptPriorityBits;
2580 uint32_t SubPriorityBits;
2581
2582 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2583 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2584
2585 return (
2586 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2587 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2588 );
2589}
2590
2591
2603__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2604{
2605 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2606 uint32_t PreemptPriorityBits;
2607 uint32_t SubPriorityBits;
2608
2609 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2610 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2611
2612 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2613 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2614}
2615
2616
2626__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2627{
2628 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2629 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2630 __DSB();
2631}
2632
2633
2642__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2643{
2644 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2645 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2646}
2647
2648
2653__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2654{
2655 __DSB(); /* Ensure all outstanding memory accesses including
2656 buffered write are completed before reset */
2657 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2658 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2659 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2660 __DSB(); /* Ensure completion of memory access */
2661
2662 for(;;) /* wait until reset */
2663 {
2664 __NOP();
2665 }
2666}
2667
2672__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void)
2673{
2674 __DSB(); /* Ensure all outstanding memory accesses including
2675 buffered write are completed before reset */
2676 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2677 (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */
2678 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */
2679 SCB_AIRCR_SYSRESETREQ_Msk );
2680 __DSB(); /* Ensure completion of memory access */
2681
2682 for(;;) /* wait until reset */
2683 {
2684 __NOP();
2685 }
2686}
2687
2688
2689#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2699__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
2700{
2701 uint32_t reg_value;
2702 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2703
2704 reg_value = SCB_NS->AIRCR; /* read old register configuration */
2705 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2706 reg_value = (reg_value |
2707 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2708 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2709 SCB_NS->AIRCR = reg_value;
2710}
2711
2712
2718__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
2719{
2720 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2721}
2722
2723
2730__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
2731{
2732 if ((int32_t)(IRQn) >= 0)
2733 {
2734 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2735 }
2736}
2737
2738
2747__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
2748{
2749 if ((int32_t)(IRQn) >= 0)
2750 {
2751 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2752 }
2753 else
2754 {
2755 return(0U);
2756 }
2757}
2758
2759
2766__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
2767{
2768 if ((int32_t)(IRQn) >= 0)
2769 {
2770 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2771 }
2772}
2773
2774
2783__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
2784{
2785 if ((int32_t)(IRQn) >= 0)
2786 {
2787 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2788 }
2789 else
2790 {
2791 return(0U);
2792 }
2793}
2794
2795
2802__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
2803{
2804 if ((int32_t)(IRQn) >= 0)
2805 {
2806 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2807 }
2808}
2809
2810
2817__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
2818{
2819 if ((int32_t)(IRQn) >= 0)
2820 {
2821 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2822 }
2823}
2824
2825
2834__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
2835{
2836 if ((int32_t)(IRQn) >= 0)
2837 {
2838 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2839 }
2840 else
2841 {
2842 return(0U);
2843 }
2844}
2845
2846
2856__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
2857{
2858 if ((int32_t)(IRQn) >= 0)
2859 {
2860 NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2861 }
2862 else
2863 {
2864 SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2865 }
2866}
2867
2868
2877__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
2878{
2879
2880 if ((int32_t)(IRQn) >= 0)
2881 {
2882 return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2883 }
2884 else
2885 {
2886 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2887 }
2888}
2889#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
2890
2893/* ########################## MPU functions #################################### */
2894
2895#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2896
2897#include "mpu_armv8.h"
2898
2899#endif
2900
2901/* ########################## FPU functions #################################### */
2917__STATIC_INLINE uint32_t SCB_GetFPUType(void)
2918{
2919 uint32_t mvfr0;
2920
2921 mvfr0 = FPU->MVFR0;
2922 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
2923 {
2924 return 2U; /* Double + Single precision FPU */
2925 }
2926 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2927 {
2928 return 1U; /* Single precision FPU */
2929 }
2930 else
2931 {
2932 return 0U; /* No FPU */
2933 }
2934}
2935
2936
2941/* ########################## SAU functions #################################### */
2949#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2950
2955__STATIC_INLINE void TZ_SAU_Enable(void)
2956{
2957 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
2958}
2959
2960
2961
2966__STATIC_INLINE void TZ_SAU_Disable(void)
2967{
2968 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
2969}
2970
2971#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2972
2977/* ################################## Debug Control function ############################################ */
2991__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
2992{
2993 __DSB();
2994 __ISB();
2995 DCB->DAUTHCTRL = value;
2996 __DSB();
2997 __ISB();
2998}
2999
3000
3006__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
3007{
3008 return (DCB->DAUTHCTRL);
3009}
3010
3011
3012#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3018__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
3019{
3020 __DSB();
3021 __ISB();
3022 DCB_NS->DAUTHCTRL = value;
3023 __DSB();
3024 __ISB();
3025}
3026
3027
3033__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
3034{
3035 return (DCB_NS->DAUTHCTRL);
3036}
3037#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3038
3044/* ################################## Debug Identification function ############################################ */
3058__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
3059{
3060 return (DIB->DAUTHSTATUS);
3061}
3062
3063
3064#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3070__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
3071{
3072 return (DIB_NS->DAUTHSTATUS);
3073}
3074#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3075
3079#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
3080 (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
3081
3082/* ########################## Cache functions #################################### */
3090/* Cache Size ID Register Macros */
3091#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
3092#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
3093
3094#define __SCB_DCACHE_LINE_SIZE 32U
3095#define __SCB_ICACHE_LINE_SIZE 32U
3101__STATIC_FORCEINLINE void SCB_EnableICache (void)
3102{
3103 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
3104 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
3105
3106 __DSB();
3107 __ISB();
3108 SCB->ICIALLU = 0UL; /* invalidate I-Cache */
3109 __DSB();
3110 __ISB();
3111 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
3112 __DSB();
3113 __ISB();
3114 #endif
3115}
3116
3117
3122__STATIC_FORCEINLINE void SCB_DisableICache (void)
3123{
3124 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
3125 __DSB();
3126 __ISB();
3127 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
3128 SCB->ICIALLU = 0UL; /* invalidate I-Cache */
3129 __DSB();
3130 __ISB();
3131 #endif
3132}
3133
3134
3139__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
3140{
3141 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
3142 __DSB();
3143 __ISB();
3144 SCB->ICIALLU = 0UL;
3145 __DSB();
3146 __ISB();
3147 #endif
3148}
3149
3150
3159__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
3160{
3161 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
3162 if ( isize > 0 ) {
3163 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
3164 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
3165
3166 __DSB();
3167
3168 do {
3169 SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
3170 op_addr += __SCB_ICACHE_LINE_SIZE;
3171 op_size -= __SCB_ICACHE_LINE_SIZE;
3172 } while ( op_size > 0 );
3173
3174 __DSB();
3175 __ISB();
3176 }
3177 #endif
3178}
3179
3180
3185__STATIC_FORCEINLINE void SCB_EnableDCache (void)
3186{
3187 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3188 uint32_t ccsidr;
3189 uint32_t sets;
3190 uint32_t ways;
3191
3192 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
3193
3194 SCB->CSSELR = 0U; /* select Level 1 data cache */
3195 __DSB();
3196
3197 ccsidr = SCB->CCSIDR;
3198
3199 /* invalidate D-Cache */
3200 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
3201 do {
3202 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
3203 do {
3204 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
3205 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
3206 #if defined ( __CC_ARM )
3207 __schedule_barrier();
3208 #endif
3209 } while (ways-- != 0U);
3210 } while(sets-- != 0U);
3211 __DSB();
3212
3213 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
3214
3215 __DSB();
3216 __ISB();
3217 #endif
3218}
3219
3220
3225__STATIC_FORCEINLINE void SCB_DisableDCache (void)
3226{
3227 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3228 uint32_t ccsidr;
3229 uint32_t sets;
3230 uint32_t ways;
3231
3232 SCB->CSSELR = 0U; /* select Level 1 data cache */
3233 __DSB();
3234
3235 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
3236 __DSB();
3237
3238 ccsidr = SCB->CCSIDR;
3239
3240 /* clean & invalidate D-Cache */
3241 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
3242 do {
3243 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
3244 do {
3245 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
3246 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
3247 #if defined ( __CC_ARM )
3248 __schedule_barrier();
3249 #endif
3250 } while (ways-- != 0U);
3251 } while(sets-- != 0U);
3252
3253 __DSB();
3254 __ISB();
3255 #endif
3256}
3257
3258
3263__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
3264{
3265 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3266 uint32_t ccsidr;
3267 uint32_t sets;
3268 uint32_t ways;
3269
3270 SCB->CSSELR = 0U; /* select Level 1 data cache */
3271 __DSB();
3272
3273 ccsidr = SCB->CCSIDR;
3274
3275 /* invalidate D-Cache */
3276 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
3277 do {
3278 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
3279 do {
3280 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
3281 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
3282 #if defined ( __CC_ARM )
3283 __schedule_barrier();
3284 #endif
3285 } while (ways-- != 0U);
3286 } while(sets-- != 0U);
3287
3288 __DSB();
3289 __ISB();
3290 #endif
3291}
3292
3293
3298__STATIC_FORCEINLINE void SCB_CleanDCache (void)
3299{
3300 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3301 uint32_t ccsidr;
3302 uint32_t sets;
3303 uint32_t ways;
3304
3305 SCB->CSSELR = 0U; /* select Level 1 data cache */
3306 __DSB();
3307
3308 ccsidr = SCB->CCSIDR;
3309
3310 /* clean D-Cache */
3311 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
3312 do {
3313 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
3314 do {
3315 SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
3316 ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
3317 #if defined ( __CC_ARM )
3318 __schedule_barrier();
3319 #endif
3320 } while (ways-- != 0U);
3321 } while(sets-- != 0U);
3322
3323 __DSB();
3324 __ISB();
3325 #endif
3326}
3327
3328
3333__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
3334{
3335 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3336 uint32_t ccsidr;
3337 uint32_t sets;
3338 uint32_t ways;
3339
3340 SCB->CSSELR = 0U; /* select Level 1 data cache */
3341 __DSB();
3342
3343 ccsidr = SCB->CCSIDR;
3344
3345 /* clean & invalidate D-Cache */
3346 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
3347 do {
3348 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
3349 do {
3350 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
3351 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
3352 #if defined ( __CC_ARM )
3353 __schedule_barrier();
3354 #endif
3355 } while (ways-- != 0U);
3356 } while(sets-- != 0U);
3357
3358 __DSB();
3359 __ISB();
3360 #endif
3361}
3362
3363
3372__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
3373{
3374 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3375 if ( dsize > 0 ) {
3376 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
3377 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
3378
3379 __DSB();
3380
3381 do {
3382 SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
3383 op_addr += __SCB_DCACHE_LINE_SIZE;
3384 op_size -= __SCB_DCACHE_LINE_SIZE;
3385 } while ( op_size > 0 );
3386
3387 __DSB();
3388 __ISB();
3389 }
3390 #endif
3391}
3392
3393
3402__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
3403{
3404 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3405 if ( dsize > 0 ) {
3406 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
3407 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
3408
3409 __DSB();
3410
3411 do {
3412 SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
3413 op_addr += __SCB_DCACHE_LINE_SIZE;
3414 op_size -= __SCB_DCACHE_LINE_SIZE;
3415 } while ( op_size > 0 );
3416
3417 __DSB();
3418 __ISB();
3419 }
3420 #endif
3421}
3422
3423
3432__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
3433{
3434 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3435 if ( dsize > 0 ) {
3436 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
3437 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
3438
3439 __DSB();
3440
3441 do {
3442 SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
3443 op_addr += __SCB_DCACHE_LINE_SIZE;
3444 op_size -= __SCB_DCACHE_LINE_SIZE;
3445 } while ( op_size > 0 );
3446
3447 __DSB();
3448 __ISB();
3449 }
3450 #endif
3451}
3452
3454#endif
3455
3456
3457/* ################################## SysTick function ############################################ */
3465#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
3466
3478__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
3479{
3480 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
3481 {
3482 return (1UL); /* Reload value impossible */
3483 }
3484
3485 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
3486 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
3487 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
3488 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
3489 SysTick_CTRL_TICKINT_Msk |
3490 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
3491 return (0UL); /* Function successful */
3492}
3493
3494#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3507__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
3508{
3509 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
3510 {
3511 return (1UL); /* Reload value impossible */
3512 }
3513
3514 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
3515 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
3516 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
3517 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
3518 SysTick_CTRL_TICKINT_Msk |
3519 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
3520 return (0UL); /* Function successful */
3521}
3522#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3523
3524#endif
3525
3530/* ##################################### Debug In/Output function ########################################### */
3538extern volatile int32_t ITM_RxBuffer;
3539#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
3550__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
3551{
3552 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
3553 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
3554 {
3555 while (ITM->PORT[0U].u32 == 0UL)
3556 {
3557 __NOP();
3558 }
3559 ITM->PORT[0U].u8 = (uint8_t)ch;
3560 }
3561 return (ch);
3562}
3563
3564
3571__STATIC_INLINE int32_t ITM_ReceiveChar (void)
3572{
3573 int32_t ch = -1; /* no character available */
3574
3575 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
3576 {
3577 ch = ITM_RxBuffer;
3578 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
3579 }
3580
3581 return (ch);
3582}
3583
3584
3591__STATIC_INLINE int32_t ITM_CheckChar (void)
3592{
3593
3594 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
3595 {
3596 return (0); /* no character available */
3597 }
3598 else
3599 {
3600 return (1); /* character available */
3601 }
3602}
3603
3609#ifdef __cplusplus
3610}
3611#endif
3612
3613#endif /* __CORE_STAR_H_DEPENDANT */
3614
3615#endif /* __CMSIS_GENERIC */
cmsis_compiler.h
CMSIS compiler generic header file.
cmsis_version.h
CMSIS Core(M) Version definitions.
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition core_starmc1.h:1065
DCB
#define DCB
Definition core_starmc1.h:2168
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition core_starmc1.h:1069
FPU_MVFR0_Double_precision_Msk
#define FPU_MVFR0_Double_precision_Msk
Definition core_starmc1.h:1854
SCB_DCCISW_SET_Pos
#define SCB_DCCISW_SET_Pos
Definition core_starmc1.h:977
SCB_CCR_DC_Msk
#define SCB_CCR_DC_Msk
Definition core_starmc1.h:699
SCB_DCCSW_SET_Msk
#define SCB_DCCSW_SET_Msk
Definition core_starmc1.h:968
SCB_DCCSW_WAY_Pos
#define SCB_DCCSW_WAY_Pos
Definition core_starmc1.h:964
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition core_starmc1.h:1173
SCB_DCCSW_WAY_Msk
#define SCB_DCCSW_WAY_Msk
Definition core_starmc1.h:965
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition core_starmc1.h:667
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition core_starmc1.h:652
FPU_MVFR0_Single_precision_Msk
#define FPU_MVFR0_Single_precision_Msk
Definition core_starmc1.h:1857
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition core_starmc1.h:1062
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition core_starmc1.h:1059
SCB_DCISW_WAY_Pos
#define SCB_DCISW_WAY_Pos
Definition core_starmc1.h:954
SCB_DCCISW_WAY_Pos
#define SCB_DCCISW_WAY_Pos
Definition core_starmc1.h:974
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition core_starmc1.h:651
SCB
#define SCB
Definition core_starmc1.h:2162
DIB
#define DIB
Definition core_starmc1.h:2169
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition core_starmc1.h:673
SCB_DCISW_SET_Msk
#define SCB_DCISW_SET_Msk
Definition core_starmc1.h:958
ITM
#define ITM
Definition core_starmc1.h:2165
SCB_AIRCR_BFHFNMINS_Msk
#define SCB_AIRCR_BFHFNMINS_Msk
Definition core_starmc1.h:664
FPU
#define FPU
Definition core_starmc1.h:2183
SCB_DCISW_WAY_Msk
#define SCB_DCISW_WAY_Msk
Definition core_starmc1.h:955
NVIC
#define NVIC
Definition core_starmc1.h:2164
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition core_starmc1.h:666
SysTick
#define SysTick
Definition core_starmc1.h:2163
SCB_DCCSW_SET_Pos
#define SCB_DCCSW_SET_Pos
Definition core_starmc1.h:967
SCB_DCISW_SET_Pos
#define SCB_DCISW_SET_Pos
Definition core_starmc1.h:957
SCB_DCCISW_SET_Msk
#define SCB_DCCISW_SET_Msk
Definition core_starmc1.h:978
SCB_DCCISW_WAY_Msk
#define SCB_DCCISW_WAY_Msk
Definition core_starmc1.h:975
SCB_CCR_IC_Msk
#define SCB_CCR_IC_Msk
Definition core_starmc1.h:696
SCB_InvalidateDCache_by_Addr
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr(volatile void *addr, int32_t dsize)
D-Cache Invalidate by address.
Definition cachel1_armv7.h:358
SCB_EnableDCache
__STATIC_FORCEINLINE void SCB_EnableDCache(void)
Enable D-Cache.
Definition cachel1_armv7.h:141
SCB_DisableICache
__STATIC_FORCEINLINE void SCB_DisableICache(void)
Disable I-Cache.
Definition cachel1_armv7.h:78
SCB_CleanInvalidateDCache
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache(void)
Clean & Invalidate D-Cache.
Definition cachel1_armv7.h:319
SCB_InvalidateICache
__STATIC_FORCEINLINE void SCB_InvalidateICache(void)
Invalidate I-Cache.
Definition cachel1_armv7.h:95
SCB_CleanInvalidateDCache_by_Addr
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr(volatile void *addr, int32_t dsize)
D-Cache Clean and Invalidate by address.
Definition cachel1_armv7.h:418
__SCB_DCACHE_LINE_SIZE
#define __SCB_DCACHE_LINE_SIZE
Definition cachel1_armv7.h:46
SCB_EnableICache
__STATIC_FORCEINLINE void SCB_EnableICache(void)
Enable I-Cache.
Definition cachel1_armv7.h:57
SCB_InvalidateDCache
__STATIC_FORCEINLINE void SCB_InvalidateDCache(void)
Invalidate D-Cache.
Definition cachel1_armv7.h:249
SCB_CleanDCache_by_Addr
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr(volatile void *addr, int32_t dsize)
D-Cache Clean by address.
Definition cachel1_armv7.h:388
__SCB_ICACHE_LINE_SIZE
#define __SCB_ICACHE_LINE_SIZE
Definition cachel1_armv7.h:50
SCB_InvalidateICache_by_Addr
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr(volatile void *addr, int32_t isize)
I-Cache Invalidate by address.
Definition cachel1_armv7.h:115
SCB_CleanDCache
__STATIC_FORCEINLINE void SCB_CleanDCache(void)
Clean D-Cache.
Definition cachel1_armv7.h:284
SCB_DisableDCache
__STATIC_FORCEINLINE void SCB_DisableDCache(void)
Disable D-Cache.
Definition cachel1_armv7.h:181
__ISB
#define __ISB()
Instruction Synchronization Barrier.
Definition cmsis_armcc.h:181
__DSB
#define __DSB()
Data Synchronization Barrier.
Definition cmsis_armcc.h:188
__NOP
#define __NOP
No Operation.
Definition cmsis_armcc.h:150
__SW_SystemReset
__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void)
Software Reset.
Definition core_starmc1.h:2672
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition core_armv81mml.h:3634
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition core_armv81mml.h:3607
DIB_GetAuthStatus
__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
Get Debug Authentication Status Register.
Definition core_armv81mml.h:4070
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition core_armv81mml.h:3584
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition core_armv81mml.h:3623
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition core_armv81mml.h:3510
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition core_armv81mml.h:3404
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition core_armv81mml.h:3370
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition core_armv81mml.h:3885
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition core_armv81mml.h:3313
DCB_SetAuthCtrl
__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
Set Debug Authentication Control Register.
Definition core_armv81mml.h:4003
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition core_armv81mml.h:3421
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition core_armv81mml.h:3389
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition core_armv81mml.h:3332
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition core_armv81mml.h:3557
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition core_armv81mml.h:3351
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition core_armv81mml.h:3532
DCB_GetAuthCtrl
__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
Get Debug Authentication Control Register.
Definition core_armv81mml.h:4018
__NVIC_GetPriorityGrouping
#define __NVIC_GetPriorityGrouping()
Get Priority Grouping.
Definition core_armv8mbl.h:1446
ITM_Type::@78::u8
__OM uint8_t u8
Definition core_starmc1.h:1102
ITM_Type::@78::u32
__OM uint32_t u32
Definition core_starmc1.h:1104
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
EMSS_Type::ITCMCR
__IOM uint32_t ITCMCR
Definition core_starmc1.h:586
APSR_Type::@74::N
uint32_t N
Definition core_starmc1.h:361
xPSR_Type::@76::_reserved0
uint32_t _reserved0
Definition core_starmc1.h:412
IPSR_Type::@75::_reserved0
uint32_t _reserved0
Definition core_starmc1.h:394
xPSR_Type::@76::Z
uint32_t Z
Definition core_starmc1.h:420
xPSR_Type::@76::ISR
uint32_t ISR
Definition core_starmc1.h:411
IPSR_Type::@75::ISR
uint32_t ISR
Definition core_starmc1.h:393
xPSR_Type::@76::N
uint32_t N
Definition core_starmc1.h:421
APSR_Type::@74::GE
uint32_t GE
Definition core_starmc1.h:355
xPSR_Type::@76::V
uint32_t V
Definition core_starmc1.h:418
xPSR_Type::@76::IT
uint32_t IT
Definition core_starmc1.h:416
xPSR_Type::@76::C
uint32_t C
Definition core_starmc1.h:419
xPSR_Type::@76::GE
uint32_t GE
Definition core_starmc1.h:413
APSR_Type::@74::Z
uint32_t Z
Definition core_starmc1.h:360
xPSR_Type::@76::Q
uint32_t Q
Definition core_starmc1.h:417
EMSS_Type::CACR
__IOM uint32_t CACR
Definition core_starmc1.h:585
APSR_Type::@74::Q
uint32_t Q
Definition core_starmc1.h:357
APSR_Type::@74::_reserved0
uint32_t _reserved0
Definition core_starmc1.h:354
CONTROL_Type::@77::_reserved1
uint32_t _reserved1
Definition core_starmc1.h:466
CONTROL_Type::@77::nPRIV
uint32_t nPRIV
Definition core_starmc1.h:462
APSR_Type::@74::C
uint32_t C
Definition core_starmc1.h:359
APSR_Type::@74::_reserved1
uint32_t _reserved1
Definition core_starmc1.h:356
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition core_starmc1.h:3539
CONTROL_Type::@77::FPCA
uint32_t FPCA
Definition core_starmc1.h:464
CONTROL_Type::@77::SPSEL
uint32_t SPSEL
Definition core_starmc1.h:463
ITM_Type::@78::u16
__OM uint16_t u16
Definition core_starmc1.h:1103
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition core_armv81mml.h:4207
APSR_Type::@74::V
uint32_t V
Definition core_starmc1.h:358
ITM_SendChar
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
ITM Send Character.
Definition core_armv81mml.h:4186
EMSS_Type::DTCMCR
__IOM uint32_t DTCMCR
Definition core_starmc1.h:587
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition core_armv81mml.h:4227
CONTROL_Type::@77::SFPA
uint32_t SFPA
Definition core_starmc1.h:465
xPSR_Type::@76::_reserved1
uint32_t _reserved1
Definition core_starmc1.h:414
xPSR_Type::@76::T
uint32_t T
Definition core_starmc1.h:415
DCB_Type
Structure type to access the Debug Control Block Registers (DCB).
Definition core_armv81mml.h:2818
DIB_Type
Structure type to access the Debug Identification Block Registers (DIB).
Definition core_armv81mml.h:3009
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition core_armv81mml.h:1203
EMSS_Type
Definition core_starmc1.h:584
FPU_Type
Structure type to access the Floating Point Unit (FPU).
Definition core_armv81mml.h:2506
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition core_armv81mml.h:1102
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition core_armv81mml.h:499
SCB_Type
Structure type to access the System Control Block (SCB).
Definition core_armv81mml.h:535
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition core_armv81mml.h:1025
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition core_armv81mml.h:1050
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition core_armv81mml.h:1389
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition core_armv81mml.h:352
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition core_armv81mml.h:460
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition core_armv81mml.h:391
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition core_armv81mml.h:409
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