YAHAL
Yet Another Hardware Abstraction Library
Loading...
Searching...
No Matches
Macros | Functions
Cache Functions
Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » Implementation Control Block register (ICB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » Implementation Control Block register (ICB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Memory System Control Registers (IMPLEMENTATION DEFINED) » Power Mode Control Registers » External Wakeup Interrupt Controller Registers » External Wakeup Interrupt Controller (EWIC) interrupt status access registers » Error Banking Registers (IMPLEMENTATION DEFINED) » Processor Configuration Information Registers (IMPLEMENTATION DEFINED) » Software Test Library Observation Registers » Trace Port Interface (TPI) » Floating Point Unit (FPU) » Core Debug Registers (CoreDebug) » Debug Control Block » Debug Identification Block » Core register bit field macros » Core Definitions » Backwards Compatibility Aliases » Functions and Instructions Reference

Functions that configure Instruction and Data cache. More...

Macros

#define CCSIDR_WAYS(x)
 
#define CCSIDR_SETS(x)
 
#define __SCB_DCACHE_LINE_SIZE   32U
 
#define __SCB_ICACHE_LINE_SIZE   32U
 
#define CCSIDR_WAYS(x)
 
#define CCSIDR_SETS(x)
 
#define __SCB_DCACHE_LINE_SIZE   32U
 
#define __SCB_ICACHE_LINE_SIZE   32U
 
#define CCSIDR_WAYS(x)
 
#define CCSIDR_SETS(x)
 
#define __SCB_DCACHE_LINE_SIZE   32U
 
#define __SCB_ICACHE_LINE_SIZE   32U
 
#define CCSIDR_WAYS(x)
 
#define CCSIDR_SETS(x)
 
#define __SCB_DCACHE_LINE_SIZE   32U
 
#define __SCB_ICACHE_LINE_SIZE   32U
 

Functions

__STATIC_FORCEINLINE void SCB_EnableICache (void)
 Enable I-Cache.
 
__STATIC_FORCEINLINE void SCB_DisableICache (void)
 Disable I-Cache.
 
__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
 Invalidate I-Cache.
 
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
 I-Cache Invalidate by address.
 
__STATIC_FORCEINLINE void SCB_EnableDCache (void)
 Enable D-Cache.
 
__STATIC_FORCEINLINE void SCB_DisableDCache (void)
 Disable D-Cache.
 
__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
 Invalidate D-Cache.
 
__STATIC_FORCEINLINE void SCB_CleanDCache (void)
 Clean D-Cache.
 
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
 Clean & Invalidate D-Cache.
 
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
 D-Cache Invalidate by address.
 
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
 D-Cache Clean by address.
 
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
 D-Cache Clean and Invalidate by address.
 

Detailed Description

Functions that configure Instruction and Data cache.

Macro Definition Documentation

◆ __SCB_DCACHE_LINE_SIZE [1/4]

#define __SCB_DCACHE_LINE_SIZE   32U

Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR

Definition at line 46 of file cachel1_armv7.h.

◆ __SCB_DCACHE_LINE_SIZE [2/4]

#define __SCB_DCACHE_LINE_SIZE   32U

Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR

Definition at line 46 of file cachel1_armv7.h.

◆ __SCB_DCACHE_LINE_SIZE [3/4]

#define __SCB_DCACHE_LINE_SIZE   32U

Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR

Definition at line 46 of file cachel1_armv7.h.

◆ __SCB_DCACHE_LINE_SIZE [4/4]

#define __SCB_DCACHE_LINE_SIZE   32U

Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR

Definition at line 46 of file cachel1_armv7.h.

◆ __SCB_ICACHE_LINE_SIZE [1/4]

#define __SCB_ICACHE_LINE_SIZE   32U

Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR

Definition at line 50 of file cachel1_armv7.h.

◆ __SCB_ICACHE_LINE_SIZE [2/4]

#define __SCB_ICACHE_LINE_SIZE   32U

Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR

Definition at line 50 of file cachel1_armv7.h.

◆ __SCB_ICACHE_LINE_SIZE [3/4]

#define __SCB_ICACHE_LINE_SIZE   32U

Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR

Definition at line 50 of file cachel1_armv7.h.

◆ __SCB_ICACHE_LINE_SIZE [4/4]

#define __SCB_ICACHE_LINE_SIZE   32U

Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR

Definition at line 50 of file cachel1_armv7.h.

◆ CCSIDR_SETS [1/4]

#define CCSIDR_SETS ( x)
Value:
(((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
SCB_CCSIDR_NUMSETS_Pos
#define SCB_CCSIDR_NUMSETS_Pos
Definition core_armv81mml.h:960
SCB_CCSIDR_NUMSETS_Msk
#define SCB_CCSIDR_NUMSETS_Msk
Definition core_armv81mml.h:961

Definition at line 43 of file cachel1_armv7.h.

◆ CCSIDR_SETS [2/4]

#define CCSIDR_SETS ( x)
Value:
(((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )

Definition at line 43 of file cachel1_armv7.h.

◆ CCSIDR_SETS [3/4]

#define CCSIDR_SETS ( x)
Value:
(((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )

Definition at line 43 of file cachel1_armv7.h.

◆ CCSIDR_SETS [4/4]

#define CCSIDR_SETS ( x)
Value:
(((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )

Definition at line 43 of file cachel1_armv7.h.

◆ CCSIDR_WAYS [1/4]

#define CCSIDR_WAYS ( x)
Value:
(((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
SCB_CCSIDR_ASSOCIATIVITY_Msk
#define SCB_CCSIDR_ASSOCIATIVITY_Msk
Definition core_armv81mml.h:964
SCB_CCSIDR_ASSOCIATIVITY_Pos
#define SCB_CCSIDR_ASSOCIATIVITY_Pos
Definition core_armv81mml.h:963

Definition at line 42 of file cachel1_armv7.h.

◆ CCSIDR_WAYS [2/4]

#define CCSIDR_WAYS ( x)
Value:
(((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)

Definition at line 42 of file cachel1_armv7.h.

◆ CCSIDR_WAYS [3/4]

#define CCSIDR_WAYS ( x)
Value:
(((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)

Definition at line 42 of file cachel1_armv7.h.

◆ CCSIDR_WAYS [4/4]

#define CCSIDR_WAYS ( x)
Value:
(((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)

Definition at line 42 of file cachel1_armv7.h.

Function Documentation

◆ SCB_CleanDCache()

__STATIC_FORCEINLINE void SCB_CleanDCache ( void )

Clean D-Cache.

Cleans D-Cache

Definition at line 284 of file cachel1_armv7.h.

◆ SCB_CleanDCache_by_Addr()

__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr ( volatile void * addr,
int32_t dsize )

D-Cache Clean by address.

Cleans D-Cache for the given address D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. D-Cache memory blocks which are part of given address + given size are cleaned.

Parameters
[in]addraddress
[in]dsizesize of memory block (in number of bytes)

Definition at line 388 of file cachel1_armv7.h.

◆ SCB_CleanInvalidateDCache()

__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache ( void )

Clean & Invalidate D-Cache.

Cleans and Invalidates D-Cache

Definition at line 319 of file cachel1_armv7.h.

◆ SCB_CleanInvalidateDCache_by_Addr()

__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr ( volatile void * addr,
int32_t dsize )

D-Cache Clean and Invalidate by address.

Cleans and invalidates D_Cache for the given address D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.

Parameters
[in]addraddress (aligned to 32-byte boundary)
[in]dsizesize of memory block (in number of bytes)

Definition at line 418 of file cachel1_armv7.h.

◆ SCB_DisableDCache()

__STATIC_FORCEINLINE void SCB_DisableDCache ( void )

Disable D-Cache.

Turns off D-Cache

Definition at line 181 of file cachel1_armv7.h.

◆ SCB_DisableICache()

__STATIC_FORCEINLINE void SCB_DisableICache ( void )

Disable I-Cache.

Turns off I-Cache

Definition at line 78 of file cachel1_armv7.h.

◆ SCB_EnableDCache()

__STATIC_FORCEINLINE void SCB_EnableDCache ( void )

Enable D-Cache.

Turns on D-Cache

Definition at line 141 of file cachel1_armv7.h.

◆ SCB_EnableICache()

__STATIC_FORCEINLINE void SCB_EnableICache ( void )

Enable I-Cache.

Turns on I-Cache

Definition at line 57 of file cachel1_armv7.h.

◆ SCB_InvalidateDCache()

__STATIC_FORCEINLINE void SCB_InvalidateDCache ( void )

Invalidate D-Cache.

Invalidates D-Cache

Definition at line 249 of file cachel1_armv7.h.

◆ SCB_InvalidateDCache_by_Addr()

__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr ( volatile void * addr,
int32_t dsize )

D-Cache Invalidate by address.

Invalidates D-Cache for the given address. D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. D-Cache memory blocks which are part of given address + given size are invalidated.

Parameters
[in]addraddress
[in]dsizesize of memory block (in number of bytes)

Definition at line 358 of file cachel1_armv7.h.

◆ SCB_InvalidateICache()

__STATIC_FORCEINLINE void SCB_InvalidateICache ( void )

Invalidate I-Cache.

Invalidates I-Cache

Definition at line 95 of file cachel1_armv7.h.

◆ SCB_InvalidateICache_by_Addr()

__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr ( volatile void * addr,
int32_t isize )

I-Cache Invalidate by address.

Invalidates I-Cache for the given address. I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. I-Cache memory blocks which are part of given address + given size are invalidated.

Parameters
[in]addraddress
[in]isizesize of memory block (in number of bytes)

Definition at line 115 of file cachel1_armv7.h.

Generated by doxygen 1.12.0