YAHAL
Yet Another Hardware Abstraction Library
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Implementation Control Block register (ICB)
Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB)

Type definitions for the Implementation Control Block Register. More...

Topics

 System Tick Timer (SysTick)
 Type definitions for the System Timer Registers.
 

Classes

struct  ICB_Type
 Structure type to access the Implementation Control Block (ICB). More...
 

Macros

#define MEMSYSCTL_MSCR_CPWRDN_Pos   17U
 
#define MEMSYSCTL_MSCR_CPWRDN_Msk   (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos)
 
#define MEMSYSCTL_MSCR_DCCLEAN_Pos   16U
 
#define MEMSYSCTL_MSCR_DCCLEAN_Msk   (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos)
 
#define MEMSYSCTL_MSCR_ICACTIVE_Pos   13U
 
#define MEMSYSCTL_MSCR_ICACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos)
 
#define MEMSYSCTL_MSCR_DCACTIVE_Pos   12U
 
#define MEMSYSCTL_MSCR_DCACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos)
 
#define MEMSYSCTL_MSCR_EVECCFAULT_Pos   3U
 
#define MEMSYSCTL_MSCR_EVECCFAULT_Msk   (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos)
 
#define MEMSYSCTL_MSCR_FORCEWT_Pos   2U
 
#define MEMSYSCTL_MSCR_FORCEWT_Msk   (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos)
 
#define MEMSYSCTL_MSCR_ECCEN_Pos   1U
 
#define MEMSYSCTL_MSCR_ECCEN_Msk   (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos)
 
#define MEMSYSCTL_PFCR_DIS_NLP_Pos   7U
 
#define MEMSYSCTL_PFCR_DIS_NLP_Msk   (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos)
 
#define MEMSYSCTL_PFCR_ENABLE_Pos   0U
 
#define MEMSYSCTL_PFCR_ENABLE_Msk   (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/)
 
#define MEMSYSCTL_ITCMCR_SZ_Pos   3U
 
#define MEMSYSCTL_ITCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos)
 
#define MEMSYSCTL_ITCMCR_EN_Pos   0U
 
#define MEMSYSCTL_ITCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/)
 
#define MEMSYSCTL_DTCMCR_SZ_Pos   3U
 
#define MEMSYSCTL_DTCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos)
 
#define MEMSYSCTL_DTCMCR_EN_Pos   0U
 
#define MEMSYSCTL_DTCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/)
 
#define MEMSYSCTL_PAHBCR_SZ_Pos   1U
 
#define MEMSYSCTL_PAHBCR_SZ_Msk   (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos)
 
#define MEMSYSCTL_PAHBCR_EN_Pos   0U
 
#define MEMSYSCTL_PAHBCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/)
 
#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos   1U
 
#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos)
 
#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos   0U
 
#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/)
 
#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos   31U
 
#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos)
 
#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos   8U
 
#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos)
 
#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos   0U
 
#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/)
 
#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos   1U
 
#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos)
 
#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos   0U
 
#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/)
 
#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos   31U
 
#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos)
 
#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos   8U
 
#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos)
 
#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos   0U
 
#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/)
 
#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos   8U
 
#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos)
 
#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos   4U
 
#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos)
 
#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos   0U
 
#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/)
 
#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos   0U
 
#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/)
 
#define EWIC_EWIC_CR_EN_Pos   0U
 
#define EWIC_EWIC_CR_EN_Msk   (0x1UL /*<< EWIC_EWIC_CR_EN_Pos*/)
 
#define EWIC_EWIC_ASCR_ASPU_Pos   1U
 
#define EWIC_EWIC_ASCR_ASPU_Msk   (0x1UL << EWIC_EWIC_ASCR_ASPU_Pos)
 
#define EWIC_EWIC_ASCR_ASPD_Pos   0U
 
#define EWIC_EWIC_ASCR_ASPD_Msk   (0x1UL /*<< EWIC_EWIC_ASCR_ASPD_Pos*/)
 
#define EWIC_EWIC_NUMID_NUMEVENT_Pos   0U
 
#define EWIC_EWIC_NUMID_NUMEVENT_Msk   (0xFFFFUL /*<< EWIC_EWIC_NUMID_NUMEVENT_Pos*/)
 
#define EWIC_EWIC_MASKA_EDBGREQ_Pos   2U
 
#define EWIC_EWIC_MASKA_EDBGREQ_Msk   (0x1UL << EWIC_EWIC_MASKA_EDBGREQ_Pos)
 
#define EWIC_EWIC_MASKA_NMI_Pos   1U
 
#define EWIC_EWIC_MASKA_NMI_Msk   (0x1UL << EWIC_EWIC_MASKA_NMI_Pos)
 
#define EWIC_EWIC_MASKA_EVENT_Pos   0U
 
#define EWIC_EWIC_MASKA_EVENT_Msk   (0x1UL /*<< EWIC_EWIC_MASKA_EVENT_Pos*/)
 
#define EWIC_EWIC_MASKn_IRQ_Pos   0U
 
#define EWIC_EWIC_MASKn_IRQ_Msk   (0xFFFFFFFFUL /*<< EWIC_EWIC_MASKn_IRQ_Pos*/)
 
#define EWIC_EWIC_PENDA_EDBGREQ_Pos   2U
 
#define EWIC_EWIC_PENDA_EDBGREQ_Msk   (0x1UL << EWIC_EWIC_PENDA_EDBGREQ_Pos)
 
#define EWIC_EWIC_PENDA_NMI_Pos   1U
 
#define EWIC_EWIC_PENDA_NMI_Msk   (0x1UL << EWIC_EWIC_PENDA_NMI_Pos)
 
#define EWIC_EWIC_PENDA_EVENT_Pos   0U
 
#define EWIC_EWIC_PENDA_EVENT_Msk   (0x1UL /*<< EWIC_EWIC_PENDA_EVENT_Pos*/)
 
#define EWIC_EWIC_PENDn_IRQ_Pos   0U
 
#define EWIC_EWIC_PENDn_IRQ_Msk   (0xFFFFFFFFUL /*<< EWIC_EWIC_PENDn_IRQ_Pos*/)
 
#define EWIC_EWIC_PSR_NZ_Pos   1U
 
#define EWIC_EWIC_PSR_NZ_Msk   (0x7FFFUL << EWIC_EWIC_PSR_NZ_Pos)
 
#define EWIC_EWIC_PSR_NZA_Pos   0U
 
#define EWIC_EWIC_PSR_NZA_Msk   (0x1UL /*<< EWIC_EWIC_PSR_NZA_Pos*/)
 
#define EWIC_ISA_EVENTSPR_EDBGREQ_Pos   2U
 
#define EWIC_ISA_EVENTSPR_EDBGREQ_Msk   (0x1UL << EWIC_ISA_EVENTSPR_EDBGREQ_Pos)
 
#define EWIC_ISA_EVENTSPR_NMI_Pos   1U
 
#define EWIC_ISA_EVENTSPR_NMI_Msk   (0x1UL << EWIC_ISA_EVENTSPR_NMI_Pos)
 
#define EWIC_ISA_EVENTSPR_EVENT_Pos   0U
 
#define EWIC_ISA_EVENTSPR_EVENT_Msk   (0x1UL /*<< EWIC_ISA_EVENTSPR_EVENT_Pos*/)
 
#define EWIC_ISA_EVENTMASKA_EDBGREQ_Pos   2U
 
#define EWIC_ISA_EVENTMASKA_EDBGREQ_Msk   (0x1UL << EWIC_ISA_EVENTMASKA_EDBGREQ_Pos)
 
#define EWIC_ISA_EVENTMASKA_NMI_Pos   1U
 
#define EWIC_ISA_EVENTMASKA_NMI_Msk   (0x1UL << EWIC_ISA_EVENTMASKA_NMI_Pos)
 
#define EWIC_ISA_EVENTMASKA_EVENT_Pos   0U
 
#define EWIC_ISA_EVENTMASKA_EVENT_Msk   (0x1UL /*<< EWIC_ISA_EVENTMASKA_EVENT_Pos*/)
 
#define EWIC_ISA_EVENTMASKn_IRQ_Pos   0U
 
#define EWIC_ISA_EVENTMASKn_IRQ_Msk   (0xFFFFFFFFUL /*<< EWIC_ISA_EVENTMASKn_IRQ_Pos*/)
 
#define ERRBNK_IEBR0_SWDEF_Pos   30U
 
#define ERRBNK_IEBR0_SWDEF_Msk   (0x3UL << ERRBNK_IEBR0_SWDEF_Pos)
 
#define ERRBNK_IEBR0_BANK_Pos   16U
 
#define ERRBNK_IEBR0_BANK_Msk   (0x1UL << ERRBNK_IEBR0_BANK_Pos)
 
#define ERRBNK_IEBR0_LOCATION_Pos   2U
 
#define ERRBNK_IEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos)
 
#define ERRBNK_IEBR0_LOCKED_Pos   1U
 
#define ERRBNK_IEBR0_LOCKED_Msk   (0x1UL << ERRBNK_IEBR0_LOCKED_Pos)
 
#define ERRBNK_IEBR0_VALID_Pos   0U
 
#define ERRBNK_IEBR0_VALID_Msk   (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/)
 
#define ERRBNK_IEBR1_SWDEF_Pos   30U
 
#define ERRBNK_IEBR1_SWDEF_Msk   (0x3UL << ERRBNK_IEBR1_SWDEF_Pos)
 
#define ERRBNK_IEBR1_BANK_Pos   16U
 
#define ERRBNK_IEBR1_BANK_Msk   (0x1UL << ERRBNK_IEBR1_BANK_Pos)
 
#define ERRBNK_IEBR1_LOCATION_Pos   2U
 
#define ERRBNK_IEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos)
 
#define ERRBNK_IEBR1_LOCKED_Pos   1U
 
#define ERRBNK_IEBR1_LOCKED_Msk   (0x1UL << ERRBNK_IEBR1_LOCKED_Pos)
 
#define ERRBNK_IEBR1_VALID_Pos   0U
 
#define ERRBNK_IEBR1_VALID_Msk   (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/)
 
#define ERRBNK_DEBR0_SWDEF_Pos   30U
 
#define ERRBNK_DEBR0_SWDEF_Msk   (0x3UL << ERRBNK_DEBR0_SWDEF_Pos)
 
#define ERRBNK_DEBR0_TYPE_Pos   17U
 
#define ERRBNK_DEBR0_TYPE_Msk   (0x1UL << ERRBNK_DEBR0_TYPE_Pos)
 
#define ERRBNK_DEBR0_BANK_Pos   16U
 
#define ERRBNK_DEBR0_BANK_Msk   (0x1UL << ERRBNK_DEBR0_BANK_Pos)
 
#define ERRBNK_DEBR0_LOCATION_Pos   2U
 
#define ERRBNK_DEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos)
 
#define ERRBNK_DEBR0_LOCKED_Pos   1U
 
#define ERRBNK_DEBR0_LOCKED_Msk   (0x1UL << ERRBNK_DEBR0_LOCKED_Pos)
 
#define ERRBNK_DEBR0_VALID_Pos   0U
 
#define ERRBNK_DEBR0_VALID_Msk   (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/)
 
#define ERRBNK_DEBR1_SWDEF_Pos   30U
 
#define ERRBNK_DEBR1_SWDEF_Msk   (0x3UL << ERRBNK_DEBR1_SWDEF_Pos)
 
#define ERRBNK_DEBR1_TYPE_Pos   17U
 
#define ERRBNK_DEBR1_TYPE_Msk   (0x1UL << ERRBNK_DEBR1_TYPE_Pos)
 
#define ERRBNK_DEBR1_BANK_Pos   16U
 
#define ERRBNK_DEBR1_BANK_Msk   (0x1UL << ERRBNK_DEBR1_BANK_Pos)
 
#define ERRBNK_DEBR1_LOCATION_Pos   2U
 
#define ERRBNK_DEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos)
 
#define ERRBNK_DEBR1_LOCKED_Pos   1U
 
#define ERRBNK_DEBR1_LOCKED_Msk   (0x1UL << ERRBNK_DEBR1_LOCKED_Pos)
 
#define ERRBNK_DEBR1_VALID_Pos   0U
 
#define ERRBNK_DEBR1_VALID_Msk   (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/)
 
#define ERRBNK_TEBR0_SWDEF_Pos   30U
 
#define ERRBNK_TEBR0_SWDEF_Msk   (0x3UL << ERRBNK_TEBR0_SWDEF_Pos)
 
#define ERRBNK_TEBR0_POISON_Pos   28U
 
#define ERRBNK_TEBR0_POISON_Msk   (0x1UL << ERRBNK_TEBR0_POISON_Pos)
 
#define ERRBNK_TEBR0_TYPE_Pos   27U
 
#define ERRBNK_TEBR0_TYPE_Msk   (0x1UL << ERRBNK_TEBR0_TYPE_Pos)
 
#define ERRBNK_TEBR0_BANK_Pos   24U
 
#define ERRBNK_TEBR0_BANK_Msk   (0x7UL << ERRBNK_TEBR0_BANK_Pos)
 
#define ERRBNK_TEBR0_LOCATION_Pos   2U
 
#define ERRBNK_TEBR0_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos)
 
#define ERRBNK_TEBR0_LOCKED_Pos   1U
 
#define ERRBNK_TEBR0_LOCKED_Msk   (0x1UL << ERRBNK_TEBR0_LOCKED_Pos)
 
#define ERRBNK_TEBR0_VALID_Pos   0U
 
#define ERRBNK_TEBR0_VALID_Msk   (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/)
 
#define ERRBNK_TEBR1_SWDEF_Pos   30U
 
#define ERRBNK_TEBR1_SWDEF_Msk   (0x3UL << ERRBNK_TEBR1_SWDEF_Pos)
 
#define ERRBNK_TEBR1_POISON_Pos   28U
 
#define ERRBNK_TEBR1_POISON_Msk   (0x1UL << ERRBNK_TEBR1_POISON_Pos)
 
#define ERRBNK_TEBR1_TYPE_Pos   27U
 
#define ERRBNK_TEBR1_TYPE_Msk   (0x1UL << ERRBNK_TEBR1_TYPE_Pos)
 
#define ERRBNK_TEBR1_BANK_Pos   24U
 
#define ERRBNK_TEBR1_BANK_Msk   (0x7UL << ERRBNK_TEBR1_BANK_Pos)
 
#define ERRBNK_TEBR1_LOCATION_Pos   2U
 
#define ERRBNK_TEBR1_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos)
 
#define ERRBNK_TEBR1_LOCKED_Pos   1U
 
#define ERRBNK_TEBR1_LOCKED_Msk   (0x1UL << ERRBNK_TEBR1_LOCKED_Pos)
 
#define ERRBNK_TEBR1_VALID_Pos   0U
 
#define ERRBNK_TEBR1_VALID_Msk   (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/)
 
#define ICB_ACTLR_DISCRITAXIRUW_Pos   27U
 
#define ICB_ACTLR_DISCRITAXIRUW_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos)
 
#define ICB_ACTLR_DISCRITAXIRUR_Pos   15U
 
#define ICB_ACTLR_DISCRITAXIRUR_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos)
 
#define ICB_ACTLR_EVENTBUSEN_Pos   14U
 
#define ICB_ACTLR_EVENTBUSEN_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_Pos)
 
#define ICB_ACTLR_EVENTBUSEN_S_Pos   13U
 
#define ICB_ACTLR_EVENTBUSEN_S_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos)
 
#define ICB_ACTLR_DISITMATBFLUSH_Pos   12U
 
#define ICB_ACTLR_DISITMATBFLUSH_Msk   (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos)
 
#define ICB_ACTLR_DISNWAMODE_Pos   11U
 
#define ICB_ACTLR_DISNWAMODE_Msk   (1UL << ICB_ACTLR_DISNWAMODE_Pos)
 
#define ICB_ACTLR_FPEXCODIS_Pos   10U
 
#define ICB_ACTLR_FPEXCODIS_Msk   (1UL << ICB_ACTLR_FPEXCODIS_Pos)
 
#define ICB_ICTR_INTLINESNUM_Pos   0U
 
#define ICB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/)
 
#define ICB_ACTLR_DISCRITAXIRUW_Pos   27U
 
#define ICB_ACTLR_DISCRITAXIRUW_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos)
 
#define ICB_ACTLR_DISCRITAXIRUR_Pos   15U
 
#define ICB_ACTLR_DISCRITAXIRUR_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos)
 
#define ICB_ACTLR_EVENTBUSEN_Pos   14U
 
#define ICB_ACTLR_EVENTBUSEN_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_Pos)
 
#define ICB_ACTLR_EVENTBUSEN_S_Pos   13U
 
#define ICB_ACTLR_EVENTBUSEN_S_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos)
 
#define ICB_ACTLR_DISITMATBFLUSH_Pos   12U
 
#define ICB_ACTLR_DISITMATBFLUSH_Msk   (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos)
 
#define ICB_ACTLR_DISNWAMODE_Pos   11U
 
#define ICB_ACTLR_DISNWAMODE_Msk   (1UL << ICB_ACTLR_DISNWAMODE_Pos)
 
#define ICB_ACTLR_FPEXCODIS_Pos   10U
 
#define ICB_ACTLR_FPEXCODIS_Msk   (1UL << ICB_ACTLR_FPEXCODIS_Pos)
 
#define ICB_ICTR_INTLINESNUM_Pos   0U
 
#define ICB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/)
 
#define ITM_ITREAD_AFVALID_Pos   1U
 
#define ITM_ITREAD_AFVALID_Msk   (0x1UL << ITM_ITREAD_AFVALID_Pos)
 
#define ITM_ITREAD_ATREADY_Pos   0U
 
#define ITM_ITREAD_ATREADY_Msk   (0x1UL /*<< ITM_ITREAD_ATREADY_Pos*/)
 
#define ITM_ITWRITE_AFVALID_Pos   1U
 
#define ITM_ITWRITE_AFVALID_Msk   (0x1UL << ITM_ITWRITE_AFVALID_Pos)
 
#define ITM_ITWRITE_ATREADY_Pos   0U
 
#define ITM_ITWRITE_ATREADY_Msk   (0x1UL /*<< ITM_ITWRITE_ATREADY_Pos*/)
 
#define ITM_ITCTRL_IME_Pos   0U
 
#define ITM_ITCTRL_IME_Msk   (0x1UL /*<< ITM_ITCTRL_IME_Pos*/)
 
#define MEMSYSCTL_MSCR_CPWRDN_Pos   17U
 
#define MEMSYSCTL_MSCR_CPWRDN_Msk   (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos)
 
#define MEMSYSCTL_MSCR_DCCLEAN_Pos   16U
 
#define MEMSYSCTL_MSCR_DCCLEAN_Msk   (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos)
 
#define MEMSYSCTL_MSCR_ICACTIVE_Pos   13U
 
#define MEMSYSCTL_MSCR_ICACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos)
 
#define MEMSYSCTL_MSCR_DCACTIVE_Pos   12U
 
#define MEMSYSCTL_MSCR_DCACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos)
 
#define MEMSYSCTL_MSCR_EVECCFAULT_Pos   3U
 
#define MEMSYSCTL_MSCR_EVECCFAULT_Msk   (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos)
 
#define MEMSYSCTL_MSCR_FORCEWT_Pos   2U
 
#define MEMSYSCTL_MSCR_FORCEWT_Msk   (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos)
 
#define MEMSYSCTL_MSCR_ECCEN_Pos   1U
 
#define MEMSYSCTL_MSCR_ECCEN_Msk   (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos)
 
#define MEMSYSCTL_PFCR_ENABLE_Pos   0U
 
#define MEMSYSCTL_PFCR_ENABLE_Msk   (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/)
 
#define MEMSYSCTL_ITCMCR_SZ_Pos   3U
 
#define MEMSYSCTL_ITCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos)
 
#define MEMSYSCTL_ITCMCR_EN_Pos   0U
 
#define MEMSYSCTL_ITCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/)
 
#define MEMSYSCTL_DTCMCR_SZ_Pos   3U
 
#define MEMSYSCTL_DTCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos)
 
#define MEMSYSCTL_DTCMCR_EN_Pos   0U
 
#define MEMSYSCTL_DTCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/)
 
#define MEMSYSCTL_PAHBCR_SZ_Pos   1U
 
#define MEMSYSCTL_PAHBCR_SZ_Msk   (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos)
 
#define MEMSYSCTL_PAHBCR_EN_Pos   0U
 
#define MEMSYSCTL_PAHBCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/)
 
#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos   1U
 
#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos)
 
#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos   0U
 
#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/)
 
#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos   31U
 
#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos)
 
#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos   8U
 
#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos)
 
#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos   0U
 
#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/)
 
#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos   1U
 
#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos)
 
#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos   0U
 
#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/)
 
#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos   31U
 
#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos)
 
#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos   8U
 
#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos)
 
#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos   0U
 
#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/)
 
#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos   8U
 
#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos)
 
#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos   4U
 
#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos)
 
#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos   0U
 
#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/)
 
#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos   0U
 
#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/)
 
#define EWIC_EWIC_CR_EN_Pos   0U
 
#define EWIC_EWIC_CR_EN_Msk   (0x1UL /*<< EWIC_EWIC_CR_EN_Pos*/)
 
#define EWIC_EWIC_ASCR_ASPU_Pos   1U
 
#define EWIC_EWIC_ASCR_ASPU_Msk   (0x1UL << EWIC_EWIC_ASCR_ASPU_Pos)
 
#define EWIC_EWIC_ASCR_ASPD_Pos   0U
 
#define EWIC_EWIC_ASCR_ASPD_Msk   (0x1UL /*<< EWIC_EWIC_ASCR_ASPD_Pos*/)
 
#define EWIC_EWIC_NUMID_NUMEVENT_Pos   0U
 
#define EWIC_EWIC_NUMID_NUMEVENT_Msk   (0xFFFFUL /*<< EWIC_EWIC_NUMID_NUMEVENT_Pos*/)
 
#define EWIC_EWIC_MASKA_EDBGREQ_Pos   2U
 
#define EWIC_EWIC_MASKA_EDBGREQ_Msk   (0x1UL << EWIC_EWIC_MASKA_EDBGREQ_Pos)
 
#define EWIC_EWIC_MASKA_NMI_Pos   1U
 
#define EWIC_EWIC_MASKA_NMI_Msk   (0x1UL << EWIC_EWIC_MASKA_NMI_Pos)
 
#define EWIC_EWIC_MASKA_EVENT_Pos   0U
 
#define EWIC_EWIC_MASKA_EVENT_Msk   (0x1UL /*<< EWIC_EWIC_MASKA_EVENT_Pos*/)
 
#define EWIC_EWIC_MASKn_IRQ_Pos   0U
 
#define EWIC_EWIC_MASKn_IRQ_Msk   (0xFFFFFFFFUL /*<< EWIC_EWIC_MASKn_IRQ_Pos*/)
 
#define EWIC_EWIC_PENDA_EDBGREQ_Pos   2U
 
#define EWIC_EWIC_PENDA_EDBGREQ_Msk   (0x1UL << EWIC_EWIC_PENDA_EDBGREQ_Pos)
 
#define EWIC_EWIC_PENDA_NMI_Pos   1U
 
#define EWIC_EWIC_PENDA_NMI_Msk   (0x1UL << EWIC_EWIC_PENDA_NMI_Pos)
 
#define EWIC_EWIC_PENDA_EVENT_Pos   0U
 
#define EWIC_EWIC_PENDA_EVENT_Msk   (0x1UL /*<< EWIC_EWIC_PENDA_EVENT_Pos*/)
 
#define EWIC_EWIC_PENDn_IRQ_Pos   0U
 
#define EWIC_EWIC_PENDn_IRQ_Msk   (0xFFFFFFFFUL /*<< EWIC_EWIC_PENDn_IRQ_Pos*/)
 
#define EWIC_EWIC_PSR_NZ_Pos   1U
 
#define EWIC_EWIC_PSR_NZ_Msk   (0x7FFFUL << EWIC_EWIC_PSR_NZ_Pos)
 
#define EWIC_EWIC_PSR_NZA_Pos   0U
 
#define EWIC_EWIC_PSR_NZA_Msk   (0x1UL /*<< EWIC_EWIC_PSR_NZA_Pos*/)
 
#define EWIC_ISA_EVENTSPR_EDBGREQ_Pos   2U
 
#define EWIC_ISA_EVENTSPR_EDBGREQ_Msk   (0x1UL << EWIC_ISA_EVENTSPR_EDBGREQ_Pos)
 
#define EWIC_ISA_EVENTSPR_NMI_Pos   1U
 
#define EWIC_ISA_EVENTSPR_NMI_Msk   (0x1UL << EWIC_ISA_EVENTSPR_NMI_Pos)
 
#define EWIC_ISA_EVENTSPR_EVENT_Pos   0U
 
#define EWIC_ISA_EVENTSPR_EVENT_Msk   (0x1UL /*<< EWIC_ISA_EVENTSPR_EVENT_Pos*/)
 
#define EWIC_ISA_EVENTMASKA_EDBGREQ_Pos   2U
 
#define EWIC_ISA_EVENTMASKA_EDBGREQ_Msk   (0x1UL << EWIC_ISA_EVENTMASKA_EDBGREQ_Pos)
 
#define EWIC_ISA_EVENTMASKA_NMI_Pos   1U
 
#define EWIC_ISA_EVENTMASKA_NMI_Msk   (0x1UL << EWIC_ISA_EVENTMASKA_NMI_Pos)
 
#define EWIC_ISA_EVENTMASKA_EVENT_Pos   0U
 
#define EWIC_ISA_EVENTMASKA_EVENT_Msk   (0x1UL /*<< EWIC_ISA_EVENTMASKA_EVENT_Pos*/)
 
#define EWIC_ISA_EVENTMASKn_IRQ_Pos   0U
 
#define EWIC_ISA_EVENTMASKn_IRQ_Msk   (0xFFFFFFFFUL /*<< EWIC_ISA_EVENTMASKn_IRQ_Pos*/)
 
#define ERRBNK_IEBR0_SWDEF_Pos   30U
 
#define ERRBNK_IEBR0_SWDEF_Msk   (0x3UL << ERRBNK_IEBR0_SWDEF_Pos)
 
#define ERRBNK_IEBR0_BANK_Pos   16U
 
#define ERRBNK_IEBR0_BANK_Msk   (0x1UL << ERRBNK_IEBR0_BANK_Pos)
 
#define ERRBNK_IEBR0_LOCATION_Pos   2U
 
#define ERRBNK_IEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos)
 
#define ERRBNK_IEBR0_LOCKED_Pos   1U
 
#define ERRBNK_IEBR0_LOCKED_Msk   (0x1UL << ERRBNK_IEBR0_LOCKED_Pos)
 
#define ERRBNK_IEBR0_VALID_Pos   0U
 
#define ERRBNK_IEBR0_VALID_Msk   (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/)
 
#define ERRBNK_IEBR1_SWDEF_Pos   30U
 
#define ERRBNK_IEBR1_SWDEF_Msk   (0x3UL << ERRBNK_IEBR1_SWDEF_Pos)
 
#define ERRBNK_IEBR1_BANK_Pos   16U
 
#define ERRBNK_IEBR1_BANK_Msk   (0x1UL << ERRBNK_IEBR1_BANK_Pos)
 
#define ERRBNK_IEBR1_LOCATION_Pos   2U
 
#define ERRBNK_IEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos)
 
#define ERRBNK_IEBR1_LOCKED_Pos   1U
 
#define ERRBNK_IEBR1_LOCKED_Msk   (0x1UL << ERRBNK_IEBR1_LOCKED_Pos)
 
#define ERRBNK_IEBR1_VALID_Pos   0U
 
#define ERRBNK_IEBR1_VALID_Msk   (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/)
 
#define ERRBNK_DEBR0_SWDEF_Pos   30U
 
#define ERRBNK_DEBR0_SWDEF_Msk   (0x3UL << ERRBNK_DEBR0_SWDEF_Pos)
 
#define ERRBNK_DEBR0_TYPE_Pos   17U
 
#define ERRBNK_DEBR0_TYPE_Msk   (0x1UL << ERRBNK_DEBR0_TYPE_Pos)
 
#define ERRBNK_DEBR0_BANK_Pos   16U
 
#define ERRBNK_DEBR0_BANK_Msk   (0x1UL << ERRBNK_DEBR0_BANK_Pos)
 
#define ERRBNK_DEBR0_LOCATION_Pos   2U
 
#define ERRBNK_DEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos)
 
#define ERRBNK_DEBR0_LOCKED_Pos   1U
 
#define ERRBNK_DEBR0_LOCKED_Msk   (0x1UL << ERRBNK_DEBR0_LOCKED_Pos)
 
#define ERRBNK_DEBR0_VALID_Pos   0U
 
#define ERRBNK_DEBR0_VALID_Msk   (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/)
 
#define ERRBNK_DEBR1_SWDEF_Pos   30U
 
#define ERRBNK_DEBR1_SWDEF_Msk   (0x3UL << ERRBNK_DEBR1_SWDEF_Pos)
 
#define ERRBNK_DEBR1_TYPE_Pos   17U
 
#define ERRBNK_DEBR1_TYPE_Msk   (0x1UL << ERRBNK_DEBR1_TYPE_Pos)
 
#define ERRBNK_DEBR1_BANK_Pos   16U
 
#define ERRBNK_DEBR1_BANK_Msk   (0x1UL << ERRBNK_DEBR1_BANK_Pos)
 
#define ERRBNK_DEBR1_LOCATION_Pos   2U
 
#define ERRBNK_DEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos)
 
#define ERRBNK_DEBR1_LOCKED_Pos   1U
 
#define ERRBNK_DEBR1_LOCKED_Msk   (0x1UL << ERRBNK_DEBR1_LOCKED_Pos)
 
#define ERRBNK_DEBR1_VALID_Pos   0U
 
#define ERRBNK_DEBR1_VALID_Msk   (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/)
 
#define ERRBNK_TEBR0_SWDEF_Pos   30U
 
#define ERRBNK_TEBR0_SWDEF_Msk   (0x3UL << ERRBNK_TEBR0_SWDEF_Pos)
 
#define ERRBNK_TEBR0_POISON_Pos   28U
 
#define ERRBNK_TEBR0_POISON_Msk   (0x1UL << ERRBNK_TEBR0_POISON_Pos)
 
#define ERRBNK_TEBR0_TYPE_Pos   27U
 
#define ERRBNK_TEBR0_TYPE_Msk   (0x1UL << ERRBNK_TEBR0_TYPE_Pos)
 
#define ERRBNK_TEBR0_BANK_Pos   24U
 
#define ERRBNK_TEBR0_BANK_Msk   (0x7UL << ERRBNK_TEBR0_BANK_Pos)
 
#define ERRBNK_TEBR0_LOCATION_Pos   2U
 
#define ERRBNK_TEBR0_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos)
 
#define ERRBNK_TEBR0_LOCKED_Pos   1U
 
#define ERRBNK_TEBR0_LOCKED_Msk   (0x1UL << ERRBNK_TEBR0_LOCKED_Pos)
 
#define ERRBNK_TEBR0_VALID_Pos   0U
 
#define ERRBNK_TEBR0_VALID_Msk   (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/)
 
#define ERRBNK_TEBR1_SWDEF_Pos   30U
 
#define ERRBNK_TEBR1_SWDEF_Msk   (0x3UL << ERRBNK_TEBR1_SWDEF_Pos)
 
#define ERRBNK_TEBR1_POISON_Pos   28U
 
#define ERRBNK_TEBR1_POISON_Msk   (0x1UL << ERRBNK_TEBR1_POISON_Pos)
 
#define ERRBNK_TEBR1_TYPE_Pos   27U
 
#define ERRBNK_TEBR1_TYPE_Msk   (0x1UL << ERRBNK_TEBR1_TYPE_Pos)
 
#define ERRBNK_TEBR1_BANK_Pos   24U
 
#define ERRBNK_TEBR1_BANK_Msk   (0x7UL << ERRBNK_TEBR1_BANK_Pos)
 
#define ERRBNK_TEBR1_LOCATION_Pos   2U
 
#define ERRBNK_TEBR1_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos)
 
#define ERRBNK_TEBR1_LOCKED_Pos   1U
 
#define ERRBNK_TEBR1_LOCKED_Msk   (0x1UL << ERRBNK_TEBR1_LOCKED_Pos)
 
#define ERRBNK_TEBR1_VALID_Pos   0U
 
#define ERRBNK_TEBR1_VALID_Msk   (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/)
 
#define MEMSYSCTL_BASE   (0xE001E000UL)
 
#define ERRBNK_BASE   (0xE001E100UL)
 
#define PWRMODCTL_BASE   (0xE001E300UL)
 
#define EWIC_ISA_BASE   (0xE001E400UL)
 
#define PRCCFGINF_BASE   (0xE001E700UL)
 
#define EWIC_BASE   (0xE0047000UL)
 
#define ICB   ((ICB_Type *) SCS_BASE )
 
#define MEMSYSCTL   ((MemSysCtl_Type *) MEMSYSCTL_BASE )
 
#define ERRBNK   ((ErrBnk_Type *) ERRBNK_BASE )
 
#define PWRMODCTL   ((PwrModCtl_Type *) PWRMODCTL_BASE )
 
#define EWIC_ISA   ((EWIC_ISA_Type *) EWIC_ISA_BASE )
 
#define EWIC   ((EWIC_Type *) EWIC_BASE )
 
#define PRCCFGINF   ((PrcCfgInf_Type *) PRCCFGINF_BASE )
 
#define ITM_ITREAD_AFVALID_Pos   1U
 
#define ITM_ITREAD_AFVALID_Msk   (0x1UL << ITM_ITREAD_AFVALID_Pos)
 
#define ITM_ITREAD_ATREADY_Pos   0U
 
#define ITM_ITREAD_ATREADY_Msk   (0x1UL /*<< ITM_ITREAD_ATREADY_Pos*/)
 
#define ITM_ITWRITE_AFVALID_Pos   1U
 
#define ITM_ITWRITE_AFVALID_Msk   (0x1UL << ITM_ITWRITE_AFVALID_Pos)
 
#define ITM_ITWRITE_ATREADY_Pos   0U
 
#define ITM_ITWRITE_ATREADY_Msk   (0x1UL /*<< ITM_ITWRITE_ATREADY_Pos*/)
 
#define ITM_ITCTRL_IME_Pos   0U
 
#define ITM_ITCTRL_IME_Msk   (0x1UL /*<< ITM_ITCTRL_IME_Pos*/)
 
#define MEMSYSCTL_BASE   (0xE001E000UL)
 
#define ERRBNK_BASE   (0xE001E100UL)
 
#define PWRMODCTL_BASE   (0xE001E300UL)
 
#define EWIC_ISA_BASE   (0xE001E400UL)
 
#define PRCCFGINF_BASE   (0xE001E700UL)
 
#define EWIC_BASE   (0xE0047000UL)
 
#define ICB   ((ICB_Type *) SCS_BASE )
 
#define MEMSYSCTL   ((MemSysCtl_Type *) MEMSYSCTL_BASE )
 
#define ERRBNK   ((ErrBnk_Type *) ERRBNK_BASE )
 
#define PWRMODCTL   ((PwrModCtl_Type *) PWRMODCTL_BASE )
 
#define EWIC_ISA   ((EWIC_ISA_Type *) EWIC_ISA_BASE )
 
#define EWIC   ((EWIC_Type *) EWIC_BASE )
 
#define PRCCFGINF   ((PrcCfgInf_Type *) PRCCFGINF_BASE )
 
#define ICB_ACTLR_DISDI_Pos   16U
 
#define ICB_ACTLR_DISDI_Msk   (3UL << ICB_ACTLR_DISDI_Pos)
 
#define ICB_ACTLR_DISOLAP_Pos   7U
 
#define ICB_ACTLR_DISOLAP_Msk   (1UL << ICB_ACTLR_DISOLAP_Pos)
 
#define ICB_ACTLR_DISOLAPS_Pos   6U
 
#define ICB_ACTLR_DISOLAPS_Msk   (1UL << ICB_ACTLR_DISOLAPS_Pos)
 
#define ICB_ACTLR_DISLOBR_Pos   5U
 
#define ICB_ACTLR_DISLOBR_Msk   (1UL << ICB_ACTLR_DISLOBR_Pos)
 
#define ICB_ACTLR_DISLO_Pos   4U
 
#define ICB_ACTLR_DISLO_Msk   (1UL << ICB_ACTLR_DISLO_Pos)
 
#define ICB_ACTLR_DISLOLEP_Pos   3U
 
#define ICB_ACTLR_DISLOLEP_Msk   (1UL << ICB_ACTLR_DISLOLEP_Pos)
 
#define ICB_ACTLR_DISFOLD_Pos   2U
 
#define ICB_ACTLR_DISFOLD_Msk   (1UL << ICB_ACTLR_DISFOLD_Pos)
 

Detailed Description

Type definitions for the Implementation Control Block Register.

Macro Definition Documentation

◆ ERRBNK [1/2]

#define ERRBNK   ((ErrBnk_Type *) ERRBNK_BASE )

Error Banking configuration struct

Definition at line 3683 of file core_cm55.h.

◆ ERRBNK [2/2]

#define ERRBNK   ((ErrBnk_Type *) ERRBNK_BASE )

Error Banking configuration struct

Definition at line 3587 of file core_cm85.h.

◆ ERRBNK_BASE [1/2]

#define ERRBNK_BASE   (0xE001E100UL)

Error Banking Base Address

Definition at line 3661 of file core_cm55.h.

◆ ERRBNK_BASE [2/2]

#define ERRBNK_BASE   (0xE001E100UL)

Error Banking Base Address

Definition at line 3566 of file core_cm85.h.

◆ ERRBNK_DEBR0_BANK_Msk [1/2]

#define ERRBNK_DEBR0_BANK_Msk   (0x1UL << ERRBNK_DEBR0_BANK_Pos)

ERRBNK DEBR0: BANK Mask

Definition at line 1749 of file core_cm55.h.

◆ ERRBNK_DEBR0_BANK_Msk [2/2]

#define ERRBNK_DEBR0_BANK_Msk   (0x1UL << ERRBNK_DEBR0_BANK_Pos)

ERRBNK DEBR0: BANK Mask

Definition at line 1736 of file core_cm85.h.

◆ ERRBNK_DEBR0_BANK_Pos [1/2]

#define ERRBNK_DEBR0_BANK_Pos   16U

ERRBNK DEBR0: BANK Position

Definition at line 1748 of file core_cm55.h.

◆ ERRBNK_DEBR0_BANK_Pos [2/2]

#define ERRBNK_DEBR0_BANK_Pos   16U

ERRBNK DEBR0: BANK Position

Definition at line 1735 of file core_cm85.h.

◆ ERRBNK_DEBR0_LOCATION_Msk [1/2]

#define ERRBNK_DEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos)

ERRBNK DEBR0: LOCATION Mask

Definition at line 1752 of file core_cm55.h.

◆ ERRBNK_DEBR0_LOCATION_Msk [2/2]

#define ERRBNK_DEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos)

ERRBNK DEBR0: LOCATION Mask

Definition at line 1739 of file core_cm85.h.

◆ ERRBNK_DEBR0_LOCATION_Pos [1/2]

#define ERRBNK_DEBR0_LOCATION_Pos   2U

ERRBNK DEBR0: LOCATION Position

Definition at line 1751 of file core_cm55.h.

◆ ERRBNK_DEBR0_LOCATION_Pos [2/2]

#define ERRBNK_DEBR0_LOCATION_Pos   2U

ERRBNK DEBR0: LOCATION Position

Definition at line 1738 of file core_cm85.h.

◆ ERRBNK_DEBR0_LOCKED_Msk [1/2]

#define ERRBNK_DEBR0_LOCKED_Msk   (0x1UL << ERRBNK_DEBR0_LOCKED_Pos)

ERRBNK DEBR0: LOCKED Mask

Definition at line 1755 of file core_cm55.h.

◆ ERRBNK_DEBR0_LOCKED_Msk [2/2]

#define ERRBNK_DEBR0_LOCKED_Msk   (0x1UL << ERRBNK_DEBR0_LOCKED_Pos)

ERRBNK DEBR0: LOCKED Mask

Definition at line 1742 of file core_cm85.h.

◆ ERRBNK_DEBR0_LOCKED_Pos [1/2]

#define ERRBNK_DEBR0_LOCKED_Pos   1U

ERRBNK DEBR0: LOCKED Position

Definition at line 1754 of file core_cm55.h.

◆ ERRBNK_DEBR0_LOCKED_Pos [2/2]

#define ERRBNK_DEBR0_LOCKED_Pos   1U

ERRBNK DEBR0: LOCKED Position

Definition at line 1741 of file core_cm85.h.

◆ ERRBNK_DEBR0_SWDEF_Msk [1/2]

#define ERRBNK_DEBR0_SWDEF_Msk   (0x3UL << ERRBNK_DEBR0_SWDEF_Pos)

ERRBNK DEBR0: SWDEF Mask

Definition at line 1743 of file core_cm55.h.

◆ ERRBNK_DEBR0_SWDEF_Msk [2/2]

#define ERRBNK_DEBR0_SWDEF_Msk   (0x3UL << ERRBNK_DEBR0_SWDEF_Pos)

ERRBNK DEBR0: SWDEF Mask

Definition at line 1730 of file core_cm85.h.

◆ ERRBNK_DEBR0_SWDEF_Pos [1/2]

#define ERRBNK_DEBR0_SWDEF_Pos   30U

ERRBNK DEBR0: SWDEF Position

Definition at line 1742 of file core_cm55.h.

◆ ERRBNK_DEBR0_SWDEF_Pos [2/2]

#define ERRBNK_DEBR0_SWDEF_Pos   30U

ERRBNK DEBR0: SWDEF Position

Definition at line 1729 of file core_cm85.h.

◆ ERRBNK_DEBR0_TYPE_Msk [1/2]

#define ERRBNK_DEBR0_TYPE_Msk   (0x1UL << ERRBNK_DEBR0_TYPE_Pos)

ERRBNK DEBR0: TYPE Mask

Definition at line 1746 of file core_cm55.h.

◆ ERRBNK_DEBR0_TYPE_Msk [2/2]

#define ERRBNK_DEBR0_TYPE_Msk   (0x1UL << ERRBNK_DEBR0_TYPE_Pos)

ERRBNK DEBR0: TYPE Mask

Definition at line 1733 of file core_cm85.h.

◆ ERRBNK_DEBR0_TYPE_Pos [1/2]

#define ERRBNK_DEBR0_TYPE_Pos   17U

ERRBNK DEBR0: TYPE Position

Definition at line 1745 of file core_cm55.h.

◆ ERRBNK_DEBR0_TYPE_Pos [2/2]

#define ERRBNK_DEBR0_TYPE_Pos   17U

ERRBNK DEBR0: TYPE Position

Definition at line 1732 of file core_cm85.h.

◆ ERRBNK_DEBR0_VALID_Msk [1/2]

#define ERRBNK_DEBR0_VALID_Msk   (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/)

ERRBNK DEBR0: VALID Mask

Definition at line 1758 of file core_cm55.h.

◆ ERRBNK_DEBR0_VALID_Msk [2/2]

#define ERRBNK_DEBR0_VALID_Msk   (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/)

ERRBNK DEBR0: VALID Mask

Definition at line 1745 of file core_cm85.h.

◆ ERRBNK_DEBR0_VALID_Pos [1/2]

#define ERRBNK_DEBR0_VALID_Pos   0U

ERRBNK DEBR0: VALID Position

Definition at line 1757 of file core_cm55.h.

◆ ERRBNK_DEBR0_VALID_Pos [2/2]

#define ERRBNK_DEBR0_VALID_Pos   0U

ERRBNK DEBR0: VALID Position

Definition at line 1744 of file core_cm85.h.

◆ ERRBNK_DEBR1_BANK_Msk [1/2]

#define ERRBNK_DEBR1_BANK_Msk   (0x1UL << ERRBNK_DEBR1_BANK_Pos)

ERRBNK DEBR1: BANK Mask

Definition at line 1768 of file core_cm55.h.

◆ ERRBNK_DEBR1_BANK_Msk [2/2]

#define ERRBNK_DEBR1_BANK_Msk   (0x1UL << ERRBNK_DEBR1_BANK_Pos)

ERRBNK DEBR1: BANK Mask

Definition at line 1755 of file core_cm85.h.

◆ ERRBNK_DEBR1_BANK_Pos [1/2]

#define ERRBNK_DEBR1_BANK_Pos   16U

ERRBNK DEBR1: BANK Position

Definition at line 1767 of file core_cm55.h.

◆ ERRBNK_DEBR1_BANK_Pos [2/2]

#define ERRBNK_DEBR1_BANK_Pos   16U

ERRBNK DEBR1: BANK Position

Definition at line 1754 of file core_cm85.h.

◆ ERRBNK_DEBR1_LOCATION_Msk [1/2]

#define ERRBNK_DEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos)

ERRBNK DEBR1: LOCATION Mask

Definition at line 1771 of file core_cm55.h.

◆ ERRBNK_DEBR1_LOCATION_Msk [2/2]

#define ERRBNK_DEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos)

ERRBNK DEBR1: LOCATION Mask

Definition at line 1758 of file core_cm85.h.

◆ ERRBNK_DEBR1_LOCATION_Pos [1/2]

#define ERRBNK_DEBR1_LOCATION_Pos   2U

ERRBNK DEBR1: LOCATION Position

Definition at line 1770 of file core_cm55.h.

◆ ERRBNK_DEBR1_LOCATION_Pos [2/2]

#define ERRBNK_DEBR1_LOCATION_Pos   2U

ERRBNK DEBR1: LOCATION Position

Definition at line 1757 of file core_cm85.h.

◆ ERRBNK_DEBR1_LOCKED_Msk [1/2]

#define ERRBNK_DEBR1_LOCKED_Msk   (0x1UL << ERRBNK_DEBR1_LOCKED_Pos)

ERRBNK DEBR1: LOCKED Mask

Definition at line 1774 of file core_cm55.h.

◆ ERRBNK_DEBR1_LOCKED_Msk [2/2]

#define ERRBNK_DEBR1_LOCKED_Msk   (0x1UL << ERRBNK_DEBR1_LOCKED_Pos)

ERRBNK DEBR1: LOCKED Mask

Definition at line 1761 of file core_cm85.h.

◆ ERRBNK_DEBR1_LOCKED_Pos [1/2]

#define ERRBNK_DEBR1_LOCKED_Pos   1U

ERRBNK DEBR1: LOCKED Position

Definition at line 1773 of file core_cm55.h.

◆ ERRBNK_DEBR1_LOCKED_Pos [2/2]

#define ERRBNK_DEBR1_LOCKED_Pos   1U

ERRBNK DEBR1: LOCKED Position

Definition at line 1760 of file core_cm85.h.

◆ ERRBNK_DEBR1_SWDEF_Msk [1/2]

#define ERRBNK_DEBR1_SWDEF_Msk   (0x3UL << ERRBNK_DEBR1_SWDEF_Pos)

ERRBNK DEBR1: SWDEF Mask

Definition at line 1762 of file core_cm55.h.

◆ ERRBNK_DEBR1_SWDEF_Msk [2/2]

#define ERRBNK_DEBR1_SWDEF_Msk   (0x3UL << ERRBNK_DEBR1_SWDEF_Pos)

ERRBNK DEBR1: SWDEF Mask

Definition at line 1749 of file core_cm85.h.

◆ ERRBNK_DEBR1_SWDEF_Pos [1/2]

#define ERRBNK_DEBR1_SWDEF_Pos   30U

ERRBNK DEBR1: SWDEF Position

Definition at line 1761 of file core_cm55.h.

◆ ERRBNK_DEBR1_SWDEF_Pos [2/2]

#define ERRBNK_DEBR1_SWDEF_Pos   30U

ERRBNK DEBR1: SWDEF Position

Definition at line 1748 of file core_cm85.h.

◆ ERRBNK_DEBR1_TYPE_Msk [1/2]

#define ERRBNK_DEBR1_TYPE_Msk   (0x1UL << ERRBNK_DEBR1_TYPE_Pos)

ERRBNK DEBR1: TYPE Mask

Definition at line 1765 of file core_cm55.h.

◆ ERRBNK_DEBR1_TYPE_Msk [2/2]

#define ERRBNK_DEBR1_TYPE_Msk   (0x1UL << ERRBNK_DEBR1_TYPE_Pos)

ERRBNK DEBR1: TYPE Mask

Definition at line 1752 of file core_cm85.h.

◆ ERRBNK_DEBR1_TYPE_Pos [1/2]

#define ERRBNK_DEBR1_TYPE_Pos   17U

ERRBNK DEBR1: TYPE Position

Definition at line 1764 of file core_cm55.h.

◆ ERRBNK_DEBR1_TYPE_Pos [2/2]

#define ERRBNK_DEBR1_TYPE_Pos   17U

ERRBNK DEBR1: TYPE Position

Definition at line 1751 of file core_cm85.h.

◆ ERRBNK_DEBR1_VALID_Msk [1/2]

#define ERRBNK_DEBR1_VALID_Msk   (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/)

ERRBNK DEBR1: VALID Mask

Definition at line 1777 of file core_cm55.h.

◆ ERRBNK_DEBR1_VALID_Msk [2/2]

#define ERRBNK_DEBR1_VALID_Msk   (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/)

ERRBNK DEBR1: VALID Mask

Definition at line 1764 of file core_cm85.h.

◆ ERRBNK_DEBR1_VALID_Pos [1/2]

#define ERRBNK_DEBR1_VALID_Pos   0U

ERRBNK DEBR1: VALID Position

Definition at line 1776 of file core_cm55.h.

◆ ERRBNK_DEBR1_VALID_Pos [2/2]

#define ERRBNK_DEBR1_VALID_Pos   0U

ERRBNK DEBR1: VALID Position

Definition at line 1763 of file core_cm85.h.

◆ ERRBNK_IEBR0_BANK_Msk [1/2]

#define ERRBNK_IEBR0_BANK_Msk   (0x1UL << ERRBNK_IEBR0_BANK_Pos)

ERRBNK IEBR0: BANK Mask

Definition at line 1714 of file core_cm55.h.

◆ ERRBNK_IEBR0_BANK_Msk [2/2]

#define ERRBNK_IEBR0_BANK_Msk   (0x1UL << ERRBNK_IEBR0_BANK_Pos)

ERRBNK IEBR0: BANK Mask

Definition at line 1701 of file core_cm85.h.

◆ ERRBNK_IEBR0_BANK_Pos [1/2]

#define ERRBNK_IEBR0_BANK_Pos   16U

ERRBNK IEBR0: BANK Position

Definition at line 1713 of file core_cm55.h.

◆ ERRBNK_IEBR0_BANK_Pos [2/2]

#define ERRBNK_IEBR0_BANK_Pos   16U

ERRBNK IEBR0: BANK Position

Definition at line 1700 of file core_cm85.h.

◆ ERRBNK_IEBR0_LOCATION_Msk [1/2]

#define ERRBNK_IEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos)

ERRBNK IEBR0: LOCATION Mask

Definition at line 1717 of file core_cm55.h.

◆ ERRBNK_IEBR0_LOCATION_Msk [2/2]

#define ERRBNK_IEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos)

ERRBNK IEBR0: LOCATION Mask

Definition at line 1704 of file core_cm85.h.

◆ ERRBNK_IEBR0_LOCATION_Pos [1/2]

#define ERRBNK_IEBR0_LOCATION_Pos   2U

ERRBNK IEBR0: LOCATION Position

Definition at line 1716 of file core_cm55.h.

◆ ERRBNK_IEBR0_LOCATION_Pos [2/2]

#define ERRBNK_IEBR0_LOCATION_Pos   2U

ERRBNK IEBR0: LOCATION Position

Definition at line 1703 of file core_cm85.h.

◆ ERRBNK_IEBR0_LOCKED_Msk [1/2]

#define ERRBNK_IEBR0_LOCKED_Msk   (0x1UL << ERRBNK_IEBR0_LOCKED_Pos)

ERRBNK IEBR0: LOCKED Mask

Definition at line 1720 of file core_cm55.h.

◆ ERRBNK_IEBR0_LOCKED_Msk [2/2]

#define ERRBNK_IEBR0_LOCKED_Msk   (0x1UL << ERRBNK_IEBR0_LOCKED_Pos)

ERRBNK IEBR0: LOCKED Mask

Definition at line 1707 of file core_cm85.h.

◆ ERRBNK_IEBR0_LOCKED_Pos [1/2]

#define ERRBNK_IEBR0_LOCKED_Pos   1U

ERRBNK IEBR0: LOCKED Position

Definition at line 1719 of file core_cm55.h.

◆ ERRBNK_IEBR0_LOCKED_Pos [2/2]

#define ERRBNK_IEBR0_LOCKED_Pos   1U

ERRBNK IEBR0: LOCKED Position

Definition at line 1706 of file core_cm85.h.

◆ ERRBNK_IEBR0_SWDEF_Msk [1/2]

#define ERRBNK_IEBR0_SWDEF_Msk   (0x3UL << ERRBNK_IEBR0_SWDEF_Pos)

ERRBNK IEBR0: SWDEF Mask

Definition at line 1711 of file core_cm55.h.

◆ ERRBNK_IEBR0_SWDEF_Msk [2/2]

#define ERRBNK_IEBR0_SWDEF_Msk   (0x3UL << ERRBNK_IEBR0_SWDEF_Pos)

ERRBNK IEBR0: SWDEF Mask

Definition at line 1698 of file core_cm85.h.

◆ ERRBNK_IEBR0_SWDEF_Pos [1/2]

#define ERRBNK_IEBR0_SWDEF_Pos   30U

ERRBNK IEBR0: SWDEF Position

Definition at line 1710 of file core_cm55.h.

◆ ERRBNK_IEBR0_SWDEF_Pos [2/2]

#define ERRBNK_IEBR0_SWDEF_Pos   30U

ERRBNK IEBR0: SWDEF Position

Definition at line 1697 of file core_cm85.h.

◆ ERRBNK_IEBR0_VALID_Msk [1/2]

#define ERRBNK_IEBR0_VALID_Msk   (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/)

ERRBNK IEBR0: VALID Mask

Definition at line 1723 of file core_cm55.h.

◆ ERRBNK_IEBR0_VALID_Msk [2/2]

#define ERRBNK_IEBR0_VALID_Msk   (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/)

ERRBNK IEBR0: VALID Mask

Definition at line 1710 of file core_cm85.h.

◆ ERRBNK_IEBR0_VALID_Pos [1/2]

#define ERRBNK_IEBR0_VALID_Pos   0U

ERRBNK IEBR0: VALID Position

Definition at line 1722 of file core_cm55.h.

◆ ERRBNK_IEBR0_VALID_Pos [2/2]

#define ERRBNK_IEBR0_VALID_Pos   0U

ERRBNK IEBR0: VALID Position

Definition at line 1709 of file core_cm85.h.

◆ ERRBNK_IEBR1_BANK_Msk [1/2]

#define ERRBNK_IEBR1_BANK_Msk   (0x1UL << ERRBNK_IEBR1_BANK_Pos)

ERRBNK IEBR1: BANK Mask

Definition at line 1730 of file core_cm55.h.

◆ ERRBNK_IEBR1_BANK_Msk [2/2]

#define ERRBNK_IEBR1_BANK_Msk   (0x1UL << ERRBNK_IEBR1_BANK_Pos)

ERRBNK IEBR1: BANK Mask

Definition at line 1717 of file core_cm85.h.

◆ ERRBNK_IEBR1_BANK_Pos [1/2]

#define ERRBNK_IEBR1_BANK_Pos   16U

ERRBNK IEBR1: BANK Position

Definition at line 1729 of file core_cm55.h.

◆ ERRBNK_IEBR1_BANK_Pos [2/2]

#define ERRBNK_IEBR1_BANK_Pos   16U

ERRBNK IEBR1: BANK Position

Definition at line 1716 of file core_cm85.h.

◆ ERRBNK_IEBR1_LOCATION_Msk [1/2]

#define ERRBNK_IEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos)

ERRBNK IEBR1: LOCATION Mask

Definition at line 1733 of file core_cm55.h.

◆ ERRBNK_IEBR1_LOCATION_Msk [2/2]

#define ERRBNK_IEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos)

ERRBNK IEBR1: LOCATION Mask

Definition at line 1720 of file core_cm85.h.

◆ ERRBNK_IEBR1_LOCATION_Pos [1/2]

#define ERRBNK_IEBR1_LOCATION_Pos   2U

ERRBNK IEBR1: LOCATION Position

Definition at line 1732 of file core_cm55.h.

◆ ERRBNK_IEBR1_LOCATION_Pos [2/2]

#define ERRBNK_IEBR1_LOCATION_Pos   2U

ERRBNK IEBR1: LOCATION Position

Definition at line 1719 of file core_cm85.h.

◆ ERRBNK_IEBR1_LOCKED_Msk [1/2]

#define ERRBNK_IEBR1_LOCKED_Msk   (0x1UL << ERRBNK_IEBR1_LOCKED_Pos)

ERRBNK IEBR1: LOCKED Mask

Definition at line 1736 of file core_cm55.h.

◆ ERRBNK_IEBR1_LOCKED_Msk [2/2]

#define ERRBNK_IEBR1_LOCKED_Msk   (0x1UL << ERRBNK_IEBR1_LOCKED_Pos)

ERRBNK IEBR1: LOCKED Mask

Definition at line 1723 of file core_cm85.h.

◆ ERRBNK_IEBR1_LOCKED_Pos [1/2]

#define ERRBNK_IEBR1_LOCKED_Pos   1U

ERRBNK IEBR1: LOCKED Position

Definition at line 1735 of file core_cm55.h.

◆ ERRBNK_IEBR1_LOCKED_Pos [2/2]

#define ERRBNK_IEBR1_LOCKED_Pos   1U

ERRBNK IEBR1: LOCKED Position

Definition at line 1722 of file core_cm85.h.

◆ ERRBNK_IEBR1_SWDEF_Msk [1/2]

#define ERRBNK_IEBR1_SWDEF_Msk   (0x3UL << ERRBNK_IEBR1_SWDEF_Pos)

ERRBNK IEBR1: SWDEF Mask

Definition at line 1727 of file core_cm55.h.

◆ ERRBNK_IEBR1_SWDEF_Msk [2/2]

#define ERRBNK_IEBR1_SWDEF_Msk   (0x3UL << ERRBNK_IEBR1_SWDEF_Pos)

ERRBNK IEBR1: SWDEF Mask

Definition at line 1714 of file core_cm85.h.

◆ ERRBNK_IEBR1_SWDEF_Pos [1/2]

#define ERRBNK_IEBR1_SWDEF_Pos   30U

ERRBNK IEBR1: SWDEF Position

Definition at line 1726 of file core_cm55.h.

◆ ERRBNK_IEBR1_SWDEF_Pos [2/2]

#define ERRBNK_IEBR1_SWDEF_Pos   30U

ERRBNK IEBR1: SWDEF Position

Definition at line 1713 of file core_cm85.h.

◆ ERRBNK_IEBR1_VALID_Msk [1/2]

#define ERRBNK_IEBR1_VALID_Msk   (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/)

ERRBNK IEBR1: VALID Mask

Definition at line 1739 of file core_cm55.h.

◆ ERRBNK_IEBR1_VALID_Msk [2/2]

#define ERRBNK_IEBR1_VALID_Msk   (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/)

ERRBNK IEBR1: VALID Mask

Definition at line 1726 of file core_cm85.h.

◆ ERRBNK_IEBR1_VALID_Pos [1/2]

#define ERRBNK_IEBR1_VALID_Pos   0U

ERRBNK IEBR1: VALID Position

Definition at line 1738 of file core_cm55.h.

◆ ERRBNK_IEBR1_VALID_Pos [2/2]

#define ERRBNK_IEBR1_VALID_Pos   0U

ERRBNK IEBR1: VALID Position

Definition at line 1725 of file core_cm85.h.

◆ ERRBNK_TEBR0_BANK_Msk [1/2]

#define ERRBNK_TEBR0_BANK_Msk   (0x7UL << ERRBNK_TEBR0_BANK_Pos)

ERRBNK TEBR0: BANK Mask

Definition at line 1790 of file core_cm55.h.

◆ ERRBNK_TEBR0_BANK_Msk [2/2]

#define ERRBNK_TEBR0_BANK_Msk   (0x7UL << ERRBNK_TEBR0_BANK_Pos)

ERRBNK TEBR0: BANK Mask

Definition at line 1777 of file core_cm85.h.

◆ ERRBNK_TEBR0_BANK_Pos [1/2]

#define ERRBNK_TEBR0_BANK_Pos   24U

ERRBNK TEBR0: BANK Position

Definition at line 1789 of file core_cm55.h.

◆ ERRBNK_TEBR0_BANK_Pos [2/2]

#define ERRBNK_TEBR0_BANK_Pos   24U

ERRBNK TEBR0: BANK Position

Definition at line 1776 of file core_cm85.h.

◆ ERRBNK_TEBR0_LOCATION_Msk [1/2]

#define ERRBNK_TEBR0_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos)

ERRBNK TEBR0: LOCATION Mask

Definition at line 1793 of file core_cm55.h.

◆ ERRBNK_TEBR0_LOCATION_Msk [2/2]

#define ERRBNK_TEBR0_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos)

ERRBNK TEBR0: LOCATION Mask

Definition at line 1780 of file core_cm85.h.

◆ ERRBNK_TEBR0_LOCATION_Pos [1/2]

#define ERRBNK_TEBR0_LOCATION_Pos   2U

ERRBNK TEBR0: LOCATION Position

Definition at line 1792 of file core_cm55.h.

◆ ERRBNK_TEBR0_LOCATION_Pos [2/2]

#define ERRBNK_TEBR0_LOCATION_Pos   2U

ERRBNK TEBR0: LOCATION Position

Definition at line 1779 of file core_cm85.h.

◆ ERRBNK_TEBR0_LOCKED_Msk [1/2]

#define ERRBNK_TEBR0_LOCKED_Msk   (0x1UL << ERRBNK_TEBR0_LOCKED_Pos)

ERRBNK TEBR0: LOCKED Mask

Definition at line 1796 of file core_cm55.h.

◆ ERRBNK_TEBR0_LOCKED_Msk [2/2]

#define ERRBNK_TEBR0_LOCKED_Msk   (0x1UL << ERRBNK_TEBR0_LOCKED_Pos)

ERRBNK TEBR0: LOCKED Mask

Definition at line 1783 of file core_cm85.h.

◆ ERRBNK_TEBR0_LOCKED_Pos [1/2]

#define ERRBNK_TEBR0_LOCKED_Pos   1U

ERRBNK TEBR0: LOCKED Position

Definition at line 1795 of file core_cm55.h.

◆ ERRBNK_TEBR0_LOCKED_Pos [2/2]

#define ERRBNK_TEBR0_LOCKED_Pos   1U

ERRBNK TEBR0: LOCKED Position

Definition at line 1782 of file core_cm85.h.

◆ ERRBNK_TEBR0_POISON_Msk [1/2]

#define ERRBNK_TEBR0_POISON_Msk   (0x1UL << ERRBNK_TEBR0_POISON_Pos)

ERRBNK TEBR0: POISON Mask

Definition at line 1784 of file core_cm55.h.

◆ ERRBNK_TEBR0_POISON_Msk [2/2]

#define ERRBNK_TEBR0_POISON_Msk   (0x1UL << ERRBNK_TEBR0_POISON_Pos)

ERRBNK TEBR0: POISON Mask

Definition at line 1771 of file core_cm85.h.

◆ ERRBNK_TEBR0_POISON_Pos [1/2]

#define ERRBNK_TEBR0_POISON_Pos   28U

ERRBNK TEBR0: POISON Position

Definition at line 1783 of file core_cm55.h.

◆ ERRBNK_TEBR0_POISON_Pos [2/2]

#define ERRBNK_TEBR0_POISON_Pos   28U

ERRBNK TEBR0: POISON Position

Definition at line 1770 of file core_cm85.h.

◆ ERRBNK_TEBR0_SWDEF_Msk [1/2]

#define ERRBNK_TEBR0_SWDEF_Msk   (0x3UL << ERRBNK_TEBR0_SWDEF_Pos)

ERRBNK TEBR0: SWDEF Mask

Definition at line 1781 of file core_cm55.h.

◆ ERRBNK_TEBR0_SWDEF_Msk [2/2]

#define ERRBNK_TEBR0_SWDEF_Msk   (0x3UL << ERRBNK_TEBR0_SWDEF_Pos)

ERRBNK TEBR0: SWDEF Mask

Definition at line 1768 of file core_cm85.h.

◆ ERRBNK_TEBR0_SWDEF_Pos [1/2]

#define ERRBNK_TEBR0_SWDEF_Pos   30U

ERRBNK TEBR0: SWDEF Position

Definition at line 1780 of file core_cm55.h.

◆ ERRBNK_TEBR0_SWDEF_Pos [2/2]

#define ERRBNK_TEBR0_SWDEF_Pos   30U

ERRBNK TEBR0: SWDEF Position

Definition at line 1767 of file core_cm85.h.

◆ ERRBNK_TEBR0_TYPE_Msk [1/2]

#define ERRBNK_TEBR0_TYPE_Msk   (0x1UL << ERRBNK_TEBR0_TYPE_Pos)

ERRBNK TEBR0: TYPE Mask

Definition at line 1787 of file core_cm55.h.

◆ ERRBNK_TEBR0_TYPE_Msk [2/2]

#define ERRBNK_TEBR0_TYPE_Msk   (0x1UL << ERRBNK_TEBR0_TYPE_Pos)

ERRBNK TEBR0: TYPE Mask

Definition at line 1774 of file core_cm85.h.

◆ ERRBNK_TEBR0_TYPE_Pos [1/2]

#define ERRBNK_TEBR0_TYPE_Pos   27U

ERRBNK TEBR0: TYPE Position

Definition at line 1786 of file core_cm55.h.

◆ ERRBNK_TEBR0_TYPE_Pos [2/2]

#define ERRBNK_TEBR0_TYPE_Pos   27U

ERRBNK TEBR0: TYPE Position

Definition at line 1773 of file core_cm85.h.

◆ ERRBNK_TEBR0_VALID_Msk [1/2]

#define ERRBNK_TEBR0_VALID_Msk   (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/)

ERRBNK TEBR0: VALID Mask

Definition at line 1799 of file core_cm55.h.

◆ ERRBNK_TEBR0_VALID_Msk [2/2]

#define ERRBNK_TEBR0_VALID_Msk   (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/)

ERRBNK TEBR0: VALID Mask

Definition at line 1786 of file core_cm85.h.

◆ ERRBNK_TEBR0_VALID_Pos [1/2]

#define ERRBNK_TEBR0_VALID_Pos   0U

ERRBNK TEBR0: VALID Position

Definition at line 1798 of file core_cm55.h.

◆ ERRBNK_TEBR0_VALID_Pos [2/2]

#define ERRBNK_TEBR0_VALID_Pos   0U

ERRBNK TEBR0: VALID Position

Definition at line 1785 of file core_cm85.h.

◆ ERRBNK_TEBR1_BANK_Msk [1/2]

#define ERRBNK_TEBR1_BANK_Msk   (0x7UL << ERRBNK_TEBR1_BANK_Pos)

ERRBNK TEBR1: BANK Mask

Definition at line 1812 of file core_cm55.h.

◆ ERRBNK_TEBR1_BANK_Msk [2/2]

#define ERRBNK_TEBR1_BANK_Msk   (0x7UL << ERRBNK_TEBR1_BANK_Pos)

ERRBNK TEBR1: BANK Mask

Definition at line 1799 of file core_cm85.h.

◆ ERRBNK_TEBR1_BANK_Pos [1/2]

#define ERRBNK_TEBR1_BANK_Pos   24U

ERRBNK TEBR1: BANK Position

Definition at line 1811 of file core_cm55.h.

◆ ERRBNK_TEBR1_BANK_Pos [2/2]

#define ERRBNK_TEBR1_BANK_Pos   24U

ERRBNK TEBR1: BANK Position

Definition at line 1798 of file core_cm85.h.

◆ ERRBNK_TEBR1_LOCATION_Msk [1/2]

#define ERRBNK_TEBR1_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos)

ERRBNK TEBR1: LOCATION Mask

Definition at line 1815 of file core_cm55.h.

◆ ERRBNK_TEBR1_LOCATION_Msk [2/2]

#define ERRBNK_TEBR1_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos)

ERRBNK TEBR1: LOCATION Mask

Definition at line 1802 of file core_cm85.h.

◆ ERRBNK_TEBR1_LOCATION_Pos [1/2]

#define ERRBNK_TEBR1_LOCATION_Pos   2U

ERRBNK TEBR1: LOCATION Position

Definition at line 1814 of file core_cm55.h.

◆ ERRBNK_TEBR1_LOCATION_Pos [2/2]

#define ERRBNK_TEBR1_LOCATION_Pos   2U

ERRBNK TEBR1: LOCATION Position

Definition at line 1801 of file core_cm85.h.

◆ ERRBNK_TEBR1_LOCKED_Msk [1/2]

#define ERRBNK_TEBR1_LOCKED_Msk   (0x1UL << ERRBNK_TEBR1_LOCKED_Pos)

ERRBNK TEBR1: LOCKED Mask

Definition at line 1818 of file core_cm55.h.

◆ ERRBNK_TEBR1_LOCKED_Msk [2/2]

#define ERRBNK_TEBR1_LOCKED_Msk   (0x1UL << ERRBNK_TEBR1_LOCKED_Pos)

ERRBNK TEBR1: LOCKED Mask

Definition at line 1805 of file core_cm85.h.

◆ ERRBNK_TEBR1_LOCKED_Pos [1/2]

#define ERRBNK_TEBR1_LOCKED_Pos   1U

ERRBNK TEBR1: LOCKED Position

Definition at line 1817 of file core_cm55.h.

◆ ERRBNK_TEBR1_LOCKED_Pos [2/2]

#define ERRBNK_TEBR1_LOCKED_Pos   1U

ERRBNK TEBR1: LOCKED Position

Definition at line 1804 of file core_cm85.h.

◆ ERRBNK_TEBR1_POISON_Msk [1/2]

#define ERRBNK_TEBR1_POISON_Msk   (0x1UL << ERRBNK_TEBR1_POISON_Pos)

ERRBNK TEBR1: POISON Mask

Definition at line 1806 of file core_cm55.h.

◆ ERRBNK_TEBR1_POISON_Msk [2/2]

#define ERRBNK_TEBR1_POISON_Msk   (0x1UL << ERRBNK_TEBR1_POISON_Pos)

ERRBNK TEBR1: POISON Mask

Definition at line 1793 of file core_cm85.h.

◆ ERRBNK_TEBR1_POISON_Pos [1/2]

#define ERRBNK_TEBR1_POISON_Pos   28U

ERRBNK TEBR1: POISON Position

Definition at line 1805 of file core_cm55.h.

◆ ERRBNK_TEBR1_POISON_Pos [2/2]

#define ERRBNK_TEBR1_POISON_Pos   28U

ERRBNK TEBR1: POISON Position

Definition at line 1792 of file core_cm85.h.

◆ ERRBNK_TEBR1_SWDEF_Msk [1/2]

#define ERRBNK_TEBR1_SWDEF_Msk   (0x3UL << ERRBNK_TEBR1_SWDEF_Pos)

ERRBNK TEBR1: SWDEF Mask

Definition at line 1803 of file core_cm55.h.

◆ ERRBNK_TEBR1_SWDEF_Msk [2/2]

#define ERRBNK_TEBR1_SWDEF_Msk   (0x3UL << ERRBNK_TEBR1_SWDEF_Pos)

ERRBNK TEBR1: SWDEF Mask

Definition at line 1790 of file core_cm85.h.

◆ ERRBNK_TEBR1_SWDEF_Pos [1/2]

#define ERRBNK_TEBR1_SWDEF_Pos   30U

ERRBNK TEBR1: SWDEF Position

Definition at line 1802 of file core_cm55.h.

◆ ERRBNK_TEBR1_SWDEF_Pos [2/2]

#define ERRBNK_TEBR1_SWDEF_Pos   30U

ERRBNK TEBR1: SWDEF Position

Definition at line 1789 of file core_cm85.h.

◆ ERRBNK_TEBR1_TYPE_Msk [1/2]

#define ERRBNK_TEBR1_TYPE_Msk   (0x1UL << ERRBNK_TEBR1_TYPE_Pos)

ERRBNK TEBR1: TYPE Mask

Definition at line 1809 of file core_cm55.h.

◆ ERRBNK_TEBR1_TYPE_Msk [2/2]

#define ERRBNK_TEBR1_TYPE_Msk   (0x1UL << ERRBNK_TEBR1_TYPE_Pos)

ERRBNK TEBR1: TYPE Mask

Definition at line 1796 of file core_cm85.h.

◆ ERRBNK_TEBR1_TYPE_Pos [1/2]

#define ERRBNK_TEBR1_TYPE_Pos   27U

ERRBNK TEBR1: TYPE Position

Definition at line 1808 of file core_cm55.h.

◆ ERRBNK_TEBR1_TYPE_Pos [2/2]

#define ERRBNK_TEBR1_TYPE_Pos   27U

ERRBNK TEBR1: TYPE Position

Definition at line 1795 of file core_cm85.h.

◆ ERRBNK_TEBR1_VALID_Msk [1/2]

#define ERRBNK_TEBR1_VALID_Msk   (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/)

ERRBNK TEBR1: VALID Mask

Definition at line 1821 of file core_cm55.h.

◆ ERRBNK_TEBR1_VALID_Msk [2/2]

#define ERRBNK_TEBR1_VALID_Msk   (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/)

ERRBNK TEBR1: VALID Mask

Definition at line 1808 of file core_cm85.h.

◆ ERRBNK_TEBR1_VALID_Pos [1/2]

#define ERRBNK_TEBR1_VALID_Pos   0U

ERRBNK TEBR1: VALID Position

Definition at line 1820 of file core_cm55.h.

◆ ERRBNK_TEBR1_VALID_Pos [2/2]

#define ERRBNK_TEBR1_VALID_Pos   0U

ERRBNK TEBR1: VALID Position

Definition at line 1807 of file core_cm85.h.

◆ EWIC [1/2]

#define EWIC   ((EWIC_Type *) EWIC_BASE )

EWIC configuration struct

Definition at line 3686 of file core_cm55.h.

◆ EWIC [2/2]

#define EWIC   ((EWIC_Type *) EWIC_BASE )

EWIC configuration struct

Definition at line 3590 of file core_cm85.h.

◆ EWIC_BASE [1/2]

#define EWIC_BASE   (0xE0047000UL)

External Wakeup Interrupt Controller Base Address

Definition at line 3667 of file core_cm55.h.

◆ EWIC_BASE [2/2]

#define EWIC_BASE   (0xE0047000UL)

External Wakeup Interrupt Controller Base Address

Definition at line 3571 of file core_cm85.h.

◆ EWIC_EWIC_ASCR_ASPD_Msk [1/2]

#define EWIC_EWIC_ASCR_ASPD_Msk   (0x1UL /*<< EWIC_EWIC_ASCR_ASPD_Pos*/)

EWIC EWIC_ASCR: ASPD Mask

Definition at line 1597 of file core_cm55.h.

◆ EWIC_EWIC_ASCR_ASPD_Msk [2/2]

#define EWIC_EWIC_ASCR_ASPD_Msk   (0x1UL /*<< EWIC_EWIC_ASCR_ASPD_Pos*/)

EWIC EWIC_ASCR: ASPD Mask

Definition at line 1584 of file core_cm85.h.

◆ EWIC_EWIC_ASCR_ASPD_Pos [1/2]

#define EWIC_EWIC_ASCR_ASPD_Pos   0U

EWIC EWIC_ASCR: ASPD Position

Definition at line 1596 of file core_cm55.h.

◆ EWIC_EWIC_ASCR_ASPD_Pos [2/2]

#define EWIC_EWIC_ASCR_ASPD_Pos   0U

EWIC EWIC_ASCR: ASPD Position

Definition at line 1583 of file core_cm85.h.

◆ EWIC_EWIC_ASCR_ASPU_Msk [1/2]

#define EWIC_EWIC_ASCR_ASPU_Msk   (0x1UL << EWIC_EWIC_ASCR_ASPU_Pos)

EWIC EWIC_ASCR: ASPU Mask

Definition at line 1594 of file core_cm55.h.

◆ EWIC_EWIC_ASCR_ASPU_Msk [2/2]

#define EWIC_EWIC_ASCR_ASPU_Msk   (0x1UL << EWIC_EWIC_ASCR_ASPU_Pos)

EWIC EWIC_ASCR: ASPU Mask

Definition at line 1581 of file core_cm85.h.

◆ EWIC_EWIC_ASCR_ASPU_Pos [1/2]

#define EWIC_EWIC_ASCR_ASPU_Pos   1U

EWIC EWIC_ASCR: ASPU Position

Definition at line 1593 of file core_cm55.h.

◆ EWIC_EWIC_ASCR_ASPU_Pos [2/2]

#define EWIC_EWIC_ASCR_ASPU_Pos   1U

EWIC EWIC_ASCR: ASPU Position

Definition at line 1580 of file core_cm85.h.

◆ EWIC_EWIC_CR_EN_Msk [1/2]

#define EWIC_EWIC_CR_EN_Msk   (0x1UL /*<< EWIC_EWIC_CR_EN_Pos*/)

EWIC EWIC_CR: EN Mask

Definition at line 1590 of file core_cm55.h.

◆ EWIC_EWIC_CR_EN_Msk [2/2]

#define EWIC_EWIC_CR_EN_Msk   (0x1UL /*<< EWIC_EWIC_CR_EN_Pos*/)

EWIC EWIC_CR: EN Mask

Definition at line 1577 of file core_cm85.h.

◆ EWIC_EWIC_CR_EN_Pos [1/2]

#define EWIC_EWIC_CR_EN_Pos   0U

EWIC EWIC_CR: EN Position

Definition at line 1589 of file core_cm55.h.

◆ EWIC_EWIC_CR_EN_Pos [2/2]

#define EWIC_EWIC_CR_EN_Pos   0U

EWIC EWIC_CR: EN Position

Definition at line 1576 of file core_cm85.h.

◆ EWIC_EWIC_MASKA_EDBGREQ_Msk [1/2]

#define EWIC_EWIC_MASKA_EDBGREQ_Msk   (0x1UL << EWIC_EWIC_MASKA_EDBGREQ_Pos)

EWIC EWIC_MASKA: EDBGREQ Mask

Definition at line 1605 of file core_cm55.h.

◆ EWIC_EWIC_MASKA_EDBGREQ_Msk [2/2]

#define EWIC_EWIC_MASKA_EDBGREQ_Msk   (0x1UL << EWIC_EWIC_MASKA_EDBGREQ_Pos)

EWIC EWIC_MASKA: EDBGREQ Mask

Definition at line 1592 of file core_cm85.h.

◆ EWIC_EWIC_MASKA_EDBGREQ_Pos [1/2]

#define EWIC_EWIC_MASKA_EDBGREQ_Pos   2U

EWIC EWIC_MASKA: EDBGREQ Position

Definition at line 1604 of file core_cm55.h.

◆ EWIC_EWIC_MASKA_EDBGREQ_Pos [2/2]

#define EWIC_EWIC_MASKA_EDBGREQ_Pos   2U

EWIC EWIC_MASKA: EDBGREQ Position

Definition at line 1591 of file core_cm85.h.

◆ EWIC_EWIC_MASKA_EVENT_Msk [1/2]

#define EWIC_EWIC_MASKA_EVENT_Msk   (0x1UL /*<< EWIC_EWIC_MASKA_EVENT_Pos*/)

EWIC EWIC_MASKA: EVENT Mask

Definition at line 1611 of file core_cm55.h.

◆ EWIC_EWIC_MASKA_EVENT_Msk [2/2]

#define EWIC_EWIC_MASKA_EVENT_Msk   (0x1UL /*<< EWIC_EWIC_MASKA_EVENT_Pos*/)

EWIC EWIC_MASKA: EVENT Mask

Definition at line 1598 of file core_cm85.h.

◆ EWIC_EWIC_MASKA_EVENT_Pos [1/2]

#define EWIC_EWIC_MASKA_EVENT_Pos   0U

EWIC EWIC_MASKA: EVENT Position

Definition at line 1610 of file core_cm55.h.

◆ EWIC_EWIC_MASKA_EVENT_Pos [2/2]

#define EWIC_EWIC_MASKA_EVENT_Pos   0U

EWIC EWIC_MASKA: EVENT Position

Definition at line 1597 of file core_cm85.h.

◆ EWIC_EWIC_MASKA_NMI_Msk [1/2]

#define EWIC_EWIC_MASKA_NMI_Msk   (0x1UL << EWIC_EWIC_MASKA_NMI_Pos)

EWIC EWIC_MASKA: NMI Mask

Definition at line 1608 of file core_cm55.h.

◆ EWIC_EWIC_MASKA_NMI_Msk [2/2]

#define EWIC_EWIC_MASKA_NMI_Msk   (0x1UL << EWIC_EWIC_MASKA_NMI_Pos)

EWIC EWIC_MASKA: NMI Mask

Definition at line 1595 of file core_cm85.h.

◆ EWIC_EWIC_MASKA_NMI_Pos [1/2]

#define EWIC_EWIC_MASKA_NMI_Pos   1U

EWIC EWIC_MASKA: NMI Position

Definition at line 1607 of file core_cm55.h.

◆ EWIC_EWIC_MASKA_NMI_Pos [2/2]

#define EWIC_EWIC_MASKA_NMI_Pos   1U

EWIC EWIC_MASKA: NMI Position

Definition at line 1594 of file core_cm85.h.

◆ EWIC_EWIC_MASKn_IRQ_Msk [1/2]

#define EWIC_EWIC_MASKn_IRQ_Msk   (0xFFFFFFFFUL /*<< EWIC_EWIC_MASKn_IRQ_Pos*/)

EWIC EWIC_MASKn: IRQ Mask

Definition at line 1615 of file core_cm55.h.

◆ EWIC_EWIC_MASKn_IRQ_Msk [2/2]

#define EWIC_EWIC_MASKn_IRQ_Msk   (0xFFFFFFFFUL /*<< EWIC_EWIC_MASKn_IRQ_Pos*/)

EWIC EWIC_MASKn: IRQ Mask

Definition at line 1602 of file core_cm85.h.

◆ EWIC_EWIC_MASKn_IRQ_Pos [1/2]

#define EWIC_EWIC_MASKn_IRQ_Pos   0U

EWIC EWIC_MASKn: IRQ Position

Definition at line 1614 of file core_cm55.h.

◆ EWIC_EWIC_MASKn_IRQ_Pos [2/2]

#define EWIC_EWIC_MASKn_IRQ_Pos   0U

EWIC EWIC_MASKn: IRQ Position

Definition at line 1601 of file core_cm85.h.

◆ EWIC_EWIC_NUMID_NUMEVENT_Msk [1/2]

#define EWIC_EWIC_NUMID_NUMEVENT_Msk   (0xFFFFUL /*<< EWIC_EWIC_NUMID_NUMEVENT_Pos*/)

EWIC_NUMID: NUMEVENT Mask

Definition at line 1601 of file core_cm55.h.

◆ EWIC_EWIC_NUMID_NUMEVENT_Msk [2/2]

#define EWIC_EWIC_NUMID_NUMEVENT_Msk   (0xFFFFUL /*<< EWIC_EWIC_NUMID_NUMEVENT_Pos*/)

EWIC_NUMID: NUMEVENT Mask

Definition at line 1588 of file core_cm85.h.

◆ EWIC_EWIC_NUMID_NUMEVENT_Pos [1/2]

#define EWIC_EWIC_NUMID_NUMEVENT_Pos   0U

EWIC_NUMID: NUMEVENT Position

Definition at line 1600 of file core_cm55.h.

◆ EWIC_EWIC_NUMID_NUMEVENT_Pos [2/2]

#define EWIC_EWIC_NUMID_NUMEVENT_Pos   0U

EWIC_NUMID: NUMEVENT Position

Definition at line 1587 of file core_cm85.h.

◆ EWIC_EWIC_PENDA_EDBGREQ_Msk [1/2]

#define EWIC_EWIC_PENDA_EDBGREQ_Msk   (0x1UL << EWIC_EWIC_PENDA_EDBGREQ_Pos)

EWIC EWIC_PENDA: EDBGREQ Mask

Definition at line 1619 of file core_cm55.h.

◆ EWIC_EWIC_PENDA_EDBGREQ_Msk [2/2]

#define EWIC_EWIC_PENDA_EDBGREQ_Msk   (0x1UL << EWIC_EWIC_PENDA_EDBGREQ_Pos)

EWIC EWIC_PENDA: EDBGREQ Mask

Definition at line 1606 of file core_cm85.h.

◆ EWIC_EWIC_PENDA_EDBGREQ_Pos [1/2]

#define EWIC_EWIC_PENDA_EDBGREQ_Pos   2U

EWIC EWIC_PENDA: EDBGREQ Position

Definition at line 1618 of file core_cm55.h.

◆ EWIC_EWIC_PENDA_EDBGREQ_Pos [2/2]

#define EWIC_EWIC_PENDA_EDBGREQ_Pos   2U

EWIC EWIC_PENDA: EDBGREQ Position

Definition at line 1605 of file core_cm85.h.

◆ EWIC_EWIC_PENDA_EVENT_Msk [1/2]

#define EWIC_EWIC_PENDA_EVENT_Msk   (0x1UL /*<< EWIC_EWIC_PENDA_EVENT_Pos*/)

EWIC EWIC_PENDA: EVENT Mask

Definition at line 1625 of file core_cm55.h.

◆ EWIC_EWIC_PENDA_EVENT_Msk [2/2]

#define EWIC_EWIC_PENDA_EVENT_Msk   (0x1UL /*<< EWIC_EWIC_PENDA_EVENT_Pos*/)

EWIC EWIC_PENDA: EVENT Mask

Definition at line 1612 of file core_cm85.h.

◆ EWIC_EWIC_PENDA_EVENT_Pos [1/2]

#define EWIC_EWIC_PENDA_EVENT_Pos   0U

EWIC EWIC_PENDA: EVENT Position

Definition at line 1624 of file core_cm55.h.

◆ EWIC_EWIC_PENDA_EVENT_Pos [2/2]

#define EWIC_EWIC_PENDA_EVENT_Pos   0U

EWIC EWIC_PENDA: EVENT Position

Definition at line 1611 of file core_cm85.h.

◆ EWIC_EWIC_PENDA_NMI_Msk [1/2]

#define EWIC_EWIC_PENDA_NMI_Msk   (0x1UL << EWIC_EWIC_PENDA_NMI_Pos)

EWIC EWIC_PENDA: NMI Mask

Definition at line 1622 of file core_cm55.h.

◆ EWIC_EWIC_PENDA_NMI_Msk [2/2]

#define EWIC_EWIC_PENDA_NMI_Msk   (0x1UL << EWIC_EWIC_PENDA_NMI_Pos)

EWIC EWIC_PENDA: NMI Mask

Definition at line 1609 of file core_cm85.h.

◆ EWIC_EWIC_PENDA_NMI_Pos [1/2]

#define EWIC_EWIC_PENDA_NMI_Pos   1U

EWIC EWIC_PENDA: NMI Position

Definition at line 1621 of file core_cm55.h.

◆ EWIC_EWIC_PENDA_NMI_Pos [2/2]

#define EWIC_EWIC_PENDA_NMI_Pos   1U

EWIC EWIC_PENDA: NMI Position

Definition at line 1608 of file core_cm85.h.

◆ EWIC_EWIC_PENDn_IRQ_Msk [1/2]

#define EWIC_EWIC_PENDn_IRQ_Msk   (0xFFFFFFFFUL /*<< EWIC_EWIC_PENDn_IRQ_Pos*/)

EWIC EWIC_PENDn: IRQ Mask

Definition at line 1629 of file core_cm55.h.

◆ EWIC_EWIC_PENDn_IRQ_Msk [2/2]

#define EWIC_EWIC_PENDn_IRQ_Msk   (0xFFFFFFFFUL /*<< EWIC_EWIC_PENDn_IRQ_Pos*/)

EWIC EWIC_PENDn: IRQ Mask

Definition at line 1616 of file core_cm85.h.

◆ EWIC_EWIC_PENDn_IRQ_Pos [1/2]

#define EWIC_EWIC_PENDn_IRQ_Pos   0U

EWIC EWIC_PENDn: IRQ Position

Definition at line 1628 of file core_cm55.h.

◆ EWIC_EWIC_PENDn_IRQ_Pos [2/2]

#define EWIC_EWIC_PENDn_IRQ_Pos   0U

EWIC EWIC_PENDn: IRQ Position

Definition at line 1615 of file core_cm85.h.

◆ EWIC_EWIC_PSR_NZ_Msk [1/2]

#define EWIC_EWIC_PSR_NZ_Msk   (0x7FFFUL << EWIC_EWIC_PSR_NZ_Pos)

EWIC EWIC_PSR: NZ Mask

Definition at line 1633 of file core_cm55.h.

◆ EWIC_EWIC_PSR_NZ_Msk [2/2]

#define EWIC_EWIC_PSR_NZ_Msk   (0x7FFFUL << EWIC_EWIC_PSR_NZ_Pos)

EWIC EWIC_PSR: NZ Mask

Definition at line 1620 of file core_cm85.h.

◆ EWIC_EWIC_PSR_NZ_Pos [1/2]

#define EWIC_EWIC_PSR_NZ_Pos   1U

EWIC EWIC_PSR: NZ Position

Definition at line 1632 of file core_cm55.h.

◆ EWIC_EWIC_PSR_NZ_Pos [2/2]

#define EWIC_EWIC_PSR_NZ_Pos   1U

EWIC EWIC_PSR: NZ Position

Definition at line 1619 of file core_cm85.h.

◆ EWIC_EWIC_PSR_NZA_Msk [1/2]

#define EWIC_EWIC_PSR_NZA_Msk   (0x1UL /*<< EWIC_EWIC_PSR_NZA_Pos*/)

EWIC EWIC_PSR: NZA Mask

Definition at line 1636 of file core_cm55.h.

◆ EWIC_EWIC_PSR_NZA_Msk [2/2]

#define EWIC_EWIC_PSR_NZA_Msk   (0x1UL /*<< EWIC_EWIC_PSR_NZA_Pos*/)

EWIC EWIC_PSR: NZA Mask

Definition at line 1623 of file core_cm85.h.

◆ EWIC_EWIC_PSR_NZA_Pos [1/2]

#define EWIC_EWIC_PSR_NZA_Pos   0U

EWIC EWIC_PSR: NZA Position

Definition at line 1635 of file core_cm55.h.

◆ EWIC_EWIC_PSR_NZA_Pos [2/2]

#define EWIC_EWIC_PSR_NZA_Pos   0U

EWIC EWIC_PSR: NZA Position

Definition at line 1622 of file core_cm85.h.

◆ EWIC_ISA [1/2]

#define EWIC_ISA   ((EWIC_ISA_Type *) EWIC_ISA_BASE )

EWIC interrupt status access struct

Definition at line 3685 of file core_cm55.h.

◆ EWIC_ISA [2/2]

#define EWIC_ISA   ((EWIC_ISA_Type *) EWIC_ISA_BASE )

EWIC interrupt status access struct

Definition at line 3589 of file core_cm85.h.

◆ EWIC_ISA_BASE [1/2]

#define EWIC_ISA_BASE   (0xE001E400UL)

External Wakeup Interrupt Controller interrupt status access Base Address

Definition at line 3663 of file core_cm55.h.

◆ EWIC_ISA_BASE [2/2]

#define EWIC_ISA_BASE   (0xE001E400UL)

External Wakeup Interrupt Controller interrupt status access Base Address

Definition at line 3568 of file core_cm85.h.

◆ EWIC_ISA_EVENTMASKA_EDBGREQ_Msk [1/2]

#define EWIC_ISA_EVENTMASKA_EDBGREQ_Msk   (0x1UL << EWIC_ISA_EVENTMASKA_EDBGREQ_Pos)

EWIC_ISA EVENTMASKA: EDBGREQ Mask

Definition at line 1671 of file core_cm55.h.

◆ EWIC_ISA_EVENTMASKA_EDBGREQ_Msk [2/2]

#define EWIC_ISA_EVENTMASKA_EDBGREQ_Msk   (0x1UL << EWIC_ISA_EVENTMASKA_EDBGREQ_Pos)

EWIC_ISA EVENTMASKA: EDBGREQ Mask

Definition at line 1658 of file core_cm85.h.

◆ EWIC_ISA_EVENTMASKA_EDBGREQ_Pos [1/2]

#define EWIC_ISA_EVENTMASKA_EDBGREQ_Pos   2U

EWIC_ISA EVENTMASKA: EDBGREQ Position

Definition at line 1670 of file core_cm55.h.

◆ EWIC_ISA_EVENTMASKA_EDBGREQ_Pos [2/2]

#define EWIC_ISA_EVENTMASKA_EDBGREQ_Pos   2U

EWIC_ISA EVENTMASKA: EDBGREQ Position

Definition at line 1657 of file core_cm85.h.

◆ EWIC_ISA_EVENTMASKA_EVENT_Msk [1/2]

#define EWIC_ISA_EVENTMASKA_EVENT_Msk   (0x1UL /*<< EWIC_ISA_EVENTMASKA_EVENT_Pos*/)

EWIC_ISA EVENTMASKA: EVENT Mask

Definition at line 1677 of file core_cm55.h.

◆ EWIC_ISA_EVENTMASKA_EVENT_Msk [2/2]

#define EWIC_ISA_EVENTMASKA_EVENT_Msk   (0x1UL /*<< EWIC_ISA_EVENTMASKA_EVENT_Pos*/)

EWIC_ISA EVENTMASKA: EVENT Mask

Definition at line 1664 of file core_cm85.h.

◆ EWIC_ISA_EVENTMASKA_EVENT_Pos [1/2]

#define EWIC_ISA_EVENTMASKA_EVENT_Pos   0U

EWIC_ISA EVENTMASKA: EVENT Position

Definition at line 1676 of file core_cm55.h.

◆ EWIC_ISA_EVENTMASKA_EVENT_Pos [2/2]

#define EWIC_ISA_EVENTMASKA_EVENT_Pos   0U

EWIC_ISA EVENTMASKA: EVENT Position

Definition at line 1663 of file core_cm85.h.

◆ EWIC_ISA_EVENTMASKA_NMI_Msk [1/2]

#define EWIC_ISA_EVENTMASKA_NMI_Msk   (0x1UL << EWIC_ISA_EVENTMASKA_NMI_Pos)

EWIC_ISA EVENTMASKA: NMI Mask

Definition at line 1674 of file core_cm55.h.

◆ EWIC_ISA_EVENTMASKA_NMI_Msk [2/2]

#define EWIC_ISA_EVENTMASKA_NMI_Msk   (0x1UL << EWIC_ISA_EVENTMASKA_NMI_Pos)

EWIC_ISA EVENTMASKA: NMI Mask

Definition at line 1661 of file core_cm85.h.

◆ EWIC_ISA_EVENTMASKA_NMI_Pos [1/2]

#define EWIC_ISA_EVENTMASKA_NMI_Pos   1U

EWIC_ISA EVENTMASKA: NMI Position

Definition at line 1673 of file core_cm55.h.

◆ EWIC_ISA_EVENTMASKA_NMI_Pos [2/2]

#define EWIC_ISA_EVENTMASKA_NMI_Pos   1U

EWIC_ISA EVENTMASKA: NMI Position

Definition at line 1660 of file core_cm85.h.

◆ EWIC_ISA_EVENTMASKn_IRQ_Msk [1/2]

#define EWIC_ISA_EVENTMASKn_IRQ_Msk   (0xFFFFFFFFUL /*<< EWIC_ISA_EVENTMASKn_IRQ_Pos*/)

EWIC_ISA EVENTMASKn: IRQ Mask

Definition at line 1681 of file core_cm55.h.

◆ EWIC_ISA_EVENTMASKn_IRQ_Msk [2/2]

#define EWIC_ISA_EVENTMASKn_IRQ_Msk   (0xFFFFFFFFUL /*<< EWIC_ISA_EVENTMASKn_IRQ_Pos*/)

EWIC_ISA EVENTMASKn: IRQ Mask

Definition at line 1668 of file core_cm85.h.

◆ EWIC_ISA_EVENTMASKn_IRQ_Pos [1/2]

#define EWIC_ISA_EVENTMASKn_IRQ_Pos   0U

EWIC_ISA EVENTMASKn: IRQ Position

Definition at line 1680 of file core_cm55.h.

◆ EWIC_ISA_EVENTMASKn_IRQ_Pos [2/2]

#define EWIC_ISA_EVENTMASKn_IRQ_Pos   0U

EWIC_ISA EVENTMASKn: IRQ Position

Definition at line 1667 of file core_cm85.h.

◆ EWIC_ISA_EVENTSPR_EDBGREQ_Msk [1/2]

#define EWIC_ISA_EVENTSPR_EDBGREQ_Msk   (0x1UL << EWIC_ISA_EVENTSPR_EDBGREQ_Pos)

EWIC_ISA EVENTSPR: EDBGREQ Mask

Definition at line 1661 of file core_cm55.h.

◆ EWIC_ISA_EVENTSPR_EDBGREQ_Msk [2/2]

#define EWIC_ISA_EVENTSPR_EDBGREQ_Msk   (0x1UL << EWIC_ISA_EVENTSPR_EDBGREQ_Pos)

EWIC_ISA EVENTSPR: EDBGREQ Mask

Definition at line 1648 of file core_cm85.h.

◆ EWIC_ISA_EVENTSPR_EDBGREQ_Pos [1/2]

#define EWIC_ISA_EVENTSPR_EDBGREQ_Pos   2U

EWIC_ISA EVENTSPR: EDBGREQ Position

Definition at line 1660 of file core_cm55.h.

◆ EWIC_ISA_EVENTSPR_EDBGREQ_Pos [2/2]

#define EWIC_ISA_EVENTSPR_EDBGREQ_Pos   2U

EWIC_ISA EVENTSPR: EDBGREQ Position

Definition at line 1647 of file core_cm85.h.

◆ EWIC_ISA_EVENTSPR_EVENT_Msk [1/2]

#define EWIC_ISA_EVENTSPR_EVENT_Msk   (0x1UL /*<< EWIC_ISA_EVENTSPR_EVENT_Pos*/)

EWIC_ISA EVENTSPR: EVENT Mask

Definition at line 1667 of file core_cm55.h.

◆ EWIC_ISA_EVENTSPR_EVENT_Msk [2/2]

#define EWIC_ISA_EVENTSPR_EVENT_Msk   (0x1UL /*<< EWIC_ISA_EVENTSPR_EVENT_Pos*/)

EWIC_ISA EVENTSPR: EVENT Mask

Definition at line 1654 of file core_cm85.h.

◆ EWIC_ISA_EVENTSPR_EVENT_Pos [1/2]

#define EWIC_ISA_EVENTSPR_EVENT_Pos   0U

EWIC_ISA EVENTSPR: EVENT Position

Definition at line 1666 of file core_cm55.h.

◆ EWIC_ISA_EVENTSPR_EVENT_Pos [2/2]

#define EWIC_ISA_EVENTSPR_EVENT_Pos   0U

EWIC_ISA EVENTSPR: EVENT Position

Definition at line 1653 of file core_cm85.h.

◆ EWIC_ISA_EVENTSPR_NMI_Msk [1/2]

#define EWIC_ISA_EVENTSPR_NMI_Msk   (0x1UL << EWIC_ISA_EVENTSPR_NMI_Pos)

EWIC_ISA EVENTSPR: NMI Mask

Definition at line 1664 of file core_cm55.h.

◆ EWIC_ISA_EVENTSPR_NMI_Msk [2/2]

#define EWIC_ISA_EVENTSPR_NMI_Msk   (0x1UL << EWIC_ISA_EVENTSPR_NMI_Pos)

EWIC_ISA EVENTSPR: NMI Mask

Definition at line 1651 of file core_cm85.h.

◆ EWIC_ISA_EVENTSPR_NMI_Pos [1/2]

#define EWIC_ISA_EVENTSPR_NMI_Pos   1U

EWIC_ISA EVENTSPR: NMI Position

Definition at line 1663 of file core_cm55.h.

◆ EWIC_ISA_EVENTSPR_NMI_Pos [2/2]

#define EWIC_ISA_EVENTSPR_NMI_Pos   1U

EWIC_ISA EVENTSPR: NMI Position

Definition at line 1650 of file core_cm85.h.

◆ ICB [1/2]

#define ICB   ((ICB_Type *) SCS_BASE )

System control Register not in SCB

Definition at line 3675 of file core_cm55.h.

◆ ICB [2/2]

#define ICB   ((ICB_Type *) SCS_BASE )

System control Register not in SCB

Definition at line 3579 of file core_cm85.h.

◆ ICB_ACTLR_DISCRITAXIRUR_Msk [1/2]

#define ICB_ACTLR_DISCRITAXIRUR_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos)

ACTLR: DISCRITAXIRUR Mask

Definition at line 1043 of file core_cm55.h.

◆ ICB_ACTLR_DISCRITAXIRUR_Msk [2/2]

#define ICB_ACTLR_DISCRITAXIRUR_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos)

ACTLR: DISCRITAXIRUR Mask

Definition at line 1057 of file core_cm85.h.

◆ ICB_ACTLR_DISCRITAXIRUR_Pos [1/2]

#define ICB_ACTLR_DISCRITAXIRUR_Pos   15U

ACTLR: DISCRITAXIRUR Position

Definition at line 1042 of file core_cm55.h.

◆ ICB_ACTLR_DISCRITAXIRUR_Pos [2/2]

#define ICB_ACTLR_DISCRITAXIRUR_Pos   15U

ACTLR: DISCRITAXIRUR Position

Definition at line 1056 of file core_cm85.h.

◆ ICB_ACTLR_DISCRITAXIRUW_Msk [1/2]

#define ICB_ACTLR_DISCRITAXIRUW_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos)

ACTLR: DISCRITAXIRUW Mask

Definition at line 1037 of file core_cm55.h.

◆ ICB_ACTLR_DISCRITAXIRUW_Msk [2/2]

#define ICB_ACTLR_DISCRITAXIRUW_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos)

ACTLR: DISCRITAXIRUW Mask

Definition at line 1054 of file core_cm85.h.

◆ ICB_ACTLR_DISCRITAXIRUW_Pos [1/2]

#define ICB_ACTLR_DISCRITAXIRUW_Pos   27U

ACTLR: DISCRITAXIRUW Position

Definition at line 1036 of file core_cm55.h.

◆ ICB_ACTLR_DISCRITAXIRUW_Pos [2/2]

#define ICB_ACTLR_DISCRITAXIRUW_Pos   27U

ACTLR: DISCRITAXIRUW Position

Definition at line 1053 of file core_cm85.h.

◆ ICB_ACTLR_DISDI_Msk

#define ICB_ACTLR_DISDI_Msk   (3UL << ICB_ACTLR_DISDI_Pos)

ACTLR: DISDI Mask

Definition at line 1040 of file core_cm55.h.

◆ ICB_ACTLR_DISDI_Pos

#define ICB_ACTLR_DISDI_Pos   16U

ACTLR: DISDI Position

Definition at line 1039 of file core_cm55.h.

◆ ICB_ACTLR_DISFOLD_Msk

#define ICB_ACTLR_DISFOLD_Msk   (1UL << ICB_ACTLR_DISFOLD_Pos)

ACTLR: DISFOLD Mask

Definition at line 1076 of file core_cm55.h.

◆ ICB_ACTLR_DISFOLD_Pos

#define ICB_ACTLR_DISFOLD_Pos   2U

ACTLR: DISFOLD Position

Definition at line 1075 of file core_cm55.h.

◆ ICB_ACTLR_DISITMATBFLUSH_Msk [1/2]

#define ICB_ACTLR_DISITMATBFLUSH_Msk   (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos)

ACTLR: DISITMATBFLUSH Mask

Definition at line 1052 of file core_cm55.h.

◆ ICB_ACTLR_DISITMATBFLUSH_Msk [2/2]

#define ICB_ACTLR_DISITMATBFLUSH_Msk   (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos)

ACTLR: DISITMATBFLUSH Mask

Definition at line 1066 of file core_cm85.h.

◆ ICB_ACTLR_DISITMATBFLUSH_Pos [1/2]

#define ICB_ACTLR_DISITMATBFLUSH_Pos   12U

ACTLR: DISITMATBFLUSH Position

Definition at line 1051 of file core_cm55.h.

◆ ICB_ACTLR_DISITMATBFLUSH_Pos [2/2]

#define ICB_ACTLR_DISITMATBFLUSH_Pos   12U

ACTLR: DISITMATBFLUSH Position

Definition at line 1065 of file core_cm85.h.

◆ ICB_ACTLR_DISLO_Msk

#define ICB_ACTLR_DISLO_Msk   (1UL << ICB_ACTLR_DISLO_Pos)

ACTLR: DISLO Mask

Definition at line 1070 of file core_cm55.h.

◆ ICB_ACTLR_DISLO_Pos

#define ICB_ACTLR_DISLO_Pos   4U

ACTLR: DISLO Position

Definition at line 1069 of file core_cm55.h.

◆ ICB_ACTLR_DISLOBR_Msk

#define ICB_ACTLR_DISLOBR_Msk   (1UL << ICB_ACTLR_DISLOBR_Pos)

ACTLR: DISLOBR Mask

Definition at line 1067 of file core_cm55.h.

◆ ICB_ACTLR_DISLOBR_Pos

#define ICB_ACTLR_DISLOBR_Pos   5U

ACTLR: DISLOBR Position

Definition at line 1066 of file core_cm55.h.

◆ ICB_ACTLR_DISLOLEP_Msk

#define ICB_ACTLR_DISLOLEP_Msk   (1UL << ICB_ACTLR_DISLOLEP_Pos)

ACTLR: DISLOLEP Mask

Definition at line 1073 of file core_cm55.h.

◆ ICB_ACTLR_DISLOLEP_Pos

#define ICB_ACTLR_DISLOLEP_Pos   3U

ACTLR: DISLOLEP Position

Definition at line 1072 of file core_cm55.h.

◆ ICB_ACTLR_DISNWAMODE_Msk [1/2]

#define ICB_ACTLR_DISNWAMODE_Msk   (1UL << ICB_ACTLR_DISNWAMODE_Pos)

ACTLR: DISNWAMODE Mask

Definition at line 1055 of file core_cm55.h.

◆ ICB_ACTLR_DISNWAMODE_Msk [2/2]

#define ICB_ACTLR_DISNWAMODE_Msk   (1UL << ICB_ACTLR_DISNWAMODE_Pos)

ACTLR: DISNWAMODE Mask

Definition at line 1069 of file core_cm85.h.

◆ ICB_ACTLR_DISNWAMODE_Pos [1/2]

#define ICB_ACTLR_DISNWAMODE_Pos   11U

ACTLR: DISNWAMODE Position

Definition at line 1054 of file core_cm55.h.

◆ ICB_ACTLR_DISNWAMODE_Pos [2/2]

#define ICB_ACTLR_DISNWAMODE_Pos   11U

ACTLR: DISNWAMODE Position

Definition at line 1068 of file core_cm85.h.

◆ ICB_ACTLR_DISOLAP_Msk

#define ICB_ACTLR_DISOLAP_Msk   (1UL << ICB_ACTLR_DISOLAP_Pos)

ACTLR: DISOLAP Mask

Definition at line 1061 of file core_cm55.h.

◆ ICB_ACTLR_DISOLAP_Pos

#define ICB_ACTLR_DISOLAP_Pos   7U

ACTLR: DISOLAP Position

Definition at line 1060 of file core_cm55.h.

◆ ICB_ACTLR_DISOLAPS_Msk

#define ICB_ACTLR_DISOLAPS_Msk   (1UL << ICB_ACTLR_DISOLAPS_Pos)

ACTLR: DISOLAPS Mask

Definition at line 1064 of file core_cm55.h.

◆ ICB_ACTLR_DISOLAPS_Pos

#define ICB_ACTLR_DISOLAPS_Pos   6U

ACTLR: DISOLAPS Position

Definition at line 1063 of file core_cm55.h.

◆ ICB_ACTLR_EVENTBUSEN_Msk [1/2]

#define ICB_ACTLR_EVENTBUSEN_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_Pos)

ACTLR: EVENTBUSEN Mask

Definition at line 1046 of file core_cm55.h.

◆ ICB_ACTLR_EVENTBUSEN_Msk [2/2]

#define ICB_ACTLR_EVENTBUSEN_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_Pos)

ACTLR: EVENTBUSEN Mask

Definition at line 1060 of file core_cm85.h.

◆ ICB_ACTLR_EVENTBUSEN_Pos [1/2]

#define ICB_ACTLR_EVENTBUSEN_Pos   14U

ACTLR: EVENTBUSEN Position

Definition at line 1045 of file core_cm55.h.

◆ ICB_ACTLR_EVENTBUSEN_Pos [2/2]

#define ICB_ACTLR_EVENTBUSEN_Pos   14U

ACTLR: EVENTBUSEN Position

Definition at line 1059 of file core_cm85.h.

◆ ICB_ACTLR_EVENTBUSEN_S_Msk [1/2]

#define ICB_ACTLR_EVENTBUSEN_S_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos)

ACTLR: EVENTBUSEN_S Mask

Definition at line 1049 of file core_cm55.h.

◆ ICB_ACTLR_EVENTBUSEN_S_Msk [2/2]

#define ICB_ACTLR_EVENTBUSEN_S_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos)

ACTLR: EVENTBUSEN_S Mask

Definition at line 1063 of file core_cm85.h.

◆ ICB_ACTLR_EVENTBUSEN_S_Pos [1/2]

#define ICB_ACTLR_EVENTBUSEN_S_Pos   13U

ACTLR: EVENTBUSEN_S Position

Definition at line 1048 of file core_cm55.h.

◆ ICB_ACTLR_EVENTBUSEN_S_Pos [2/2]

#define ICB_ACTLR_EVENTBUSEN_S_Pos   13U

ACTLR: EVENTBUSEN_S Position

Definition at line 1062 of file core_cm85.h.

◆ ICB_ACTLR_FPEXCODIS_Msk [1/2]

#define ICB_ACTLR_FPEXCODIS_Msk   (1UL << ICB_ACTLR_FPEXCODIS_Pos)

ACTLR: FPEXCODIS Mask

Definition at line 1058 of file core_cm55.h.

◆ ICB_ACTLR_FPEXCODIS_Msk [2/2]

#define ICB_ACTLR_FPEXCODIS_Msk   (1UL << ICB_ACTLR_FPEXCODIS_Pos)

ACTLR: FPEXCODIS Mask

Definition at line 1072 of file core_cm85.h.

◆ ICB_ACTLR_FPEXCODIS_Pos [1/2]

#define ICB_ACTLR_FPEXCODIS_Pos   10U

ACTLR: FPEXCODIS Position

Definition at line 1057 of file core_cm55.h.

◆ ICB_ACTLR_FPEXCODIS_Pos [2/2]

#define ICB_ACTLR_FPEXCODIS_Pos   10U

ACTLR: FPEXCODIS Position

Definition at line 1071 of file core_cm85.h.

◆ ICB_ICTR_INTLINESNUM_Msk [1/2]

#define ICB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

Definition at line 1080 of file core_cm55.h.

◆ ICB_ICTR_INTLINESNUM_Msk [2/2]

#define ICB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

Definition at line 1076 of file core_cm85.h.

◆ ICB_ICTR_INTLINESNUM_Pos [1/2]

#define ICB_ICTR_INTLINESNUM_Pos   0U

ICTR: INTLINESNUM Position

Definition at line 1079 of file core_cm55.h.

◆ ICB_ICTR_INTLINESNUM_Pos [2/2]

#define ICB_ICTR_INTLINESNUM_Pos   0U

ICTR: INTLINESNUM Position

Definition at line 1075 of file core_cm85.h.

◆ ITM_ITCTRL_IME_Msk [1/2]

#define ITM_ITCTRL_IME_Msk   (0x1UL /*<< ITM_ITCTRL_IME_Pos*/)

ITM ITCTRL: IME Mask

Definition at line 1243 of file core_cm55.h.

◆ ITM_ITCTRL_IME_Msk [2/2]

#define ITM_ITCTRL_IME_Msk   (0x1UL /*<< ITM_ITCTRL_IME_Pos*/)

ITM ITCTRL: IME Mask

Definition at line 1239 of file core_cm85.h.

◆ ITM_ITCTRL_IME_Pos [1/2]

#define ITM_ITCTRL_IME_Pos   0U

ITM ITCTRL: IME Position

Definition at line 1242 of file core_cm55.h.

◆ ITM_ITCTRL_IME_Pos [2/2]

#define ITM_ITCTRL_IME_Pos   0U

ITM ITCTRL: IME Position

Definition at line 1238 of file core_cm85.h.

◆ ITM_ITREAD_AFVALID_Msk [1/2]

#define ITM_ITREAD_AFVALID_Msk   (0x1UL << ITM_ITREAD_AFVALID_Pos)

ITM ITREAD: AFVALID Mask

Definition at line 1229 of file core_cm55.h.

◆ ITM_ITREAD_AFVALID_Msk [2/2]

#define ITM_ITREAD_AFVALID_Msk   (0x1UL << ITM_ITREAD_AFVALID_Pos)

ITM ITREAD: AFVALID Mask

Definition at line 1225 of file core_cm85.h.

◆ ITM_ITREAD_AFVALID_Pos [1/2]

#define ITM_ITREAD_AFVALID_Pos   1U

ITM ITREAD: AFVALID Position

Definition at line 1228 of file core_cm55.h.

◆ ITM_ITREAD_AFVALID_Pos [2/2]

#define ITM_ITREAD_AFVALID_Pos   1U

ITM ITREAD: AFVALID Position

Definition at line 1224 of file core_cm85.h.

◆ ITM_ITREAD_ATREADY_Msk [1/2]

#define ITM_ITREAD_ATREADY_Msk   (0x1UL /*<< ITM_ITREAD_ATREADY_Pos*/)

ITM ITREAD: ATREADY Mask

Definition at line 1232 of file core_cm55.h.

◆ ITM_ITREAD_ATREADY_Msk [2/2]

#define ITM_ITREAD_ATREADY_Msk   (0x1UL /*<< ITM_ITREAD_ATREADY_Pos*/)

ITM ITREAD: ATREADY Mask

Definition at line 1228 of file core_cm85.h.

◆ ITM_ITREAD_ATREADY_Pos [1/2]

#define ITM_ITREAD_ATREADY_Pos   0U

ITM ITREAD: ATREADY Position

Definition at line 1231 of file core_cm55.h.

◆ ITM_ITREAD_ATREADY_Pos [2/2]

#define ITM_ITREAD_ATREADY_Pos   0U

ITM ITREAD: ATREADY Position

Definition at line 1227 of file core_cm85.h.

◆ ITM_ITWRITE_AFVALID_Msk [1/2]

#define ITM_ITWRITE_AFVALID_Msk   (0x1UL << ITM_ITWRITE_AFVALID_Pos)

ITM ITWRITE: AFVALID Mask

Definition at line 1236 of file core_cm55.h.

◆ ITM_ITWRITE_AFVALID_Msk [2/2]

#define ITM_ITWRITE_AFVALID_Msk   (0x1UL << ITM_ITWRITE_AFVALID_Pos)

ITM ITWRITE: AFVALID Mask

Definition at line 1232 of file core_cm85.h.

◆ ITM_ITWRITE_AFVALID_Pos [1/2]

#define ITM_ITWRITE_AFVALID_Pos   1U

ITM ITWRITE: AFVALID Position

Definition at line 1235 of file core_cm55.h.

◆ ITM_ITWRITE_AFVALID_Pos [2/2]

#define ITM_ITWRITE_AFVALID_Pos   1U

ITM ITWRITE: AFVALID Position

Definition at line 1231 of file core_cm85.h.

◆ ITM_ITWRITE_ATREADY_Msk [1/2]

#define ITM_ITWRITE_ATREADY_Msk   (0x1UL /*<< ITM_ITWRITE_ATREADY_Pos*/)

ITM ITWRITE: ATREADY Mask

Definition at line 1239 of file core_cm55.h.

◆ ITM_ITWRITE_ATREADY_Msk [2/2]

#define ITM_ITWRITE_ATREADY_Msk   (0x1UL /*<< ITM_ITWRITE_ATREADY_Pos*/)

ITM ITWRITE: ATREADY Mask

Definition at line 1235 of file core_cm85.h.

◆ ITM_ITWRITE_ATREADY_Pos [1/2]

#define ITM_ITWRITE_ATREADY_Pos   0U

ITM ITWRITE: ATREADY Position

Definition at line 1238 of file core_cm55.h.

◆ ITM_ITWRITE_ATREADY_Pos [2/2]

#define ITM_ITWRITE_ATREADY_Pos   0U

ITM ITWRITE: ATREADY Position

Definition at line 1234 of file core_cm85.h.

◆ MEMSYSCTL [1/2]

#define MEMSYSCTL   ((MemSysCtl_Type *) MEMSYSCTL_BASE )

Memory System Control configuration struct

Definition at line 3682 of file core_cm55.h.

◆ MEMSYSCTL [2/2]

#define MEMSYSCTL   ((MemSysCtl_Type *) MEMSYSCTL_BASE )

Memory System Control configuration struct

Definition at line 3586 of file core_cm85.h.

◆ MEMSYSCTL_BASE [1/2]

#define MEMSYSCTL_BASE   (0xE001E000UL)

Memory System Control Base Address

Definition at line 3660 of file core_cm55.h.

◆ MEMSYSCTL_BASE [2/2]

#define MEMSYSCTL_BASE   (0xE001E000UL)

Memory System Control Base Address

Definition at line 3565 of file core_cm85.h.

◆ MEMSYSCTL_DTCMCR_EN_Msk [1/2]

#define MEMSYSCTL_DTCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/)

MEMSYSCTL DTCMCR: EN Mask

Definition at line 1482 of file core_cm55.h.

◆ MEMSYSCTL_DTCMCR_EN_Msk [2/2]

#define MEMSYSCTL_DTCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/)

MEMSYSCTL DTCMCR: EN Mask

Definition at line 1469 of file core_cm85.h.

◆ MEMSYSCTL_DTCMCR_EN_Pos [1/2]

#define MEMSYSCTL_DTCMCR_EN_Pos   0U

MEMSYSCTL DTCMCR: EN Position

Definition at line 1481 of file core_cm55.h.

◆ MEMSYSCTL_DTCMCR_EN_Pos [2/2]

#define MEMSYSCTL_DTCMCR_EN_Pos   0U

MEMSYSCTL DTCMCR: EN Position

Definition at line 1468 of file core_cm85.h.

◆ MEMSYSCTL_DTCMCR_SZ_Msk [1/2]

#define MEMSYSCTL_DTCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos)

MEMSYSCTL DTCMCR: SZ Mask

Definition at line 1479 of file core_cm55.h.

◆ MEMSYSCTL_DTCMCR_SZ_Msk [2/2]

#define MEMSYSCTL_DTCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos)

MEMSYSCTL DTCMCR: SZ Mask

Definition at line 1466 of file core_cm85.h.

◆ MEMSYSCTL_DTCMCR_SZ_Pos [1/2]

#define MEMSYSCTL_DTCMCR_SZ_Pos   3U

MEMSYSCTL DTCMCR: SZ Position

Definition at line 1478 of file core_cm55.h.

◆ MEMSYSCTL_DTCMCR_SZ_Pos [2/2]

#define MEMSYSCTL_DTCMCR_SZ_Pos   3U

MEMSYSCTL DTCMCR: SZ Position

Definition at line 1465 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CFG_BLKSZ_Msk [1/2]

#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/)

MEMSYSCTL DTGU_CFG: BLKSZ Mask

Definition at line 1523 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CFG_BLKSZ_Msk [2/2]

#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/)

MEMSYSCTL DTGU_CFG: BLKSZ Mask

Definition at line 1510 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CFG_BLKSZ_Pos [1/2]

#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos   0U

MEMSYSCTL DTGU_CFG: BLKSZ Position

Definition at line 1522 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CFG_BLKSZ_Pos [2/2]

#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos   0U

MEMSYSCTL DTGU_CFG: BLKSZ Position

Definition at line 1509 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk [1/2]

#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos)

MEMSYSCTL DTGU_CFG: NUMBLKS Mask

Definition at line 1520 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk [2/2]

#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos)

MEMSYSCTL DTGU_CFG: NUMBLKS Mask

Definition at line 1507 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos [1/2]

#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos   8U

MEMSYSCTL DTGU_CFG: NUMBLKS Position

Definition at line 1519 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos [2/2]

#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos   8U

MEMSYSCTL DTGU_CFG: NUMBLKS Position

Definition at line 1506 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CFG_PRESENT_Msk [1/2]

#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos)

MEMSYSCTL DTGU_CFG: PRESENT Mask

Definition at line 1517 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CFG_PRESENT_Msk [2/2]

#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos)

MEMSYSCTL DTGU_CFG: PRESENT Mask

Definition at line 1504 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CFG_PRESENT_Pos [1/2]

#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos   31U

MEMSYSCTL DTGU_CFG: PRESENT Position

Definition at line 1516 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CFG_PRESENT_Pos [2/2]

#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos   31U

MEMSYSCTL DTGU_CFG: PRESENT Position

Definition at line 1503 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CTRL_DBFEN_Msk [1/2]

#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/)

MEMSYSCTL DTGU_CTRL: DBFEN Mask

Definition at line 1513 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CTRL_DBFEN_Msk [2/2]

#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/)

MEMSYSCTL DTGU_CTRL: DBFEN Mask

Definition at line 1500 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CTRL_DBFEN_Pos [1/2]

#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos   0U

MEMSYSCTL DTGU_CTRL: DBFEN Position

Definition at line 1512 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CTRL_DBFEN_Pos [2/2]

#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos   0U

MEMSYSCTL DTGU_CTRL: DBFEN Position

Definition at line 1499 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CTRL_DEREN_Msk [1/2]

#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos)

MEMSYSCTL DTGU_CTRL: DEREN Mask

Definition at line 1510 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CTRL_DEREN_Msk [2/2]

#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos)

MEMSYSCTL DTGU_CTRL: DEREN Mask

Definition at line 1497 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CTRL_DEREN_Pos [1/2]

#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos   1U

MEMSYSCTL DTGU_CTRL: DEREN Position

Definition at line 1509 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CTRL_DEREN_Pos [2/2]

#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos   1U

MEMSYSCTL DTGU_CTRL: DEREN Position

Definition at line 1496 of file core_cm85.h.

◆ MEMSYSCTL_ITCMCR_EN_Msk [1/2]

#define MEMSYSCTL_ITCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/)

MEMSYSCTL ITCMCR: EN Mask

Definition at line 1475 of file core_cm55.h.

◆ MEMSYSCTL_ITCMCR_EN_Msk [2/2]

#define MEMSYSCTL_ITCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/)

MEMSYSCTL ITCMCR: EN Mask

Definition at line 1462 of file core_cm85.h.

◆ MEMSYSCTL_ITCMCR_EN_Pos [1/2]

#define MEMSYSCTL_ITCMCR_EN_Pos   0U

MEMSYSCTL ITCMCR: EN Position

Definition at line 1474 of file core_cm55.h.

◆ MEMSYSCTL_ITCMCR_EN_Pos [2/2]

#define MEMSYSCTL_ITCMCR_EN_Pos   0U

MEMSYSCTL ITCMCR: EN Position

Definition at line 1461 of file core_cm85.h.

◆ MEMSYSCTL_ITCMCR_SZ_Msk [1/2]

#define MEMSYSCTL_ITCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos)

MEMSYSCTL ITCMCR: SZ Mask

Definition at line 1472 of file core_cm55.h.

◆ MEMSYSCTL_ITCMCR_SZ_Msk [2/2]

#define MEMSYSCTL_ITCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos)

MEMSYSCTL ITCMCR: SZ Mask

Definition at line 1459 of file core_cm85.h.

◆ MEMSYSCTL_ITCMCR_SZ_Pos [1/2]

#define MEMSYSCTL_ITCMCR_SZ_Pos   3U

MEMSYSCTL ITCMCR: SZ Position

Definition at line 1471 of file core_cm55.h.

◆ MEMSYSCTL_ITCMCR_SZ_Pos [2/2]

#define MEMSYSCTL_ITCMCR_SZ_Pos   3U

MEMSYSCTL ITCMCR: SZ Position

Definition at line 1458 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CFG_BLKSZ_Msk [1/2]

#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/)

MEMSYSCTL ITGU_CFG: BLKSZ Mask

Definition at line 1506 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CFG_BLKSZ_Msk [2/2]

#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/)

MEMSYSCTL ITGU_CFG: BLKSZ Mask

Definition at line 1493 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CFG_BLKSZ_Pos [1/2]

#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos   0U

MEMSYSCTL ITGU_CFG: BLKSZ Position

Definition at line 1505 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CFG_BLKSZ_Pos [2/2]

#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos   0U

MEMSYSCTL ITGU_CFG: BLKSZ Position

Definition at line 1492 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk [1/2]

#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos)

MEMSYSCTL ITGU_CFG: NUMBLKS Mask

Definition at line 1503 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk [2/2]

#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos)

MEMSYSCTL ITGU_CFG: NUMBLKS Mask

Definition at line 1490 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos [1/2]

#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos   8U

MEMSYSCTL ITGU_CFG: NUMBLKS Position

Definition at line 1502 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos [2/2]

#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos   8U

MEMSYSCTL ITGU_CFG: NUMBLKS Position

Definition at line 1489 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CFG_PRESENT_Msk [1/2]

#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos)

MEMSYSCTL ITGU_CFG: PRESENT Mask

Definition at line 1500 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CFG_PRESENT_Msk [2/2]

#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos)

MEMSYSCTL ITGU_CFG: PRESENT Mask

Definition at line 1487 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CFG_PRESENT_Pos [1/2]

#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos   31U

MEMSYSCTL ITGU_CFG: PRESENT Position

Definition at line 1499 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CFG_PRESENT_Pos [2/2]

#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos   31U

MEMSYSCTL ITGU_CFG: PRESENT Position

Definition at line 1486 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CTRL_DBFEN_Msk [1/2]

#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/)

MEMSYSCTL ITGU_CTRL: DBFEN Mask

Definition at line 1496 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CTRL_DBFEN_Msk [2/2]

#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/)

MEMSYSCTL ITGU_CTRL: DBFEN Mask

Definition at line 1483 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CTRL_DBFEN_Pos [1/2]

#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos   0U

MEMSYSCTL ITGU_CTRL: DBFEN Position

Definition at line 1495 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CTRL_DBFEN_Pos [2/2]

#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos   0U

MEMSYSCTL ITGU_CTRL: DBFEN Position

Definition at line 1482 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CTRL_DEREN_Msk [1/2]

#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos)

MEMSYSCTL ITGU_CTRL: DEREN Mask

Definition at line 1493 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CTRL_DEREN_Msk [2/2]

#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos)

MEMSYSCTL ITGU_CTRL: DEREN Mask

Definition at line 1480 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CTRL_DEREN_Pos [1/2]

#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos   1U

MEMSYSCTL ITGU_CTRL: DEREN Position

Definition at line 1492 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CTRL_DEREN_Pos [2/2]

#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos   1U

MEMSYSCTL ITGU_CTRL: DEREN Position

Definition at line 1479 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_CPWRDN_Msk [1/2]

#define MEMSYSCTL_MSCR_CPWRDN_Msk   (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos)

MEMSYSCTL MSCR: CPWRDN Mask

Definition at line 1434 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_CPWRDN_Msk [2/2]

#define MEMSYSCTL_MSCR_CPWRDN_Msk   (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos)

MEMSYSCTL MSCR: CPWRDN Mask

Definition at line 1430 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_CPWRDN_Pos [1/2]

#define MEMSYSCTL_MSCR_CPWRDN_Pos   17U

MEMSYSCTL MSCR: CPWRDN Position

Definition at line 1433 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_CPWRDN_Pos [2/2]

#define MEMSYSCTL_MSCR_CPWRDN_Pos   17U

MEMSYSCTL MSCR: CPWRDN Position

Definition at line 1429 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_DCACTIVE_Msk [1/2]

#define MEMSYSCTL_MSCR_DCACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos)

MEMSYSCTL MSCR: DCACTIVE Mask

Definition at line 1443 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_DCACTIVE_Msk [2/2]

#define MEMSYSCTL_MSCR_DCACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos)

MEMSYSCTL MSCR: DCACTIVE Mask

Definition at line 1439 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_DCACTIVE_Pos [1/2]

#define MEMSYSCTL_MSCR_DCACTIVE_Pos   12U

MEMSYSCTL MSCR: DCACTIVE Position

Definition at line 1442 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_DCACTIVE_Pos [2/2]

#define MEMSYSCTL_MSCR_DCACTIVE_Pos   12U

MEMSYSCTL MSCR: DCACTIVE Position

Definition at line 1438 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_DCCLEAN_Msk [1/2]

#define MEMSYSCTL_MSCR_DCCLEAN_Msk   (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos)

MEMSYSCTL MSCR: DCCLEAN Mask

Definition at line 1437 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_DCCLEAN_Msk [2/2]

#define MEMSYSCTL_MSCR_DCCLEAN_Msk   (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos)

MEMSYSCTL MSCR: DCCLEAN Mask

Definition at line 1433 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_DCCLEAN_Pos [1/2]

#define MEMSYSCTL_MSCR_DCCLEAN_Pos   16U

MEMSYSCTL MSCR: DCCLEAN Position

Definition at line 1436 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_DCCLEAN_Pos [2/2]

#define MEMSYSCTL_MSCR_DCCLEAN_Pos   16U

MEMSYSCTL MSCR: DCCLEAN Position

Definition at line 1432 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_ECCEN_Msk [1/2]

#define MEMSYSCTL_MSCR_ECCEN_Msk   (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos)

MEMSYSCTL MSCR: ECCEN Mask

Definition at line 1455 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_ECCEN_Msk [2/2]

#define MEMSYSCTL_MSCR_ECCEN_Msk   (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos)

MEMSYSCTL MSCR: ECCEN Mask

Definition at line 1448 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_ECCEN_Pos [1/2]

#define MEMSYSCTL_MSCR_ECCEN_Pos   1U

MEMSYSCTL MSCR: ECCEN Position

Definition at line 1454 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_ECCEN_Pos [2/2]

#define MEMSYSCTL_MSCR_ECCEN_Pos   1U

MEMSYSCTL MSCR: ECCEN Position

Definition at line 1447 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_EVECCFAULT_Msk [1/2]

#define MEMSYSCTL_MSCR_EVECCFAULT_Msk   (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos)

MEMSYSCTL MSCR: EVECCFAULT Mask

Definition at line 1449 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_EVECCFAULT_Msk [2/2]

#define MEMSYSCTL_MSCR_EVECCFAULT_Msk   (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos)

MEMSYSCTL MSCR: EVECCFAULT Mask

Definition at line 1442 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_EVECCFAULT_Pos [1/2]

#define MEMSYSCTL_MSCR_EVECCFAULT_Pos   3U

MEMSYSCTL MSCR: EVECCFAULT Position

Definition at line 1448 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_EVECCFAULT_Pos [2/2]

#define MEMSYSCTL_MSCR_EVECCFAULT_Pos   3U

MEMSYSCTL MSCR: EVECCFAULT Position

Definition at line 1441 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_FORCEWT_Msk [1/2]

#define MEMSYSCTL_MSCR_FORCEWT_Msk   (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos)

MEMSYSCTL MSCR: FORCEWT Mask

Definition at line 1452 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_FORCEWT_Msk [2/2]

#define MEMSYSCTL_MSCR_FORCEWT_Msk   (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos)

MEMSYSCTL MSCR: FORCEWT Mask

Definition at line 1445 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_FORCEWT_Pos [1/2]

#define MEMSYSCTL_MSCR_FORCEWT_Pos   2U

MEMSYSCTL MSCR: FORCEWT Position

Definition at line 1451 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_FORCEWT_Pos [2/2]

#define MEMSYSCTL_MSCR_FORCEWT_Pos   2U

MEMSYSCTL MSCR: FORCEWT Position

Definition at line 1444 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_ICACTIVE_Msk [1/2]

#define MEMSYSCTL_MSCR_ICACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos)

MEMSYSCTL MSCR: ICACTIVE Mask

Definition at line 1440 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_ICACTIVE_Msk [2/2]

#define MEMSYSCTL_MSCR_ICACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos)

MEMSYSCTL MSCR: ICACTIVE Mask

Definition at line 1436 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_ICACTIVE_Pos [1/2]

#define MEMSYSCTL_MSCR_ICACTIVE_Pos   13U

MEMSYSCTL MSCR: ICACTIVE Position

Definition at line 1439 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_ICACTIVE_Pos [2/2]

#define MEMSYSCTL_MSCR_ICACTIVE_Pos   13U

MEMSYSCTL MSCR: ICACTIVE Position

Definition at line 1435 of file core_cm85.h.

◆ MEMSYSCTL_PAHBCR_EN_Msk [1/2]

#define MEMSYSCTL_PAHBCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/)

MEMSYSCTL PAHBCR: EN Mask

Definition at line 1489 of file core_cm55.h.

◆ MEMSYSCTL_PAHBCR_EN_Msk [2/2]

#define MEMSYSCTL_PAHBCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/)

MEMSYSCTL PAHBCR: EN Mask

Definition at line 1476 of file core_cm85.h.

◆ MEMSYSCTL_PAHBCR_EN_Pos [1/2]

#define MEMSYSCTL_PAHBCR_EN_Pos   0U

MEMSYSCTL PAHBCR: EN Position

Definition at line 1488 of file core_cm55.h.

◆ MEMSYSCTL_PAHBCR_EN_Pos [2/2]

#define MEMSYSCTL_PAHBCR_EN_Pos   0U

MEMSYSCTL PAHBCR: EN Position

Definition at line 1475 of file core_cm85.h.

◆ MEMSYSCTL_PAHBCR_SZ_Msk [1/2]

#define MEMSYSCTL_PAHBCR_SZ_Msk   (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos)

MEMSYSCTL PAHBCR: SZ Mask

Definition at line 1486 of file core_cm55.h.

◆ MEMSYSCTL_PAHBCR_SZ_Msk [2/2]

#define MEMSYSCTL_PAHBCR_SZ_Msk   (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos)

MEMSYSCTL PAHBCR: SZ Mask

Definition at line 1473 of file core_cm85.h.

◆ MEMSYSCTL_PAHBCR_SZ_Pos [1/2]

#define MEMSYSCTL_PAHBCR_SZ_Pos   1U

MEMSYSCTL PAHBCR: SZ Position

Definition at line 1485 of file core_cm55.h.

◆ MEMSYSCTL_PAHBCR_SZ_Pos [2/2]

#define MEMSYSCTL_PAHBCR_SZ_Pos   1U

MEMSYSCTL PAHBCR: SZ Position

Definition at line 1472 of file core_cm85.h.

◆ MEMSYSCTL_PFCR_DIS_NLP_Msk

#define MEMSYSCTL_PFCR_DIS_NLP_Msk   (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos)

MEMSYSCTL PFCR: DIS_NLP Mask

Definition at line 1452 of file core_cm85.h.

◆ MEMSYSCTL_PFCR_DIS_NLP_Pos

#define MEMSYSCTL_PFCR_DIS_NLP_Pos   7U

MEMSYSCTL PFCR: DIS_NLP Position

Definition at line 1451 of file core_cm85.h.

◆ MEMSYSCTL_PFCR_ENABLE_Msk [1/2]

#define MEMSYSCTL_PFCR_ENABLE_Msk   (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/)

MEMSYSCTL PFCR: ENABLE Mask

Definition at line 1468 of file core_cm55.h.

◆ MEMSYSCTL_PFCR_ENABLE_Msk [2/2]

#define MEMSYSCTL_PFCR_ENABLE_Msk   (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/)

MEMSYSCTL PFCR: ENABLE Mask

Definition at line 1455 of file core_cm85.h.

◆ MEMSYSCTL_PFCR_ENABLE_Pos [1/2]

#define MEMSYSCTL_PFCR_ENABLE_Pos   0U

MEMSYSCTL PFCR: ENABLE Position

Definition at line 1467 of file core_cm55.h.

◆ MEMSYSCTL_PFCR_ENABLE_Pos [2/2]

#define MEMSYSCTL_PFCR_ENABLE_Pos   0U

MEMSYSCTL PFCR: ENABLE Position

Definition at line 1454 of file core_cm85.h.

◆ PRCCFGINF [1/2]

#define PRCCFGINF   ((PrcCfgInf_Type *) PRCCFGINF_BASE )

Processor Configuration Information configuration struct

Definition at line 3687 of file core_cm55.h.

◆ PRCCFGINF [2/2]

#define PRCCFGINF   ((PrcCfgInf_Type *) PRCCFGINF_BASE )

Processor Configuration Information configuration struct

Definition at line 3591 of file core_cm85.h.

◆ PRCCFGINF_BASE [1/2]

#define PRCCFGINF_BASE   (0xE001E700UL)

Processor Configuration Information Base Address

Definition at line 3664 of file core_cm55.h.

◆ PRCCFGINF_BASE [2/2]

#define PRCCFGINF_BASE   (0xE001E700UL)

Processor Configuration Information Base Address

Definition at line 3569 of file core_cm85.h.

◆ PWRMODCTL [1/2]

#define PWRMODCTL   ((PwrModCtl_Type *) PWRMODCTL_BASE )

Power Mode Control configuration struct

Definition at line 3684 of file core_cm55.h.

◆ PWRMODCTL [2/2]

#define PWRMODCTL   ((PwrModCtl_Type *) PWRMODCTL_BASE )

Power Mode Control configuration struct

Definition at line 3588 of file core_cm85.h.

◆ PWRMODCTL_BASE [1/2]

#define PWRMODCTL_BASE   (0xE001E300UL)

Power Mode Control Base Address

Definition at line 3662 of file core_cm55.h.

◆ PWRMODCTL_BASE [2/2]

#define PWRMODCTL_BASE   (0xE001E300UL)

Power Mode Control Base Address

Definition at line 3567 of file core_cm85.h.

◆ PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk [1/2]

#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/)

PWRMODCTL CPDLPSTATE: CLPSTATE Mask

Definition at line 1553 of file core_cm55.h.

◆ PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk [2/2]

#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/)

PWRMODCTL CPDLPSTATE: CLPSTATE Mask

Definition at line 1540 of file core_cm85.h.

◆ PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos [1/2]

#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos   0U

PWRMODCTL CPDLPSTATE: CLPSTATE Position

Definition at line 1552 of file core_cm55.h.

◆ PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos [2/2]

#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos   0U

PWRMODCTL CPDLPSTATE: CLPSTATE Position

Definition at line 1539 of file core_cm85.h.

◆ PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk [1/2]

#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos)

PWRMODCTL CPDLPSTATE: ELPSTATE Mask

Definition at line 1550 of file core_cm55.h.

◆ PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk [2/2]

#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos)

PWRMODCTL CPDLPSTATE: ELPSTATE Mask

Definition at line 1537 of file core_cm85.h.

◆ PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos [1/2]

#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos   4U

PWRMODCTL CPDLPSTATE: ELPSTATE Position

Definition at line 1549 of file core_cm55.h.

◆ PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos [2/2]

#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos   4U

PWRMODCTL CPDLPSTATE: ELPSTATE Position

Definition at line 1536 of file core_cm85.h.

◆ PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk [1/2]

#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos)

PWRMODCTL CPDLPSTATE: RLPSTATE Mask

Definition at line 1547 of file core_cm55.h.

◆ PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk [2/2]

#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos)

PWRMODCTL CPDLPSTATE: RLPSTATE Mask

Definition at line 1534 of file core_cm85.h.

◆ PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos [1/2]

#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos   8U

PWRMODCTL CPDLPSTATE: RLPSTATE Position

Definition at line 1546 of file core_cm55.h.

◆ PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos [2/2]

#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos   8U

PWRMODCTL CPDLPSTATE: RLPSTATE Position

Definition at line 1533 of file core_cm85.h.

◆ PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk [1/2]

#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/)

PWRMODCTL DPDLPSTATE: DLPSTATE Mask

Definition at line 1557 of file core_cm55.h.

◆ PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk [2/2]

#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/)

PWRMODCTL DPDLPSTATE: DLPSTATE Mask

Definition at line 1544 of file core_cm85.h.

◆ PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos [1/2]

#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos   0U

PWRMODCTL DPDLPSTATE: DLPSTATE Position

Definition at line 1556 of file core_cm55.h.

◆ PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos [2/2]

#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos   0U

PWRMODCTL DPDLPSTATE: DLPSTATE Position

Definition at line 1543 of file core_cm85.h.

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