Trace Port Interface (TPI)

Type definitions for the Trace Port Interface (TPI) More...

Topics
	Floating Point Unit (FPU)
	Type definitions for the Floating Point Unit (FPU)

Classes
struct	TPI_Type
	Structure type to access the Trace Port Interface Register (TPI). More...

Macros
#define	TPI_ACPR_SWOSCALER_Pos   0U
#define	TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
#define	TPI_PSCR_PSCount_Pos   0U
#define	TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
#define	TPI_LSR_nTT_Pos   1U
#define	TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)
#define	TPI_LSR_SLK_Pos   1U
#define	TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)
#define	TPI_LSR_SLI_Pos   0U
#define	TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)
#define	CoreDebug_DEMCR_DWTENA_Pos   24U
#define	CoreDebug_DEMCR_DWTENA_Msk   (1UL << CoreDebug_DEMCR_DWTENA_Pos)
#define	CoreDebug_DEMCR_DWTENA_Pos   24U
#define	CoreDebug_DEMCR_DWTENA_Msk   (1UL << CoreDebug_DEMCR_DWTENA_Pos)
#define	_BIT_SHIFT(IRQn)
#define	_SHP_IDX(IRQn)
#define	_IP_IDX(IRQn)
#define	__NVIC_SetPriorityGrouping(X)
#define	__NVIC_GetPriorityGrouping()
#define	_BIT_SHIFT(IRQn)
#define	_SHP_IDX(IRQn)
#define	_IP_IDX(IRQn)
#define	__NVIC_SetPriorityGrouping(X)
#define	__NVIC_GetPriorityGrouping()
#define	_BIT_SHIFT(IRQn)
#define	_SHP_IDX(IRQn)
#define	_IP_IDX(IRQn)
#define	__NVIC_SetPriorityGrouping(X)
#define	__NVIC_GetPriorityGrouping()
#define	_BIT_SHIFT(IRQn)
#define	_SHP_IDX(IRQn)
#define	_IP_IDX(IRQn)
#define	__NVIC_SetPriorityGrouping(X)
#define	__NVIC_GetPriorityGrouping()
#define	_BIT_SHIFT(IRQn)
#define	_SHP_IDX(IRQn)
#define	_IP_IDX(IRQn)
#define	_BIT_SHIFT(IRQn)
#define	_SHP_IDX(IRQn)
#define	_IP_IDX(IRQn)
#define	__NVIC_SetPriorityGrouping(X)
#define	__NVIC_GetPriorityGrouping()
#define	_BIT_SHIFT(IRQn)
#define	_SHP_IDX(IRQn)
#define	_IP_IDX(IRQn)
#define	__NVIC_SetPriorityGrouping(X)
#define	__NVIC_GetPriorityGrouping()
#define	_BIT_SHIFT(IRQn)
#define	_SHP_IDX(IRQn)
#define	_IP_IDX(IRQn)
#define	__NVIC_SetPriorityGrouping(X)
#define	__NVIC_GetPriorityGrouping()
#define	TPI_ACPR_SWOSCALER_Pos   0U
#define	TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
#define	TPI_PSCR_PSCount_Pos   0U
#define	TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
#define	TPI_LSR_nTT_Pos   1U
#define	TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)
#define	TPI_LSR_SLK_Pos   1U
#define	TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)
#define	TPI_LSR_SLI_Pos   0U
#define	TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)
#define	TPI_ACPR_SWOSCALER_Pos   0U
#define	TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
#define	TPI_PSCR_PSCount_Pos   0U
#define	TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
#define	TPI_LSR_nTT_Pos   1U
#define	TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)
#define	TPI_LSR_SLK_Pos   1U
#define	TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)
#define	TPI_LSR_SLI_Pos   0U
#define	TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)
#define	TPI_ACPR_SWOSCALER_Pos   0U
#define	TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
#define	TPI_PSCR_PSCount_Pos   0U
#define	TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
#define	TPI_LSR_nTT_Pos   1U
#define	TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)
#define	TPI_LSR_SLK_Pos   1U
#define	TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)
#define	TPI_LSR_SLI_Pos   0U
#define	TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)
#define	TPI_ACPR_SWOSCALER_Pos   0U
#define	TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
#define	TPI_PSCR_PSCount_Pos   0U
#define	TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
#define	TPI_LSR_nTT_Pos   1U
#define	TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)
#define	TPI_LSR_SLK_Pos   1U
#define	TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)
#define	TPI_LSR_SLI_Pos   0U
#define	TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)
#define	TPI_ACPR_SWOSCALER_Pos   0U
#define	TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
#define	TPI_PSCR_PSCount_Pos   0U
#define	TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
#define	TPI_LSR_nTT_Pos   1U
#define	TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)
#define	TPI_LSR_SLK_Pos   1U
#define	TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)
#define	TPI_LSR_SLI_Pos   0U
#define	TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)
#define	TPI_ACPR_SWOSCALER_Pos   0U
#define	TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
#define	TPI_PSCR_PSCount_Pos   0U
#define	TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
#define	TPI_LSR_nTT_Pos   1U
#define	TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)
#define	TPI_LSR_SLK_Pos   1U
#define	TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)
#define	TPI_LSR_SLI_Pos   0U
#define	TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)
#define	TPI_ACPR_SWOSCALER_Pos   0U
#define	TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
#define	TPI_PSCR_PSCount_Pos   0U
#define	TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
#define	TPI_LSR_nTT_Pos   1U
#define	TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)
#define	TPI_LSR_SLK_Pos   1U
#define	TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)
#define	TPI_LSR_SLI_Pos   0U
#define	TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)
#define	CoreDebug_DEMCR_DWTENA_Pos   24U
#define	CoreDebug_DEMCR_DWTENA_Msk   (1UL << CoreDebug_DEMCR_DWTENA_Pos)
#define	_BIT_SHIFT(IRQn)
#define	_SHP_IDX(IRQn)
#define	_IP_IDX(IRQn)
#define	__NVIC_SetPriorityGrouping(X)
#define	__NVIC_GetPriorityGrouping()
	Get Priority Grouping.
#define	TPI_SPPR_TXMODE_Pos   0U
#define	TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define	TPI_FFSR_FtNonStop_Pos   3U
#define	TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define	TPI_FFSR_TCPresent_Pos   2U
#define	TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
#define	TPI_FFSR_FtStopped_Pos   1U
#define	TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
#define	TPI_FFSR_FlInProg_Pos   0U
#define	TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define	TPI_FFCR_TrigIn_Pos   8U
#define	TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
#define	TPI_DEVID_NRZVALID_Pos   11U
#define	TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define	TPI_DEVID_MANCVALID_Pos   10U
#define	TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define	TPI_DEVID_PTINVALID_Pos   9U
#define	TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define	TPI_DEVTYPE_SubType_Pos   4U
#define	TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define	TPI_DEVTYPE_MajorType_Pos   0U
#define	TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define	TPI_SPPR_TXMODE_Pos   0U
#define	TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define	TPI_FFSR_FtNonStop_Pos   3U
#define	TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define	TPI_FFSR_TCPresent_Pos   2U
#define	TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
#define	TPI_FFSR_FtStopped_Pos   1U
#define	TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
#define	TPI_FFSR_FlInProg_Pos   0U
#define	TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define	TPI_FFCR_TrigIn_Pos   8U
#define	TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
#define	TPI_FFCR_EnFCont_Pos   1U
#define	TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
#define	TPI_DEVID_NRZVALID_Pos   11U
#define	TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define	TPI_DEVID_MANCVALID_Pos   10U
#define	TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define	TPI_DEVID_PTINVALID_Pos   9U
#define	TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define	TPI_DEVTYPE_SubType_Pos   4U
#define	TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define	TPI_DEVTYPE_MajorType_Pos   0U
#define	TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define	TPI_SPPR_TXMODE_Pos   0U
#define	TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define	TPI_FFSR_FtNonStop_Pos   3U
#define	TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define	TPI_FFSR_TCPresent_Pos   2U
#define	TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
#define	TPI_FFSR_FtStopped_Pos   1U
#define	TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
#define	TPI_FFSR_FlInProg_Pos   0U
#define	TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define	TPI_FFCR_TrigIn_Pos   8U
#define	TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
#define	TPI_FFCR_EnFCont_Pos   1U
#define	TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
#define	TPI_DEVID_NRZVALID_Pos   11U
#define	TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define	TPI_DEVID_MANCVALID_Pos   10U
#define	TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define	TPI_DEVID_PTINVALID_Pos   9U
#define	TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define	TPI_DEVTYPE_SubType_Pos   4U
#define	TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define	TPI_DEVTYPE_MajorType_Pos   0U
#define	TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define	TPI_ACPR_PRESCALER_Pos   0U
#define	TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
#define	TPI_SPPR_TXMODE_Pos   0U
#define	TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define	TPI_FFSR_FtNonStop_Pos   3U
#define	TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define	TPI_FFSR_TCPresent_Pos   2U
#define	TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
#define	TPI_FFSR_FtStopped_Pos   1U
#define	TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
#define	TPI_FFSR_FlInProg_Pos   0U
#define	TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define	TPI_FFCR_TrigIn_Pos   8U
#define	TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
#define	TPI_FFCR_EnFCont_Pos   1U
#define	TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
#define	TPI_TRIGGER_TRIGGER_Pos   0U
#define	TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
#define	TPI_ITCTRL_Mode_Pos   0U
#define	TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
#define	TPI_DEVID_NRZVALID_Pos   11U
#define	TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define	TPI_DEVID_MANCVALID_Pos   10U
#define	TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define	TPI_DEVID_PTINVALID_Pos   9U
#define	TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define	TPI_DEVID_NrTraceInput_Pos   0U
#define	TPI_DEVID_NrTraceInput_Msk   (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
#define	TPI_DEVTYPE_SubType_Pos   4U
#define	TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define	TPI_DEVTYPE_MajorType_Pos   0U
#define	TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define	TPI_ACPR_PRESCALER_Pos   0U
#define	TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
#define	TPI_SPPR_TXMODE_Pos   0U
#define	TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define	TPI_FFSR_FtNonStop_Pos   3U
#define	TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define	TPI_FFSR_TCPresent_Pos   2U
#define	TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
#define	TPI_FFSR_FtStopped_Pos   1U
#define	TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
#define	TPI_FFSR_FlInProg_Pos   0U
#define	TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define	TPI_FFCR_TrigIn_Pos   8U
#define	TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
#define	TPI_FFCR_EnFCont_Pos   1U
#define	TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
#define	TPI_TRIGGER_TRIGGER_Pos   0U
#define	TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
#define	TPI_FIFO0_ITM_ATVALID_Pos   29U
#define	TPI_FIFO0_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)
#define	TPI_FIFO0_ITM_bytecount_Pos   27U
#define	TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
#define	TPI_FIFO0_ETM_ATVALID_Pos   26U
#define	TPI_FIFO0_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)
#define	TPI_FIFO0_ETM_bytecount_Pos   24U
#define	TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
#define	TPI_FIFO0_ETM2_Pos   16U
#define	TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)
#define	TPI_FIFO0_ETM1_Pos   8U
#define	TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)
#define	TPI_FIFO0_ETM0_Pos   0U
#define	TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
#define	TPI_ITATBCTR2_ATREADY2_Pos   0U
#define	TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)
#define	TPI_ITATBCTR2_ATREADY1_Pos   0U
#define	TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)
#define	TPI_FIFO1_ITM_ATVALID_Pos   29U
#define	TPI_FIFO1_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)
#define	TPI_FIFO1_ITM_bytecount_Pos   27U
#define	TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
#define	TPI_FIFO1_ETM_ATVALID_Pos   26U
#define	TPI_FIFO1_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)
#define	TPI_FIFO1_ETM_bytecount_Pos   24U
#define	TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
#define	TPI_FIFO1_ITM2_Pos   16U
#define	TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)
#define	TPI_FIFO1_ITM1_Pos   8U
#define	TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)
#define	TPI_FIFO1_ITM0_Pos   0U
#define	TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
#define	TPI_ITATBCTR0_ATREADY2_Pos   0U
#define	TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)
#define	TPI_ITATBCTR0_ATREADY1_Pos   0U
#define	TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)
#define	TPI_ITCTRL_Mode_Pos   0U
#define	TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
#define	TPI_DEVID_NRZVALID_Pos   11U
#define	TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define	TPI_DEVID_MANCVALID_Pos   10U
#define	TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define	TPI_DEVID_PTINVALID_Pos   9U
#define	TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define	TPI_DEVID_MinBufSz_Pos   6U
#define	TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)
#define	TPI_DEVID_AsynClkIn_Pos   5U
#define	TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)
#define	TPI_DEVID_NrTraceInput_Pos   0U
#define	TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
#define	TPI_DEVTYPE_SubType_Pos   4U
#define	TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define	TPI_DEVTYPE_MajorType_Pos   0U
#define	TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define	TPI_ACPR_PRESCALER_Pos   0U
#define	TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
#define	TPI_SPPR_TXMODE_Pos   0U
#define	TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define	TPI_FFSR_FtNonStop_Pos   3U
#define	TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define	TPI_FFSR_TCPresent_Pos   2U
#define	TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
#define	TPI_FFSR_FtStopped_Pos   1U
#define	TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
#define	TPI_FFSR_FlInProg_Pos   0U
#define	TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define	TPI_FFCR_TrigIn_Pos   8U
#define	TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
#define	TPI_FFCR_EnFCont_Pos   1U
#define	TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
#define	TPI_TRIGGER_TRIGGER_Pos   0U
#define	TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
#define	TPI_ITCTRL_Mode_Pos   0U
#define	TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
#define	TPI_DEVID_NRZVALID_Pos   11U
#define	TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define	TPI_DEVID_MANCVALID_Pos   10U
#define	TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define	TPI_DEVID_PTINVALID_Pos   9U
#define	TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define	TPI_DEVID_NrTraceInput_Pos   0U
#define	TPI_DEVID_NrTraceInput_Msk   (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
#define	TPI_DEVTYPE_SubType_Pos   4U
#define	TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define	TPI_DEVTYPE_MajorType_Pos   0U
#define	TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define	TPI_ACPR_PRESCALER_Pos   0U
#define	TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
#define	TPI_SPPR_TXMODE_Pos   0U
#define	TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define	TPI_FFSR_FtNonStop_Pos   3U
#define	TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define	TPI_FFSR_TCPresent_Pos   2U
#define	TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
#define	TPI_FFSR_FtStopped_Pos   1U
#define	TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
#define	TPI_FFSR_FlInProg_Pos   0U
#define	TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define	TPI_FFCR_TrigIn_Pos   8U
#define	TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
#define	TPI_FFCR_EnFCont_Pos   1U
#define	TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
#define	TPI_TRIGGER_TRIGGER_Pos   0U
#define	TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
#define	TPI_ITCTRL_Mode_Pos   0U
#define	TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
#define	TPI_DEVID_NRZVALID_Pos   11U
#define	TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define	TPI_DEVID_MANCVALID_Pos   10U
#define	TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define	TPI_DEVID_PTINVALID_Pos   9U
#define	TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define	TPI_DEVID_NrTraceInput_Pos   0U
#define	TPI_DEVID_NrTraceInput_Msk   (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
#define	TPI_DEVTYPE_SubType_Pos   4U
#define	TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define	TPI_DEVTYPE_MajorType_Pos   0U
#define	TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define	TPI_ACPR_PRESCALER_Pos   0U
#define	TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
#define	TPI_SPPR_TXMODE_Pos   0U
#define	TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define	TPI_FFSR_FtNonStop_Pos   3U
#define	TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define	TPI_FFSR_TCPresent_Pos   2U
#define	TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
#define	TPI_FFSR_FtStopped_Pos   1U
#define	TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
#define	TPI_FFSR_FlInProg_Pos   0U
#define	TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define	TPI_FFCR_TrigIn_Pos   8U
#define	TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
#define	TPI_FFCR_EnFCont_Pos   1U
#define	TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
#define	TPI_TRIGGER_TRIGGER_Pos   0U
#define	TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
#define	TPI_FIFO0_ITM_ATVALID_Pos   29U
#define	TPI_FIFO0_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)
#define	TPI_FIFO0_ITM_bytecount_Pos   27U
#define	TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
#define	TPI_FIFO0_ETM_ATVALID_Pos   26U
#define	TPI_FIFO0_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)
#define	TPI_FIFO0_ETM_bytecount_Pos   24U
#define	TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
#define	TPI_FIFO0_ETM2_Pos   16U
#define	TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)
#define	TPI_FIFO0_ETM1_Pos   8U
#define	TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)
#define	TPI_FIFO0_ETM0_Pos   0U
#define	TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
#define	TPI_ITATBCTR2_ATREADY2_Pos   0U
#define	TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)
#define	TPI_ITATBCTR2_ATREADY1_Pos   0U
#define	TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)
#define	TPI_FIFO1_ITM_ATVALID_Pos   29U
#define	TPI_FIFO1_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)
#define	TPI_FIFO1_ITM_bytecount_Pos   27U
#define	TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
#define	TPI_FIFO1_ETM_ATVALID_Pos   26U
#define	TPI_FIFO1_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)
#define	TPI_FIFO1_ETM_bytecount_Pos   24U
#define	TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
#define	TPI_FIFO1_ITM2_Pos   16U
#define	TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)
#define	TPI_FIFO1_ITM1_Pos   8U
#define	TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)
#define	TPI_FIFO1_ITM0_Pos   0U
#define	TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
#define	TPI_ITATBCTR0_ATREADY2_Pos   0U
#define	TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)
#define	TPI_ITATBCTR0_ATREADY1_Pos   0U
#define	TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)
#define	TPI_ITCTRL_Mode_Pos   0U
#define	TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
#define	TPI_DEVID_NRZVALID_Pos   11U
#define	TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define	TPI_DEVID_MANCVALID_Pos   10U
#define	TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define	TPI_DEVID_PTINVALID_Pos   9U
#define	TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define	TPI_DEVID_MinBufSz_Pos   6U
#define	TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)
#define	TPI_DEVID_AsynClkIn_Pos   5U
#define	TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)
#define	TPI_DEVID_NrTraceInput_Pos   0U
#define	TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
#define	TPI_DEVTYPE_SubType_Pos   4U
#define	TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define	TPI_DEVTYPE_MajorType_Pos   0U
#define	TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define	TPI_SPPR_TXMODE_Pos   0U
#define	TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define	TPI_FFSR_FtNonStop_Pos   3U
#define	TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define	TPI_FFSR_TCPresent_Pos   2U
#define	TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
#define	TPI_FFSR_FtStopped_Pos   1U
#define	TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
#define	TPI_FFSR_FlInProg_Pos   0U
#define	TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define	TPI_FFCR_TrigIn_Pos   8U
#define	TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
#define	TPI_DEVID_NRZVALID_Pos   11U
#define	TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define	TPI_DEVID_MANCVALID_Pos   10U
#define	TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define	TPI_DEVID_PTINVALID_Pos   9U
#define	TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define	TPI_DEVTYPE_SubType_Pos   4U
#define	TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define	TPI_DEVTYPE_MajorType_Pos   0U
#define	TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define	TPI_ACPR_PRESCALER_Pos   0U
#define	TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
#define	TPI_SPPR_TXMODE_Pos   0U
#define	TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define	TPI_FFSR_FtNonStop_Pos   3U
#define	TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define	TPI_FFSR_TCPresent_Pos   2U
#define	TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
#define	TPI_FFSR_FtStopped_Pos   1U
#define	TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
#define	TPI_FFSR_FlInProg_Pos   0U
#define	TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define	TPI_FFCR_TrigIn_Pos   8U
#define	TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
#define	TPI_FFCR_EnFCont_Pos   1U
#define	TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
#define	TPI_TRIGGER_TRIGGER_Pos   0U
#define	TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
#define	TPI_FIFO0_ITM_ATVALID_Pos   29U
#define	TPI_FIFO0_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)
#define	TPI_FIFO0_ITM_bytecount_Pos   27U
#define	TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
#define	TPI_FIFO0_ETM_ATVALID_Pos   26U
#define	TPI_FIFO0_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)
#define	TPI_FIFO0_ETM_bytecount_Pos   24U
#define	TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
#define	TPI_FIFO0_ETM2_Pos   16U
#define	TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)
#define	TPI_FIFO0_ETM1_Pos   8U
#define	TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)
#define	TPI_FIFO0_ETM0_Pos   0U
#define	TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
#define	TPI_ITATBCTR2_ATREADY2_Pos   0U
#define	TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)
#define	TPI_ITATBCTR2_ATREADY1_Pos   0U
#define	TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)
#define	TPI_FIFO1_ITM_ATVALID_Pos   29U
#define	TPI_FIFO1_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)
#define	TPI_FIFO1_ITM_bytecount_Pos   27U
#define	TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
#define	TPI_FIFO1_ETM_ATVALID_Pos   26U
#define	TPI_FIFO1_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)
#define	TPI_FIFO1_ETM_bytecount_Pos   24U
#define	TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
#define	TPI_FIFO1_ITM2_Pos   16U
#define	TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)
#define	TPI_FIFO1_ITM1_Pos   8U
#define	TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)
#define	TPI_FIFO1_ITM0_Pos   0U
#define	TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
#define	TPI_ITATBCTR0_ATREADY2_Pos   0U
#define	TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)
#define	TPI_ITATBCTR0_ATREADY1_Pos   0U
#define	TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)
#define	TPI_ITCTRL_Mode_Pos   0U
#define	TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
#define	TPI_DEVID_NRZVALID_Pos   11U
#define	TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define	TPI_DEVID_MANCVALID_Pos   10U
#define	TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define	TPI_DEVID_PTINVALID_Pos   9U
#define	TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define	TPI_DEVID_MinBufSz_Pos   6U
#define	TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)
#define	TPI_DEVID_AsynClkIn_Pos   5U
#define	TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)
#define	TPI_DEVID_NrTraceInput_Pos   0U
#define	TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
#define	TPI_DEVTYPE_SubType_Pos   4U
#define	TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define	TPI_DEVTYPE_MajorType_Pos   0U
#define	TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define	TPI_SPPR_TXMODE_Pos   0U
#define	TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define	TPI_FFSR_FtNonStop_Pos   3U
#define	TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define	TPI_FFSR_TCPresent_Pos   2U
#define	TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
#define	TPI_FFSR_FtStopped_Pos   1U
#define	TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
#define	TPI_FFSR_FlInProg_Pos   0U
#define	TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define	TPI_FFCR_TrigIn_Pos   8U
#define	TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
#define	TPI_DEVID_NRZVALID_Pos   11U
#define	TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define	TPI_DEVID_MANCVALID_Pos   10U
#define	TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define	TPI_DEVID_PTINVALID_Pos   9U
#define	TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define	TPI_DEVTYPE_SubType_Pos   4U
#define	TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define	TPI_DEVTYPE_MajorType_Pos   0U
#define	TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define	TPI_ACPR_PRESCALER_Pos   0U
#define	TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
#define	TPI_SPPR_TXMODE_Pos   0U
#define	TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define	TPI_FFSR_FtNonStop_Pos   3U
#define	TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define	TPI_FFSR_TCPresent_Pos   2U
#define	TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
#define	TPI_FFSR_FtStopped_Pos   1U
#define	TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
#define	TPI_FFSR_FlInProg_Pos   0U
#define	TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define	TPI_FFCR_TrigIn_Pos   8U
#define	TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
#define	TPI_FFCR_EnFCont_Pos   1U
#define	TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
#define	TPI_TRIGGER_TRIGGER_Pos   0U
#define	TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
#define	TPI_FIFO0_ITM_ATVALID_Pos   29U
#define	TPI_FIFO0_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)
#define	TPI_FIFO0_ITM_bytecount_Pos   27U
#define	TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
#define	TPI_FIFO0_ETM_ATVALID_Pos   26U
#define	TPI_FIFO0_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)
#define	TPI_FIFO0_ETM_bytecount_Pos   24U
#define	TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
#define	TPI_FIFO0_ETM2_Pos   16U
#define	TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)
#define	TPI_FIFO0_ETM1_Pos   8U
#define	TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)
#define	TPI_FIFO0_ETM0_Pos   0U
#define	TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
#define	TPI_ITATBCTR2_ATREADY2_Pos   0U
#define	TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)
#define	TPI_ITATBCTR2_ATREADY1_Pos   0U
#define	TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)
#define	TPI_FIFO1_ITM_ATVALID_Pos   29U
#define	TPI_FIFO1_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)
#define	TPI_FIFO1_ITM_bytecount_Pos   27U
#define	TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
#define	TPI_FIFO1_ETM_ATVALID_Pos   26U
#define	TPI_FIFO1_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)
#define	TPI_FIFO1_ETM_bytecount_Pos   24U
#define	TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
#define	TPI_FIFO1_ITM2_Pos   16U
#define	TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)
#define	TPI_FIFO1_ITM1_Pos   8U
#define	TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)
#define	TPI_FIFO1_ITM0_Pos   0U
#define	TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
#define	TPI_ITATBCTR0_ATREADY2_Pos   0U
#define	TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)
#define	TPI_ITATBCTR0_ATREADY1_Pos   0U
#define	TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)
#define	TPI_ITCTRL_Mode_Pos   0U
#define	TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
#define	TPI_DEVID_NRZVALID_Pos   11U
#define	TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define	TPI_DEVID_MANCVALID_Pos   10U
#define	TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define	TPI_DEVID_PTINVALID_Pos   9U
#define	TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define	TPI_DEVID_MinBufSz_Pos   6U
#define	TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)
#define	TPI_DEVID_AsynClkIn_Pos   5U
#define	TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)
#define	TPI_DEVID_NrTraceInput_Pos   0U
#define	TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
#define	TPI_DEVTYPE_SubType_Pos   4U
#define	TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define	TPI_DEVTYPE_MajorType_Pos   0U
#define	TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define	TPI_ACPR_PRESCALER_Pos   0U
#define	TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
#define	TPI_SPPR_TXMODE_Pos   0U
#define	TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define	TPI_FFSR_FtNonStop_Pos   3U
#define	TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define	TPI_FFSR_TCPresent_Pos   2U
#define	TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
#define	TPI_FFSR_FtStopped_Pos   1U
#define	TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
#define	TPI_FFSR_FlInProg_Pos   0U
#define	TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define	TPI_FFCR_TrigIn_Pos   8U
#define	TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
#define	TPI_FFCR_EnFCont_Pos   1U
#define	TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
#define	TPI_TRIGGER_TRIGGER_Pos   0U
#define	TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
#define	TPI_ITCTRL_Mode_Pos   0U
#define	TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
#define	TPI_DEVID_NRZVALID_Pos   11U
#define	TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define	TPI_DEVID_MANCVALID_Pos   10U
#define	TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define	TPI_DEVID_PTINVALID_Pos   9U
#define	TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define	TPI_DEVID_NrTraceInput_Pos   0U
#define	TPI_DEVID_NrTraceInput_Msk   (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
#define	TPI_DEVTYPE_SubType_Pos   4U
#define	TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define	TPI_DEVTYPE_MajorType_Pos   0U
#define	TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define	TPI_SPPR_TXMODE_Pos   0U
#define	TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define	TPI_FFSR_FtNonStop_Pos   3U
#define	TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define	TPI_FFSR_TCPresent_Pos   2U
#define	TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
#define	TPI_FFSR_FtStopped_Pos   1U
#define	TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
#define	TPI_FFSR_FlInProg_Pos   0U
#define	TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define	TPI_FFCR_TrigIn_Pos   8U
#define	TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
#define	TPI_DEVID_NRZVALID_Pos   11U
#define	TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define	TPI_DEVID_MANCVALID_Pos   10U
#define	TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define	TPI_DEVID_PTINVALID_Pos   9U
#define	TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define	TPI_DEVTYPE_SubType_Pos   4U
#define	TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define	TPI_DEVTYPE_MajorType_Pos   0U
#define	TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define	TPI_SPPR_TXMODE_Pos   0U
#define	TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define	TPI_FFSR_FtNonStop_Pos   3U
#define	TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define	TPI_FFSR_TCPresent_Pos   2U
#define	TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
#define	TPI_FFSR_FtStopped_Pos   1U
#define	TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
#define	TPI_FFSR_FlInProg_Pos   0U
#define	TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define	TPI_FFCR_TrigIn_Pos   8U
#define	TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
#define	TPI_FFCR_EnFCont_Pos   1U
#define	TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
#define	TPI_DEVID_NRZVALID_Pos   11U
#define	TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define	TPI_DEVID_MANCVALID_Pos   10U
#define	TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define	TPI_DEVID_PTINVALID_Pos   9U
#define	TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define	TPI_DEVTYPE_SubType_Pos   4U
#define	TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define	TPI_DEVTYPE_MajorType_Pos   0U
#define	TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define	TPI_SPPR_TXMODE_Pos   0U
#define	TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define	TPI_FFSR_FtNonStop_Pos   3U
#define	TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define	TPI_FFSR_TCPresent_Pos   2U
#define	TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
#define	TPI_FFSR_FtStopped_Pos   1U
#define	TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
#define	TPI_FFSR_FlInProg_Pos   0U
#define	TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define	TPI_FFCR_TrigIn_Pos   8U
#define	TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
#define	TPI_FFCR_EnFCont_Pos   1U
#define	TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
#define	TPI_DEVID_NRZVALID_Pos   11U
#define	TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define	TPI_DEVID_MANCVALID_Pos   10U
#define	TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define	TPI_DEVID_PTINVALID_Pos   9U
#define	TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define	TPI_DEVTYPE_SubType_Pos   4U
#define	TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define	TPI_DEVTYPE_MajorType_Pos   0U
#define	TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define	TPI_ACPR_PRESCALER_Pos   0U
#define	TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
#define	TPI_SPPR_TXMODE_Pos   0U
#define	TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define	TPI_FFSR_FtNonStop_Pos   3U
#define	TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define	TPI_FFSR_TCPresent_Pos   2U
#define	TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
#define	TPI_FFSR_FtStopped_Pos   1U
#define	TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
#define	TPI_FFSR_FlInProg_Pos   0U
#define	TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define	TPI_FFCR_TrigIn_Pos   8U
#define	TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
#define	TPI_FFCR_EnFCont_Pos   1U
#define	TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
#define	TPI_TRIGGER_TRIGGER_Pos   0U
#define	TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
#define	TPI_ITCTRL_Mode_Pos   0U
#define	TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
#define	TPI_DEVID_NRZVALID_Pos   11U
#define	TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define	TPI_DEVID_MANCVALID_Pos   10U
#define	TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define	TPI_DEVID_PTINVALID_Pos   9U
#define	TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define	TPI_DEVID_NrTraceInput_Pos   0U
#define	TPI_DEVID_NrTraceInput_Msk   (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
#define	TPI_DEVTYPE_SubType_Pos   4U
#define	TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define	TPI_DEVTYPE_MajorType_Pos   0U
#define	TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define	TPI_ACPR_PRESCALER_Pos   0U
#define	TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
#define	TPI_SPPR_TXMODE_Pos   0U
#define	TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
#define	TPI_FFSR_FtNonStop_Pos   3U
#define	TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define	TPI_FFSR_TCPresent_Pos   2U
#define	TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
#define	TPI_FFSR_FtStopped_Pos   1U
#define	TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
#define	TPI_FFSR_FlInProg_Pos   0U
#define	TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
#define	TPI_FFCR_TrigIn_Pos   8U
#define	TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
#define	TPI_FFCR_EnFCont_Pos   1U
#define	TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
#define	TPI_TRIGGER_TRIGGER_Pos   0U
#define	TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
#define	TPI_FIFO0_ITM_ATVALID_Pos   29U
#define	TPI_FIFO0_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)
#define	TPI_FIFO0_ITM_bytecount_Pos   27U
#define	TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
#define	TPI_FIFO0_ETM_ATVALID_Pos   26U
#define	TPI_FIFO0_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)
#define	TPI_FIFO0_ETM_bytecount_Pos   24U
#define	TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
#define	TPI_FIFO0_ETM2_Pos   16U
#define	TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)
#define	TPI_FIFO0_ETM1_Pos   8U
#define	TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)
#define	TPI_FIFO0_ETM0_Pos   0U
#define	TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
#define	TPI_ITATBCTR2_ATREADY2_Pos   0U
#define	TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)
#define	TPI_ITATBCTR2_ATREADY1_Pos   0U
#define	TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)
#define	TPI_FIFO1_ITM_ATVALID_Pos   29U
#define	TPI_FIFO1_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)
#define	TPI_FIFO1_ITM_bytecount_Pos   27U
#define	TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
#define	TPI_FIFO1_ETM_ATVALID_Pos   26U
#define	TPI_FIFO1_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)
#define	TPI_FIFO1_ETM_bytecount_Pos   24U
#define	TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
#define	TPI_FIFO1_ITM2_Pos   16U
#define	TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)
#define	TPI_FIFO1_ITM1_Pos   8U
#define	TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)
#define	TPI_FIFO1_ITM0_Pos   0U
#define	TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
#define	TPI_ITATBCTR0_ATREADY2_Pos   0U
#define	TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)
#define	TPI_ITATBCTR0_ATREADY1_Pos   0U
#define	TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)
#define	TPI_ITCTRL_Mode_Pos   0U
#define	TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
#define	TPI_DEVID_NRZVALID_Pos   11U
#define	TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define	TPI_DEVID_MANCVALID_Pos   10U
#define	TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define	TPI_DEVID_PTINVALID_Pos   9U
#define	TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define	TPI_DEVID_MinBufSz_Pos   6U
#define	TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)
#define	TPI_DEVID_AsynClkIn_Pos   5U
#define	TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)
#define	TPI_DEVID_NrTraceInput_Pos   0U
#define	TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
#define	TPI_DEVTYPE_SubType_Pos   4U
#define	TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
#define	TPI_DEVTYPE_MajorType_Pos   0U
#define	TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define	TPI_FFCR_FOnMan_Pos   6U
#define	TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)
#define	TPI_DEVID_FIFOSZ_Pos   6U
#define	TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)
#define	TPI_FFCR_FOnMan_Pos   6U
#define	TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)
#define	TPI_DEVID_FIFOSZ_Pos   6U
#define	TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)
#define	TPI_FFCR_FOnMan_Pos   6U
#define	TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)
#define	TPI_DEVID_FIFOSZ_Pos   6U
#define	TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)
#define	TPI_FFCR_FOnMan_Pos   6U
#define	TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)
#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos   29U
#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)
#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos   27U
#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)
#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos   26U
#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)
#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos   24U
#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)
#define	TPI_ITFTTD0_ATB_IF1_data2_Pos   16U
#define	TPI_ITFTTD0_ATB_IF1_data2_Msk   (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
#define	TPI_ITFTTD0_ATB_IF1_data1_Pos   8U
#define	TPI_ITFTTD0_ATB_IF1_data1_Msk   (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
#define	TPI_ITFTTD0_ATB_IF1_data0_Pos   0U
#define	TPI_ITFTTD0_ATB_IF1_data0_Msk   (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/)
#define	TPI_ITATBCTR2_AFVALID2S_Pos   1U
#define	TPI_ITATBCTR2_AFVALID2S_Msk   (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)
#define	TPI_ITATBCTR2_AFVALID1S_Pos   1U
#define	TPI_ITATBCTR2_AFVALID1S_Msk   (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)
#define	TPI_ITATBCTR2_ATREADY2S_Pos   0U
#define	TPI_ITATBCTR2_ATREADY2S_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)
#define	TPI_ITATBCTR2_ATREADY1S_Pos   0U
#define	TPI_ITATBCTR2_ATREADY1S_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)
#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos   29U
#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)
#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos   27U
#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)
#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos   26U
#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)
#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos   24U
#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)
#define	TPI_ITFTTD1_ATB_IF2_data2_Pos   16U
#define	TPI_ITFTTD1_ATB_IF2_data2_Msk   (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
#define	TPI_ITFTTD1_ATB_IF2_data1_Pos   8U
#define	TPI_ITFTTD1_ATB_IF2_data1_Msk   (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
#define	TPI_ITFTTD1_ATB_IF2_data0_Pos   0U
#define	TPI_ITFTTD1_ATB_IF2_data0_Msk   (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/)
#define	TPI_ITATBCTR0_AFVALID2S_Pos   1U
#define	TPI_ITATBCTR0_AFVALID2S_Msk   (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)
#define	TPI_ITATBCTR0_AFVALID1S_Pos   1U
#define	TPI_ITATBCTR0_AFVALID1S_Msk   (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)
#define	TPI_ITATBCTR0_ATREADY2S_Pos   0U
#define	TPI_ITATBCTR0_ATREADY2S_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)
#define	TPI_ITATBCTR0_ATREADY1S_Pos   0U
#define	TPI_ITATBCTR0_ATREADY1S_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)
#define	TPI_DEVID_FIFOSZ_Pos   6U
#define	TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)
#define	TPI_FFCR_FOnMan_Pos   6U
#define	TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)
#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos   29U
#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)
#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos   27U
#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)
#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos   26U
#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)
#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos   24U
#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)
#define	TPI_ITFTTD0_ATB_IF1_data2_Pos   16U
#define	TPI_ITFTTD0_ATB_IF1_data2_Msk   (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
#define	TPI_ITFTTD0_ATB_IF1_data1_Pos   8U
#define	TPI_ITFTTD0_ATB_IF1_data1_Msk   (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
#define	TPI_ITFTTD0_ATB_IF1_data0_Pos   0U
#define	TPI_ITFTTD0_ATB_IF1_data0_Msk   (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/)
#define	TPI_ITATBCTR2_AFVALID2S_Pos   1U
#define	TPI_ITATBCTR2_AFVALID2S_Msk   (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)
#define	TPI_ITATBCTR2_AFVALID1S_Pos   1U
#define	TPI_ITATBCTR2_AFVALID1S_Msk   (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)
#define	TPI_ITATBCTR2_ATREADY2S_Pos   0U
#define	TPI_ITATBCTR2_ATREADY2S_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)
#define	TPI_ITATBCTR2_ATREADY1S_Pos   0U
#define	TPI_ITATBCTR2_ATREADY1S_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)
#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos   29U
#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)
#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos   27U
#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)
#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos   26U
#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)
#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos   24U
#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)
#define	TPI_ITFTTD1_ATB_IF2_data2_Pos   16U
#define	TPI_ITFTTD1_ATB_IF2_data2_Msk   (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
#define	TPI_ITFTTD1_ATB_IF2_data1_Pos   8U
#define	TPI_ITFTTD1_ATB_IF2_data1_Msk   (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
#define	TPI_ITFTTD1_ATB_IF2_data0_Pos   0U
#define	TPI_ITFTTD1_ATB_IF2_data0_Msk   (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/)
#define	TPI_ITATBCTR0_AFVALID2S_Pos   1U
#define	TPI_ITATBCTR0_AFVALID2S_Msk   (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)
#define	TPI_ITATBCTR0_AFVALID1S_Pos   1U
#define	TPI_ITATBCTR0_AFVALID1S_Msk   (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)
#define	TPI_ITATBCTR0_ATREADY2S_Pos   0U
#define	TPI_ITATBCTR0_ATREADY2S_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)
#define	TPI_ITATBCTR0_ATREADY1S_Pos   0U
#define	TPI_ITATBCTR0_ATREADY1S_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)
#define	TPI_DEVID_FIFOSZ_Pos   6U
#define	TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)
#define	TPI_FFCR_FOnMan_Pos   6U
#define	TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)
#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos   29U
#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)
#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos   27U
#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)
#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos   26U
#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)
#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos   24U
#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)
#define	TPI_ITFTTD0_ATB_IF1_data2_Pos   16U
#define	TPI_ITFTTD0_ATB_IF1_data2_Msk   (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
#define	TPI_ITFTTD0_ATB_IF1_data1_Pos   8U
#define	TPI_ITFTTD0_ATB_IF1_data1_Msk   (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
#define	TPI_ITFTTD0_ATB_IF1_data0_Pos   0U
#define	TPI_ITFTTD0_ATB_IF1_data0_Msk   (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/)
#define	TPI_ITATBCTR2_AFVALID2S_Pos   1U
#define	TPI_ITATBCTR2_AFVALID2S_Msk   (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)
#define	TPI_ITATBCTR2_AFVALID1S_Pos   1U
#define	TPI_ITATBCTR2_AFVALID1S_Msk   (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)
#define	TPI_ITATBCTR2_ATREADY2S_Pos   0U
#define	TPI_ITATBCTR2_ATREADY2S_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)
#define	TPI_ITATBCTR2_ATREADY1S_Pos   0U
#define	TPI_ITATBCTR2_ATREADY1S_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)
#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos   29U
#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)
#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos   27U
#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)
#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos   26U
#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)
#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos   24U
#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)
#define	TPI_ITFTTD1_ATB_IF2_data2_Pos   16U
#define	TPI_ITFTTD1_ATB_IF2_data2_Msk   (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
#define	TPI_ITFTTD1_ATB_IF2_data1_Pos   8U
#define	TPI_ITFTTD1_ATB_IF2_data1_Msk   (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
#define	TPI_ITFTTD1_ATB_IF2_data0_Pos   0U
#define	TPI_ITFTTD1_ATB_IF2_data0_Msk   (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/)
#define	TPI_ITATBCTR0_AFVALID2S_Pos   1U
#define	TPI_ITATBCTR0_AFVALID2S_Msk   (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)
#define	TPI_ITATBCTR0_AFVALID1S_Pos   1U
#define	TPI_ITATBCTR0_AFVALID1S_Msk   (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)
#define	TPI_ITATBCTR0_ATREADY2S_Pos   0U
#define	TPI_ITATBCTR0_ATREADY2S_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)
#define	TPI_ITATBCTR0_ATREADY1S_Pos   0U
#define	TPI_ITATBCTR0_ATREADY1S_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)
#define	TPI_DEVID_FIFOSZ_Pos   6U
#define	TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)
#define	TPI_FFCR_FOnMan_Pos   6U
#define	TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)
#define	TPI_DEVID_FIFOSZ_Pos   6U
#define	TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)
#define	TPI_FFCR_FOnMan_Pos   6U
#define	TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)
#define	TPI_DEVID_FIFOSZ_Pos   6U
#define	TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)
#define	TPI_FFCR_FOnMan_Pos   6U
#define	TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)
#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos   29U
#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)
#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos   27U
#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)
#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos   26U
#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)
#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos   24U
#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)
#define	TPI_ITFTTD0_ATB_IF1_data2_Pos   16U
#define	TPI_ITFTTD0_ATB_IF1_data2_Msk   (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
#define	TPI_ITFTTD0_ATB_IF1_data1_Pos   8U
#define	TPI_ITFTTD0_ATB_IF1_data1_Msk   (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
#define	TPI_ITFTTD0_ATB_IF1_data0_Pos   0U
#define	TPI_ITFTTD0_ATB_IF1_data0_Msk   (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/)
#define	TPI_ITATBCTR2_AFVALID2S_Pos   1U
#define	TPI_ITATBCTR2_AFVALID2S_Msk   (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)
#define	TPI_ITATBCTR2_AFVALID1S_Pos   1U
#define	TPI_ITATBCTR2_AFVALID1S_Msk   (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)
#define	TPI_ITATBCTR2_ATREADY2S_Pos   0U
#define	TPI_ITATBCTR2_ATREADY2S_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)
#define	TPI_ITATBCTR2_ATREADY1S_Pos   0U
#define	TPI_ITATBCTR2_ATREADY1S_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)
#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos   29U
#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)
#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos   27U
#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)
#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos   26U
#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)
#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos   24U
#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)
#define	TPI_ITFTTD1_ATB_IF2_data2_Pos   16U
#define	TPI_ITFTTD1_ATB_IF2_data2_Msk   (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
#define	TPI_ITFTTD1_ATB_IF2_data1_Pos   8U
#define	TPI_ITFTTD1_ATB_IF2_data1_Msk   (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
#define	TPI_ITFTTD1_ATB_IF2_data0_Pos   0U
#define	TPI_ITFTTD1_ATB_IF2_data0_Msk   (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/)
#define	TPI_ITATBCTR0_AFVALID2S_Pos   1U
#define	TPI_ITATBCTR0_AFVALID2S_Msk   (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)
#define	TPI_ITATBCTR0_AFVALID1S_Pos   1U
#define	TPI_ITATBCTR0_AFVALID1S_Msk   (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)
#define	TPI_ITATBCTR0_ATREADY2S_Pos   0U
#define	TPI_ITATBCTR0_ATREADY2S_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)
#define	TPI_ITATBCTR0_ATREADY1S_Pos   0U
#define	TPI_ITATBCTR0_ATREADY1S_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)
#define	TPI_DEVID_FIFOSZ_Pos   6U
#define	TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)
#define	TPI_FFCR_FOnMan_Pos   6U
#define	TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)
#define	TPI_DEVID_FIFOSZ_Pos   6U
#define	TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)
#define	TPI_FFCR_FOnMan_Pos   6U
#define	TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)
#define	TPI_DEVID_FIFOSZ_Pos   6U
#define	TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)
#define	TPI_FFCR_FOnMan_Pos   6U
#define	TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)
#define	TPI_DEVID_FIFOSZ_Pos   6U
#define	TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)
#define	TPI_FFCR_FOnMan_Pos   6U
#define	TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)
#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos   29U
#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)
#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos   27U
#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)
#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos   26U
#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)
#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos   24U
#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)
#define	TPI_ITFTTD0_ATB_IF1_data2_Pos   16U
#define	TPI_ITFTTD0_ATB_IF1_data2_Msk   (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
#define	TPI_ITFTTD0_ATB_IF1_data1_Pos   8U
#define	TPI_ITFTTD0_ATB_IF1_data1_Msk   (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
#define	TPI_ITFTTD0_ATB_IF1_data0_Pos   0U
#define	TPI_ITFTTD0_ATB_IF1_data0_Msk   (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/)
#define	TPI_ITATBCTR2_AFVALID2S_Pos   1U
#define	TPI_ITATBCTR2_AFVALID2S_Msk   (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)
#define	TPI_ITATBCTR2_AFVALID1S_Pos   1U
#define	TPI_ITATBCTR2_AFVALID1S_Msk   (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)
#define	TPI_ITATBCTR2_ATREADY2S_Pos   0U
#define	TPI_ITATBCTR2_ATREADY2S_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)
#define	TPI_ITATBCTR2_ATREADY1S_Pos   0U
#define	TPI_ITATBCTR2_ATREADY1S_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)
#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos   29U
#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)
#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos   27U
#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)
#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos   26U
#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)
#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos   24U
#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)
#define	TPI_ITFTTD1_ATB_IF2_data2_Pos   16U
#define	TPI_ITFTTD1_ATB_IF2_data2_Msk   (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
#define	TPI_ITFTTD1_ATB_IF2_data1_Pos   8U
#define	TPI_ITFTTD1_ATB_IF2_data1_Msk   (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
#define	TPI_ITFTTD1_ATB_IF2_data0_Pos   0U
#define	TPI_ITFTTD1_ATB_IF2_data0_Msk   (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/)
#define	TPI_ITATBCTR0_AFVALID2S_Pos   1U
#define	TPI_ITATBCTR0_AFVALID2S_Msk   (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)
#define	TPI_ITATBCTR0_AFVALID1S_Pos   1U
#define	TPI_ITATBCTR0_AFVALID1S_Msk   (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)
#define	TPI_ITATBCTR0_ATREADY2S_Pos   0U
#define	TPI_ITATBCTR0_ATREADY2S_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)
#define	TPI_ITATBCTR0_ATREADY1S_Pos   0U
#define	TPI_ITATBCTR0_ATREADY1S_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)
#define	TPI_DEVID_FIFOSZ_Pos   6U
#define	TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)
#define	TPI_FFCR_EnFmt_Pos   0U
#define	TPI_FFCR_EnFmt_Msk   (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)
#define	TPI_FFCR_EnFmt_Pos   0U
#define	TPI_FFCR_EnFmt_Msk   (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)
#define	TPI_FFCR_EnFmt_Pos   0U
#define	TPI_FFCR_EnFmt_Msk   (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)
#define	TPI_FFCR_EnFmt_Pos   0U
#define	TPI_FFCR_EnFmt_Msk   (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)

Detailed Description

Type definitions for the Trace Port Interface (TPI)

Macro Definition Documentation

__NVIC_GetPriorityGrouping [1/8]

__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping

(

void

)

Value:

(0U)

Get Priority Grouping.

Reads the priority grouping field from the NVIC Interrupt Controller.

Returns

Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).

Definition at line 1446 of file core_armv8mbl.h.

__NVIC_GetPriorityGrouping [2/8]

#define __NVIC_GetPriorityGrouping

(

void

)

Value:

(0U)

Definition at line 620 of file core_cm0.h.

__NVIC_GetPriorityGrouping [3/8]

#define __NVIC_GetPriorityGrouping

(

void

)

Value:

(0U)

Definition at line 738 of file core_cm0plus.h.

__NVIC_GetPriorityGrouping [4/8]

#define __NVIC_GetPriorityGrouping

(

void

)

Value:

(0U)

Definition at line 647 of file core_cm1.h.

__NVIC_GetPriorityGrouping [5/8]

#define __NVIC_GetPriorityGrouping

(

void

)

Value:

(0U)

Definition at line 1521 of file core_cm23.h.

__NVIC_GetPriorityGrouping [6/8]

#define __NVIC_GetPriorityGrouping

(

void

)

Value:

(0U)

Definition at line 620 of file core_cm0.h.

__NVIC_GetPriorityGrouping [7/8]

#define __NVIC_GetPriorityGrouping

(

void

)

Value:

(0U)

Definition at line 738 of file core_cm0plus.h.

__NVIC_GetPriorityGrouping [8/8]

#define __NVIC_GetPriorityGrouping

(

void

)

Value:

(0U)

Definition at line 1446 of file core_armv8mbl.h.

__NVIC_SetPriorityGrouping [1/8]

#define __NVIC_SetPriorityGrouping

(

X

)

Value:

(void)(X)

Definition at line 1445 of file core_armv8mbl.h.

__NVIC_SetPriorityGrouping [2/8]

#define __NVIC_SetPriorityGrouping

(

X

)

Value:

(void)(X)

Definition at line 619 of file core_cm0.h.

__NVIC_SetPriorityGrouping [3/8]

#define __NVIC_SetPriorityGrouping

(

X

)

Value:

(void)(X)

Definition at line 737 of file core_cm0plus.h.

__NVIC_SetPriorityGrouping [4/8]

#define __NVIC_SetPriorityGrouping

(

X

)

Value:

(void)(X)

Definition at line 646 of file core_cm1.h.

__NVIC_SetPriorityGrouping [5/8]

#define __NVIC_SetPriorityGrouping

(

X

)

Value:

(void)(X)

Definition at line 1520 of file core_cm23.h.

__NVIC_SetPriorityGrouping [6/8]

#define __NVIC_SetPriorityGrouping

(

X

)

Value:

(void)(X)

Definition at line 619 of file core_cm0.h.

__NVIC_SetPriorityGrouping [7/8]

#define __NVIC_SetPriorityGrouping

(

X

)

Value:

(void)(X)

Definition at line 737 of file core_cm0plus.h.

__NVIC_SetPriorityGrouping [8/8]

#define __NVIC_SetPriorityGrouping

(

X

)

Value:

(void)(X)

Definition at line 1445 of file core_armv8mbl.h.

_BIT_SHIFT [1/9]

#define _BIT_SHIFT

(

IRQn

)

Value:

(  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)

Definition at line 1441 of file core_armv8mbl.h.

_BIT_SHIFT [2/9]

#define _BIT_SHIFT

(

IRQn

)

Value:

(  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)

Definition at line 615 of file core_cm0.h.

_BIT_SHIFT [3/9]

#define _BIT_SHIFT

(

IRQn

)

Value:

(  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)

Definition at line 733 of file core_cm0plus.h.

_BIT_SHIFT [4/9]

#define _BIT_SHIFT

(

IRQn

)

Value:

(  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)

Definition at line 642 of file core_cm1.h.

_BIT_SHIFT [5/9]

#define _BIT_SHIFT

(

IRQn

)

Value:

(  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)

Definition at line 1516 of file core_cm23.h.

_BIT_SHIFT [6/9]

#define _BIT_SHIFT

(

IRQn

)

Value:

(  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)

Definition at line 748 of file core_sc000.h.

_BIT_SHIFT [7/9]

#define _BIT_SHIFT

(

IRQn

)

Value:

(  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)

Definition at line 615 of file core_cm0.h.

_BIT_SHIFT [8/9]

#define _BIT_SHIFT

(

IRQn

)

Value:

(  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)

Definition at line 733 of file core_cm0plus.h.

_BIT_SHIFT [9/9]

#define _BIT_SHIFT

(

IRQn

)

Value:

(  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)

Definition at line 1441 of file core_armv8mbl.h.

_IP_IDX [1/9]

#define _IP_IDX

(

IRQn

)

Value:

(   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )

Definition at line 1443 of file core_armv8mbl.h.

_IP_IDX [2/9]

#define _IP_IDX

(

IRQn

)

Value:

(   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )

Definition at line 617 of file core_cm0.h.

_IP_IDX [3/9]

#define _IP_IDX

(

IRQn

)

Value:

(   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )

Definition at line 735 of file core_cm0plus.h.

_IP_IDX [4/9]

#define _IP_IDX

(

IRQn

)

Value:

(   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )

Definition at line 644 of file core_cm1.h.

_IP_IDX [5/9]

#define _IP_IDX

(

IRQn

)

Value:

(   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )

Definition at line 1518 of file core_cm23.h.

_IP_IDX [6/9]

#define _IP_IDX

(

IRQn

)

Value:

(   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )

Definition at line 750 of file core_sc000.h.

_IP_IDX [7/9]

#define _IP_IDX

(

IRQn

)

Value:

(   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )

Definition at line 617 of file core_cm0.h.

_IP_IDX [8/9]

#define _IP_IDX

(

IRQn

)

Value:

(   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )

Definition at line 735 of file core_cm0plus.h.

_IP_IDX [9/9]

#define _IP_IDX

(

IRQn

)

Value:

(   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )

Definition at line 1443 of file core_armv8mbl.h.

_SHP_IDX [1/9]

#define _SHP_IDX

(

IRQn

)

Value:

( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )

Definition at line 1442 of file core_armv8mbl.h.

_SHP_IDX [2/9]

#define _SHP_IDX

(

IRQn

)

Value:

( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )

Definition at line 616 of file core_cm0.h.

_SHP_IDX [3/9]

#define _SHP_IDX

(

IRQn

)

Value:

( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )

Definition at line 734 of file core_cm0plus.h.

_SHP_IDX [4/9]

#define _SHP_IDX

(

IRQn

)

Value:

( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )

Definition at line 643 of file core_cm1.h.

_SHP_IDX [5/9]

#define _SHP_IDX

(

IRQn

)

Value:

( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )

Definition at line 1517 of file core_cm23.h.

_SHP_IDX [6/9]

#define _SHP_IDX

(

IRQn

)

Value:

( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )

Definition at line 749 of file core_sc000.h.

_SHP_IDX [7/9]

#define _SHP_IDX

(

IRQn

)

Value:

( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )

Definition at line 616 of file core_cm0.h.

_SHP_IDX [8/9]

#define _SHP_IDX

(

IRQn

)

Value:

( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )

Definition at line 734 of file core_cm0plus.h.

_SHP_IDX [9/9]

#define _SHP_IDX

(

IRQn

)

Value:

( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )

Definition at line 1442 of file core_armv8mbl.h.

CoreDebug_DEMCR_DWTENA_Msk [1/3]

#define CoreDebug_DEMCR_DWTENA_Msk   (1UL << CoreDebug_DEMCR_DWTENA_Pos)

Deprecated

CoreDebug DEMCR: DWTENA Mask

Deprecated

CoreDebug DEMCR: DWTENA Mask

Deprecated

CoreDebug DEMCR: DWTENA Mask

Definition at line 1053 of file core_armv8mbl.h.

CoreDebug_DEMCR_DWTENA_Msk [2/3]

#define CoreDebug_DEMCR_DWTENA_Msk   (1UL << CoreDebug_DEMCR_DWTENA_Pos)

Deprecated

CoreDebug DEMCR: DWTENA Mask

Deprecated

CoreDebug DEMCR: DWTENA Mask

Definition at line 1128 of file core_cm23.h.

CoreDebug_DEMCR_DWTENA_Msk [3/3]

#define CoreDebug_DEMCR_DWTENA_Msk   (1UL << CoreDebug_DEMCR_DWTENA_Pos)

Deprecated

CoreDebug DEMCR: DWTENA Mask

Definition at line 1053 of file core_armv8mbl.h.

CoreDebug_DEMCR_DWTENA_Pos [1/3]

#define CoreDebug_DEMCR_DWTENA_Pos   24U

Deprecated

CoreDebug DEMCR: DWTENA Position

Deprecated

CoreDebug DEMCR: DWTENA Position

Deprecated

CoreDebug DEMCR: DWTENA Position

Definition at line 1052 of file core_armv8mbl.h.

CoreDebug_DEMCR_DWTENA_Pos [2/3]

#define CoreDebug_DEMCR_DWTENA_Pos   24U

Deprecated

CoreDebug DEMCR: DWTENA Position

Deprecated

CoreDebug DEMCR: DWTENA Position

Definition at line 1127 of file core_cm23.h.

CoreDebug_DEMCR_DWTENA_Pos [3/3]

#define CoreDebug_DEMCR_DWTENA_Pos   24U

Deprecated

CoreDebug DEMCR: DWTENA Position

Definition at line 1052 of file core_armv8mbl.h.

TPI_ACPR_PRESCALER_Msk [1/10]

#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 762 of file core_cm23.h.

TPI_ACPR_PRESCALER_Msk [2/10]

#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1028 of file core_cm3.h.

TPI_ACPR_PRESCALER_Msk [3/10]

#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1356 of file core_cm33.h.

TPI_ACPR_PRESCALER_Msk [4/10]

#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1356 of file core_cm35p.h.

TPI_ACPR_PRESCALER_Msk [5/10]

#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1093 of file core_cm4.h.

TPI_ACPR_PRESCALER_Msk [6/10]

#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1320 of file core_cm7.h.

TPI_ACPR_PRESCALER_Msk [7/10]

#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1013 of file core_sc300.h.

TPI_ACPR_PRESCALER_Msk [8/10]

#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1414 of file core_starmc1.h.

TPI_ACPR_PRESCALER_Msk [9/10]

#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1356 of file core_cm33.h.

TPI_ACPR_PRESCALER_Msk [10/10]

#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1093 of file core_cm4.h.

TPI_ACPR_PRESCALER_Pos [1/10]

#define TPI_ACPR_PRESCALER_Pos   0U

TPI ACPR: PRESCALER Position

Definition at line 761 of file core_cm23.h.

TPI_ACPR_PRESCALER_Pos [2/10]

#define TPI_ACPR_PRESCALER_Pos   0U

TPI ACPR: PRESCALER Position

Definition at line 1027 of file core_cm3.h.

TPI_ACPR_PRESCALER_Pos [3/10]

#define TPI_ACPR_PRESCALER_Pos   0U

TPI ACPR: PRESCALER Position

Definition at line 1355 of file core_cm33.h.

TPI_ACPR_PRESCALER_Pos [4/10]

#define TPI_ACPR_PRESCALER_Pos   0U

TPI ACPR: PRESCALER Position

Definition at line 1355 of file core_cm35p.h.

TPI_ACPR_PRESCALER_Pos [5/10]

#define TPI_ACPR_PRESCALER_Pos   0U

TPI ACPR: PRESCALER Position

Definition at line 1092 of file core_cm4.h.

TPI_ACPR_PRESCALER_Pos [6/10]

#define TPI_ACPR_PRESCALER_Pos   0U

TPI ACPR: PRESCALER Position

Definition at line 1319 of file core_cm7.h.

TPI_ACPR_PRESCALER_Pos [7/10]

#define TPI_ACPR_PRESCALER_Pos   0U

TPI ACPR: PRESCALER Position

Definition at line 1012 of file core_sc300.h.

TPI_ACPR_PRESCALER_Pos [8/10]

#define TPI_ACPR_PRESCALER_Pos   0U

TPI ACPR: PRESCALER Position

Definition at line 1413 of file core_starmc1.h.

TPI_ACPR_PRESCALER_Pos [9/10]

#define TPI_ACPR_PRESCALER_Pos   0U

TPI ACPR: PRESCALER Position

Definition at line 1355 of file core_cm33.h.

TPI_ACPR_PRESCALER_Pos [10/10]

#define TPI_ACPR_PRESCALER_Pos   0U

TPI ACPR: PRESCALER Position

Definition at line 1092 of file core_cm4.h.

TPI_ACPR_SWOSCALER_Msk [1/8]

#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 1410 of file core_armv81mml.h.

TPI_ACPR_SWOSCALER_Msk [2/8]

#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 754 of file core_armv8mbl.h.

TPI_ACPR_SWOSCALER_Msk [3/8]

#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 1348 of file core_armv8mml.h.

TPI_ACPR_SWOSCALER_Msk [4/8]

#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 1963 of file core_cm55.h.

TPI_ACPR_SWOSCALER_Msk [5/8]

#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 1868 of file core_cm85.h.

TPI_ACPR_SWOSCALER_Msk [6/8]

#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 1410 of file core_armv81mml.h.

TPI_ACPR_SWOSCALER_Msk [7/8]

#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 754 of file core_armv8mbl.h.

TPI_ACPR_SWOSCALER_Msk [8/8]

#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 1348 of file core_armv8mml.h.

TPI_ACPR_SWOSCALER_Pos [1/8]

#define TPI_ACPR_SWOSCALER_Pos   0U

TPI ACPR: SWOSCALER Position

Definition at line 1409 of file core_armv81mml.h.

TPI_ACPR_SWOSCALER_Pos [2/8]

#define TPI_ACPR_SWOSCALER_Pos   0U

TPI ACPR: SWOSCALER Position

Definition at line 753 of file core_armv8mbl.h.

TPI_ACPR_SWOSCALER_Pos [3/8]

#define TPI_ACPR_SWOSCALER_Pos   0U

TPI ACPR: SWOSCALER Position

Definition at line 1347 of file core_armv8mml.h.

TPI_ACPR_SWOSCALER_Pos [4/8]

#define TPI_ACPR_SWOSCALER_Pos   0U

TPI ACPR: SWOSCALER Position

Definition at line 1962 of file core_cm55.h.

TPI_ACPR_SWOSCALER_Pos [5/8]

#define TPI_ACPR_SWOSCALER_Pos   0U

TPI ACPR: SWOSCALER Position

Definition at line 1867 of file core_cm85.h.

TPI_ACPR_SWOSCALER_Pos [6/8]

#define TPI_ACPR_SWOSCALER_Pos   0U

TPI ACPR: SWOSCALER Position

Definition at line 1409 of file core_armv81mml.h.

TPI_ACPR_SWOSCALER_Pos [7/8]

#define TPI_ACPR_SWOSCALER_Pos   0U

TPI ACPR: SWOSCALER Position

Definition at line 753 of file core_armv8mbl.h.

TPI_ACPR_SWOSCALER_Pos [8/8]

#define TPI_ACPR_SWOSCALER_Pos   0U

TPI ACPR: SWOSCALER Position

Definition at line 1347 of file core_armv8mml.h.

TPI_DEVID_AsynClkIn_Msk [1/5]

#define TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1134 of file core_cm3.h.

TPI_DEVID_AsynClkIn_Msk [2/5]

#define TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1199 of file core_cm4.h.

TPI_DEVID_AsynClkIn_Msk [3/5]

#define TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1426 of file core_cm7.h.

TPI_DEVID_AsynClkIn_Msk [4/5]

#define TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1119 of file core_sc300.h.

TPI_DEVID_AsynClkIn_Msk [5/5]

#define TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1199 of file core_cm4.h.

TPI_DEVID_AsynClkIn_Pos [1/5]

#define TPI_DEVID_AsynClkIn_Pos   5U

TPI DEVID: AsynClkIn Position

Definition at line 1133 of file core_cm3.h.

TPI_DEVID_AsynClkIn_Pos [2/5]

#define TPI_DEVID_AsynClkIn_Pos   5U

TPI DEVID: AsynClkIn Position

Definition at line 1198 of file core_cm4.h.

TPI_DEVID_AsynClkIn_Pos [3/5]

#define TPI_DEVID_AsynClkIn_Pos   5U

TPI DEVID: AsynClkIn Position

Definition at line 1425 of file core_cm7.h.

TPI_DEVID_AsynClkIn_Pos [4/5]

#define TPI_DEVID_AsynClkIn_Pos   5U

TPI DEVID: AsynClkIn Position

Definition at line 1118 of file core_sc300.h.

TPI_DEVID_AsynClkIn_Pos [5/5]

#define TPI_DEVID_AsynClkIn_Pos   5U

TPI DEVID: AsynClkIn Position

Definition at line 1198 of file core_cm4.h.

TPI_DEVID_FIFOSZ_Msk [1/13]

#define TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask

TPI DEVID: FIFOSZ Mask

Definition at line 1464 of file core_armv81mml.h.

TPI_DEVID_FIFOSZ_Msk [2/13]

#define TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask

TPI DEVID: FIFOSZ Mask

Definition at line 808 of file core_armv8mbl.h.

TPI_DEVID_FIFOSZ_Msk [3/13]

#define TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask

TPI DEVID: FIFOSZ Mask

Definition at line 1402 of file core_armv8mml.h.

TPI_DEVID_FIFOSZ_Msk [4/13]

#define TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFOSZ Mask

TPI DEVID: FIFO depth Mask

Definition at line 880 of file core_cm23.h.

TPI_DEVID_FIFOSZ_Msk [5/13]

#define TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFOSZ Mask

TPI DEVID: FIFO depth Mask

Definition at line 1474 of file core_cm33.h.

TPI_DEVID_FIFOSZ_Msk [6/13]

#define TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFOSZ Mask

TPI DEVID: FIFO depth Mask

Definition at line 1474 of file core_cm35p.h.

TPI_DEVID_FIFOSZ_Msk [7/13]

#define TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask

TPI DEVID: FIFOSZ Mask

Definition at line 2017 of file core_cm55.h.

TPI_DEVID_FIFOSZ_Msk [8/13]

#define TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask

TPI DEVID: FIFOSZ Mask

Definition at line 1922 of file core_cm85.h.

TPI_DEVID_FIFOSZ_Msk [9/13]

#define TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFOSZ Mask

TPI DEVID: FIFO depth Mask

Definition at line 1532 of file core_starmc1.h.

TPI_DEVID_FIFOSZ_Msk [10/13]

#define TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask

TPI DEVID: FIFOSZ Mask

Definition at line 1464 of file core_armv81mml.h.

TPI_DEVID_FIFOSZ_Msk [11/13]

#define TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask

TPI DEVID: FIFOSZ Mask

Definition at line 808 of file core_armv8mbl.h.

TPI_DEVID_FIFOSZ_Msk [12/13]

#define TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask

TPI DEVID: FIFOSZ Mask

Definition at line 1402 of file core_armv8mml.h.

TPI_DEVID_FIFOSZ_Msk [13/13]

#define TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFOSZ Mask

Definition at line 1474 of file core_cm33.h.

TPI_DEVID_FIFOSZ_Pos [1/13]

#define TPI_DEVID_FIFOSZ_Pos   6U

TPI DEVID: FIFO depth Position

TPI DEVID: FIFOSZ Position

Definition at line 1463 of file core_armv81mml.h.

TPI_DEVID_FIFOSZ_Pos [2/13]

#define TPI_DEVID_FIFOSZ_Pos   6U

TPI DEVID: FIFO depth Position

TPI DEVID: FIFOSZ Position

Definition at line 807 of file core_armv8mbl.h.

TPI_DEVID_FIFOSZ_Pos [3/13]

#define TPI_DEVID_FIFOSZ_Pos   6U

TPI DEVID: FIFO depth Position

TPI DEVID: FIFOSZ Position

Definition at line 1401 of file core_armv8mml.h.

TPI_DEVID_FIFOSZ_Pos [4/13]

#define TPI_DEVID_FIFOSZ_Pos   6U

TPI DEVID: FIFOSZ Position

TPI DEVID: FIFO depth Position

Definition at line 879 of file core_cm23.h.

TPI_DEVID_FIFOSZ_Pos [5/13]

#define TPI_DEVID_FIFOSZ_Pos   6U

TPI DEVID: FIFOSZ Position

TPI DEVID: FIFO depth Position

Definition at line 1473 of file core_cm33.h.

TPI_DEVID_FIFOSZ_Pos [6/13]

#define TPI_DEVID_FIFOSZ_Pos   6U

TPI DEVID: FIFOSZ Position

TPI DEVID: FIFO depth Position

Definition at line 1473 of file core_cm35p.h.

TPI_DEVID_FIFOSZ_Pos [7/13]

#define TPI_DEVID_FIFOSZ_Pos   6U

TPI DEVID: FIFO depth Position

TPI DEVID: FIFOSZ Position

Definition at line 2016 of file core_cm55.h.

TPI_DEVID_FIFOSZ_Pos [8/13]

#define TPI_DEVID_FIFOSZ_Pos   6U

TPI DEVID: FIFO depth Position

TPI DEVID: FIFOSZ Position

Definition at line 1921 of file core_cm85.h.

TPI_DEVID_FIFOSZ_Pos [9/13]

#define TPI_DEVID_FIFOSZ_Pos   6U

TPI DEVID: FIFOSZ Position

TPI DEVID: FIFO depth Position

Definition at line 1531 of file core_starmc1.h.

TPI_DEVID_FIFOSZ_Pos [10/13]

#define TPI_DEVID_FIFOSZ_Pos   6U

TPI DEVID: FIFO depth Position

TPI DEVID: FIFOSZ Position

Definition at line 1463 of file core_armv81mml.h.

TPI_DEVID_FIFOSZ_Pos [11/13]

#define TPI_DEVID_FIFOSZ_Pos   6U

TPI DEVID: FIFO depth Position

TPI DEVID: FIFOSZ Position

Definition at line 807 of file core_armv8mbl.h.

TPI_DEVID_FIFOSZ_Pos [12/13]

#define TPI_DEVID_FIFOSZ_Pos   6U

TPI DEVID: FIFO depth Position

TPI DEVID: FIFOSZ Position

Definition at line 1401 of file core_armv8mml.h.

TPI_DEVID_FIFOSZ_Pos [13/13]

#define TPI_DEVID_FIFOSZ_Pos   6U

TPI DEVID: FIFOSZ Position

Definition at line 1473 of file core_cm33.h.

TPI_DEVID_MANCVALID_Msk [1/18]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1458 of file core_armv81mml.h.

TPI_DEVID_MANCVALID_Msk [2/18]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 802 of file core_armv8mbl.h.

TPI_DEVID_MANCVALID_Msk [3/18]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1396 of file core_armv8mml.h.

TPI_DEVID_MANCVALID_Msk [4/18]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 874 of file core_cm23.h.

TPI_DEVID_MANCVALID_Msk [5/18]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1125 of file core_cm3.h.

TPI_DEVID_MANCVALID_Msk [6/18]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1468 of file core_cm33.h.

TPI_DEVID_MANCVALID_Msk [7/18]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1468 of file core_cm35p.h.

TPI_DEVID_MANCVALID_Msk [8/18]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1190 of file core_cm4.h.

TPI_DEVID_MANCVALID_Msk [9/18]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 2011 of file core_cm55.h.

TPI_DEVID_MANCVALID_Msk [10/18]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1417 of file core_cm7.h.

TPI_DEVID_MANCVALID_Msk [11/18]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1916 of file core_cm85.h.

TPI_DEVID_MANCVALID_Msk [12/18]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1110 of file core_sc300.h.

TPI_DEVID_MANCVALID_Msk [13/18]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1526 of file core_starmc1.h.

TPI_DEVID_MANCVALID_Msk [14/18]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1458 of file core_armv81mml.h.

TPI_DEVID_MANCVALID_Msk [15/18]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 802 of file core_armv8mbl.h.

TPI_DEVID_MANCVALID_Msk [16/18]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1396 of file core_armv8mml.h.

TPI_DEVID_MANCVALID_Msk [17/18]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1468 of file core_cm33.h.

TPI_DEVID_MANCVALID_Msk [18/18]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1190 of file core_cm4.h.

TPI_DEVID_MANCVALID_Pos [1/18]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

Definition at line 1457 of file core_armv81mml.h.

TPI_DEVID_MANCVALID_Pos [2/18]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

Definition at line 801 of file core_armv8mbl.h.

TPI_DEVID_MANCVALID_Pos [3/18]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

Definition at line 1395 of file core_armv8mml.h.

TPI_DEVID_MANCVALID_Pos [4/18]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

Definition at line 873 of file core_cm23.h.

TPI_DEVID_MANCVALID_Pos [5/18]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

Definition at line 1124 of file core_cm3.h.

TPI_DEVID_MANCVALID_Pos [6/18]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

Definition at line 1467 of file core_cm33.h.

TPI_DEVID_MANCVALID_Pos [7/18]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

Definition at line 1467 of file core_cm35p.h.

TPI_DEVID_MANCVALID_Pos [8/18]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

Definition at line 1189 of file core_cm4.h.

TPI_DEVID_MANCVALID_Pos [9/18]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

Definition at line 2010 of file core_cm55.h.

TPI_DEVID_MANCVALID_Pos [10/18]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

Definition at line 1416 of file core_cm7.h.

TPI_DEVID_MANCVALID_Pos [11/18]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

Definition at line 1915 of file core_cm85.h.

TPI_DEVID_MANCVALID_Pos [12/18]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

Definition at line 1109 of file core_sc300.h.

TPI_DEVID_MANCVALID_Pos [13/18]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

Definition at line 1525 of file core_starmc1.h.

TPI_DEVID_MANCVALID_Pos [14/18]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

Definition at line 1457 of file core_armv81mml.h.

TPI_DEVID_MANCVALID_Pos [15/18]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

Definition at line 801 of file core_armv8mbl.h.

TPI_DEVID_MANCVALID_Pos [16/18]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

Definition at line 1395 of file core_armv8mml.h.

TPI_DEVID_MANCVALID_Pos [17/18]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

Definition at line 1467 of file core_cm33.h.

TPI_DEVID_MANCVALID_Pos [18/18]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

Definition at line 1189 of file core_cm4.h.

TPI_DEVID_MinBufSz_Msk [1/5]

#define TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1131 of file core_cm3.h.

TPI_DEVID_MinBufSz_Msk [2/5]

#define TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1196 of file core_cm4.h.

TPI_DEVID_MinBufSz_Msk [3/5]

#define TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1423 of file core_cm7.h.

TPI_DEVID_MinBufSz_Msk [4/5]

#define TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1116 of file core_sc300.h.

TPI_DEVID_MinBufSz_Msk [5/5]

#define TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1196 of file core_cm4.h.

TPI_DEVID_MinBufSz_Pos [1/5]

#define TPI_DEVID_MinBufSz_Pos   6U

TPI DEVID: MinBufSz Position

Definition at line 1130 of file core_cm3.h.

TPI_DEVID_MinBufSz_Pos [2/5]

#define TPI_DEVID_MinBufSz_Pos   6U

TPI DEVID: MinBufSz Position

Definition at line 1195 of file core_cm4.h.

TPI_DEVID_MinBufSz_Pos [3/5]

#define TPI_DEVID_MinBufSz_Pos   6U

TPI DEVID: MinBufSz Position

Definition at line 1422 of file core_cm7.h.

TPI_DEVID_MinBufSz_Pos [4/5]

#define TPI_DEVID_MinBufSz_Pos   6U

TPI DEVID: MinBufSz Position

Definition at line 1115 of file core_sc300.h.

TPI_DEVID_MinBufSz_Pos [5/5]

#define TPI_DEVID_MinBufSz_Pos   6U

TPI DEVID: MinBufSz Position

Definition at line 1195 of file core_cm4.h.

TPI_DEVID_NrTraceInput_Msk [1/10]

#define TPI_DEVID_NrTraceInput_Msk   (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 883 of file core_cm23.h.

TPI_DEVID_NrTraceInput_Msk [2/10]

#define TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1137 of file core_cm3.h.

TPI_DEVID_NrTraceInput_Msk [3/10]

#define TPI_DEVID_NrTraceInput_Msk   (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1477 of file core_cm33.h.

TPI_DEVID_NrTraceInput_Msk [4/10]

#define TPI_DEVID_NrTraceInput_Msk   (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1477 of file core_cm35p.h.

TPI_DEVID_NrTraceInput_Msk [5/10]

#define TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1202 of file core_cm4.h.

TPI_DEVID_NrTraceInput_Msk [6/10]

#define TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1429 of file core_cm7.h.

TPI_DEVID_NrTraceInput_Msk [7/10]

#define TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1122 of file core_sc300.h.

TPI_DEVID_NrTraceInput_Msk [8/10]

#define TPI_DEVID_NrTraceInput_Msk   (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1535 of file core_starmc1.h.

TPI_DEVID_NrTraceInput_Msk [9/10]

#define TPI_DEVID_NrTraceInput_Msk   (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1477 of file core_cm33.h.

TPI_DEVID_NrTraceInput_Msk [10/10]

#define TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1202 of file core_cm4.h.

TPI_DEVID_NrTraceInput_Pos [1/10]

#define TPI_DEVID_NrTraceInput_Pos   0U

TPI DEVID: NrTraceInput Position

Definition at line 882 of file core_cm23.h.

TPI_DEVID_NrTraceInput_Pos [2/10]

#define TPI_DEVID_NrTraceInput_Pos   0U

TPI DEVID: NrTraceInput Position

Definition at line 1136 of file core_cm3.h.

TPI_DEVID_NrTraceInput_Pos [3/10]

#define TPI_DEVID_NrTraceInput_Pos   0U

TPI DEVID: NrTraceInput Position

Definition at line 1476 of file core_cm33.h.

TPI_DEVID_NrTraceInput_Pos [4/10]

#define TPI_DEVID_NrTraceInput_Pos   0U

TPI DEVID: NrTraceInput Position

Definition at line 1476 of file core_cm35p.h.

TPI_DEVID_NrTraceInput_Pos [5/10]

#define TPI_DEVID_NrTraceInput_Pos   0U

TPI DEVID: NrTraceInput Position

Definition at line 1201 of file core_cm4.h.

TPI_DEVID_NrTraceInput_Pos [6/10]

#define TPI_DEVID_NrTraceInput_Pos   0U

TPI DEVID: NrTraceInput Position

Definition at line 1428 of file core_cm7.h.

TPI_DEVID_NrTraceInput_Pos [7/10]

#define TPI_DEVID_NrTraceInput_Pos   0U

TPI DEVID: NrTraceInput Position

Definition at line 1121 of file core_sc300.h.

TPI_DEVID_NrTraceInput_Pos [8/10]

#define TPI_DEVID_NrTraceInput_Pos   0U

TPI DEVID: NrTraceInput Position

Definition at line 1534 of file core_starmc1.h.

TPI_DEVID_NrTraceInput_Pos [9/10]

#define TPI_DEVID_NrTraceInput_Pos   0U

TPI DEVID: NrTraceInput Position

Definition at line 1476 of file core_cm33.h.

TPI_DEVID_NrTraceInput_Pos [10/10]

#define TPI_DEVID_NrTraceInput_Pos   0U

TPI DEVID: NrTraceInput Position

Definition at line 1201 of file core_cm4.h.

TPI_DEVID_NRZVALID_Msk [1/18]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1455 of file core_armv81mml.h.

TPI_DEVID_NRZVALID_Msk [2/18]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 799 of file core_armv8mbl.h.

TPI_DEVID_NRZVALID_Msk [3/18]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1393 of file core_armv8mml.h.

TPI_DEVID_NRZVALID_Msk [4/18]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 871 of file core_cm23.h.

TPI_DEVID_NRZVALID_Msk [5/18]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1122 of file core_cm3.h.

TPI_DEVID_NRZVALID_Msk [6/18]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1465 of file core_cm33.h.

TPI_DEVID_NRZVALID_Msk [7/18]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1465 of file core_cm35p.h.

TPI_DEVID_NRZVALID_Msk [8/18]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1187 of file core_cm4.h.

TPI_DEVID_NRZVALID_Msk [9/18]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 2008 of file core_cm55.h.

TPI_DEVID_NRZVALID_Msk [10/18]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1414 of file core_cm7.h.

TPI_DEVID_NRZVALID_Msk [11/18]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1913 of file core_cm85.h.

TPI_DEVID_NRZVALID_Msk [12/18]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1107 of file core_sc300.h.

TPI_DEVID_NRZVALID_Msk [13/18]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1523 of file core_starmc1.h.

TPI_DEVID_NRZVALID_Msk [14/18]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1455 of file core_armv81mml.h.

TPI_DEVID_NRZVALID_Msk [15/18]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 799 of file core_armv8mbl.h.

TPI_DEVID_NRZVALID_Msk [16/18]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1393 of file core_armv8mml.h.

TPI_DEVID_NRZVALID_Msk [17/18]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1465 of file core_cm33.h.

TPI_DEVID_NRZVALID_Msk [18/18]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1187 of file core_cm4.h.

TPI_DEVID_NRZVALID_Pos [1/18]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

Definition at line 1454 of file core_armv81mml.h.

TPI_DEVID_NRZVALID_Pos [2/18]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

Definition at line 798 of file core_armv8mbl.h.

TPI_DEVID_NRZVALID_Pos [3/18]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

Definition at line 1392 of file core_armv8mml.h.

TPI_DEVID_NRZVALID_Pos [4/18]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

Definition at line 870 of file core_cm23.h.

TPI_DEVID_NRZVALID_Pos [5/18]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

Definition at line 1121 of file core_cm3.h.

TPI_DEVID_NRZVALID_Pos [6/18]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

Definition at line 1464 of file core_cm33.h.

TPI_DEVID_NRZVALID_Pos [7/18]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

Definition at line 1464 of file core_cm35p.h.

TPI_DEVID_NRZVALID_Pos [8/18]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

Definition at line 1186 of file core_cm4.h.

TPI_DEVID_NRZVALID_Pos [9/18]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

Definition at line 2007 of file core_cm55.h.

TPI_DEVID_NRZVALID_Pos [10/18]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

Definition at line 1413 of file core_cm7.h.

TPI_DEVID_NRZVALID_Pos [11/18]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

Definition at line 1912 of file core_cm85.h.

TPI_DEVID_NRZVALID_Pos [12/18]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

Definition at line 1106 of file core_sc300.h.

TPI_DEVID_NRZVALID_Pos [13/18]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

Definition at line 1522 of file core_starmc1.h.

TPI_DEVID_NRZVALID_Pos [14/18]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

Definition at line 1454 of file core_armv81mml.h.

TPI_DEVID_NRZVALID_Pos [15/18]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

Definition at line 798 of file core_armv8mbl.h.

TPI_DEVID_NRZVALID_Pos [16/18]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

Definition at line 1392 of file core_armv8mml.h.

TPI_DEVID_NRZVALID_Pos [17/18]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

Definition at line 1464 of file core_cm33.h.

TPI_DEVID_NRZVALID_Pos [18/18]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

Definition at line 1186 of file core_cm4.h.

TPI_DEVID_PTINVALID_Msk [1/18]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1461 of file core_armv81mml.h.

TPI_DEVID_PTINVALID_Msk [2/18]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 805 of file core_armv8mbl.h.

TPI_DEVID_PTINVALID_Msk [3/18]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1399 of file core_armv8mml.h.

TPI_DEVID_PTINVALID_Msk [4/18]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 877 of file core_cm23.h.

TPI_DEVID_PTINVALID_Msk [5/18]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1128 of file core_cm3.h.

TPI_DEVID_PTINVALID_Msk [6/18]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1471 of file core_cm33.h.

TPI_DEVID_PTINVALID_Msk [7/18]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1471 of file core_cm35p.h.

TPI_DEVID_PTINVALID_Msk [8/18]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1193 of file core_cm4.h.

TPI_DEVID_PTINVALID_Msk [9/18]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 2014 of file core_cm55.h.

TPI_DEVID_PTINVALID_Msk [10/18]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1420 of file core_cm7.h.

TPI_DEVID_PTINVALID_Msk [11/18]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1919 of file core_cm85.h.

TPI_DEVID_PTINVALID_Msk [12/18]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1113 of file core_sc300.h.

TPI_DEVID_PTINVALID_Msk [13/18]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1529 of file core_starmc1.h.

TPI_DEVID_PTINVALID_Msk [14/18]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1461 of file core_armv81mml.h.

TPI_DEVID_PTINVALID_Msk [15/18]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 805 of file core_armv8mbl.h.

TPI_DEVID_PTINVALID_Msk [16/18]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1399 of file core_armv8mml.h.

TPI_DEVID_PTINVALID_Msk [17/18]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1471 of file core_cm33.h.

TPI_DEVID_PTINVALID_Msk [18/18]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1193 of file core_cm4.h.

TPI_DEVID_PTINVALID_Pos [1/18]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

Definition at line 1460 of file core_armv81mml.h.

TPI_DEVID_PTINVALID_Pos [2/18]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

Definition at line 804 of file core_armv8mbl.h.

TPI_DEVID_PTINVALID_Pos [3/18]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

Definition at line 1398 of file core_armv8mml.h.

TPI_DEVID_PTINVALID_Pos [4/18]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

Definition at line 876 of file core_cm23.h.

TPI_DEVID_PTINVALID_Pos [5/18]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

Definition at line 1127 of file core_cm3.h.

TPI_DEVID_PTINVALID_Pos [6/18]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

Definition at line 1470 of file core_cm33.h.

TPI_DEVID_PTINVALID_Pos [7/18]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

Definition at line 1470 of file core_cm35p.h.

TPI_DEVID_PTINVALID_Pos [8/18]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

Definition at line 1192 of file core_cm4.h.

TPI_DEVID_PTINVALID_Pos [9/18]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

Definition at line 2013 of file core_cm55.h.

TPI_DEVID_PTINVALID_Pos [10/18]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

Definition at line 1419 of file core_cm7.h.

TPI_DEVID_PTINVALID_Pos [11/18]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

Definition at line 1918 of file core_cm85.h.

TPI_DEVID_PTINVALID_Pos [12/18]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

Definition at line 1112 of file core_sc300.h.

TPI_DEVID_PTINVALID_Pos [13/18]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

Definition at line 1528 of file core_starmc1.h.

TPI_DEVID_PTINVALID_Pos [14/18]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

Definition at line 1460 of file core_armv81mml.h.

TPI_DEVID_PTINVALID_Pos [15/18]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

Definition at line 804 of file core_armv8mbl.h.

TPI_DEVID_PTINVALID_Pos [16/18]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

Definition at line 1398 of file core_armv8mml.h.

TPI_DEVID_PTINVALID_Pos [17/18]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

Definition at line 1470 of file core_cm33.h.

TPI_DEVID_PTINVALID_Pos [18/18]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

Definition at line 1192 of file core_cm4.h.

TPI_DEVTYPE_MajorType_Msk [1/18]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1471 of file core_armv81mml.h.

TPI_DEVTYPE_MajorType_Msk [2/18]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 815 of file core_armv8mbl.h.

TPI_DEVTYPE_MajorType_Msk [3/18]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1409 of file core_armv8mml.h.

TPI_DEVTYPE_MajorType_Msk [4/18]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 890 of file core_cm23.h.

TPI_DEVTYPE_MajorType_Msk [5/18]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1144 of file core_cm3.h.

TPI_DEVTYPE_MajorType_Msk [6/18]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1484 of file core_cm33.h.

TPI_DEVTYPE_MajorType_Msk [7/18]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1484 of file core_cm35p.h.

TPI_DEVTYPE_MajorType_Msk [8/18]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1209 of file core_cm4.h.

TPI_DEVTYPE_MajorType_Msk [9/18]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 2024 of file core_cm55.h.

TPI_DEVTYPE_MajorType_Msk [10/18]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1436 of file core_cm7.h.

TPI_DEVTYPE_MajorType_Msk [11/18]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1929 of file core_cm85.h.

TPI_DEVTYPE_MajorType_Msk [12/18]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1129 of file core_sc300.h.

TPI_DEVTYPE_MajorType_Msk [13/18]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1542 of file core_starmc1.h.

TPI_DEVTYPE_MajorType_Msk [14/18]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1471 of file core_armv81mml.h.

TPI_DEVTYPE_MajorType_Msk [15/18]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 815 of file core_armv8mbl.h.

TPI_DEVTYPE_MajorType_Msk [16/18]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1409 of file core_armv8mml.h.

TPI_DEVTYPE_MajorType_Msk [17/18]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1484 of file core_cm33.h.

TPI_DEVTYPE_MajorType_Msk [18/18]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1209 of file core_cm4.h.

TPI_DEVTYPE_MajorType_Pos [1/18]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

Definition at line 1470 of file core_armv81mml.h.

TPI_DEVTYPE_MajorType_Pos [2/18]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

Definition at line 814 of file core_armv8mbl.h.

TPI_DEVTYPE_MajorType_Pos [3/18]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

Definition at line 1408 of file core_armv8mml.h.

TPI_DEVTYPE_MajorType_Pos [4/18]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

Definition at line 889 of file core_cm23.h.

TPI_DEVTYPE_MajorType_Pos [5/18]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

Definition at line 1143 of file core_cm3.h.

TPI_DEVTYPE_MajorType_Pos [6/18]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

Definition at line 1483 of file core_cm33.h.

TPI_DEVTYPE_MajorType_Pos [7/18]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

Definition at line 1483 of file core_cm35p.h.

TPI_DEVTYPE_MajorType_Pos [8/18]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

Definition at line 1208 of file core_cm4.h.

TPI_DEVTYPE_MajorType_Pos [9/18]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

Definition at line 2023 of file core_cm55.h.

TPI_DEVTYPE_MajorType_Pos [10/18]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

Definition at line 1435 of file core_cm7.h.

TPI_DEVTYPE_MajorType_Pos [11/18]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

Definition at line 1928 of file core_cm85.h.

TPI_DEVTYPE_MajorType_Pos [12/18]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

Definition at line 1128 of file core_sc300.h.

TPI_DEVTYPE_MajorType_Pos [13/18]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

Definition at line 1541 of file core_starmc1.h.

TPI_DEVTYPE_MajorType_Pos [14/18]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

Definition at line 1470 of file core_armv81mml.h.

TPI_DEVTYPE_MajorType_Pos [15/18]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

Definition at line 814 of file core_armv8mbl.h.

TPI_DEVTYPE_MajorType_Pos [16/18]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

Definition at line 1408 of file core_armv8mml.h.

TPI_DEVTYPE_MajorType_Pos [17/18]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

Definition at line 1483 of file core_cm33.h.

TPI_DEVTYPE_MajorType_Pos [18/18]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

Definition at line 1208 of file core_cm4.h.

TPI_DEVTYPE_SubType_Msk [1/18]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

Definition at line 1468 of file core_armv81mml.h.

TPI_DEVTYPE_SubType_Msk [2/18]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

Definition at line 812 of file core_armv8mbl.h.

TPI_DEVTYPE_SubType_Msk [3/18]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

Definition at line 1406 of file core_armv8mml.h.

TPI_DEVTYPE_SubType_Msk [4/18]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

Definition at line 887 of file core_cm23.h.

TPI_DEVTYPE_SubType_Msk [5/18]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

Definition at line 1141 of file core_cm3.h.

TPI_DEVTYPE_SubType_Msk [6/18]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

Definition at line 1481 of file core_cm33.h.

TPI_DEVTYPE_SubType_Msk [7/18]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

Definition at line 1481 of file core_cm35p.h.

TPI_DEVTYPE_SubType_Msk [8/18]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

Definition at line 1206 of file core_cm4.h.

TPI_DEVTYPE_SubType_Msk [9/18]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

Definition at line 2021 of file core_cm55.h.

TPI_DEVTYPE_SubType_Msk [10/18]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

Definition at line 1433 of file core_cm7.h.

TPI_DEVTYPE_SubType_Msk [11/18]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

Definition at line 1926 of file core_cm85.h.

TPI_DEVTYPE_SubType_Msk [12/18]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

Definition at line 1126 of file core_sc300.h.

TPI_DEVTYPE_SubType_Msk [13/18]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

Definition at line 1539 of file core_starmc1.h.

TPI_DEVTYPE_SubType_Msk [14/18]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

Definition at line 1468 of file core_armv81mml.h.

TPI_DEVTYPE_SubType_Msk [15/18]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

Definition at line 812 of file core_armv8mbl.h.

TPI_DEVTYPE_SubType_Msk [16/18]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

Definition at line 1406 of file core_armv8mml.h.

TPI_DEVTYPE_SubType_Msk [17/18]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

Definition at line 1481 of file core_cm33.h.

TPI_DEVTYPE_SubType_Msk [18/18]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

Definition at line 1206 of file core_cm4.h.

TPI_DEVTYPE_SubType_Pos [1/18]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

Definition at line 1467 of file core_armv81mml.h.

TPI_DEVTYPE_SubType_Pos [2/18]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

Definition at line 811 of file core_armv8mbl.h.

TPI_DEVTYPE_SubType_Pos [3/18]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

Definition at line 1405 of file core_armv8mml.h.

TPI_DEVTYPE_SubType_Pos [4/18]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

Definition at line 886 of file core_cm23.h.

TPI_DEVTYPE_SubType_Pos [5/18]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

Definition at line 1140 of file core_cm3.h.

TPI_DEVTYPE_SubType_Pos [6/18]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

Definition at line 1480 of file core_cm33.h.

TPI_DEVTYPE_SubType_Pos [7/18]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

Definition at line 1480 of file core_cm35p.h.

TPI_DEVTYPE_SubType_Pos [8/18]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

Definition at line 1205 of file core_cm4.h.

TPI_DEVTYPE_SubType_Pos [9/18]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

Definition at line 2020 of file core_cm55.h.

TPI_DEVTYPE_SubType_Pos [10/18]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

Definition at line 1432 of file core_cm7.h.

TPI_DEVTYPE_SubType_Pos [11/18]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

Definition at line 1925 of file core_cm85.h.

TPI_DEVTYPE_SubType_Pos [12/18]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

Definition at line 1125 of file core_sc300.h.

TPI_DEVTYPE_SubType_Pos [13/18]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

Definition at line 1538 of file core_starmc1.h.

TPI_DEVTYPE_SubType_Pos [14/18]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

Definition at line 1467 of file core_armv81mml.h.

TPI_DEVTYPE_SubType_Pos [15/18]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

Definition at line 811 of file core_armv8mbl.h.

TPI_DEVTYPE_SubType_Pos [16/18]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

Definition at line 1405 of file core_armv8mml.h.

TPI_DEVTYPE_SubType_Pos [17/18]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

Definition at line 1480 of file core_cm33.h.

TPI_DEVTYPE_SubType_Pos [18/18]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

Definition at line 1205 of file core_cm4.h.

TPI_FFCR_EnFCont_Msk [1/14]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

Definition at line 781 of file core_armv8mbl.h.

TPI_FFCR_EnFCont_Msk [2/14]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

Definition at line 1375 of file core_armv8mml.h.

TPI_FFCR_EnFCont_Msk [3/14]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

Definition at line 789 of file core_cm23.h.

TPI_FFCR_EnFCont_Msk [4/14]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

Definition at line 1052 of file core_cm3.h.

TPI_FFCR_EnFCont_Msk [5/14]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

Definition at line 1383 of file core_cm33.h.

TPI_FFCR_EnFCont_Msk [6/14]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

Definition at line 1383 of file core_cm35p.h.

TPI_FFCR_EnFCont_Msk [7/14]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

Definition at line 1117 of file core_cm4.h.

TPI_FFCR_EnFCont_Msk [8/14]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

Definition at line 1344 of file core_cm7.h.

TPI_FFCR_EnFCont_Msk [9/14]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

Definition at line 1037 of file core_sc300.h.

TPI_FFCR_EnFCont_Msk [10/14]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

Definition at line 1441 of file core_starmc1.h.

TPI_FFCR_EnFCont_Msk [11/14]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

Definition at line 781 of file core_armv8mbl.h.

TPI_FFCR_EnFCont_Msk [12/14]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

Definition at line 1375 of file core_armv8mml.h.

TPI_FFCR_EnFCont_Msk [13/14]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

Definition at line 1383 of file core_cm33.h.

TPI_FFCR_EnFCont_Msk [14/14]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

Definition at line 1117 of file core_cm4.h.

TPI_FFCR_EnFCont_Pos [1/14]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

Definition at line 780 of file core_armv8mbl.h.

TPI_FFCR_EnFCont_Pos [2/14]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

Definition at line 1374 of file core_armv8mml.h.

TPI_FFCR_EnFCont_Pos [3/14]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

Definition at line 788 of file core_cm23.h.

TPI_FFCR_EnFCont_Pos [4/14]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

Definition at line 1051 of file core_cm3.h.

TPI_FFCR_EnFCont_Pos [5/14]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

Definition at line 1382 of file core_cm33.h.

TPI_FFCR_EnFCont_Pos [6/14]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

Definition at line 1382 of file core_cm35p.h.

TPI_FFCR_EnFCont_Pos [7/14]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

Definition at line 1116 of file core_cm4.h.

TPI_FFCR_EnFCont_Pos [8/14]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

Definition at line 1343 of file core_cm7.h.

TPI_FFCR_EnFCont_Pos [9/14]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

Definition at line 1036 of file core_sc300.h.

TPI_FFCR_EnFCont_Pos [10/14]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

Definition at line 1440 of file core_starmc1.h.

TPI_FFCR_EnFCont_Pos [11/14]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

Definition at line 780 of file core_armv8mbl.h.

TPI_FFCR_EnFCont_Pos [12/14]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

Definition at line 1374 of file core_armv8mml.h.

TPI_FFCR_EnFCont_Pos [13/14]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

Definition at line 1382 of file core_cm33.h.

TPI_FFCR_EnFCont_Pos [14/14]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

Definition at line 1116 of file core_cm4.h.

TPI_FFCR_EnFmt_Msk [1/4]

#define TPI_FFCR_EnFmt_Msk   (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)

TPI FFCR: EnFmt Mask

Definition at line 1437 of file core_armv81mml.h.

TPI_FFCR_EnFmt_Msk [2/4]

#define TPI_FFCR_EnFmt_Msk   (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)

TPI FFCR: EnFmt Mask

Definition at line 1990 of file core_cm55.h.

TPI_FFCR_EnFmt_Msk [3/4]

#define TPI_FFCR_EnFmt_Msk   (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)

TPI FFCR: EnFmt Mask

Definition at line 1895 of file core_cm85.h.

TPI_FFCR_EnFmt_Msk [4/4]

#define TPI_FFCR_EnFmt_Msk   (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)

TPI FFCR: EnFmt Mask

Definition at line 1437 of file core_armv81mml.h.

TPI_FFCR_EnFmt_Pos [1/4]

#define TPI_FFCR_EnFmt_Pos   0U

TPI FFCR: EnFmt Position

Definition at line 1436 of file core_armv81mml.h.

TPI_FFCR_EnFmt_Pos [2/4]

#define TPI_FFCR_EnFmt_Pos   0U

TPI FFCR: EnFmt Position

Definition at line 1989 of file core_cm55.h.

TPI_FFCR_EnFmt_Pos [3/4]

#define TPI_FFCR_EnFmt_Pos   0U

TPI FFCR: EnFmt Position

Definition at line 1894 of file core_cm85.h.

TPI_FFCR_EnFmt_Pos [4/4]

#define TPI_FFCR_EnFmt_Pos   0U

TPI FFCR: EnFmt Position

Definition at line 1436 of file core_armv81mml.h.

TPI_FFCR_FOnMan_Msk [1/13]

#define TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)

TPI FFCR: FOnMan Mask

Definition at line 1434 of file core_armv81mml.h.

TPI_FFCR_FOnMan_Msk [2/13]

#define TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)

TPI FFCR: FOnMan Mask

Definition at line 778 of file core_armv8mbl.h.

TPI_FFCR_FOnMan_Msk [3/13]

#define TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)

TPI FFCR: FOnMan Mask

Definition at line 1372 of file core_armv8mml.h.

TPI_FFCR_FOnMan_Msk [4/13]

#define TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)

TPI FFCR: FOnMan Mask

Definition at line 786 of file core_cm23.h.

TPI_FFCR_FOnMan_Msk [5/13]

#define TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)

TPI FFCR: FOnMan Mask

Definition at line 1380 of file core_cm33.h.

TPI_FFCR_FOnMan_Msk [6/13]

#define TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)

TPI FFCR: FOnMan Mask

Definition at line 1380 of file core_cm35p.h.

TPI_FFCR_FOnMan_Msk [7/13]

#define TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)

TPI FFCR: FOnMan Mask

Definition at line 1987 of file core_cm55.h.

TPI_FFCR_FOnMan_Msk [8/13]

#define TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)

TPI FFCR: FOnMan Mask

Definition at line 1892 of file core_cm85.h.

TPI_FFCR_FOnMan_Msk [9/13]

#define TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)

TPI FFCR: FOnMan Mask

Definition at line 1438 of file core_starmc1.h.

TPI_FFCR_FOnMan_Msk [10/13]

#define TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)

TPI FFCR: FOnMan Mask

Definition at line 1434 of file core_armv81mml.h.

TPI_FFCR_FOnMan_Msk [11/13]

#define TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)

TPI FFCR: FOnMan Mask

Definition at line 778 of file core_armv8mbl.h.

TPI_FFCR_FOnMan_Msk [12/13]

#define TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)

TPI FFCR: FOnMan Mask

Definition at line 1372 of file core_armv8mml.h.

TPI_FFCR_FOnMan_Msk [13/13]

#define TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)

TPI FFCR: FOnMan Mask

Definition at line 1380 of file core_cm33.h.

TPI_FFCR_FOnMan_Pos [1/13]

#define TPI_FFCR_FOnMan_Pos   6U

TPI FFCR: FOnMan Position

Definition at line 1433 of file core_armv81mml.h.

TPI_FFCR_FOnMan_Pos [2/13]

#define TPI_FFCR_FOnMan_Pos   6U

TPI FFCR: FOnMan Position

Definition at line 777 of file core_armv8mbl.h.

TPI_FFCR_FOnMan_Pos [3/13]

#define TPI_FFCR_FOnMan_Pos   6U

TPI FFCR: FOnMan Position

Definition at line 1371 of file core_armv8mml.h.

TPI_FFCR_FOnMan_Pos [4/13]

#define TPI_FFCR_FOnMan_Pos   6U

TPI FFCR: FOnMan Position

Definition at line 785 of file core_cm23.h.

TPI_FFCR_FOnMan_Pos [5/13]

#define TPI_FFCR_FOnMan_Pos   6U

TPI FFCR: FOnMan Position

Definition at line 1379 of file core_cm33.h.

TPI_FFCR_FOnMan_Pos [6/13]

#define TPI_FFCR_FOnMan_Pos   6U

TPI FFCR: FOnMan Position

Definition at line 1379 of file core_cm35p.h.

TPI_FFCR_FOnMan_Pos [7/13]

#define TPI_FFCR_FOnMan_Pos   6U

TPI FFCR: FOnMan Position

Definition at line 1986 of file core_cm55.h.

TPI_FFCR_FOnMan_Pos [8/13]

#define TPI_FFCR_FOnMan_Pos   6U

TPI FFCR: FOnMan Position

Definition at line 1891 of file core_cm85.h.

TPI_FFCR_FOnMan_Pos [9/13]

#define TPI_FFCR_FOnMan_Pos   6U

TPI FFCR: FOnMan Position

Definition at line 1437 of file core_starmc1.h.

TPI_FFCR_FOnMan_Pos [10/13]

#define TPI_FFCR_FOnMan_Pos   6U

TPI FFCR: FOnMan Position

Definition at line 1433 of file core_armv81mml.h.

TPI_FFCR_FOnMan_Pos [11/13]

#define TPI_FFCR_FOnMan_Pos   6U

TPI FFCR: FOnMan Position

Definition at line 777 of file core_armv8mbl.h.

TPI_FFCR_FOnMan_Pos [12/13]

#define TPI_FFCR_FOnMan_Pos   6U

TPI FFCR: FOnMan Position

Definition at line 1371 of file core_armv8mml.h.

TPI_FFCR_FOnMan_Pos [13/13]

#define TPI_FFCR_FOnMan_Pos   6U

TPI FFCR: FOnMan Position

Definition at line 1379 of file core_cm33.h.

TPI_FFCR_TrigIn_Msk [1/18]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

Definition at line 1431 of file core_armv81mml.h.

TPI_FFCR_TrigIn_Msk [2/18]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

Definition at line 775 of file core_armv8mbl.h.

TPI_FFCR_TrigIn_Msk [3/18]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

Definition at line 1369 of file core_armv8mml.h.

TPI_FFCR_TrigIn_Msk [4/18]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

Definition at line 783 of file core_cm23.h.

TPI_FFCR_TrigIn_Msk [5/18]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

Definition at line 1049 of file core_cm3.h.

TPI_FFCR_TrigIn_Msk [6/18]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

Definition at line 1377 of file core_cm33.h.

TPI_FFCR_TrigIn_Msk [7/18]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

Definition at line 1377 of file core_cm35p.h.

TPI_FFCR_TrigIn_Msk [8/18]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

Definition at line 1114 of file core_cm4.h.

TPI_FFCR_TrigIn_Msk [9/18]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

Definition at line 1984 of file core_cm55.h.

TPI_FFCR_TrigIn_Msk [10/18]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

Definition at line 1341 of file core_cm7.h.

TPI_FFCR_TrigIn_Msk [11/18]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

Definition at line 1889 of file core_cm85.h.

TPI_FFCR_TrigIn_Msk [12/18]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

Definition at line 1034 of file core_sc300.h.

TPI_FFCR_TrigIn_Msk [13/18]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

Definition at line 1435 of file core_starmc1.h.

TPI_FFCR_TrigIn_Msk [14/18]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

Definition at line 1431 of file core_armv81mml.h.

TPI_FFCR_TrigIn_Msk [15/18]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

Definition at line 775 of file core_armv8mbl.h.

TPI_FFCR_TrigIn_Msk [16/18]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

Definition at line 1369 of file core_armv8mml.h.

TPI_FFCR_TrigIn_Msk [17/18]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

Definition at line 1377 of file core_cm33.h.

TPI_FFCR_TrigIn_Msk [18/18]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

Definition at line 1114 of file core_cm4.h.

TPI_FFCR_TrigIn_Pos [1/18]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

Definition at line 1430 of file core_armv81mml.h.

TPI_FFCR_TrigIn_Pos [2/18]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

Definition at line 774 of file core_armv8mbl.h.

TPI_FFCR_TrigIn_Pos [3/18]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

Definition at line 1368 of file core_armv8mml.h.

TPI_FFCR_TrigIn_Pos [4/18]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

Definition at line 782 of file core_cm23.h.

TPI_FFCR_TrigIn_Pos [5/18]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

Definition at line 1048 of file core_cm3.h.

TPI_FFCR_TrigIn_Pos [6/18]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

Definition at line 1376 of file core_cm33.h.

TPI_FFCR_TrigIn_Pos [7/18]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

Definition at line 1376 of file core_cm35p.h.

TPI_FFCR_TrigIn_Pos [8/18]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

Definition at line 1113 of file core_cm4.h.

TPI_FFCR_TrigIn_Pos [9/18]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

Definition at line 1983 of file core_cm55.h.

TPI_FFCR_TrigIn_Pos [10/18]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

Definition at line 1340 of file core_cm7.h.

TPI_FFCR_TrigIn_Pos [11/18]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

Definition at line 1888 of file core_cm85.h.

TPI_FFCR_TrigIn_Pos [12/18]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

Definition at line 1033 of file core_sc300.h.

TPI_FFCR_TrigIn_Pos [13/18]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

Definition at line 1434 of file core_starmc1.h.

TPI_FFCR_TrigIn_Pos [14/18]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

Definition at line 1430 of file core_armv81mml.h.

TPI_FFCR_TrigIn_Pos [15/18]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

Definition at line 774 of file core_armv8mbl.h.

TPI_FFCR_TrigIn_Pos [16/18]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

Definition at line 1368 of file core_armv8mml.h.

TPI_FFCR_TrigIn_Pos [17/18]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

Definition at line 1376 of file core_cm33.h.

TPI_FFCR_TrigIn_Pos [18/18]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

Definition at line 1113 of file core_cm4.h.

TPI_FFSR_FlInProg_Msk [1/18]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

Definition at line 1427 of file core_armv81mml.h.

TPI_FFSR_FlInProg_Msk [2/18]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

Definition at line 771 of file core_armv8mbl.h.

TPI_FFSR_FlInProg_Msk [3/18]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

Definition at line 1365 of file core_armv8mml.h.

TPI_FFSR_FlInProg_Msk [4/18]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

Definition at line 779 of file core_cm23.h.

TPI_FFSR_FlInProg_Msk [5/18]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

Definition at line 1045 of file core_cm3.h.

TPI_FFSR_FlInProg_Msk [6/18]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

Definition at line 1373 of file core_cm33.h.

TPI_FFSR_FlInProg_Msk [7/18]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

Definition at line 1373 of file core_cm35p.h.

TPI_FFSR_FlInProg_Msk [8/18]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

Definition at line 1110 of file core_cm4.h.

TPI_FFSR_FlInProg_Msk [9/18]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

Definition at line 1980 of file core_cm55.h.

TPI_FFSR_FlInProg_Msk [10/18]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

Definition at line 1337 of file core_cm7.h.

TPI_FFSR_FlInProg_Msk [11/18]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

Definition at line 1885 of file core_cm85.h.

TPI_FFSR_FlInProg_Msk [12/18]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

Definition at line 1030 of file core_sc300.h.

TPI_FFSR_FlInProg_Msk [13/18]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

Definition at line 1431 of file core_starmc1.h.

TPI_FFSR_FlInProg_Msk [14/18]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

Definition at line 1427 of file core_armv81mml.h.

TPI_FFSR_FlInProg_Msk [15/18]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

Definition at line 771 of file core_armv8mbl.h.

TPI_FFSR_FlInProg_Msk [16/18]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

Definition at line 1365 of file core_armv8mml.h.

TPI_FFSR_FlInProg_Msk [17/18]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

Definition at line 1373 of file core_cm33.h.

TPI_FFSR_FlInProg_Msk [18/18]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

Definition at line 1110 of file core_cm4.h.

TPI_FFSR_FlInProg_Pos [1/18]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

Definition at line 1426 of file core_armv81mml.h.

TPI_FFSR_FlInProg_Pos [2/18]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

Definition at line 770 of file core_armv8mbl.h.

TPI_FFSR_FlInProg_Pos [3/18]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

Definition at line 1364 of file core_armv8mml.h.

TPI_FFSR_FlInProg_Pos [4/18]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

Definition at line 778 of file core_cm23.h.

TPI_FFSR_FlInProg_Pos [5/18]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

Definition at line 1044 of file core_cm3.h.

TPI_FFSR_FlInProg_Pos [6/18]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

Definition at line 1372 of file core_cm33.h.

TPI_FFSR_FlInProg_Pos [7/18]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

Definition at line 1372 of file core_cm35p.h.

TPI_FFSR_FlInProg_Pos [8/18]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

Definition at line 1109 of file core_cm4.h.

TPI_FFSR_FlInProg_Pos [9/18]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

Definition at line 1979 of file core_cm55.h.

TPI_FFSR_FlInProg_Pos [10/18]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

Definition at line 1336 of file core_cm7.h.

TPI_FFSR_FlInProg_Pos [11/18]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

Definition at line 1884 of file core_cm85.h.

TPI_FFSR_FlInProg_Pos [12/18]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

Definition at line 1029 of file core_sc300.h.

TPI_FFSR_FlInProg_Pos [13/18]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

Definition at line 1430 of file core_starmc1.h.

TPI_FFSR_FlInProg_Pos [14/18]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

Definition at line 1426 of file core_armv81mml.h.

TPI_FFSR_FlInProg_Pos [15/18]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

Definition at line 770 of file core_armv8mbl.h.

TPI_FFSR_FlInProg_Pos [16/18]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

Definition at line 1364 of file core_armv8mml.h.

TPI_FFSR_FlInProg_Pos [17/18]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

Definition at line 1372 of file core_cm33.h.

TPI_FFSR_FlInProg_Pos [18/18]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

Definition at line 1109 of file core_cm4.h.

TPI_FFSR_FtNonStop_Msk [1/18]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

Definition at line 1418 of file core_armv81mml.h.

TPI_FFSR_FtNonStop_Msk [2/18]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

Definition at line 762 of file core_armv8mbl.h.

TPI_FFSR_FtNonStop_Msk [3/18]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

Definition at line 1356 of file core_armv8mml.h.

TPI_FFSR_FtNonStop_Msk [4/18]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

Definition at line 770 of file core_cm23.h.

TPI_FFSR_FtNonStop_Msk [5/18]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

Definition at line 1036 of file core_cm3.h.

TPI_FFSR_FtNonStop_Msk [6/18]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

Definition at line 1364 of file core_cm33.h.

TPI_FFSR_FtNonStop_Msk [7/18]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

Definition at line 1364 of file core_cm35p.h.

TPI_FFSR_FtNonStop_Msk [8/18]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

Definition at line 1101 of file core_cm4.h.

TPI_FFSR_FtNonStop_Msk [9/18]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

Definition at line 1971 of file core_cm55.h.

TPI_FFSR_FtNonStop_Msk [10/18]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

Definition at line 1328 of file core_cm7.h.

TPI_FFSR_FtNonStop_Msk [11/18]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

Definition at line 1876 of file core_cm85.h.

TPI_FFSR_FtNonStop_Msk [12/18]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

Definition at line 1021 of file core_sc300.h.

TPI_FFSR_FtNonStop_Msk [13/18]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

Definition at line 1422 of file core_starmc1.h.

TPI_FFSR_FtNonStop_Msk [14/18]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

Definition at line 1418 of file core_armv81mml.h.

TPI_FFSR_FtNonStop_Msk [15/18]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

Definition at line 762 of file core_armv8mbl.h.

TPI_FFSR_FtNonStop_Msk [16/18]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

Definition at line 1356 of file core_armv8mml.h.

TPI_FFSR_FtNonStop_Msk [17/18]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

Definition at line 1364 of file core_cm33.h.

TPI_FFSR_FtNonStop_Msk [18/18]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

Definition at line 1101 of file core_cm4.h.

TPI_FFSR_FtNonStop_Pos [1/18]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

Definition at line 1417 of file core_armv81mml.h.

TPI_FFSR_FtNonStop_Pos [2/18]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

Definition at line 761 of file core_armv8mbl.h.

TPI_FFSR_FtNonStop_Pos [3/18]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

Definition at line 1355 of file core_armv8mml.h.

TPI_FFSR_FtNonStop_Pos [4/18]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

Definition at line 769 of file core_cm23.h.

TPI_FFSR_FtNonStop_Pos [5/18]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

Definition at line 1035 of file core_cm3.h.

TPI_FFSR_FtNonStop_Pos [6/18]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

Definition at line 1363 of file core_cm33.h.

TPI_FFSR_FtNonStop_Pos [7/18]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

Definition at line 1363 of file core_cm35p.h.

TPI_FFSR_FtNonStop_Pos [8/18]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

Definition at line 1100 of file core_cm4.h.

TPI_FFSR_FtNonStop_Pos [9/18]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

Definition at line 1970 of file core_cm55.h.

TPI_FFSR_FtNonStop_Pos [10/18]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

Definition at line 1327 of file core_cm7.h.

TPI_FFSR_FtNonStop_Pos [11/18]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

Definition at line 1875 of file core_cm85.h.

TPI_FFSR_FtNonStop_Pos [12/18]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

Definition at line 1020 of file core_sc300.h.

TPI_FFSR_FtNonStop_Pos [13/18]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

Definition at line 1421 of file core_starmc1.h.

TPI_FFSR_FtNonStop_Pos [14/18]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

Definition at line 1417 of file core_armv81mml.h.

TPI_FFSR_FtNonStop_Pos [15/18]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

Definition at line 761 of file core_armv8mbl.h.

TPI_FFSR_FtNonStop_Pos [16/18]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

Definition at line 1355 of file core_armv8mml.h.

TPI_FFSR_FtNonStop_Pos [17/18]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

Definition at line 1363 of file core_cm33.h.

TPI_FFSR_FtNonStop_Pos [18/18]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

Definition at line 1100 of file core_cm4.h.

TPI_FFSR_FtStopped_Msk [1/18]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

Definition at line 1424 of file core_armv81mml.h.

TPI_FFSR_FtStopped_Msk [2/18]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

Definition at line 768 of file core_armv8mbl.h.

TPI_FFSR_FtStopped_Msk [3/18]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

Definition at line 1362 of file core_armv8mml.h.

TPI_FFSR_FtStopped_Msk [4/18]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

Definition at line 776 of file core_cm23.h.

TPI_FFSR_FtStopped_Msk [5/18]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

Definition at line 1042 of file core_cm3.h.

TPI_FFSR_FtStopped_Msk [6/18]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

Definition at line 1370 of file core_cm33.h.

TPI_FFSR_FtStopped_Msk [7/18]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

Definition at line 1370 of file core_cm35p.h.

TPI_FFSR_FtStopped_Msk [8/18]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

Definition at line 1107 of file core_cm4.h.

TPI_FFSR_FtStopped_Msk [9/18]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

Definition at line 1977 of file core_cm55.h.

TPI_FFSR_FtStopped_Msk [10/18]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

Definition at line 1334 of file core_cm7.h.

TPI_FFSR_FtStopped_Msk [11/18]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

Definition at line 1882 of file core_cm85.h.

TPI_FFSR_FtStopped_Msk [12/18]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

Definition at line 1027 of file core_sc300.h.

TPI_FFSR_FtStopped_Msk [13/18]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

Definition at line 1428 of file core_starmc1.h.

TPI_FFSR_FtStopped_Msk [14/18]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

Definition at line 1424 of file core_armv81mml.h.

TPI_FFSR_FtStopped_Msk [15/18]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

Definition at line 768 of file core_armv8mbl.h.

TPI_FFSR_FtStopped_Msk [16/18]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

Definition at line 1362 of file core_armv8mml.h.

TPI_FFSR_FtStopped_Msk [17/18]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

Definition at line 1370 of file core_cm33.h.

TPI_FFSR_FtStopped_Msk [18/18]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

Definition at line 1107 of file core_cm4.h.

TPI_FFSR_FtStopped_Pos [1/18]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

Definition at line 1423 of file core_armv81mml.h.

TPI_FFSR_FtStopped_Pos [2/18]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

Definition at line 767 of file core_armv8mbl.h.

TPI_FFSR_FtStopped_Pos [3/18]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

Definition at line 1361 of file core_armv8mml.h.

TPI_FFSR_FtStopped_Pos [4/18]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

Definition at line 775 of file core_cm23.h.

TPI_FFSR_FtStopped_Pos [5/18]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

Definition at line 1041 of file core_cm3.h.

TPI_FFSR_FtStopped_Pos [6/18]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

Definition at line 1369 of file core_cm33.h.

TPI_FFSR_FtStopped_Pos [7/18]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

Definition at line 1369 of file core_cm35p.h.

TPI_FFSR_FtStopped_Pos [8/18]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

Definition at line 1106 of file core_cm4.h.

TPI_FFSR_FtStopped_Pos [9/18]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

Definition at line 1976 of file core_cm55.h.

TPI_FFSR_FtStopped_Pos [10/18]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

Definition at line 1333 of file core_cm7.h.

TPI_FFSR_FtStopped_Pos [11/18]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

Definition at line 1881 of file core_cm85.h.

TPI_FFSR_FtStopped_Pos [12/18]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

Definition at line 1026 of file core_sc300.h.

TPI_FFSR_FtStopped_Pos [13/18]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

Definition at line 1427 of file core_starmc1.h.

TPI_FFSR_FtStopped_Pos [14/18]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

Definition at line 1423 of file core_armv81mml.h.

TPI_FFSR_FtStopped_Pos [15/18]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

Definition at line 767 of file core_armv8mbl.h.

TPI_FFSR_FtStopped_Pos [16/18]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

Definition at line 1361 of file core_armv8mml.h.

TPI_FFSR_FtStopped_Pos [17/18]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

Definition at line 1369 of file core_cm33.h.

TPI_FFSR_FtStopped_Pos [18/18]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

Definition at line 1106 of file core_cm4.h.

TPI_FFSR_TCPresent_Msk [1/18]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

Definition at line 1421 of file core_armv81mml.h.

TPI_FFSR_TCPresent_Msk [2/18]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

Definition at line 765 of file core_armv8mbl.h.

TPI_FFSR_TCPresent_Msk [3/18]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

Definition at line 1359 of file core_armv8mml.h.

TPI_FFSR_TCPresent_Msk [4/18]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

Definition at line 773 of file core_cm23.h.

TPI_FFSR_TCPresent_Msk [5/18]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

Definition at line 1039 of file core_cm3.h.

TPI_FFSR_TCPresent_Msk [6/18]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

Definition at line 1367 of file core_cm33.h.

TPI_FFSR_TCPresent_Msk [7/18]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

Definition at line 1367 of file core_cm35p.h.

TPI_FFSR_TCPresent_Msk [8/18]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

Definition at line 1104 of file core_cm4.h.

TPI_FFSR_TCPresent_Msk [9/18]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

Definition at line 1974 of file core_cm55.h.

TPI_FFSR_TCPresent_Msk [10/18]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

Definition at line 1331 of file core_cm7.h.

TPI_FFSR_TCPresent_Msk [11/18]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

Definition at line 1879 of file core_cm85.h.

TPI_FFSR_TCPresent_Msk [12/18]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

Definition at line 1024 of file core_sc300.h.

TPI_FFSR_TCPresent_Msk [13/18]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

Definition at line 1425 of file core_starmc1.h.

TPI_FFSR_TCPresent_Msk [14/18]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

Definition at line 1421 of file core_armv81mml.h.

TPI_FFSR_TCPresent_Msk [15/18]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

Definition at line 765 of file core_armv8mbl.h.

TPI_FFSR_TCPresent_Msk [16/18]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

Definition at line 1359 of file core_armv8mml.h.

TPI_FFSR_TCPresent_Msk [17/18]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

Definition at line 1367 of file core_cm33.h.

TPI_FFSR_TCPresent_Msk [18/18]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

Definition at line 1104 of file core_cm4.h.

TPI_FFSR_TCPresent_Pos [1/18]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

Definition at line 1420 of file core_armv81mml.h.

TPI_FFSR_TCPresent_Pos [2/18]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

Definition at line 764 of file core_armv8mbl.h.

TPI_FFSR_TCPresent_Pos [3/18]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

Definition at line 1358 of file core_armv8mml.h.

TPI_FFSR_TCPresent_Pos [4/18]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

Definition at line 772 of file core_cm23.h.

TPI_FFSR_TCPresent_Pos [5/18]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

Definition at line 1038 of file core_cm3.h.

TPI_FFSR_TCPresent_Pos [6/18]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

Definition at line 1366 of file core_cm33.h.

TPI_FFSR_TCPresent_Pos [7/18]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

Definition at line 1366 of file core_cm35p.h.

TPI_FFSR_TCPresent_Pos [8/18]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

Definition at line 1103 of file core_cm4.h.

TPI_FFSR_TCPresent_Pos [9/18]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

Definition at line 1973 of file core_cm55.h.

TPI_FFSR_TCPresent_Pos [10/18]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

Definition at line 1330 of file core_cm7.h.

TPI_FFSR_TCPresent_Pos [11/18]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

Definition at line 1878 of file core_cm85.h.

TPI_FFSR_TCPresent_Pos [12/18]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

Definition at line 1023 of file core_sc300.h.

TPI_FFSR_TCPresent_Pos [13/18]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

Definition at line 1424 of file core_starmc1.h.

TPI_FFSR_TCPresent_Pos [14/18]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

Definition at line 1420 of file core_armv81mml.h.

TPI_FFSR_TCPresent_Pos [15/18]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

Definition at line 764 of file core_armv8mbl.h.

TPI_FFSR_TCPresent_Pos [16/18]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

Definition at line 1358 of file core_armv8mml.h.

TPI_FFSR_TCPresent_Pos [17/18]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

Definition at line 1366 of file core_cm33.h.

TPI_FFSR_TCPresent_Pos [18/18]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

Definition at line 1103 of file core_cm4.h.

TPI_FIFO0_ETM0_Msk [1/5]

#define TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)

TPI FIFO0: ETM0 Mask

Definition at line 1078 of file core_cm3.h.

TPI_FIFO0_ETM0_Msk [2/5]

#define TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)

TPI FIFO0: ETM0 Mask

Definition at line 1143 of file core_cm4.h.

TPI_FIFO0_ETM0_Msk [3/5]

#define TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)

TPI FIFO0: ETM0 Mask

Definition at line 1370 of file core_cm7.h.

TPI_FIFO0_ETM0_Msk [4/5]

#define TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)

TPI FIFO0: ETM0 Mask

Definition at line 1063 of file core_sc300.h.

TPI_FIFO0_ETM0_Msk [5/5]

#define TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)

TPI FIFO0: ETM0 Mask

Definition at line 1143 of file core_cm4.h.

TPI_FIFO0_ETM0_Pos [1/5]

#define TPI_FIFO0_ETM0_Pos   0U

TPI FIFO0: ETM0 Position

Definition at line 1077 of file core_cm3.h.

TPI_FIFO0_ETM0_Pos [2/5]

#define TPI_FIFO0_ETM0_Pos   0U

TPI FIFO0: ETM0 Position

Definition at line 1142 of file core_cm4.h.

TPI_FIFO0_ETM0_Pos [3/5]

#define TPI_FIFO0_ETM0_Pos   0U

TPI FIFO0: ETM0 Position

Definition at line 1369 of file core_cm7.h.

TPI_FIFO0_ETM0_Pos [4/5]

#define TPI_FIFO0_ETM0_Pos   0U

TPI FIFO0: ETM0 Position

Definition at line 1062 of file core_sc300.h.

TPI_FIFO0_ETM0_Pos [5/5]

#define TPI_FIFO0_ETM0_Pos   0U

TPI FIFO0: ETM0 Position

Definition at line 1142 of file core_cm4.h.

TPI_FIFO0_ETM1_Msk [1/5]

#define TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)

TPI FIFO0: ETM1 Mask

Definition at line 1075 of file core_cm3.h.

TPI_FIFO0_ETM1_Msk [2/5]

#define TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)

TPI FIFO0: ETM1 Mask

Definition at line 1140 of file core_cm4.h.

TPI_FIFO0_ETM1_Msk [3/5]

#define TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)

TPI FIFO0: ETM1 Mask

Definition at line 1367 of file core_cm7.h.

TPI_FIFO0_ETM1_Msk [4/5]

#define TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)

TPI FIFO0: ETM1 Mask

Definition at line 1060 of file core_sc300.h.

TPI_FIFO0_ETM1_Msk [5/5]

#define TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)

TPI FIFO0: ETM1 Mask

Definition at line 1140 of file core_cm4.h.

TPI_FIFO0_ETM1_Pos [1/5]

#define TPI_FIFO0_ETM1_Pos   8U

TPI FIFO0: ETM1 Position

Definition at line 1074 of file core_cm3.h.

TPI_FIFO0_ETM1_Pos [2/5]

#define TPI_FIFO0_ETM1_Pos   8U

TPI FIFO0: ETM1 Position

Definition at line 1139 of file core_cm4.h.

TPI_FIFO0_ETM1_Pos [3/5]

#define TPI_FIFO0_ETM1_Pos   8U

TPI FIFO0: ETM1 Position

Definition at line 1366 of file core_cm7.h.

TPI_FIFO0_ETM1_Pos [4/5]

#define TPI_FIFO0_ETM1_Pos   8U

TPI FIFO0: ETM1 Position

Definition at line 1059 of file core_sc300.h.

TPI_FIFO0_ETM1_Pos [5/5]

#define TPI_FIFO0_ETM1_Pos   8U

TPI FIFO0: ETM1 Position

Definition at line 1139 of file core_cm4.h.

TPI_FIFO0_ETM2_Msk [1/5]

#define TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)

TPI FIFO0: ETM2 Mask

Definition at line 1072 of file core_cm3.h.

TPI_FIFO0_ETM2_Msk [2/5]

#define TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)

TPI FIFO0: ETM2 Mask

Definition at line 1137 of file core_cm4.h.

TPI_FIFO0_ETM2_Msk [3/5]

#define TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)

TPI FIFO0: ETM2 Mask

Definition at line 1364 of file core_cm7.h.

TPI_FIFO0_ETM2_Msk [4/5]

#define TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)

TPI FIFO0: ETM2 Mask

Definition at line 1057 of file core_sc300.h.

TPI_FIFO0_ETM2_Msk [5/5]

#define TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)

TPI FIFO0: ETM2 Mask

Definition at line 1137 of file core_cm4.h.

TPI_FIFO0_ETM2_Pos [1/5]

#define TPI_FIFO0_ETM2_Pos   16U

TPI FIFO0: ETM2 Position

Definition at line 1071 of file core_cm3.h.

TPI_FIFO0_ETM2_Pos [2/5]

#define TPI_FIFO0_ETM2_Pos   16U

TPI FIFO0: ETM2 Position

Definition at line 1136 of file core_cm4.h.

TPI_FIFO0_ETM2_Pos [3/5]

#define TPI_FIFO0_ETM2_Pos   16U

TPI FIFO0: ETM2 Position

Definition at line 1363 of file core_cm7.h.

TPI_FIFO0_ETM2_Pos [4/5]

#define TPI_FIFO0_ETM2_Pos   16U

TPI FIFO0: ETM2 Position

Definition at line 1056 of file core_sc300.h.

TPI_FIFO0_ETM2_Pos [5/5]

#define TPI_FIFO0_ETM2_Pos   16U

TPI FIFO0: ETM2 Position

Definition at line 1136 of file core_cm4.h.

TPI_FIFO0_ETM_ATVALID_Msk [1/5]

#define TPI_FIFO0_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)

TPI FIFO0: ETM_ATVALID Mask

Definition at line 1066 of file core_cm3.h.

TPI_FIFO0_ETM_ATVALID_Msk [2/5]

#define TPI_FIFO0_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)

TPI FIFO0: ETM_ATVALID Mask

Definition at line 1131 of file core_cm4.h.

TPI_FIFO0_ETM_ATVALID_Msk [3/5]

#define TPI_FIFO0_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)

TPI FIFO0: ETM_ATVALID Mask

Definition at line 1358 of file core_cm7.h.

TPI_FIFO0_ETM_ATVALID_Msk [4/5]

#define TPI_FIFO0_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)

TPI FIFO0: ETM_ATVALID Mask

Definition at line 1051 of file core_sc300.h.

TPI_FIFO0_ETM_ATVALID_Msk [5/5]

#define TPI_FIFO0_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)

TPI FIFO0: ETM_ATVALID Mask

Definition at line 1131 of file core_cm4.h.

TPI_FIFO0_ETM_ATVALID_Pos [1/5]

#define TPI_FIFO0_ETM_ATVALID_Pos   26U

TPI FIFO0: ETM_ATVALID Position

Definition at line 1065 of file core_cm3.h.

TPI_FIFO0_ETM_ATVALID_Pos [2/5]

#define TPI_FIFO0_ETM_ATVALID_Pos   26U

TPI FIFO0: ETM_ATVALID Position

Definition at line 1130 of file core_cm4.h.

TPI_FIFO0_ETM_ATVALID_Pos [3/5]

#define TPI_FIFO0_ETM_ATVALID_Pos   26U

TPI FIFO0: ETM_ATVALID Position

Definition at line 1357 of file core_cm7.h.

TPI_FIFO0_ETM_ATVALID_Pos [4/5]

#define TPI_FIFO0_ETM_ATVALID_Pos   26U

TPI FIFO0: ETM_ATVALID Position

Definition at line 1050 of file core_sc300.h.

TPI_FIFO0_ETM_ATVALID_Pos [5/5]

#define TPI_FIFO0_ETM_ATVALID_Pos   26U

TPI FIFO0: ETM_ATVALID Position

Definition at line 1130 of file core_cm4.h.

TPI_FIFO0_ETM_bytecount_Msk [1/5]

#define TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

TPI FIFO0: ETM_bytecount Mask

Definition at line 1069 of file core_cm3.h.

TPI_FIFO0_ETM_bytecount_Msk [2/5]

#define TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

TPI FIFO0: ETM_bytecount Mask

Definition at line 1134 of file core_cm4.h.

TPI_FIFO0_ETM_bytecount_Msk [3/5]

#define TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

TPI FIFO0: ETM_bytecount Mask

Definition at line 1361 of file core_cm7.h.

TPI_FIFO0_ETM_bytecount_Msk [4/5]

#define TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

TPI FIFO0: ETM_bytecount Mask

Definition at line 1054 of file core_sc300.h.

TPI_FIFO0_ETM_bytecount_Msk [5/5]

#define TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

TPI FIFO0: ETM_bytecount Mask

Definition at line 1134 of file core_cm4.h.

TPI_FIFO0_ETM_bytecount_Pos [1/5]

#define TPI_FIFO0_ETM_bytecount_Pos   24U

TPI FIFO0: ETM_bytecount Position

Definition at line 1068 of file core_cm3.h.

TPI_FIFO0_ETM_bytecount_Pos [2/5]

#define TPI_FIFO0_ETM_bytecount_Pos   24U

TPI FIFO0: ETM_bytecount Position

Definition at line 1133 of file core_cm4.h.

TPI_FIFO0_ETM_bytecount_Pos [3/5]

#define TPI_FIFO0_ETM_bytecount_Pos   24U

TPI FIFO0: ETM_bytecount Position

Definition at line 1360 of file core_cm7.h.

TPI_FIFO0_ETM_bytecount_Pos [4/5]

#define TPI_FIFO0_ETM_bytecount_Pos   24U

TPI FIFO0: ETM_bytecount Position

Definition at line 1053 of file core_sc300.h.

TPI_FIFO0_ETM_bytecount_Pos [5/5]

#define TPI_FIFO0_ETM_bytecount_Pos   24U

TPI FIFO0: ETM_bytecount Position

Definition at line 1133 of file core_cm4.h.

TPI_FIFO0_ITM_ATVALID_Msk [1/5]

#define TPI_FIFO0_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)

TPI FIFO0: ITM_ATVALID Mask

Definition at line 1060 of file core_cm3.h.

TPI_FIFO0_ITM_ATVALID_Msk [2/5]

#define TPI_FIFO0_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)

TPI FIFO0: ITM_ATVALID Mask

Definition at line 1125 of file core_cm4.h.

TPI_FIFO0_ITM_ATVALID_Msk [3/5]

#define TPI_FIFO0_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)

TPI FIFO0: ITM_ATVALID Mask

Definition at line 1352 of file core_cm7.h.

TPI_FIFO0_ITM_ATVALID_Msk [4/5]

#define TPI_FIFO0_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)

TPI FIFO0: ITM_ATVALID Mask

Definition at line 1045 of file core_sc300.h.

TPI_FIFO0_ITM_ATVALID_Msk [5/5]

#define TPI_FIFO0_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)

TPI FIFO0: ITM_ATVALID Mask

Definition at line 1125 of file core_cm4.h.

TPI_FIFO0_ITM_ATVALID_Pos [1/5]

#define TPI_FIFO0_ITM_ATVALID_Pos   29U

TPI FIFO0: ITM_ATVALID Position

Definition at line 1059 of file core_cm3.h.

TPI_FIFO0_ITM_ATVALID_Pos [2/5]

#define TPI_FIFO0_ITM_ATVALID_Pos   29U

TPI FIFO0: ITM_ATVALID Position

Definition at line 1124 of file core_cm4.h.

TPI_FIFO0_ITM_ATVALID_Pos [3/5]

#define TPI_FIFO0_ITM_ATVALID_Pos   29U

TPI FIFO0: ITM_ATVALID Position

Definition at line 1351 of file core_cm7.h.

TPI_FIFO0_ITM_ATVALID_Pos [4/5]

#define TPI_FIFO0_ITM_ATVALID_Pos   29U

TPI FIFO0: ITM_ATVALID Position

Definition at line 1044 of file core_sc300.h.

TPI_FIFO0_ITM_ATVALID_Pos [5/5]

#define TPI_FIFO0_ITM_ATVALID_Pos   29U

TPI FIFO0: ITM_ATVALID Position

Definition at line 1124 of file core_cm4.h.

TPI_FIFO0_ITM_bytecount_Msk [1/5]

#define TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

TPI FIFO0: ITM_bytecount Mask

Definition at line 1063 of file core_cm3.h.

TPI_FIFO0_ITM_bytecount_Msk [2/5]

#define TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

TPI FIFO0: ITM_bytecount Mask

Definition at line 1128 of file core_cm4.h.

TPI_FIFO0_ITM_bytecount_Msk [3/5]

#define TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

TPI FIFO0: ITM_bytecount Mask

Definition at line 1355 of file core_cm7.h.

TPI_FIFO0_ITM_bytecount_Msk [4/5]

#define TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

TPI FIFO0: ITM_bytecount Mask

Definition at line 1048 of file core_sc300.h.

TPI_FIFO0_ITM_bytecount_Msk [5/5]

#define TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

TPI FIFO0: ITM_bytecount Mask

Definition at line 1128 of file core_cm4.h.

TPI_FIFO0_ITM_bytecount_Pos [1/5]

#define TPI_FIFO0_ITM_bytecount_Pos   27U

TPI FIFO0: ITM_bytecount Position

Definition at line 1062 of file core_cm3.h.

TPI_FIFO0_ITM_bytecount_Pos [2/5]

#define TPI_FIFO0_ITM_bytecount_Pos   27U

TPI FIFO0: ITM_bytecount Position

Definition at line 1127 of file core_cm4.h.

TPI_FIFO0_ITM_bytecount_Pos [3/5]

#define TPI_FIFO0_ITM_bytecount_Pos   27U

TPI FIFO0: ITM_bytecount Position

Definition at line 1354 of file core_cm7.h.

TPI_FIFO0_ITM_bytecount_Pos [4/5]

#define TPI_FIFO0_ITM_bytecount_Pos   27U

TPI FIFO0: ITM_bytecount Position

Definition at line 1047 of file core_sc300.h.

TPI_FIFO0_ITM_bytecount_Pos [5/5]

#define TPI_FIFO0_ITM_bytecount_Pos   27U

TPI FIFO0: ITM_bytecount Position

Definition at line 1127 of file core_cm4.h.

TPI_FIFO1_ETM_ATVALID_Msk [1/5]

#define TPI_FIFO1_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)

TPI FIFO1: ETM_ATVALID Mask

Definition at line 1095 of file core_cm3.h.

TPI_FIFO1_ETM_ATVALID_Msk [2/5]

#define TPI_FIFO1_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)

TPI FIFO1: ETM_ATVALID Mask

Definition at line 1160 of file core_cm4.h.

TPI_FIFO1_ETM_ATVALID_Msk [3/5]

#define TPI_FIFO1_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)

TPI FIFO1: ETM_ATVALID Mask

Definition at line 1387 of file core_cm7.h.

TPI_FIFO1_ETM_ATVALID_Msk [4/5]

#define TPI_FIFO1_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)

TPI FIFO1: ETM_ATVALID Mask

Definition at line 1080 of file core_sc300.h.

TPI_FIFO1_ETM_ATVALID_Msk [5/5]

#define TPI_FIFO1_ETM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)

TPI FIFO1: ETM_ATVALID Mask

Definition at line 1160 of file core_cm4.h.

TPI_FIFO1_ETM_ATVALID_Pos [1/5]

#define TPI_FIFO1_ETM_ATVALID_Pos   26U

TPI FIFO1: ETM_ATVALID Position

Definition at line 1094 of file core_cm3.h.

TPI_FIFO1_ETM_ATVALID_Pos [2/5]

#define TPI_FIFO1_ETM_ATVALID_Pos   26U

TPI FIFO1: ETM_ATVALID Position

Definition at line 1159 of file core_cm4.h.

TPI_FIFO1_ETM_ATVALID_Pos [3/5]

#define TPI_FIFO1_ETM_ATVALID_Pos   26U

TPI FIFO1: ETM_ATVALID Position

Definition at line 1386 of file core_cm7.h.

TPI_FIFO1_ETM_ATVALID_Pos [4/5]

#define TPI_FIFO1_ETM_ATVALID_Pos   26U

TPI FIFO1: ETM_ATVALID Position

Definition at line 1079 of file core_sc300.h.

TPI_FIFO1_ETM_ATVALID_Pos [5/5]

#define TPI_FIFO1_ETM_ATVALID_Pos   26U

TPI FIFO1: ETM_ATVALID Position

Definition at line 1159 of file core_cm4.h.

TPI_FIFO1_ETM_bytecount_Msk [1/5]

#define TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

TPI FIFO1: ETM_bytecount Mask

Definition at line 1098 of file core_cm3.h.

TPI_FIFO1_ETM_bytecount_Msk [2/5]

#define TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

TPI FIFO1: ETM_bytecount Mask

Definition at line 1163 of file core_cm4.h.

TPI_FIFO1_ETM_bytecount_Msk [3/5]

#define TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

TPI FIFO1: ETM_bytecount Mask

Definition at line 1390 of file core_cm7.h.

TPI_FIFO1_ETM_bytecount_Msk [4/5]

#define TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

TPI FIFO1: ETM_bytecount Mask

Definition at line 1083 of file core_sc300.h.

TPI_FIFO1_ETM_bytecount_Msk [5/5]

#define TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

TPI FIFO1: ETM_bytecount Mask

Definition at line 1163 of file core_cm4.h.

TPI_FIFO1_ETM_bytecount_Pos [1/5]

#define TPI_FIFO1_ETM_bytecount_Pos   24U

TPI FIFO1: ETM_bytecount Position

Definition at line 1097 of file core_cm3.h.

TPI_FIFO1_ETM_bytecount_Pos [2/5]

#define TPI_FIFO1_ETM_bytecount_Pos   24U

TPI FIFO1: ETM_bytecount Position

Definition at line 1162 of file core_cm4.h.

TPI_FIFO1_ETM_bytecount_Pos [3/5]

#define TPI_FIFO1_ETM_bytecount_Pos   24U

TPI FIFO1: ETM_bytecount Position

Definition at line 1389 of file core_cm7.h.

TPI_FIFO1_ETM_bytecount_Pos [4/5]

#define TPI_FIFO1_ETM_bytecount_Pos   24U

TPI FIFO1: ETM_bytecount Position

Definition at line 1082 of file core_sc300.h.

TPI_FIFO1_ETM_bytecount_Pos [5/5]

#define TPI_FIFO1_ETM_bytecount_Pos   24U

TPI FIFO1: ETM_bytecount Position

Definition at line 1162 of file core_cm4.h.

TPI_FIFO1_ITM0_Msk [1/5]

#define TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)

TPI FIFO1: ITM0 Mask

Definition at line 1107 of file core_cm3.h.

TPI_FIFO1_ITM0_Msk [2/5]

#define TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)

TPI FIFO1: ITM0 Mask

Definition at line 1172 of file core_cm4.h.

TPI_FIFO1_ITM0_Msk [3/5]

#define TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)

TPI FIFO1: ITM0 Mask

Definition at line 1399 of file core_cm7.h.

TPI_FIFO1_ITM0_Msk [4/5]

#define TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)

TPI FIFO1: ITM0 Mask

Definition at line 1092 of file core_sc300.h.

TPI_FIFO1_ITM0_Msk [5/5]

#define TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)

TPI FIFO1: ITM0 Mask

Definition at line 1172 of file core_cm4.h.

TPI_FIFO1_ITM0_Pos [1/5]

#define TPI_FIFO1_ITM0_Pos   0U

TPI FIFO1: ITM0 Position

Definition at line 1106 of file core_cm3.h.

TPI_FIFO1_ITM0_Pos [2/5]

#define TPI_FIFO1_ITM0_Pos   0U

TPI FIFO1: ITM0 Position

Definition at line 1171 of file core_cm4.h.

TPI_FIFO1_ITM0_Pos [3/5]

#define TPI_FIFO1_ITM0_Pos   0U

TPI FIFO1: ITM0 Position

Definition at line 1398 of file core_cm7.h.

TPI_FIFO1_ITM0_Pos [4/5]

#define TPI_FIFO1_ITM0_Pos   0U

TPI FIFO1: ITM0 Position

Definition at line 1091 of file core_sc300.h.

TPI_FIFO1_ITM0_Pos [5/5]

#define TPI_FIFO1_ITM0_Pos   0U

TPI FIFO1: ITM0 Position

Definition at line 1171 of file core_cm4.h.

TPI_FIFO1_ITM1_Msk [1/5]

#define TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)

TPI FIFO1: ITM1 Mask

Definition at line 1104 of file core_cm3.h.

TPI_FIFO1_ITM1_Msk [2/5]

#define TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)

TPI FIFO1: ITM1 Mask

Definition at line 1169 of file core_cm4.h.

TPI_FIFO1_ITM1_Msk [3/5]

#define TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)

TPI FIFO1: ITM1 Mask

Definition at line 1396 of file core_cm7.h.

TPI_FIFO1_ITM1_Msk [4/5]

#define TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)

TPI FIFO1: ITM1 Mask

Definition at line 1089 of file core_sc300.h.

TPI_FIFO1_ITM1_Msk [5/5]

#define TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)

TPI FIFO1: ITM1 Mask

Definition at line 1169 of file core_cm4.h.

TPI_FIFO1_ITM1_Pos [1/5]

#define TPI_FIFO1_ITM1_Pos   8U

TPI FIFO1: ITM1 Position

Definition at line 1103 of file core_cm3.h.

TPI_FIFO1_ITM1_Pos [2/5]

#define TPI_FIFO1_ITM1_Pos   8U

TPI FIFO1: ITM1 Position

Definition at line 1168 of file core_cm4.h.

TPI_FIFO1_ITM1_Pos [3/5]

#define TPI_FIFO1_ITM1_Pos   8U

TPI FIFO1: ITM1 Position

Definition at line 1395 of file core_cm7.h.

TPI_FIFO1_ITM1_Pos [4/5]

#define TPI_FIFO1_ITM1_Pos   8U

TPI FIFO1: ITM1 Position

Definition at line 1088 of file core_sc300.h.

TPI_FIFO1_ITM1_Pos [5/5]

#define TPI_FIFO1_ITM1_Pos   8U

TPI FIFO1: ITM1 Position

Definition at line 1168 of file core_cm4.h.

TPI_FIFO1_ITM2_Msk [1/5]

#define TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)

TPI FIFO1: ITM2 Mask

Definition at line 1101 of file core_cm3.h.

TPI_FIFO1_ITM2_Msk [2/5]

#define TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)

TPI FIFO1: ITM2 Mask

Definition at line 1166 of file core_cm4.h.

TPI_FIFO1_ITM2_Msk [3/5]

#define TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)

TPI FIFO1: ITM2 Mask

Definition at line 1393 of file core_cm7.h.

TPI_FIFO1_ITM2_Msk [4/5]

#define TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)

TPI FIFO1: ITM2 Mask

Definition at line 1086 of file core_sc300.h.

TPI_FIFO1_ITM2_Msk [5/5]

#define TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)

TPI FIFO1: ITM2 Mask

Definition at line 1166 of file core_cm4.h.

TPI_FIFO1_ITM2_Pos [1/5]

#define TPI_FIFO1_ITM2_Pos   16U

TPI FIFO1: ITM2 Position

Definition at line 1100 of file core_cm3.h.

TPI_FIFO1_ITM2_Pos [2/5]

#define TPI_FIFO1_ITM2_Pos   16U

TPI FIFO1: ITM2 Position

Definition at line 1165 of file core_cm4.h.

TPI_FIFO1_ITM2_Pos [3/5]

#define TPI_FIFO1_ITM2_Pos   16U

TPI FIFO1: ITM2 Position

Definition at line 1392 of file core_cm7.h.

TPI_FIFO1_ITM2_Pos [4/5]

#define TPI_FIFO1_ITM2_Pos   16U

TPI FIFO1: ITM2 Position

Definition at line 1085 of file core_sc300.h.

TPI_FIFO1_ITM2_Pos [5/5]

#define TPI_FIFO1_ITM2_Pos   16U

TPI FIFO1: ITM2 Position

Definition at line 1165 of file core_cm4.h.

TPI_FIFO1_ITM_ATVALID_Msk [1/5]

#define TPI_FIFO1_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)

TPI FIFO1: ITM_ATVALID Mask

Definition at line 1089 of file core_cm3.h.

TPI_FIFO1_ITM_ATVALID_Msk [2/5]

#define TPI_FIFO1_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)

TPI FIFO1: ITM_ATVALID Mask

Definition at line 1154 of file core_cm4.h.

TPI_FIFO1_ITM_ATVALID_Msk [3/5]

#define TPI_FIFO1_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)

TPI FIFO1: ITM_ATVALID Mask

Definition at line 1381 of file core_cm7.h.

TPI_FIFO1_ITM_ATVALID_Msk [4/5]

#define TPI_FIFO1_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)

TPI FIFO1: ITM_ATVALID Mask

Definition at line 1074 of file core_sc300.h.

TPI_FIFO1_ITM_ATVALID_Msk [5/5]

#define TPI_FIFO1_ITM_ATVALID_Msk   (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)

TPI FIFO1: ITM_ATVALID Mask

Definition at line 1154 of file core_cm4.h.

TPI_FIFO1_ITM_ATVALID_Pos [1/5]

#define TPI_FIFO1_ITM_ATVALID_Pos   29U

TPI FIFO1: ITM_ATVALID Position

Definition at line 1088 of file core_cm3.h.

TPI_FIFO1_ITM_ATVALID_Pos [2/5]

#define TPI_FIFO1_ITM_ATVALID_Pos   29U

TPI FIFO1: ITM_ATVALID Position

Definition at line 1153 of file core_cm4.h.

TPI_FIFO1_ITM_ATVALID_Pos [3/5]

#define TPI_FIFO1_ITM_ATVALID_Pos   29U

TPI FIFO1: ITM_ATVALID Position

Definition at line 1380 of file core_cm7.h.

TPI_FIFO1_ITM_ATVALID_Pos [4/5]

#define TPI_FIFO1_ITM_ATVALID_Pos   29U

TPI FIFO1: ITM_ATVALID Position

Definition at line 1073 of file core_sc300.h.

TPI_FIFO1_ITM_ATVALID_Pos [5/5]

#define TPI_FIFO1_ITM_ATVALID_Pos   29U

TPI FIFO1: ITM_ATVALID Position

Definition at line 1153 of file core_cm4.h.

TPI_FIFO1_ITM_bytecount_Msk [1/5]

#define TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

TPI FIFO1: ITM_bytecount Mask

Definition at line 1092 of file core_cm3.h.

TPI_FIFO1_ITM_bytecount_Msk [2/5]

#define TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

TPI FIFO1: ITM_bytecount Mask

Definition at line 1157 of file core_cm4.h.

TPI_FIFO1_ITM_bytecount_Msk [3/5]

#define TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

TPI FIFO1: ITM_bytecount Mask

Definition at line 1384 of file core_cm7.h.

TPI_FIFO1_ITM_bytecount_Msk [4/5]

#define TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

TPI FIFO1: ITM_bytecount Mask

Definition at line 1077 of file core_sc300.h.

TPI_FIFO1_ITM_bytecount_Msk [5/5]

#define TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

TPI FIFO1: ITM_bytecount Mask

Definition at line 1157 of file core_cm4.h.

TPI_FIFO1_ITM_bytecount_Pos [1/5]

#define TPI_FIFO1_ITM_bytecount_Pos   27U

TPI FIFO1: ITM_bytecount Position

Definition at line 1091 of file core_cm3.h.

TPI_FIFO1_ITM_bytecount_Pos [2/5]

#define TPI_FIFO1_ITM_bytecount_Pos   27U

TPI FIFO1: ITM_bytecount Position

Definition at line 1156 of file core_cm4.h.

TPI_FIFO1_ITM_bytecount_Pos [3/5]

#define TPI_FIFO1_ITM_bytecount_Pos   27U

TPI FIFO1: ITM_bytecount Position

Definition at line 1383 of file core_cm7.h.

TPI_FIFO1_ITM_bytecount_Pos [4/5]

#define TPI_FIFO1_ITM_bytecount_Pos   27U

TPI FIFO1: ITM_bytecount Position

Definition at line 1076 of file core_sc300.h.

TPI_FIFO1_ITM_bytecount_Pos [5/5]

#define TPI_FIFO1_ITM_bytecount_Pos   27U

TPI FIFO1: ITM_bytecount Position

Definition at line 1156 of file core_cm4.h.

TPI_ITATBCTR0_AFVALID1S_Msk [1/5]

#define TPI_ITATBCTR0_AFVALID1S_Msk   (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)

TPI ITATBCTR0: AFVALID1SS Mask

Definition at line 857 of file core_cm23.h.

TPI_ITATBCTR0_AFVALID1S_Msk [2/5]

#define TPI_ITATBCTR0_AFVALID1S_Msk   (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)

TPI ITATBCTR0: AFVALID1SS Mask

Definition at line 1451 of file core_cm33.h.

TPI_ITATBCTR0_AFVALID1S_Msk [3/5]

#define TPI_ITATBCTR0_AFVALID1S_Msk   (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)

TPI ITATBCTR0: AFVALID1SS Mask

Definition at line 1451 of file core_cm35p.h.

TPI_ITATBCTR0_AFVALID1S_Msk [4/5]

#define TPI_ITATBCTR0_AFVALID1S_Msk   (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)

TPI ITATBCTR0: AFVALID1SS Mask

Definition at line 1509 of file core_starmc1.h.

TPI_ITATBCTR0_AFVALID1S_Msk [5/5]

#define TPI_ITATBCTR0_AFVALID1S_Msk   (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)

TPI ITATBCTR0: AFVALID1SS Mask

Definition at line 1451 of file core_cm33.h.

TPI_ITATBCTR0_AFVALID1S_Pos [1/5]

#define TPI_ITATBCTR0_AFVALID1S_Pos   1U

TPI ITATBCTR0: AFVALID1S Position

Definition at line 856 of file core_cm23.h.

TPI_ITATBCTR0_AFVALID1S_Pos [2/5]

#define TPI_ITATBCTR0_AFVALID1S_Pos   1U

TPI ITATBCTR0: AFVALID1S Position

Definition at line 1450 of file core_cm33.h.

TPI_ITATBCTR0_AFVALID1S_Pos [3/5]

#define TPI_ITATBCTR0_AFVALID1S_Pos   1U

TPI ITATBCTR0: AFVALID1S Position

Definition at line 1450 of file core_cm35p.h.

TPI_ITATBCTR0_AFVALID1S_Pos [4/5]

#define TPI_ITATBCTR0_AFVALID1S_Pos   1U

TPI ITATBCTR0: AFVALID1S Position

Definition at line 1508 of file core_starmc1.h.

TPI_ITATBCTR0_AFVALID1S_Pos [5/5]

#define TPI_ITATBCTR0_AFVALID1S_Pos   1U

TPI ITATBCTR0: AFVALID1S Position

Definition at line 1450 of file core_cm33.h.

TPI_ITATBCTR0_AFVALID2S_Msk [1/5]

#define TPI_ITATBCTR0_AFVALID2S_Msk   (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)

TPI ITATBCTR0: AFVALID2SS Mask

Definition at line 854 of file core_cm23.h.

TPI_ITATBCTR0_AFVALID2S_Msk [2/5]

#define TPI_ITATBCTR0_AFVALID2S_Msk   (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)

TPI ITATBCTR0: AFVALID2SS Mask

Definition at line 1448 of file core_cm33.h.

TPI_ITATBCTR0_AFVALID2S_Msk [3/5]

#define TPI_ITATBCTR0_AFVALID2S_Msk   (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)

TPI ITATBCTR0: AFVALID2SS Mask

Definition at line 1448 of file core_cm35p.h.

TPI_ITATBCTR0_AFVALID2S_Msk [4/5]

#define TPI_ITATBCTR0_AFVALID2S_Msk   (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)

TPI ITATBCTR0: AFVALID2SS Mask

Definition at line 1506 of file core_starmc1.h.

TPI_ITATBCTR0_AFVALID2S_Msk [5/5]

#define TPI_ITATBCTR0_AFVALID2S_Msk   (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)

TPI ITATBCTR0: AFVALID2SS Mask

Definition at line 1448 of file core_cm33.h.

TPI_ITATBCTR0_AFVALID2S_Pos [1/5]

#define TPI_ITATBCTR0_AFVALID2S_Pos   1U

TPI ITATBCTR0: AFVALID2S Position

Definition at line 853 of file core_cm23.h.

TPI_ITATBCTR0_AFVALID2S_Pos [2/5]

#define TPI_ITATBCTR0_AFVALID2S_Pos   1U

TPI ITATBCTR0: AFVALID2S Position

Definition at line 1447 of file core_cm33.h.

TPI_ITATBCTR0_AFVALID2S_Pos [3/5]

#define TPI_ITATBCTR0_AFVALID2S_Pos   1U

TPI ITATBCTR0: AFVALID2S Position

Definition at line 1447 of file core_cm35p.h.

TPI_ITATBCTR0_AFVALID2S_Pos [4/5]

#define TPI_ITATBCTR0_AFVALID2S_Pos   1U

TPI ITATBCTR0: AFVALID2S Position

Definition at line 1505 of file core_starmc1.h.

TPI_ITATBCTR0_AFVALID2S_Pos [5/5]

#define TPI_ITATBCTR0_AFVALID2S_Pos   1U

TPI ITATBCTR0: AFVALID2S Position

Definition at line 1447 of file core_cm33.h.

TPI_ITATBCTR0_ATREADY1_Msk [1/5]

#define TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)

TPI ITATBCTR0: ATREADY1 Mask

Definition at line 1114 of file core_cm3.h.

TPI_ITATBCTR0_ATREADY1_Msk [2/5]

#define TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)

TPI ITATBCTR0: ATREADY1 Mask

Definition at line 1179 of file core_cm4.h.

TPI_ITATBCTR0_ATREADY1_Msk [3/5]

#define TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)

TPI ITATBCTR0: ATREADY1 Mask

Definition at line 1406 of file core_cm7.h.

TPI_ITATBCTR0_ATREADY1_Msk [4/5]

#define TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)

TPI ITATBCTR0: ATREADY1 Mask

Definition at line 1099 of file core_sc300.h.

TPI_ITATBCTR0_ATREADY1_Msk [5/5]

#define TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)

TPI ITATBCTR0: ATREADY1 Mask

Definition at line 1179 of file core_cm4.h.

TPI_ITATBCTR0_ATREADY1_Pos [1/5]

#define TPI_ITATBCTR0_ATREADY1_Pos   0U

TPI ITATBCTR0: ATREADY1 Position

Definition at line 1113 of file core_cm3.h.

TPI_ITATBCTR0_ATREADY1_Pos [2/5]

#define TPI_ITATBCTR0_ATREADY1_Pos   0U

TPI ITATBCTR0: ATREADY1 Position

Definition at line 1178 of file core_cm4.h.

TPI_ITATBCTR0_ATREADY1_Pos [3/5]

#define TPI_ITATBCTR0_ATREADY1_Pos   0U

TPI ITATBCTR0: ATREADY1 Position

Definition at line 1405 of file core_cm7.h.

TPI_ITATBCTR0_ATREADY1_Pos [4/5]

#define TPI_ITATBCTR0_ATREADY1_Pos   0U

TPI ITATBCTR0: ATREADY1 Position

Definition at line 1098 of file core_sc300.h.

TPI_ITATBCTR0_ATREADY1_Pos [5/5]

#define TPI_ITATBCTR0_ATREADY1_Pos   0U

TPI ITATBCTR0: ATREADY1 Position

Definition at line 1178 of file core_cm4.h.

TPI_ITATBCTR0_ATREADY1S_Msk [1/5]

#define TPI_ITATBCTR0_ATREADY1S_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)

TPI ITATBCTR0: ATREADY1S Mask

Definition at line 863 of file core_cm23.h.

TPI_ITATBCTR0_ATREADY1S_Msk [2/5]

#define TPI_ITATBCTR0_ATREADY1S_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)

TPI ITATBCTR0: ATREADY1S Mask

Definition at line 1457 of file core_cm33.h.

TPI_ITATBCTR0_ATREADY1S_Msk [3/5]

#define TPI_ITATBCTR0_ATREADY1S_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)

TPI ITATBCTR0: ATREADY1S Mask

Definition at line 1457 of file core_cm35p.h.

TPI_ITATBCTR0_ATREADY1S_Msk [4/5]

#define TPI_ITATBCTR0_ATREADY1S_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)

TPI ITATBCTR0: ATREADY1S Mask

Definition at line 1515 of file core_starmc1.h.

TPI_ITATBCTR0_ATREADY1S_Msk [5/5]

#define TPI_ITATBCTR0_ATREADY1S_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)

TPI ITATBCTR0: ATREADY1S Mask

Definition at line 1457 of file core_cm33.h.

TPI_ITATBCTR0_ATREADY1S_Pos [1/5]

#define TPI_ITATBCTR0_ATREADY1S_Pos   0U

TPI ITATBCTR0: ATREADY1S Position

Definition at line 862 of file core_cm23.h.

TPI_ITATBCTR0_ATREADY1S_Pos [2/5]

#define TPI_ITATBCTR0_ATREADY1S_Pos   0U

TPI ITATBCTR0: ATREADY1S Position

Definition at line 1456 of file core_cm33.h.

TPI_ITATBCTR0_ATREADY1S_Pos [3/5]

#define TPI_ITATBCTR0_ATREADY1S_Pos   0U

TPI ITATBCTR0: ATREADY1S Position

Definition at line 1456 of file core_cm35p.h.

TPI_ITATBCTR0_ATREADY1S_Pos [4/5]

#define TPI_ITATBCTR0_ATREADY1S_Pos   0U

TPI ITATBCTR0: ATREADY1S Position

Definition at line 1514 of file core_starmc1.h.

TPI_ITATBCTR0_ATREADY1S_Pos [5/5]

#define TPI_ITATBCTR0_ATREADY1S_Pos   0U

TPI ITATBCTR0: ATREADY1S Position

Definition at line 1456 of file core_cm33.h.

TPI_ITATBCTR0_ATREADY2_Msk [1/5]

#define TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)

TPI ITATBCTR0: ATREADY2 Mask

Definition at line 1111 of file core_cm3.h.

TPI_ITATBCTR0_ATREADY2_Msk [2/5]

#define TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)

TPI ITATBCTR0: ATREADY2 Mask

Definition at line 1176 of file core_cm4.h.

TPI_ITATBCTR0_ATREADY2_Msk [3/5]

#define TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)

TPI ITATBCTR0: ATREADY2 Mask

Definition at line 1403 of file core_cm7.h.

TPI_ITATBCTR0_ATREADY2_Msk [4/5]

#define TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)

TPI ITATBCTR0: ATREADY2 Mask

Definition at line 1096 of file core_sc300.h.

TPI_ITATBCTR0_ATREADY2_Msk [5/5]

#define TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)

TPI ITATBCTR0: ATREADY2 Mask

Definition at line 1176 of file core_cm4.h.

TPI_ITATBCTR0_ATREADY2_Pos [1/5]

#define TPI_ITATBCTR0_ATREADY2_Pos   0U

TPI ITATBCTR0: ATREADY2 Position

Definition at line 1110 of file core_cm3.h.

TPI_ITATBCTR0_ATREADY2_Pos [2/5]

#define TPI_ITATBCTR0_ATREADY2_Pos   0U

TPI ITATBCTR0: ATREADY2 Position

Definition at line 1175 of file core_cm4.h.

TPI_ITATBCTR0_ATREADY2_Pos [3/5]

#define TPI_ITATBCTR0_ATREADY2_Pos   0U

TPI ITATBCTR0: ATREADY2 Position

Definition at line 1402 of file core_cm7.h.

TPI_ITATBCTR0_ATREADY2_Pos [4/5]

#define TPI_ITATBCTR0_ATREADY2_Pos   0U

TPI ITATBCTR0: ATREADY2 Position

Definition at line 1095 of file core_sc300.h.

TPI_ITATBCTR0_ATREADY2_Pos [5/5]

#define TPI_ITATBCTR0_ATREADY2_Pos   0U

TPI ITATBCTR0: ATREADY2 Position

Definition at line 1175 of file core_cm4.h.

TPI_ITATBCTR0_ATREADY2S_Msk [1/5]

#define TPI_ITATBCTR0_ATREADY2S_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)

TPI ITATBCTR0: ATREADY2S Mask

Definition at line 860 of file core_cm23.h.

TPI_ITATBCTR0_ATREADY2S_Msk [2/5]

#define TPI_ITATBCTR0_ATREADY2S_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)

TPI ITATBCTR0: ATREADY2S Mask

Definition at line 1454 of file core_cm33.h.

TPI_ITATBCTR0_ATREADY2S_Msk [3/5]

#define TPI_ITATBCTR0_ATREADY2S_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)

TPI ITATBCTR0: ATREADY2S Mask

Definition at line 1454 of file core_cm35p.h.

TPI_ITATBCTR0_ATREADY2S_Msk [4/5]

#define TPI_ITATBCTR0_ATREADY2S_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)

TPI ITATBCTR0: ATREADY2S Mask

Definition at line 1512 of file core_starmc1.h.

TPI_ITATBCTR0_ATREADY2S_Msk [5/5]

#define TPI_ITATBCTR0_ATREADY2S_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)

TPI ITATBCTR0: ATREADY2S Mask

Definition at line 1454 of file core_cm33.h.

TPI_ITATBCTR0_ATREADY2S_Pos [1/5]

#define TPI_ITATBCTR0_ATREADY2S_Pos   0U

TPI ITATBCTR0: ATREADY2S Position

Definition at line 859 of file core_cm23.h.

TPI_ITATBCTR0_ATREADY2S_Pos [2/5]

#define TPI_ITATBCTR0_ATREADY2S_Pos   0U

TPI ITATBCTR0: ATREADY2S Position

Definition at line 1453 of file core_cm33.h.

TPI_ITATBCTR0_ATREADY2S_Pos [3/5]

#define TPI_ITATBCTR0_ATREADY2S_Pos   0U

TPI ITATBCTR0: ATREADY2S Position

Definition at line 1453 of file core_cm35p.h.

TPI_ITATBCTR0_ATREADY2S_Pos [4/5]

#define TPI_ITATBCTR0_ATREADY2S_Pos   0U

TPI ITATBCTR0: ATREADY2S Position

Definition at line 1511 of file core_starmc1.h.

TPI_ITATBCTR0_ATREADY2S_Pos [5/5]

#define TPI_ITATBCTR0_ATREADY2S_Pos   0U

TPI ITATBCTR0: ATREADY2S Position

Definition at line 1453 of file core_cm33.h.

TPI_ITATBCTR2_AFVALID1S_Msk [1/5]

#define TPI_ITATBCTR2_AFVALID1S_Msk   (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)

TPI ITATBCTR2: AFVALID1SS Mask

Definition at line 822 of file core_cm23.h.

TPI_ITATBCTR2_AFVALID1S_Msk [2/5]

#define TPI_ITATBCTR2_AFVALID1S_Msk   (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)

TPI ITATBCTR2: AFVALID1SS Mask

Definition at line 1416 of file core_cm33.h.

TPI_ITATBCTR2_AFVALID1S_Msk [3/5]

#define TPI_ITATBCTR2_AFVALID1S_Msk   (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)

TPI ITATBCTR2: AFVALID1SS Mask

Definition at line 1416 of file core_cm35p.h.

TPI_ITATBCTR2_AFVALID1S_Msk [4/5]

#define TPI_ITATBCTR2_AFVALID1S_Msk   (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)

TPI ITATBCTR2: AFVALID1SS Mask

Definition at line 1474 of file core_starmc1.h.

TPI_ITATBCTR2_AFVALID1S_Msk [5/5]

#define TPI_ITATBCTR2_AFVALID1S_Msk   (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)

TPI ITATBCTR2: AFVALID1SS Mask

Definition at line 1416 of file core_cm33.h.

TPI_ITATBCTR2_AFVALID1S_Pos [1/5]

#define TPI_ITATBCTR2_AFVALID1S_Pos   1U

TPI ITATBCTR2: AFVALID1S Position

Definition at line 821 of file core_cm23.h.

TPI_ITATBCTR2_AFVALID1S_Pos [2/5]

#define TPI_ITATBCTR2_AFVALID1S_Pos   1U

TPI ITATBCTR2: AFVALID1S Position

Definition at line 1415 of file core_cm33.h.

TPI_ITATBCTR2_AFVALID1S_Pos [3/5]

#define TPI_ITATBCTR2_AFVALID1S_Pos   1U

TPI ITATBCTR2: AFVALID1S Position

Definition at line 1415 of file core_cm35p.h.

TPI_ITATBCTR2_AFVALID1S_Pos [4/5]

#define TPI_ITATBCTR2_AFVALID1S_Pos   1U

TPI ITATBCTR2: AFVALID1S Position

Definition at line 1473 of file core_starmc1.h.

TPI_ITATBCTR2_AFVALID1S_Pos [5/5]

#define TPI_ITATBCTR2_AFVALID1S_Pos   1U

TPI ITATBCTR2: AFVALID1S Position

Definition at line 1415 of file core_cm33.h.

TPI_ITATBCTR2_AFVALID2S_Msk [1/5]

#define TPI_ITATBCTR2_AFVALID2S_Msk   (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)

TPI ITATBCTR2: AFVALID2SS Mask

Definition at line 819 of file core_cm23.h.

TPI_ITATBCTR2_AFVALID2S_Msk [2/5]

#define TPI_ITATBCTR2_AFVALID2S_Msk   (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)

TPI ITATBCTR2: AFVALID2SS Mask

Definition at line 1413 of file core_cm33.h.

TPI_ITATBCTR2_AFVALID2S_Msk [3/5]

#define TPI_ITATBCTR2_AFVALID2S_Msk   (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)

TPI ITATBCTR2: AFVALID2SS Mask

Definition at line 1413 of file core_cm35p.h.

TPI_ITATBCTR2_AFVALID2S_Msk [4/5]

#define TPI_ITATBCTR2_AFVALID2S_Msk   (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)

TPI ITATBCTR2: AFVALID2SS Mask

Definition at line 1471 of file core_starmc1.h.

TPI_ITATBCTR2_AFVALID2S_Msk [5/5]

#define TPI_ITATBCTR2_AFVALID2S_Msk   (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)

TPI ITATBCTR2: AFVALID2SS Mask

Definition at line 1413 of file core_cm33.h.

TPI_ITATBCTR2_AFVALID2S_Pos [1/5]

#define TPI_ITATBCTR2_AFVALID2S_Pos   1U

TPI ITATBCTR2: AFVALID2S Position

Definition at line 818 of file core_cm23.h.

TPI_ITATBCTR2_AFVALID2S_Pos [2/5]

#define TPI_ITATBCTR2_AFVALID2S_Pos   1U

TPI ITATBCTR2: AFVALID2S Position

Definition at line 1412 of file core_cm33.h.

TPI_ITATBCTR2_AFVALID2S_Pos [3/5]

#define TPI_ITATBCTR2_AFVALID2S_Pos   1U

TPI ITATBCTR2: AFVALID2S Position

Definition at line 1412 of file core_cm35p.h.

TPI_ITATBCTR2_AFVALID2S_Pos [4/5]

#define TPI_ITATBCTR2_AFVALID2S_Pos   1U

TPI ITATBCTR2: AFVALID2S Position

Definition at line 1470 of file core_starmc1.h.

TPI_ITATBCTR2_AFVALID2S_Pos [5/5]

#define TPI_ITATBCTR2_AFVALID2S_Pos   1U

TPI ITATBCTR2: AFVALID2S Position

Definition at line 1412 of file core_cm33.h.

TPI_ITATBCTR2_ATREADY1_Msk [1/5]

#define TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)

TPI ITATBCTR2: ATREADY1 Mask

Definition at line 1085 of file core_cm3.h.

TPI_ITATBCTR2_ATREADY1_Msk [2/5]

#define TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)

TPI ITATBCTR2: ATREADY1 Mask

Definition at line 1150 of file core_cm4.h.

TPI_ITATBCTR2_ATREADY1_Msk [3/5]

#define TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)

TPI ITATBCTR2: ATREADY1 Mask

Definition at line 1377 of file core_cm7.h.

TPI_ITATBCTR2_ATREADY1_Msk [4/5]

#define TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)

TPI ITATBCTR2: ATREADY1 Mask

Definition at line 1070 of file core_sc300.h.

TPI_ITATBCTR2_ATREADY1_Msk [5/5]

#define TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)

TPI ITATBCTR2: ATREADY1 Mask

Definition at line 1150 of file core_cm4.h.

TPI_ITATBCTR2_ATREADY1_Pos [1/5]

#define TPI_ITATBCTR2_ATREADY1_Pos   0U

TPI ITATBCTR2: ATREADY1 Position

Definition at line 1084 of file core_cm3.h.

TPI_ITATBCTR2_ATREADY1_Pos [2/5]

#define TPI_ITATBCTR2_ATREADY1_Pos   0U

TPI ITATBCTR2: ATREADY1 Position

Definition at line 1149 of file core_cm4.h.

TPI_ITATBCTR2_ATREADY1_Pos [3/5]

#define TPI_ITATBCTR2_ATREADY1_Pos   0U

TPI ITATBCTR2: ATREADY1 Position

Definition at line 1376 of file core_cm7.h.

TPI_ITATBCTR2_ATREADY1_Pos [4/5]

#define TPI_ITATBCTR2_ATREADY1_Pos   0U

TPI ITATBCTR2: ATREADY1 Position

Definition at line 1069 of file core_sc300.h.

TPI_ITATBCTR2_ATREADY1_Pos [5/5]

#define TPI_ITATBCTR2_ATREADY1_Pos   0U

TPI ITATBCTR2: ATREADY1 Position

Definition at line 1149 of file core_cm4.h.

TPI_ITATBCTR2_ATREADY1S_Msk [1/5]

#define TPI_ITATBCTR2_ATREADY1S_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)

TPI ITATBCTR2: ATREADY1S Mask

Definition at line 828 of file core_cm23.h.

TPI_ITATBCTR2_ATREADY1S_Msk [2/5]

#define TPI_ITATBCTR2_ATREADY1S_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)

TPI ITATBCTR2: ATREADY1S Mask

Definition at line 1422 of file core_cm33.h.

TPI_ITATBCTR2_ATREADY1S_Msk [3/5]

#define TPI_ITATBCTR2_ATREADY1S_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)

TPI ITATBCTR2: ATREADY1S Mask

Definition at line 1422 of file core_cm35p.h.

TPI_ITATBCTR2_ATREADY1S_Msk [4/5]

#define TPI_ITATBCTR2_ATREADY1S_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)

TPI ITATBCTR2: ATREADY1S Mask

Definition at line 1480 of file core_starmc1.h.

TPI_ITATBCTR2_ATREADY1S_Msk [5/5]

#define TPI_ITATBCTR2_ATREADY1S_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)

TPI ITATBCTR2: ATREADY1S Mask

Definition at line 1422 of file core_cm33.h.

TPI_ITATBCTR2_ATREADY1S_Pos [1/5]

#define TPI_ITATBCTR2_ATREADY1S_Pos   0U

TPI ITATBCTR2: ATREADY1S Position

Definition at line 827 of file core_cm23.h.

TPI_ITATBCTR2_ATREADY1S_Pos [2/5]

#define TPI_ITATBCTR2_ATREADY1S_Pos   0U

TPI ITATBCTR2: ATREADY1S Position

Definition at line 1421 of file core_cm33.h.

TPI_ITATBCTR2_ATREADY1S_Pos [3/5]

#define TPI_ITATBCTR2_ATREADY1S_Pos   0U

TPI ITATBCTR2: ATREADY1S Position

Definition at line 1421 of file core_cm35p.h.

TPI_ITATBCTR2_ATREADY1S_Pos [4/5]

#define TPI_ITATBCTR2_ATREADY1S_Pos   0U

TPI ITATBCTR2: ATREADY1S Position

Definition at line 1479 of file core_starmc1.h.

TPI_ITATBCTR2_ATREADY1S_Pos [5/5]

#define TPI_ITATBCTR2_ATREADY1S_Pos   0U

TPI ITATBCTR2: ATREADY1S Position

Definition at line 1421 of file core_cm33.h.

TPI_ITATBCTR2_ATREADY2_Msk [1/5]

#define TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)

TPI ITATBCTR2: ATREADY2 Mask

Definition at line 1082 of file core_cm3.h.

TPI_ITATBCTR2_ATREADY2_Msk [2/5]

#define TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)

TPI ITATBCTR2: ATREADY2 Mask

Definition at line 1147 of file core_cm4.h.

TPI_ITATBCTR2_ATREADY2_Msk [3/5]

#define TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)

TPI ITATBCTR2: ATREADY2 Mask

Definition at line 1374 of file core_cm7.h.

TPI_ITATBCTR2_ATREADY2_Msk [4/5]

#define TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)

TPI ITATBCTR2: ATREADY2 Mask

Definition at line 1067 of file core_sc300.h.

TPI_ITATBCTR2_ATREADY2_Msk [5/5]

#define TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)

TPI ITATBCTR2: ATREADY2 Mask

Definition at line 1147 of file core_cm4.h.

TPI_ITATBCTR2_ATREADY2_Pos [1/5]

#define TPI_ITATBCTR2_ATREADY2_Pos   0U

TPI ITATBCTR2: ATREADY2 Position

Definition at line 1081 of file core_cm3.h.

TPI_ITATBCTR2_ATREADY2_Pos [2/5]

#define TPI_ITATBCTR2_ATREADY2_Pos   0U

TPI ITATBCTR2: ATREADY2 Position

Definition at line 1146 of file core_cm4.h.

TPI_ITATBCTR2_ATREADY2_Pos [3/5]

#define TPI_ITATBCTR2_ATREADY2_Pos   0U

TPI ITATBCTR2: ATREADY2 Position

Definition at line 1373 of file core_cm7.h.

TPI_ITATBCTR2_ATREADY2_Pos [4/5]

#define TPI_ITATBCTR2_ATREADY2_Pos   0U

TPI ITATBCTR2: ATREADY2 Position

Definition at line 1066 of file core_sc300.h.

TPI_ITATBCTR2_ATREADY2_Pos [5/5]

#define TPI_ITATBCTR2_ATREADY2_Pos   0U

TPI ITATBCTR2: ATREADY2 Position

Definition at line 1146 of file core_cm4.h.

TPI_ITATBCTR2_ATREADY2S_Msk [1/5]

#define TPI_ITATBCTR2_ATREADY2S_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)

TPI ITATBCTR2: ATREADY2S Mask

Definition at line 825 of file core_cm23.h.

TPI_ITATBCTR2_ATREADY2S_Msk [2/5]

#define TPI_ITATBCTR2_ATREADY2S_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)

TPI ITATBCTR2: ATREADY2S Mask

Definition at line 1419 of file core_cm33.h.

TPI_ITATBCTR2_ATREADY2S_Msk [3/5]

#define TPI_ITATBCTR2_ATREADY2S_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)

TPI ITATBCTR2: ATREADY2S Mask

Definition at line 1419 of file core_cm35p.h.

TPI_ITATBCTR2_ATREADY2S_Msk [4/5]

#define TPI_ITATBCTR2_ATREADY2S_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)

TPI ITATBCTR2: ATREADY2S Mask

Definition at line 1477 of file core_starmc1.h.

TPI_ITATBCTR2_ATREADY2S_Msk [5/5]

#define TPI_ITATBCTR2_ATREADY2S_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)

TPI ITATBCTR2: ATREADY2S Mask

Definition at line 1419 of file core_cm33.h.

TPI_ITATBCTR2_ATREADY2S_Pos [1/5]

#define TPI_ITATBCTR2_ATREADY2S_Pos   0U

TPI ITATBCTR2: ATREADY2S Position

Definition at line 824 of file core_cm23.h.

TPI_ITATBCTR2_ATREADY2S_Pos [2/5]

#define TPI_ITATBCTR2_ATREADY2S_Pos   0U

TPI ITATBCTR2: ATREADY2S Position

Definition at line 1418 of file core_cm33.h.

TPI_ITATBCTR2_ATREADY2S_Pos [3/5]

#define TPI_ITATBCTR2_ATREADY2S_Pos   0U

TPI ITATBCTR2: ATREADY2S Position

Definition at line 1418 of file core_cm35p.h.

TPI_ITATBCTR2_ATREADY2S_Pos [4/5]

#define TPI_ITATBCTR2_ATREADY2S_Pos   0U

TPI ITATBCTR2: ATREADY2S Position

Definition at line 1476 of file core_starmc1.h.

TPI_ITATBCTR2_ATREADY2S_Pos [5/5]

#define TPI_ITATBCTR2_ATREADY2S_Pos   0U

TPI ITATBCTR2: ATREADY2S Position

Definition at line 1418 of file core_cm33.h.

TPI_ITCTRL_Mode_Msk [1/10]

#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)

TPI ITCTRL: Mode Mask

Definition at line 867 of file core_cm23.h.

TPI_ITCTRL_Mode_Msk [2/10]

#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)

TPI ITCTRL: Mode Mask

Definition at line 1118 of file core_cm3.h.

TPI_ITCTRL_Mode_Msk [3/10]

#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)

TPI ITCTRL: Mode Mask

Definition at line 1461 of file core_cm33.h.

TPI_ITCTRL_Mode_Msk [4/10]

#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)

TPI ITCTRL: Mode Mask

Definition at line 1461 of file core_cm35p.h.

TPI_ITCTRL_Mode_Msk [5/10]

#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)

TPI ITCTRL: Mode Mask

Definition at line 1183 of file core_cm4.h.

TPI_ITCTRL_Mode_Msk [6/10]

#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)

TPI ITCTRL: Mode Mask

Definition at line 1410 of file core_cm7.h.

TPI_ITCTRL_Mode_Msk [7/10]

#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)

TPI ITCTRL: Mode Mask

Definition at line 1103 of file core_sc300.h.

TPI_ITCTRL_Mode_Msk [8/10]

#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)

TPI ITCTRL: Mode Mask

Definition at line 1519 of file core_starmc1.h.

TPI_ITCTRL_Mode_Msk [9/10]

#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)

TPI ITCTRL: Mode Mask

Definition at line 1461 of file core_cm33.h.

TPI_ITCTRL_Mode_Msk [10/10]

#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)

TPI ITCTRL: Mode Mask

Definition at line 1183 of file core_cm4.h.

TPI_ITCTRL_Mode_Pos [1/10]

#define TPI_ITCTRL_Mode_Pos   0U

TPI ITCTRL: Mode Position

Definition at line 866 of file core_cm23.h.

TPI_ITCTRL_Mode_Pos [2/10]

#define TPI_ITCTRL_Mode_Pos   0U

TPI ITCTRL: Mode Position

Definition at line 1117 of file core_cm3.h.

TPI_ITCTRL_Mode_Pos [3/10]

#define TPI_ITCTRL_Mode_Pos   0U

TPI ITCTRL: Mode Position

Definition at line 1460 of file core_cm33.h.

TPI_ITCTRL_Mode_Pos [4/10]

#define TPI_ITCTRL_Mode_Pos   0U

TPI ITCTRL: Mode Position

Definition at line 1460 of file core_cm35p.h.

TPI_ITCTRL_Mode_Pos [5/10]

#define TPI_ITCTRL_Mode_Pos   0U

TPI ITCTRL: Mode Position

Definition at line 1182 of file core_cm4.h.

TPI_ITCTRL_Mode_Pos [6/10]

#define TPI_ITCTRL_Mode_Pos   0U

TPI ITCTRL: Mode Position

Definition at line 1409 of file core_cm7.h.

TPI_ITCTRL_Mode_Pos [7/10]

#define TPI_ITCTRL_Mode_Pos   0U

TPI ITCTRL: Mode Position

Definition at line 1102 of file core_sc300.h.

TPI_ITCTRL_Mode_Pos [8/10]

#define TPI_ITCTRL_Mode_Pos   0U

TPI ITCTRL: Mode Position

Definition at line 1518 of file core_starmc1.h.

TPI_ITCTRL_Mode_Pos [9/10]

#define TPI_ITCTRL_Mode_Pos   0U

TPI ITCTRL: Mode Position

Definition at line 1460 of file core_cm33.h.

TPI_ITCTRL_Mode_Pos [10/10]

#define TPI_ITCTRL_Mode_Pos   0U

TPI ITCTRL: Mode Position

Definition at line 1182 of file core_cm4.h.

TPI_ITFTTD0_ATB_IF1_ATVALID_Msk [1/5]

#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)

TPI ITFTTD0: ATB Interface 1 ATVALID Mask

Definition at line 803 of file core_cm23.h.

TPI_ITFTTD0_ATB_IF1_ATVALID_Msk [2/5]

#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)

TPI ITFTTD0: ATB Interface 1 ATVALID Mask

Definition at line 1397 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF1_ATVALID_Msk [3/5]

#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)

TPI ITFTTD0: ATB Interface 1 ATVALID Mask

Definition at line 1397 of file core_cm35p.h.

TPI_ITFTTD0_ATB_IF1_ATVALID_Msk [4/5]

#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)

TPI ITFTTD0: ATB Interface 1 ATVALID Mask

Definition at line 1455 of file core_starmc1.h.

TPI_ITFTTD0_ATB_IF1_ATVALID_Msk [5/5]

#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)

TPI ITFTTD0: ATB Interface 1 ATVALID Mask

Definition at line 1397 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF1_ATVALID_Pos [1/5]

#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos   26U

TPI ITFTTD0: ATB Interface 1 ATVALID Position

Definition at line 802 of file core_cm23.h.

TPI_ITFTTD0_ATB_IF1_ATVALID_Pos [2/5]

#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos   26U

TPI ITFTTD0: ATB Interface 1 ATVALID Position

Definition at line 1396 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF1_ATVALID_Pos [3/5]

#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos   26U

TPI ITFTTD0: ATB Interface 1 ATVALID Position

Definition at line 1396 of file core_cm35p.h.

TPI_ITFTTD0_ATB_IF1_ATVALID_Pos [4/5]

#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos   26U

TPI ITFTTD0: ATB Interface 1 ATVALID Position

Definition at line 1454 of file core_starmc1.h.

TPI_ITFTTD0_ATB_IF1_ATVALID_Pos [5/5]

#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos   26U

TPI ITFTTD0: ATB Interface 1 ATVALID Position

Definition at line 1396 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF1_bytecount_Msk [1/5]

#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)

TPI ITFTTD0: ATB Interface 1 byte countt Mask

Definition at line 806 of file core_cm23.h.

TPI_ITFTTD0_ATB_IF1_bytecount_Msk [2/5]

#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)

TPI ITFTTD0: ATB Interface 1 byte countt Mask

Definition at line 1400 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF1_bytecount_Msk [3/5]

#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)

TPI ITFTTD0: ATB Interface 1 byte countt Mask

Definition at line 1400 of file core_cm35p.h.

TPI_ITFTTD0_ATB_IF1_bytecount_Msk [4/5]

#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)

TPI ITFTTD0: ATB Interface 1 byte countt Mask

Definition at line 1458 of file core_starmc1.h.

TPI_ITFTTD0_ATB_IF1_bytecount_Msk [5/5]

#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)

TPI ITFTTD0: ATB Interface 1 byte countt Mask

Definition at line 1400 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF1_bytecount_Pos [1/5]

#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos   24U

TPI ITFTTD0: ATB Interface 1 byte count Position

Definition at line 805 of file core_cm23.h.

TPI_ITFTTD0_ATB_IF1_bytecount_Pos [2/5]

#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos   24U

TPI ITFTTD0: ATB Interface 1 byte count Position

Definition at line 1399 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF1_bytecount_Pos [3/5]

#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos   24U

TPI ITFTTD0: ATB Interface 1 byte count Position

Definition at line 1399 of file core_cm35p.h.

TPI_ITFTTD0_ATB_IF1_bytecount_Pos [4/5]

#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos   24U

TPI ITFTTD0: ATB Interface 1 byte count Position

Definition at line 1457 of file core_starmc1.h.

TPI_ITFTTD0_ATB_IF1_bytecount_Pos [5/5]

#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos   24U

TPI ITFTTD0: ATB Interface 1 byte count Position

Definition at line 1399 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF1_data0_Msk [1/5]

#define TPI_ITFTTD0_ATB_IF1_data0_Msk   (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/)

TPI ITFTTD0: ATB Interface 1 data0 Mask

Definition at line 815 of file core_cm23.h.

TPI_ITFTTD0_ATB_IF1_data0_Msk [2/5]

#define TPI_ITFTTD0_ATB_IF1_data0_Msk   (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/)

TPI ITFTTD0: ATB Interface 1 data0 Mask

Definition at line 1409 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF1_data0_Msk [3/5]

#define TPI_ITFTTD0_ATB_IF1_data0_Msk   (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/)

TPI ITFTTD0: ATB Interface 1 data0 Mask

Definition at line 1409 of file core_cm35p.h.

TPI_ITFTTD0_ATB_IF1_data0_Msk [4/5]

#define TPI_ITFTTD0_ATB_IF1_data0_Msk   (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/)

TPI ITFTTD0: ATB Interface 1 data0 Mask

Definition at line 1467 of file core_starmc1.h.

TPI_ITFTTD0_ATB_IF1_data0_Msk [5/5]

#define TPI_ITFTTD0_ATB_IF1_data0_Msk   (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/)

TPI ITFTTD0: ATB Interface 1 data0 Mask

Definition at line 1409 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF1_data0_Pos [1/5]

#define TPI_ITFTTD0_ATB_IF1_data0_Pos   0U

TPI ITFTTD0: ATB Interface 1 data0 Position

Definition at line 814 of file core_cm23.h.

TPI_ITFTTD0_ATB_IF1_data0_Pos [2/5]

#define TPI_ITFTTD0_ATB_IF1_data0_Pos   0U

TPI ITFTTD0: ATB Interface 1 data0 Position

Definition at line 1408 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF1_data0_Pos [3/5]

#define TPI_ITFTTD0_ATB_IF1_data0_Pos   0U

TPI ITFTTD0: ATB Interface 1 data0 Position

Definition at line 1408 of file core_cm35p.h.

TPI_ITFTTD0_ATB_IF1_data0_Pos [4/5]

#define TPI_ITFTTD0_ATB_IF1_data0_Pos   0U

TPI ITFTTD0: ATB Interface 1 data0 Position

Definition at line 1466 of file core_starmc1.h.

TPI_ITFTTD0_ATB_IF1_data0_Pos [5/5]

#define TPI_ITFTTD0_ATB_IF1_data0_Pos   0U

TPI ITFTTD0: ATB Interface 1 data0 Position

Definition at line 1408 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF1_data1_Msk [1/5]

#define TPI_ITFTTD0_ATB_IF1_data1_Msk   (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

TPI ITFTTD0: ATB Interface 1 data1 Mask

Definition at line 812 of file core_cm23.h.

TPI_ITFTTD0_ATB_IF1_data1_Msk [2/5]

#define TPI_ITFTTD0_ATB_IF1_data1_Msk   (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

TPI ITFTTD0: ATB Interface 1 data1 Mask

Definition at line 1406 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF1_data1_Msk [3/5]

#define TPI_ITFTTD0_ATB_IF1_data1_Msk   (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

TPI ITFTTD0: ATB Interface 1 data1 Mask

Definition at line 1406 of file core_cm35p.h.

TPI_ITFTTD0_ATB_IF1_data1_Msk [4/5]

#define TPI_ITFTTD0_ATB_IF1_data1_Msk   (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

TPI ITFTTD0: ATB Interface 1 data1 Mask

Definition at line 1464 of file core_starmc1.h.

TPI_ITFTTD0_ATB_IF1_data1_Msk [5/5]

#define TPI_ITFTTD0_ATB_IF1_data1_Msk   (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

TPI ITFTTD0: ATB Interface 1 data1 Mask

Definition at line 1406 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF1_data1_Pos [1/5]

#define TPI_ITFTTD0_ATB_IF1_data1_Pos   8U

TPI ITFTTD0: ATB Interface 1 data1 Position

Definition at line 811 of file core_cm23.h.

TPI_ITFTTD0_ATB_IF1_data1_Pos [2/5]

#define TPI_ITFTTD0_ATB_IF1_data1_Pos   8U

TPI ITFTTD0: ATB Interface 1 data1 Position

Definition at line 1405 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF1_data1_Pos [3/5]

#define TPI_ITFTTD0_ATB_IF1_data1_Pos   8U

TPI ITFTTD0: ATB Interface 1 data1 Position

Definition at line 1405 of file core_cm35p.h.

TPI_ITFTTD0_ATB_IF1_data1_Pos [4/5]

#define TPI_ITFTTD0_ATB_IF1_data1_Pos   8U

TPI ITFTTD0: ATB Interface 1 data1 Position

Definition at line 1463 of file core_starmc1.h.

TPI_ITFTTD0_ATB_IF1_data1_Pos [5/5]

#define TPI_ITFTTD0_ATB_IF1_data1_Pos   8U

TPI ITFTTD0: ATB Interface 1 data1 Position

Definition at line 1405 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF1_data2_Msk [1/5]

#define TPI_ITFTTD0_ATB_IF1_data2_Msk   (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

TPI ITFTTD0: ATB Interface 1 data2 Mask

Definition at line 809 of file core_cm23.h.

TPI_ITFTTD0_ATB_IF1_data2_Msk [2/5]

#define TPI_ITFTTD0_ATB_IF1_data2_Msk   (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

TPI ITFTTD0: ATB Interface 1 data2 Mask

Definition at line 1403 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF1_data2_Msk [3/5]

#define TPI_ITFTTD0_ATB_IF1_data2_Msk   (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

TPI ITFTTD0: ATB Interface 1 data2 Mask

Definition at line 1403 of file core_cm35p.h.

TPI_ITFTTD0_ATB_IF1_data2_Msk [4/5]

#define TPI_ITFTTD0_ATB_IF1_data2_Msk   (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

TPI ITFTTD0: ATB Interface 1 data2 Mask

Definition at line 1461 of file core_starmc1.h.

TPI_ITFTTD0_ATB_IF1_data2_Msk [5/5]

#define TPI_ITFTTD0_ATB_IF1_data2_Msk   (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

TPI ITFTTD0: ATB Interface 1 data2 Mask

Definition at line 1403 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF1_data2_Pos [1/5]

#define TPI_ITFTTD0_ATB_IF1_data2_Pos   16U

TPI ITFTTD0: ATB Interface 1 data2 Position

Definition at line 808 of file core_cm23.h.

TPI_ITFTTD0_ATB_IF1_data2_Pos [2/5]

#define TPI_ITFTTD0_ATB_IF1_data2_Pos   16U

TPI ITFTTD0: ATB Interface 1 data2 Position

Definition at line 1402 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF1_data2_Pos [3/5]

#define TPI_ITFTTD0_ATB_IF1_data2_Pos   16U

TPI ITFTTD0: ATB Interface 1 data2 Position

Definition at line 1402 of file core_cm35p.h.

TPI_ITFTTD0_ATB_IF1_data2_Pos [4/5]

#define TPI_ITFTTD0_ATB_IF1_data2_Pos   16U

TPI ITFTTD0: ATB Interface 1 data2 Position

Definition at line 1460 of file core_starmc1.h.

TPI_ITFTTD0_ATB_IF1_data2_Pos [5/5]

#define TPI_ITFTTD0_ATB_IF1_data2_Pos   16U

TPI ITFTTD0: ATB Interface 1 data2 Position

Definition at line 1402 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF2_ATVALID_Msk [1/5]

#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)

TPI ITFTTD0: ATB Interface 2 ATVALID Mask

Definition at line 797 of file core_cm23.h.

TPI_ITFTTD0_ATB_IF2_ATVALID_Msk [2/5]

#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)

TPI ITFTTD0: ATB Interface 2 ATVALID Mask

Definition at line 1391 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF2_ATVALID_Msk [3/5]

#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)

TPI ITFTTD0: ATB Interface 2 ATVALID Mask

Definition at line 1391 of file core_cm35p.h.

TPI_ITFTTD0_ATB_IF2_ATVALID_Msk [4/5]

#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)

TPI ITFTTD0: ATB Interface 2 ATVALID Mask

Definition at line 1449 of file core_starmc1.h.

TPI_ITFTTD0_ATB_IF2_ATVALID_Msk [5/5]

#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)

TPI ITFTTD0: ATB Interface 2 ATVALID Mask

Definition at line 1391 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF2_ATVALID_Pos [1/5]

#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos   29U

TPI ITFTTD0: ATB Interface 2 ATVALIDPosition

Definition at line 796 of file core_cm23.h.

TPI_ITFTTD0_ATB_IF2_ATVALID_Pos [2/5]

#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos   29U

TPI ITFTTD0: ATB Interface 2 ATVALIDPosition

Definition at line 1390 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF2_ATVALID_Pos [3/5]

#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos   29U

TPI ITFTTD0: ATB Interface 2 ATVALIDPosition

Definition at line 1390 of file core_cm35p.h.

TPI_ITFTTD0_ATB_IF2_ATVALID_Pos [4/5]

#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos   29U

TPI ITFTTD0: ATB Interface 2 ATVALIDPosition

Definition at line 1448 of file core_starmc1.h.

TPI_ITFTTD0_ATB_IF2_ATVALID_Pos [5/5]

#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos   29U

TPI ITFTTD0: ATB Interface 2 ATVALIDPosition

Definition at line 1390 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF2_bytecount_Msk [1/5]

#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)

TPI ITFTTD0: ATB Interface 2 byte count Mask

Definition at line 800 of file core_cm23.h.

TPI_ITFTTD0_ATB_IF2_bytecount_Msk [2/5]

#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)

TPI ITFTTD0: ATB Interface 2 byte count Mask

Definition at line 1394 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF2_bytecount_Msk [3/5]

#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)

TPI ITFTTD0: ATB Interface 2 byte count Mask

Definition at line 1394 of file core_cm35p.h.

TPI_ITFTTD0_ATB_IF2_bytecount_Msk [4/5]

#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)

TPI ITFTTD0: ATB Interface 2 byte count Mask

Definition at line 1452 of file core_starmc1.h.

TPI_ITFTTD0_ATB_IF2_bytecount_Msk [5/5]

#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk   (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)

TPI ITFTTD0: ATB Interface 2 byte count Mask

Definition at line 1394 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF2_bytecount_Pos [1/5]

#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos   27U

TPI ITFTTD0: ATB Interface 2 byte count Position

Definition at line 799 of file core_cm23.h.

TPI_ITFTTD0_ATB_IF2_bytecount_Pos [2/5]

#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos   27U

TPI ITFTTD0: ATB Interface 2 byte count Position

Definition at line 1393 of file core_cm33.h.

TPI_ITFTTD0_ATB_IF2_bytecount_Pos [3/5]

#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos   27U

TPI ITFTTD0: ATB Interface 2 byte count Position

Definition at line 1393 of file core_cm35p.h.

TPI_ITFTTD0_ATB_IF2_bytecount_Pos [4/5]

#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos   27U

TPI ITFTTD0: ATB Interface 2 byte count Position

Definition at line 1451 of file core_starmc1.h.

TPI_ITFTTD0_ATB_IF2_bytecount_Pos [5/5]

#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos   27U

TPI ITFTTD0: ATB Interface 2 byte count Position

Definition at line 1393 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF1_ATVALID_Msk [1/5]

#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)

TPI ITFTTD1: ATB Interface 1 ATVALID Mask

Definition at line 838 of file core_cm23.h.

TPI_ITFTTD1_ATB_IF1_ATVALID_Msk [2/5]

#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)

TPI ITFTTD1: ATB Interface 1 ATVALID Mask

Definition at line 1432 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF1_ATVALID_Msk [3/5]

#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)

TPI ITFTTD1: ATB Interface 1 ATVALID Mask

Definition at line 1432 of file core_cm35p.h.

TPI_ITFTTD1_ATB_IF1_ATVALID_Msk [4/5]

#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)

TPI ITFTTD1: ATB Interface 1 ATVALID Mask

Definition at line 1490 of file core_starmc1.h.

TPI_ITFTTD1_ATB_IF1_ATVALID_Msk [5/5]

#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)

TPI ITFTTD1: ATB Interface 1 ATVALID Mask

Definition at line 1432 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF1_ATVALID_Pos [1/5]

#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos   26U

TPI ITFTTD1: ATB Interface 1 ATVALID Position

Definition at line 837 of file core_cm23.h.

TPI_ITFTTD1_ATB_IF1_ATVALID_Pos [2/5]

#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos   26U

TPI ITFTTD1: ATB Interface 1 ATVALID Position

Definition at line 1431 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF1_ATVALID_Pos [3/5]

#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos   26U

TPI ITFTTD1: ATB Interface 1 ATVALID Position

Definition at line 1431 of file core_cm35p.h.

TPI_ITFTTD1_ATB_IF1_ATVALID_Pos [4/5]

#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos   26U

TPI ITFTTD1: ATB Interface 1 ATVALID Position

Definition at line 1489 of file core_starmc1.h.

TPI_ITFTTD1_ATB_IF1_ATVALID_Pos [5/5]

#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos   26U

TPI ITFTTD1: ATB Interface 1 ATVALID Position

Definition at line 1431 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF1_bytecount_Msk [1/5]

#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)

TPI ITFTTD1: ATB Interface 1 byte countt Mask

Definition at line 841 of file core_cm23.h.

TPI_ITFTTD1_ATB_IF1_bytecount_Msk [2/5]

#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)

TPI ITFTTD1: ATB Interface 1 byte countt Mask

Definition at line 1435 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF1_bytecount_Msk [3/5]

#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)

TPI ITFTTD1: ATB Interface 1 byte countt Mask

Definition at line 1435 of file core_cm35p.h.

TPI_ITFTTD1_ATB_IF1_bytecount_Msk [4/5]

#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)

TPI ITFTTD1: ATB Interface 1 byte countt Mask

Definition at line 1493 of file core_starmc1.h.

TPI_ITFTTD1_ATB_IF1_bytecount_Msk [5/5]

#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)

TPI ITFTTD1: ATB Interface 1 byte countt Mask

Definition at line 1435 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF1_bytecount_Pos [1/5]

#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos   24U

TPI ITFTTD1: ATB Interface 1 byte count Position

Definition at line 840 of file core_cm23.h.

TPI_ITFTTD1_ATB_IF1_bytecount_Pos [2/5]

#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos   24U

TPI ITFTTD1: ATB Interface 1 byte count Position

Definition at line 1434 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF1_bytecount_Pos [3/5]

#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos   24U

TPI ITFTTD1: ATB Interface 1 byte count Position

Definition at line 1434 of file core_cm35p.h.

TPI_ITFTTD1_ATB_IF1_bytecount_Pos [4/5]

#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos   24U

TPI ITFTTD1: ATB Interface 1 byte count Position

Definition at line 1492 of file core_starmc1.h.

TPI_ITFTTD1_ATB_IF1_bytecount_Pos [5/5]

#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos   24U

TPI ITFTTD1: ATB Interface 1 byte count Position

Definition at line 1434 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF2_ATVALID_Msk [1/5]

#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)

TPI ITFTTD1: ATB Interface 2 ATVALID Mask

Definition at line 832 of file core_cm23.h.

TPI_ITFTTD1_ATB_IF2_ATVALID_Msk [2/5]

#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)

TPI ITFTTD1: ATB Interface 2 ATVALID Mask

Definition at line 1426 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF2_ATVALID_Msk [3/5]

#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)

TPI ITFTTD1: ATB Interface 2 ATVALID Mask

Definition at line 1426 of file core_cm35p.h.

TPI_ITFTTD1_ATB_IF2_ATVALID_Msk [4/5]

#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)

TPI ITFTTD1: ATB Interface 2 ATVALID Mask

Definition at line 1484 of file core_starmc1.h.

TPI_ITFTTD1_ATB_IF2_ATVALID_Msk [5/5]

#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)

TPI ITFTTD1: ATB Interface 2 ATVALID Mask

Definition at line 1426 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF2_ATVALID_Pos [1/5]

#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos   29U

TPI ITFTTD1: ATB Interface 2 ATVALID Position

Definition at line 831 of file core_cm23.h.

TPI_ITFTTD1_ATB_IF2_ATVALID_Pos [2/5]

#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos   29U

TPI ITFTTD1: ATB Interface 2 ATVALID Position

Definition at line 1425 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF2_ATVALID_Pos [3/5]

#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos   29U

TPI ITFTTD1: ATB Interface 2 ATVALID Position

Definition at line 1425 of file core_cm35p.h.

TPI_ITFTTD1_ATB_IF2_ATVALID_Pos [4/5]

#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos   29U

TPI ITFTTD1: ATB Interface 2 ATVALID Position

Definition at line 1483 of file core_starmc1.h.

TPI_ITFTTD1_ATB_IF2_ATVALID_Pos [5/5]

#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos   29U

TPI ITFTTD1: ATB Interface 2 ATVALID Position

Definition at line 1425 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF2_bytecount_Msk [1/5]

#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)

TPI ITFTTD1: ATB Interface 2 byte count Mask

Definition at line 835 of file core_cm23.h.

TPI_ITFTTD1_ATB_IF2_bytecount_Msk [2/5]

#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)

TPI ITFTTD1: ATB Interface 2 byte count Mask

Definition at line 1429 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF2_bytecount_Msk [3/5]

#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)

TPI ITFTTD1: ATB Interface 2 byte count Mask

Definition at line 1429 of file core_cm35p.h.

TPI_ITFTTD1_ATB_IF2_bytecount_Msk [4/5]

#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)

TPI ITFTTD1: ATB Interface 2 byte count Mask

Definition at line 1487 of file core_starmc1.h.

TPI_ITFTTD1_ATB_IF2_bytecount_Msk [5/5]

#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk   (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)

TPI ITFTTD1: ATB Interface 2 byte count Mask

Definition at line 1429 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF2_bytecount_Pos [1/5]

#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos   27U

TPI ITFTTD1: ATB Interface 2 byte count Position

Definition at line 834 of file core_cm23.h.

TPI_ITFTTD1_ATB_IF2_bytecount_Pos [2/5]

#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos   27U

TPI ITFTTD1: ATB Interface 2 byte count Position

Definition at line 1428 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF2_bytecount_Pos [3/5]

#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos   27U

TPI ITFTTD1: ATB Interface 2 byte count Position

Definition at line 1428 of file core_cm35p.h.

TPI_ITFTTD1_ATB_IF2_bytecount_Pos [4/5]

#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos   27U

TPI ITFTTD1: ATB Interface 2 byte count Position

Definition at line 1486 of file core_starmc1.h.

TPI_ITFTTD1_ATB_IF2_bytecount_Pos [5/5]

#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos   27U

TPI ITFTTD1: ATB Interface 2 byte count Position

Definition at line 1428 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF2_data0_Msk [1/5]

#define TPI_ITFTTD1_ATB_IF2_data0_Msk   (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/)

TPI ITFTTD1: ATB Interface 2 data0 Mask

Definition at line 850 of file core_cm23.h.

TPI_ITFTTD1_ATB_IF2_data0_Msk [2/5]

#define TPI_ITFTTD1_ATB_IF2_data0_Msk   (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/)

TPI ITFTTD1: ATB Interface 2 data0 Mask

Definition at line 1444 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF2_data0_Msk [3/5]

#define TPI_ITFTTD1_ATB_IF2_data0_Msk   (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/)

TPI ITFTTD1: ATB Interface 2 data0 Mask

Definition at line 1444 of file core_cm35p.h.

TPI_ITFTTD1_ATB_IF2_data0_Msk [4/5]

#define TPI_ITFTTD1_ATB_IF2_data0_Msk   (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/)

TPI ITFTTD1: ATB Interface 2 data0 Mask

Definition at line 1502 of file core_starmc1.h.

TPI_ITFTTD1_ATB_IF2_data0_Msk [5/5]

#define TPI_ITFTTD1_ATB_IF2_data0_Msk   (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/)

TPI ITFTTD1: ATB Interface 2 data0 Mask

Definition at line 1444 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF2_data0_Pos [1/5]

#define TPI_ITFTTD1_ATB_IF2_data0_Pos   0U

TPI ITFTTD1: ATB Interface 2 data0 Position

Definition at line 849 of file core_cm23.h.

TPI_ITFTTD1_ATB_IF2_data0_Pos [2/5]

#define TPI_ITFTTD1_ATB_IF2_data0_Pos   0U

TPI ITFTTD1: ATB Interface 2 data0 Position

Definition at line 1443 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF2_data0_Pos [3/5]

#define TPI_ITFTTD1_ATB_IF2_data0_Pos   0U

TPI ITFTTD1: ATB Interface 2 data0 Position

Definition at line 1443 of file core_cm35p.h.

TPI_ITFTTD1_ATB_IF2_data0_Pos [4/5]

#define TPI_ITFTTD1_ATB_IF2_data0_Pos   0U

TPI ITFTTD1: ATB Interface 2 data0 Position

Definition at line 1501 of file core_starmc1.h.

TPI_ITFTTD1_ATB_IF2_data0_Pos [5/5]

#define TPI_ITFTTD1_ATB_IF2_data0_Pos   0U

TPI ITFTTD1: ATB Interface 2 data0 Position

Definition at line 1443 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF2_data1_Msk [1/5]

#define TPI_ITFTTD1_ATB_IF2_data1_Msk   (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

TPI ITFTTD1: ATB Interface 2 data1 Mask

Definition at line 847 of file core_cm23.h.

TPI_ITFTTD1_ATB_IF2_data1_Msk [2/5]

#define TPI_ITFTTD1_ATB_IF2_data1_Msk   (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

TPI ITFTTD1: ATB Interface 2 data1 Mask

Definition at line 1441 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF2_data1_Msk [3/5]

#define TPI_ITFTTD1_ATB_IF2_data1_Msk   (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

TPI ITFTTD1: ATB Interface 2 data1 Mask

Definition at line 1441 of file core_cm35p.h.

TPI_ITFTTD1_ATB_IF2_data1_Msk [4/5]

#define TPI_ITFTTD1_ATB_IF2_data1_Msk   (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

TPI ITFTTD1: ATB Interface 2 data1 Mask

Definition at line 1499 of file core_starmc1.h.

TPI_ITFTTD1_ATB_IF2_data1_Msk [5/5]

#define TPI_ITFTTD1_ATB_IF2_data1_Msk   (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

TPI ITFTTD1: ATB Interface 2 data1 Mask

Definition at line 1441 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF2_data1_Pos [1/5]

#define TPI_ITFTTD1_ATB_IF2_data1_Pos   8U

TPI ITFTTD1: ATB Interface 2 data1 Position

Definition at line 846 of file core_cm23.h.

TPI_ITFTTD1_ATB_IF2_data1_Pos [2/5]

#define TPI_ITFTTD1_ATB_IF2_data1_Pos   8U

TPI ITFTTD1: ATB Interface 2 data1 Position

Definition at line 1440 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF2_data1_Pos [3/5]

#define TPI_ITFTTD1_ATB_IF2_data1_Pos   8U

TPI ITFTTD1: ATB Interface 2 data1 Position

Definition at line 1440 of file core_cm35p.h.

TPI_ITFTTD1_ATB_IF2_data1_Pos [4/5]

#define TPI_ITFTTD1_ATB_IF2_data1_Pos   8U

TPI ITFTTD1: ATB Interface 2 data1 Position

Definition at line 1498 of file core_starmc1.h.

TPI_ITFTTD1_ATB_IF2_data1_Pos [5/5]

#define TPI_ITFTTD1_ATB_IF2_data1_Pos   8U

TPI ITFTTD1: ATB Interface 2 data1 Position

Definition at line 1440 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF2_data2_Msk [1/5]

#define TPI_ITFTTD1_ATB_IF2_data2_Msk   (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

TPI ITFTTD1: ATB Interface 2 data2 Mask

Definition at line 844 of file core_cm23.h.

TPI_ITFTTD1_ATB_IF2_data2_Msk [2/5]

#define TPI_ITFTTD1_ATB_IF2_data2_Msk   (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

TPI ITFTTD1: ATB Interface 2 data2 Mask

Definition at line 1438 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF2_data2_Msk [3/5]

#define TPI_ITFTTD1_ATB_IF2_data2_Msk   (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

TPI ITFTTD1: ATB Interface 2 data2 Mask

Definition at line 1438 of file core_cm35p.h.

TPI_ITFTTD1_ATB_IF2_data2_Msk [4/5]

#define TPI_ITFTTD1_ATB_IF2_data2_Msk   (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

TPI ITFTTD1: ATB Interface 2 data2 Mask

Definition at line 1496 of file core_starmc1.h.

TPI_ITFTTD1_ATB_IF2_data2_Msk [5/5]

#define TPI_ITFTTD1_ATB_IF2_data2_Msk   (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

TPI ITFTTD1: ATB Interface 2 data2 Mask

Definition at line 1438 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF2_data2_Pos [1/5]

#define TPI_ITFTTD1_ATB_IF2_data2_Pos   16U

TPI ITFTTD1: ATB Interface 2 data2 Position

Definition at line 843 of file core_cm23.h.

TPI_ITFTTD1_ATB_IF2_data2_Pos [2/5]

#define TPI_ITFTTD1_ATB_IF2_data2_Pos   16U

TPI ITFTTD1: ATB Interface 2 data2 Position

Definition at line 1437 of file core_cm33.h.

TPI_ITFTTD1_ATB_IF2_data2_Pos [3/5]

#define TPI_ITFTTD1_ATB_IF2_data2_Pos   16U

TPI ITFTTD1: ATB Interface 2 data2 Position

Definition at line 1437 of file core_cm35p.h.

TPI_ITFTTD1_ATB_IF2_data2_Pos [4/5]

#define TPI_ITFTTD1_ATB_IF2_data2_Pos   16U

TPI ITFTTD1: ATB Interface 2 data2 Position

Definition at line 1495 of file core_starmc1.h.

TPI_ITFTTD1_ATB_IF2_data2_Pos [5/5]

#define TPI_ITFTTD1_ATB_IF2_data2_Pos   16U

TPI ITFTTD1: ATB Interface 2 data2 Position

Definition at line 1437 of file core_cm33.h.

TPI_LSR_nTT_Msk [1/8]

#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)

TPI LSR: Not thirty-two bit. Mask

Definition at line 1445 of file core_armv81mml.h.

TPI_LSR_nTT_Msk [2/8]

#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)

TPI LSR: Not thirty-two bit. Mask

Definition at line 789 of file core_armv8mbl.h.

TPI_LSR_nTT_Msk [3/8]

#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)

TPI LSR: Not thirty-two bit. Mask

Definition at line 1383 of file core_armv8mml.h.

TPI_LSR_nTT_Msk [4/8]

#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)

TPI LSR: Not thirty-two bit. Mask

Definition at line 1998 of file core_cm55.h.

TPI_LSR_nTT_Msk [5/8]

#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)

TPI LSR: Not thirty-two bit. Mask

Definition at line 1903 of file core_cm85.h.

TPI_LSR_nTT_Msk [6/8]

#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)

TPI LSR: Not thirty-two bit. Mask

Definition at line 1445 of file core_armv81mml.h.

TPI_LSR_nTT_Msk [7/8]

#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)

TPI LSR: Not thirty-two bit. Mask

Definition at line 789 of file core_armv8mbl.h.

TPI_LSR_nTT_Msk [8/8]

#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)

TPI LSR: Not thirty-two bit. Mask

Definition at line 1383 of file core_armv8mml.h.

TPI_LSR_nTT_Pos [1/8]

#define TPI_LSR_nTT_Pos   1U

TPI LSR: Not thirty-two bit. Position

Definition at line 1444 of file core_armv81mml.h.

TPI_LSR_nTT_Pos [2/8]

#define TPI_LSR_nTT_Pos   1U

TPI LSR: Not thirty-two bit. Position

Definition at line 788 of file core_armv8mbl.h.

TPI_LSR_nTT_Pos [3/8]

#define TPI_LSR_nTT_Pos   1U

TPI LSR: Not thirty-two bit. Position

Definition at line 1382 of file core_armv8mml.h.

TPI_LSR_nTT_Pos [4/8]

#define TPI_LSR_nTT_Pos   1U

TPI LSR: Not thirty-two bit. Position

Definition at line 1997 of file core_cm55.h.

TPI_LSR_nTT_Pos [5/8]

#define TPI_LSR_nTT_Pos   1U

TPI LSR: Not thirty-two bit. Position

Definition at line 1902 of file core_cm85.h.

TPI_LSR_nTT_Pos [6/8]

#define TPI_LSR_nTT_Pos   1U

TPI LSR: Not thirty-two bit. Position

Definition at line 1444 of file core_armv81mml.h.

TPI_LSR_nTT_Pos [7/8]

#define TPI_LSR_nTT_Pos   1U

TPI LSR: Not thirty-two bit. Position

Definition at line 788 of file core_armv8mbl.h.

TPI_LSR_nTT_Pos [8/8]

#define TPI_LSR_nTT_Pos   1U

TPI LSR: Not thirty-two bit. Position

Definition at line 1382 of file core_armv8mml.h.

TPI_LSR_SLI_Msk [1/8]

#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)

TPI LSR: Software Lock implemented Mask

Definition at line 1451 of file core_armv81mml.h.

TPI_LSR_SLI_Msk [2/8]

#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)

TPI LSR: Software Lock implemented Mask

Definition at line 795 of file core_armv8mbl.h.

TPI_LSR_SLI_Msk [3/8]

#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)

TPI LSR: Software Lock implemented Mask

Definition at line 1389 of file core_armv8mml.h.

TPI_LSR_SLI_Msk [4/8]

#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)

TPI LSR: Software Lock implemented Mask

Definition at line 2004 of file core_cm55.h.

TPI_LSR_SLI_Msk [5/8]

#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)

TPI LSR: Software Lock implemented Mask

Definition at line 1909 of file core_cm85.h.

TPI_LSR_SLI_Msk [6/8]

#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)

TPI LSR: Software Lock implemented Mask

Definition at line 1451 of file core_armv81mml.h.

TPI_LSR_SLI_Msk [7/8]

#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)

TPI LSR: Software Lock implemented Mask

Definition at line 795 of file core_armv8mbl.h.

TPI_LSR_SLI_Msk [8/8]

#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)

TPI LSR: Software Lock implemented Mask

Definition at line 1389 of file core_armv8mml.h.

TPI_LSR_SLI_Pos [1/8]

#define TPI_LSR_SLI_Pos   0U

TPI LSR: Software Lock implemented Position

Definition at line 1450 of file core_armv81mml.h.

TPI_LSR_SLI_Pos [2/8]

#define TPI_LSR_SLI_Pos   0U

TPI LSR: Software Lock implemented Position

Definition at line 794 of file core_armv8mbl.h.

TPI_LSR_SLI_Pos [3/8]

#define TPI_LSR_SLI_Pos   0U

TPI LSR: Software Lock implemented Position

Definition at line 1388 of file core_armv8mml.h.

TPI_LSR_SLI_Pos [4/8]

#define TPI_LSR_SLI_Pos   0U

TPI LSR: Software Lock implemented Position

Definition at line 2003 of file core_cm55.h.

TPI_LSR_SLI_Pos [5/8]

#define TPI_LSR_SLI_Pos   0U

TPI LSR: Software Lock implemented Position

Definition at line 1908 of file core_cm85.h.

TPI_LSR_SLI_Pos [6/8]

#define TPI_LSR_SLI_Pos   0U

TPI LSR: Software Lock implemented Position

Definition at line 1450 of file core_armv81mml.h.

TPI_LSR_SLI_Pos [7/8]

#define TPI_LSR_SLI_Pos   0U

TPI LSR: Software Lock implemented Position

Definition at line 794 of file core_armv8mbl.h.

TPI_LSR_SLI_Pos [8/8]

#define TPI_LSR_SLI_Pos   0U

TPI LSR: Software Lock implemented Position

Definition at line 1388 of file core_armv8mml.h.

TPI_LSR_SLK_Msk [1/8]

#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)

TPI LSR: Software Lock status Mask

Definition at line 1448 of file core_armv81mml.h.

TPI_LSR_SLK_Msk [2/8]

#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)

TPI LSR: Software Lock status Mask

Definition at line 792 of file core_armv8mbl.h.

TPI_LSR_SLK_Msk [3/8]

#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)

TPI LSR: Software Lock status Mask

Definition at line 1386 of file core_armv8mml.h.

TPI_LSR_SLK_Msk [4/8]

#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)

TPI LSR: Software Lock status Mask

Definition at line 2001 of file core_cm55.h.

TPI_LSR_SLK_Msk [5/8]

#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)

TPI LSR: Software Lock status Mask

Definition at line 1906 of file core_cm85.h.

TPI_LSR_SLK_Msk [6/8]

#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)

TPI LSR: Software Lock status Mask

Definition at line 1448 of file core_armv81mml.h.

TPI_LSR_SLK_Msk [7/8]

#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)

TPI LSR: Software Lock status Mask

Definition at line 792 of file core_armv8mbl.h.

TPI_LSR_SLK_Msk [8/8]

#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)

TPI LSR: Software Lock status Mask

Definition at line 1386 of file core_armv8mml.h.

TPI_LSR_SLK_Pos [1/8]

#define TPI_LSR_SLK_Pos   1U

TPI LSR: Software Lock status Position

Definition at line 1447 of file core_armv81mml.h.

TPI_LSR_SLK_Pos [2/8]

#define TPI_LSR_SLK_Pos   1U

TPI LSR: Software Lock status Position

Definition at line 791 of file core_armv8mbl.h.

TPI_LSR_SLK_Pos [3/8]

#define TPI_LSR_SLK_Pos   1U

TPI LSR: Software Lock status Position

Definition at line 1385 of file core_armv8mml.h.

TPI_LSR_SLK_Pos [4/8]

#define TPI_LSR_SLK_Pos   1U

TPI LSR: Software Lock status Position

Definition at line 2000 of file core_cm55.h.

TPI_LSR_SLK_Pos [5/8]

#define TPI_LSR_SLK_Pos   1U

TPI LSR: Software Lock status Position

Definition at line 1905 of file core_cm85.h.

TPI_LSR_SLK_Pos [6/8]

#define TPI_LSR_SLK_Pos   1U

TPI LSR: Software Lock status Position

Definition at line 1447 of file core_armv81mml.h.

TPI_LSR_SLK_Pos [7/8]

#define TPI_LSR_SLK_Pos   1U

TPI LSR: Software Lock status Position

Definition at line 791 of file core_armv8mbl.h.

TPI_LSR_SLK_Pos [8/8]

#define TPI_LSR_SLK_Pos   1U

TPI LSR: Software Lock status Position

Definition at line 1385 of file core_armv8mml.h.

TPI_PSCR_PSCount_Msk [1/8]

#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)

TPI PSCR: TPSCount Mask

Definition at line 1441 of file core_armv81mml.h.

TPI_PSCR_PSCount_Msk [2/8]

#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)

TPI PSCR: TPSCount Mask

Definition at line 785 of file core_armv8mbl.h.

TPI_PSCR_PSCount_Msk [3/8]

#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)

TPI PSCR: TPSCount Mask

Definition at line 1379 of file core_armv8mml.h.

TPI_PSCR_PSCount_Msk [4/8]

#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)

TPI PSCR: TPSCount Mask

Definition at line 1994 of file core_cm55.h.

TPI_PSCR_PSCount_Msk [5/8]

#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)

TPI PSCR: TPSCount Mask

Definition at line 1899 of file core_cm85.h.

TPI_PSCR_PSCount_Msk [6/8]

#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)

TPI PSCR: TPSCount Mask

Definition at line 1441 of file core_armv81mml.h.

TPI_PSCR_PSCount_Msk [7/8]

#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)

TPI PSCR: TPSCount Mask

Definition at line 785 of file core_armv8mbl.h.

TPI_PSCR_PSCount_Msk [8/8]

#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)

TPI PSCR: TPSCount Mask

Definition at line 1379 of file core_armv8mml.h.

TPI_PSCR_PSCount_Pos [1/8]

#define TPI_PSCR_PSCount_Pos   0U

TPI PSCR: PSCount Position

Definition at line 1440 of file core_armv81mml.h.

TPI_PSCR_PSCount_Pos [2/8]

#define TPI_PSCR_PSCount_Pos   0U

TPI PSCR: PSCount Position

Definition at line 784 of file core_armv8mbl.h.

TPI_PSCR_PSCount_Pos [3/8]

#define TPI_PSCR_PSCount_Pos   0U

TPI PSCR: PSCount Position

Definition at line 1378 of file core_armv8mml.h.

TPI_PSCR_PSCount_Pos [4/8]

#define TPI_PSCR_PSCount_Pos   0U

TPI PSCR: PSCount Position

Definition at line 1993 of file core_cm55.h.

TPI_PSCR_PSCount_Pos [5/8]

#define TPI_PSCR_PSCount_Pos   0U

TPI PSCR: PSCount Position

Definition at line 1898 of file core_cm85.h.

TPI_PSCR_PSCount_Pos [6/8]

#define TPI_PSCR_PSCount_Pos   0U

TPI PSCR: PSCount Position

Definition at line 1440 of file core_armv81mml.h.

TPI_PSCR_PSCount_Pos [7/8]

#define TPI_PSCR_PSCount_Pos   0U

TPI PSCR: PSCount Position

Definition at line 784 of file core_armv8mbl.h.

TPI_PSCR_PSCount_Pos [8/8]

#define TPI_PSCR_PSCount_Pos   0U

TPI PSCR: PSCount Position

Definition at line 1378 of file core_armv8mml.h.

TPI_SPPR_TXMODE_Msk [1/18]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

Definition at line 1414 of file core_armv81mml.h.

TPI_SPPR_TXMODE_Msk [2/18]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

Definition at line 758 of file core_armv8mbl.h.

TPI_SPPR_TXMODE_Msk [3/18]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

Definition at line 1352 of file core_armv8mml.h.

TPI_SPPR_TXMODE_Msk [4/18]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

Definition at line 766 of file core_cm23.h.

TPI_SPPR_TXMODE_Msk [5/18]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

Definition at line 1032 of file core_cm3.h.

TPI_SPPR_TXMODE_Msk [6/18]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

Definition at line 1360 of file core_cm33.h.

TPI_SPPR_TXMODE_Msk [7/18]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

Definition at line 1360 of file core_cm35p.h.

TPI_SPPR_TXMODE_Msk [8/18]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

Definition at line 1097 of file core_cm4.h.

TPI_SPPR_TXMODE_Msk [9/18]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

Definition at line 1967 of file core_cm55.h.

TPI_SPPR_TXMODE_Msk [10/18]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

Definition at line 1324 of file core_cm7.h.

TPI_SPPR_TXMODE_Msk [11/18]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

Definition at line 1872 of file core_cm85.h.

TPI_SPPR_TXMODE_Msk [12/18]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

Definition at line 1017 of file core_sc300.h.

TPI_SPPR_TXMODE_Msk [13/18]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

Definition at line 1418 of file core_starmc1.h.

TPI_SPPR_TXMODE_Msk [14/18]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

Definition at line 1414 of file core_armv81mml.h.

TPI_SPPR_TXMODE_Msk [15/18]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

Definition at line 758 of file core_armv8mbl.h.

TPI_SPPR_TXMODE_Msk [16/18]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

Definition at line 1352 of file core_armv8mml.h.

TPI_SPPR_TXMODE_Msk [17/18]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

Definition at line 1360 of file core_cm33.h.

TPI_SPPR_TXMODE_Msk [18/18]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

Definition at line 1097 of file core_cm4.h.

TPI_SPPR_TXMODE_Pos [1/18]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

Definition at line 1413 of file core_armv81mml.h.

TPI_SPPR_TXMODE_Pos [2/18]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

Definition at line 757 of file core_armv8mbl.h.

TPI_SPPR_TXMODE_Pos [3/18]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

Definition at line 1351 of file core_armv8mml.h.

TPI_SPPR_TXMODE_Pos [4/18]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

Definition at line 765 of file core_cm23.h.

TPI_SPPR_TXMODE_Pos [5/18]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

Definition at line 1031 of file core_cm3.h.

TPI_SPPR_TXMODE_Pos [6/18]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

Definition at line 1359 of file core_cm33.h.

TPI_SPPR_TXMODE_Pos [7/18]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

Definition at line 1359 of file core_cm35p.h.

TPI_SPPR_TXMODE_Pos [8/18]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

Definition at line 1096 of file core_cm4.h.

TPI_SPPR_TXMODE_Pos [9/18]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

Definition at line 1966 of file core_cm55.h.

TPI_SPPR_TXMODE_Pos [10/18]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

Definition at line 1323 of file core_cm7.h.

TPI_SPPR_TXMODE_Pos [11/18]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

Definition at line 1871 of file core_cm85.h.

TPI_SPPR_TXMODE_Pos [12/18]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

Definition at line 1016 of file core_sc300.h.

TPI_SPPR_TXMODE_Pos [13/18]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

Definition at line 1417 of file core_starmc1.h.

TPI_SPPR_TXMODE_Pos [14/18]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

Definition at line 1413 of file core_armv81mml.h.

TPI_SPPR_TXMODE_Pos [15/18]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

Definition at line 757 of file core_armv8mbl.h.

TPI_SPPR_TXMODE_Pos [16/18]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

Definition at line 1351 of file core_armv8mml.h.

TPI_SPPR_TXMODE_Pos [17/18]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

Definition at line 1359 of file core_cm33.h.

TPI_SPPR_TXMODE_Pos [18/18]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

Definition at line 1096 of file core_cm4.h.

TPI_TRIGGER_TRIGGER_Msk [1/10]

#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)

TPI TRIGGER: TRIGGER Mask

Definition at line 793 of file core_cm23.h.

TPI_TRIGGER_TRIGGER_Msk [2/10]

#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)

TPI TRIGGER: TRIGGER Mask

Definition at line 1056 of file core_cm3.h.

TPI_TRIGGER_TRIGGER_Msk [3/10]

#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)

TPI TRIGGER: TRIGGER Mask

Definition at line 1387 of file core_cm33.h.

TPI_TRIGGER_TRIGGER_Msk [4/10]

#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)

TPI TRIGGER: TRIGGER Mask

Definition at line 1387 of file core_cm35p.h.

TPI_TRIGGER_TRIGGER_Msk [5/10]

#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)

TPI TRIGGER: TRIGGER Mask

Definition at line 1121 of file core_cm4.h.

TPI_TRIGGER_TRIGGER_Msk [6/10]

#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)

TPI TRIGGER: TRIGGER Mask

Definition at line 1348 of file core_cm7.h.

TPI_TRIGGER_TRIGGER_Msk [7/10]

#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)

TPI TRIGGER: TRIGGER Mask

Definition at line 1041 of file core_sc300.h.

TPI_TRIGGER_TRIGGER_Msk [8/10]

#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)

TPI TRIGGER: TRIGGER Mask

Definition at line 1445 of file core_starmc1.h.

TPI_TRIGGER_TRIGGER_Msk [9/10]

#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)

TPI TRIGGER: TRIGGER Mask

Definition at line 1387 of file core_cm33.h.

TPI_TRIGGER_TRIGGER_Msk [10/10]

#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)

TPI TRIGGER: TRIGGER Mask

Definition at line 1121 of file core_cm4.h.

TPI_TRIGGER_TRIGGER_Pos [1/10]

#define TPI_TRIGGER_TRIGGER_Pos   0U

TPI TRIGGER: TRIGGER Position

Definition at line 792 of file core_cm23.h.

TPI_TRIGGER_TRIGGER_Pos [2/10]

#define TPI_TRIGGER_TRIGGER_Pos   0U

TPI TRIGGER: TRIGGER Position

Definition at line 1055 of file core_cm3.h.

TPI_TRIGGER_TRIGGER_Pos [3/10]

#define TPI_TRIGGER_TRIGGER_Pos   0U

TPI TRIGGER: TRIGGER Position

Definition at line 1386 of file core_cm33.h.

TPI_TRIGGER_TRIGGER_Pos [4/10]

#define TPI_TRIGGER_TRIGGER_Pos   0U

TPI TRIGGER: TRIGGER Position

Definition at line 1386 of file core_cm35p.h.

TPI_TRIGGER_TRIGGER_Pos [5/10]

#define TPI_TRIGGER_TRIGGER_Pos   0U

TPI TRIGGER: TRIGGER Position

Definition at line 1120 of file core_cm4.h.

TPI_TRIGGER_TRIGGER_Pos [6/10]

#define TPI_TRIGGER_TRIGGER_Pos   0U

TPI TRIGGER: TRIGGER Position

Definition at line 1347 of file core_cm7.h.

TPI_TRIGGER_TRIGGER_Pos [7/10]

#define TPI_TRIGGER_TRIGGER_Pos   0U

TPI TRIGGER: TRIGGER Position

Definition at line 1040 of file core_sc300.h.

TPI_TRIGGER_TRIGGER_Pos [8/10]

#define TPI_TRIGGER_TRIGGER_Pos   0U

TPI TRIGGER: TRIGGER Position

Definition at line 1444 of file core_starmc1.h.

TPI_TRIGGER_TRIGGER_Pos [9/10]

#define TPI_TRIGGER_TRIGGER_Pos   0U

TPI TRIGGER: TRIGGER Position

Definition at line 1386 of file core_cm33.h.

TPI_TRIGGER_TRIGGER_Pos [10/10]

#define TPI_TRIGGER_TRIGGER_Pos   0U

TPI TRIGGER: TRIGGER Position

Definition at line 1120 of file core_cm4.h.