YAHAL
Yet Another Hardware Abstraction Library
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core_cm1.h
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1/**************************************************************************/
7/*
8 * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25#if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27#elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29#endif
30
31#ifndef __CORE_CM1_H_GENERIC
32#define __CORE_CM1_H_GENERIC
33
34#include <stdint.h>
35
36#ifdef __cplusplus
37 extern "C" {
38#endif
39
55/*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
63#include "cmsis_version.h"
64
65/* CMSIS CM1 definitions */
66#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
67#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
68#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
69 __CM1_CMSIS_VERSION_SUB )
71#define __CORTEX_M (1U)
76#define __FPU_USED 0U
77
78#if defined ( __CC_ARM )
79 #if defined __TARGET_FPU_VFP
80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
81 #endif
82
83#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84 #if defined __ARM_FP
85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
86 #endif
87
88#elif defined (__ti__)
89 #if defined __ARM_FP
90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91 #endif
92
93#elif defined ( __GNUC__ )
94 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96 #endif
97
98#elif defined ( __ICCARM__ )
99 #if defined __ARMVFP__
100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101 #endif
102
103#elif defined ( __TI_ARM__ )
104 #if defined __TI_VFP_SUPPORT__
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106 #endif
107
108#elif defined ( __TASKING__ )
109 #if defined __FPU_VFP__
110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
111 #endif
112
113#elif defined ( __CSMC__ )
114 #if ( __CSMC__ & 0x400U)
115 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
116 #endif
117
118#endif
119
120#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
121
122
123#ifdef __cplusplus
124}
125#endif
126
127#endif /* __CORE_CM1_H_GENERIC */
128
129#ifndef __CMSIS_GENERIC
130
131#ifndef __CORE_CM1_H_DEPENDANT
132#define __CORE_CM1_H_DEPENDANT
133
134#ifdef __cplusplus
135 extern "C" {
136#endif
137
138/* check device defines and use defaults */
139#if defined __CHECK_DEVICE_DEFINES
140 #ifndef __CM1_REV
141 #define __CM1_REV 0x0100U
142 #warning "__CM1_REV not defined in device header file; using default!"
143 #endif
144
145 #ifndef __NVIC_PRIO_BITS
146 #define __NVIC_PRIO_BITS 2U
147 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
148 #endif
149
150 #ifndef __Vendor_SysTickConfig
151 #define __Vendor_SysTickConfig 0U
152 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
153 #endif
154#endif
155
156/* IO definitions (access restrictions to peripheral registers) */
164#ifdef __cplusplus
165 #define __I volatile
166#else
167 #define __I volatile const
168#endif
169#define __O volatile
170#define __IO volatile
172/* following defines should be used for structure members */
173#define __IM volatile const
174#define __OM volatile
175#define __IOM volatile
181/*******************************************************************************
182 * Register Abstraction
183 Core Register contain:
184 - Core Register
185 - Core NVIC Register
186 - Core SCB Register
187 - Core SysTick Register
188 ******************************************************************************/
204typedef union
205{
206 struct
207 {
208 uint32_t _reserved0:28;
209 uint32_t V:1;
210 uint32_t C:1;
211 uint32_t Z:1;
212 uint32_t N:1;
213 } b;
214 uint32_t w;
215} APSR_Type;
216
217/* APSR Register Definitions */
218#define APSR_N_Pos 31U
219#define APSR_N_Msk (1UL << APSR_N_Pos)
221#define APSR_Z_Pos 30U
222#define APSR_Z_Msk (1UL << APSR_Z_Pos)
224#define APSR_C_Pos 29U
225#define APSR_C_Msk (1UL << APSR_C_Pos)
227#define APSR_V_Pos 28U
228#define APSR_V_Msk (1UL << APSR_V_Pos)
234typedef union
235{
236 struct
237 {
238 uint32_t ISR:9;
239 uint32_t _reserved0:23;
240 } b;
241 uint32_t w;
242} IPSR_Type;
243
244/* IPSR Register Definitions */
245#define IPSR_ISR_Pos 0U
246#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
252typedef union
253{
254 struct
255 {
256 uint32_t ISR:9;
257 uint32_t _reserved0:15;
258 uint32_t T:1;
259 uint32_t _reserved1:3;
260 uint32_t V:1;
261 uint32_t C:1;
262 uint32_t Z:1;
263 uint32_t N:1;
264 } b;
265 uint32_t w;
266} xPSR_Type;
267
268/* xPSR Register Definitions */
269#define xPSR_N_Pos 31U
270#define xPSR_N_Msk (1UL << xPSR_N_Pos)
272#define xPSR_Z_Pos 30U
273#define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
275#define xPSR_C_Pos 29U
276#define xPSR_C_Msk (1UL << xPSR_C_Pos)
278#define xPSR_V_Pos 28U
279#define xPSR_V_Msk (1UL << xPSR_V_Pos)
281#define xPSR_T_Pos 24U
282#define xPSR_T_Msk (1UL << xPSR_T_Pos)
284#define xPSR_ISR_Pos 0U
285#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
291typedef union
292{
293 struct
294 {
295 uint32_t _reserved0:1;
296 uint32_t SPSEL:1;
297 uint32_t _reserved1:30;
298 } b;
299 uint32_t w;
300} CONTROL_Type;
301
302/* CONTROL Register Definitions */
303#define CONTROL_SPSEL_Pos 1U
304#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
319typedef struct
320{
321 __IOM uint32_t ISER[1U];
322 uint32_t RESERVED0[31U];
323 __IOM uint32_t ICER[1U];
324 uint32_t RSERVED1[31U];
325 __IOM uint32_t ISPR[1U];
326 uint32_t RESERVED2[31U];
327 __IOM uint32_t ICPR[1U];
328 uint32_t RESERVED3[31U];
329 uint32_t RESERVED4[64U];
330 __IOM uint32_t IP[8U];
331} NVIC_Type;
332
346typedef struct
347{
348 __IM uint32_t CPUID;
349 __IOM uint32_t ICSR;
350 uint32_t RESERVED0;
351 __IOM uint32_t AIRCR;
352 __IOM uint32_t SCR;
353 __IOM uint32_t CCR;
354 uint32_t RESERVED1;
355 __IOM uint32_t SHP[2U];
356 __IOM uint32_t SHCSR;
357} SCB_Type;
358
359/* SCB CPUID Register Definitions */
360#define SCB_CPUID_IMPLEMENTER_Pos 24U
361#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
363#define SCB_CPUID_VARIANT_Pos 20U
364#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
366#define SCB_CPUID_ARCHITECTURE_Pos 16U
367#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
369#define SCB_CPUID_PARTNO_Pos 4U
370#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
372#define SCB_CPUID_REVISION_Pos 0U
373#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
375/* SCB Interrupt Control State Register Definitions */
376#define SCB_ICSR_NMIPENDSET_Pos 31U
377#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
379#define SCB_ICSR_PENDSVSET_Pos 28U
380#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
382#define SCB_ICSR_PENDSVCLR_Pos 27U
383#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
385#define SCB_ICSR_PENDSTSET_Pos 26U
386#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
388#define SCB_ICSR_PENDSTCLR_Pos 25U
389#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
391#define SCB_ICSR_ISRPREEMPT_Pos 23U
392#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
394#define SCB_ICSR_ISRPENDING_Pos 22U
395#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
397#define SCB_ICSR_VECTPENDING_Pos 12U
398#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
400#define SCB_ICSR_VECTACTIVE_Pos 0U
401#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
403/* SCB Application Interrupt and Reset Control Register Definitions */
404#define SCB_AIRCR_VECTKEY_Pos 16U
405#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
407#define SCB_AIRCR_VECTKEYSTAT_Pos 16U
408#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
410#define SCB_AIRCR_ENDIANESS_Pos 15U
411#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
413#define SCB_AIRCR_SYSRESETREQ_Pos 2U
414#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
416#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
417#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
419/* SCB System Control Register Definitions */
420#define SCB_SCR_SEVONPEND_Pos 4U
421#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
423#define SCB_SCR_SLEEPDEEP_Pos 2U
424#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
426#define SCB_SCR_SLEEPONEXIT_Pos 1U
427#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
429/* SCB Configuration Control Register Definitions */
430#define SCB_CCR_STKALIGN_Pos 9U
431#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
433#define SCB_CCR_UNALIGN_TRP_Pos 3U
434#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
436/* SCB System Handler Control and State Register Definitions */
437#define SCB_SHCSR_SVCALLPENDED_Pos 15U
438#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
453typedef struct
454{
455 uint32_t RESERVED0[2U];
456 __IOM uint32_t ACTLR;
457} SCnSCB_Type;
458
459/* Auxiliary Control Register Definitions */
460#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U
461#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)
463#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U
464#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)
479typedef struct
480{
481 __IOM uint32_t CTRL;
482 __IOM uint32_t LOAD;
483 __IOM uint32_t VAL;
484 __IM uint32_t CALIB;
485} SysTick_Type;
486
487/* SysTick Control / Status Register Definitions */
488#define SysTick_CTRL_COUNTFLAG_Pos 16U
489#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
491#define SysTick_CTRL_CLKSOURCE_Pos 2U
492#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
494#define SysTick_CTRL_TICKINT_Pos 1U
495#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
497#define SysTick_CTRL_ENABLE_Pos 0U
498#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
500/* SysTick Reload Register Definitions */
501#define SysTick_LOAD_RELOAD_Pos 0U
502#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
504/* SysTick Current Register Definitions */
505#define SysTick_VAL_CURRENT_Pos 0U
506#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
508/* SysTick Calibration Register Definitions */
509#define SysTick_CALIB_NOREF_Pos 31U
510#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
512#define SysTick_CALIB_SKEW_Pos 30U
513#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
515#define SysTick_CALIB_TENMS_Pos 0U
516#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
544#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
545
552#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
553
564/* Memory mapping of Core Hardware */
565#define SCS_BASE (0xE000E000UL)
566#define SysTick_BASE (SCS_BASE + 0x0010UL)
567#define NVIC_BASE (SCS_BASE + 0x0100UL)
568#define SCB_BASE (SCS_BASE + 0x0D00UL)
570#define SCnSCB ((SCnSCB_Type *) SCS_BASE )
571#define SCB ((SCB_Type *) SCB_BASE )
572#define SysTick ((SysTick_Type *) SysTick_BASE )
573#define NVIC ((NVIC_Type *) NVIC_BASE )
580/*******************************************************************************
581 * Hardware Abstraction Layer
582 Core Function Interface contains:
583 - Core NVIC Functions
584 - Core SysTick Functions
585 - Core Register Access Functions
586 ******************************************************************************/
593/* ########################## NVIC functions #################################### */
601#ifdef CMSIS_NVIC_VIRTUAL
602 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
603 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
604 #endif
605 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
606#else
607 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
608 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
609 #define NVIC_EnableIRQ __NVIC_EnableIRQ
610 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
611 #define NVIC_DisableIRQ __NVIC_DisableIRQ
612 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
613 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
614 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
615/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
616 #define NVIC_SetPriority __NVIC_SetPriority
617 #define NVIC_GetPriority __NVIC_GetPriority
618 #define NVIC_SystemReset __NVIC_SystemReset
619#endif /* CMSIS_NVIC_VIRTUAL */
620
621#ifdef CMSIS_VECTAB_VIRTUAL
622 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
623 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
624 #endif
625 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
626#else
627 #define NVIC_SetVector __NVIC_SetVector
628 #define NVIC_GetVector __NVIC_GetVector
629#endif /* (CMSIS_VECTAB_VIRTUAL) */
630
631#define NVIC_USER_IRQ_OFFSET 16
632
633
634/* The following EXC_RETURN values are saved the LR on exception entry */
635#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
636#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
637#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
638
639
640/* Interrupt Priorities are WORD accessible only under Armv6-M */
641/* The following MACROS handle generation of the register offset and byte masks */
642#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
643#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
644#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
645
646#define __NVIC_SetPriorityGrouping(X) (void)(X)
647#define __NVIC_GetPriorityGrouping() (0U)
648
655__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
656{
657 if ((int32_t)(IRQn) >= 0)
658 {
659 __COMPILER_BARRIER();
660 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
661 __COMPILER_BARRIER();
662 }
663}
664
665
674__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
675{
676 if ((int32_t)(IRQn) >= 0)
677 {
678 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
679 }
680 else
681 {
682 return(0U);
683 }
684}
685
686
693__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
694{
695 if ((int32_t)(IRQn) >= 0)
696 {
697 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
698 __DSB();
699 __ISB();
700 }
701}
702
703
712__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
713{
714 if ((int32_t)(IRQn) >= 0)
715 {
716 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
717 }
718 else
719 {
720 return(0U);
721 }
722}
723
724
731__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
732{
733 if ((int32_t)(IRQn) >= 0)
734 {
735 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
736 }
737}
738
739
746__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
747{
748 if ((int32_t)(IRQn) >= 0)
749 {
750 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
751 }
752}
753
754
764__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
765{
766 if ((int32_t)(IRQn) >= 0)
767 {
768 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
769 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
770 }
771 else
772 {
773 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
774 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
775 }
776}
777
778
788__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
789{
790
791 if ((int32_t)(IRQn) >= 0)
792 {
793 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
794 }
795 else
796 {
797 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
798 }
799}
800
801
813__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
814{
815 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
816 uint32_t PreemptPriorityBits;
817 uint32_t SubPriorityBits;
818
819 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
820 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
821
822 return (
823 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
824 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
825 );
826}
827
828
840__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
841{
842 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
843 uint32_t PreemptPriorityBits;
844 uint32_t SubPriorityBits;
845
846 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
847 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
848
849 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
850 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
851}
852
853
854
864__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
865{
866 uint32_t *vectors = (uint32_t *)0x0U;
867 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
868 /* ARM Application Note 321 states that the M1 does not require the architectural barrier */
869}
870
871
880__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
881{
882 uint32_t *vectors = (uint32_t *)0x0U;
883 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
884}
885
886
891__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
892{
893 __DSB(); /* Ensure all outstanding memory accesses included
894 buffered write are completed before reset */
895 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
896 SCB_AIRCR_SYSRESETREQ_Msk);
897 __DSB(); /* Ensure completion of memory access */
898
899 for(;;) /* wait until reset */
900 {
901 __NOP();
902 }
903}
904
908/* ########################## FPU functions #################################### */
924__STATIC_INLINE uint32_t SCB_GetFPUType(void)
925{
926 return 0U; /* No FPU */
927}
928
929
934/* ################################## SysTick function ############################################ */
942#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
943
955__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
956{
957 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
958 {
959 return (1UL); /* Reload value impossible */
960 }
961
962 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
963 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
964 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
965 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
966 SysTick_CTRL_TICKINT_Msk |
967 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
968 return (0UL); /* Function successful */
969}
970
971#endif
972
978#ifdef __cplusplus
979}
980#endif
981
982#endif /* __CORE_CM1_H_DEPENDANT */
983
984#endif /* __CMSIS_GENERIC */
cmsis_compiler.h
CMSIS compiler generic header file.
cmsis_version.h
CMSIS Core(M) Version definitions.
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition core_cm1.h:498
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition core_cm1.h:502
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition core_cm1.h:495
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition core_cm1.h:492
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition core_cm1.h:404
SCB
#define SCB
Definition core_cm1.h:571
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition core_cm1.h:414
NVIC
#define NVIC
Definition core_cm1.h:573
SysTick
#define SysTick
Definition core_cm1.h:572
__ISB
#define __ISB()
Instruction Synchronization Barrier.
Definition cmsis_armcc.h:181
__DSB
#define __DSB()
Data Synchronization Barrier.
Definition cmsis_armcc.h:188
__NOP
#define __NOP
No Operation.
Definition cmsis_armcc.h:150
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition core_armv81mml.h:3634
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition core_armv81mml.h:3607
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition core_armv81mml.h:3584
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition core_armv81mml.h:3623
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition core_armv81mml.h:3510
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition core_armv81mml.h:3404
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition core_armv81mml.h:3370
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition core_armv81mml.h:3885
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition core_armv81mml.h:3313
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition core_armv81mml.h:3389
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition core_armv81mml.h:3332
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition core_armv81mml.h:3557
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition core_armv81mml.h:3351
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition core_armv81mml.h:3532
xPSR_Type::@24::V
uint32_t V
Definition core_cm1.h:260
xPSR_Type::@24::Z
uint32_t Z
Definition core_cm1.h:262
APSR_Type::@22::_reserved0
uint32_t _reserved0
Definition core_cm1.h:208
xPSR_Type::@24::T
uint32_t T
Definition core_cm1.h:258
APSR_Type::@22::C
uint32_t C
Definition core_cm1.h:210
CONTROL_Type::@25::_reserved0
uint32_t _reserved0
Definition core_cm1.h:295
IPSR_Type::@23::ISR
uint32_t ISR
Definition core_cm1.h:238
xPSR_Type::@24::ISR
uint32_t ISR
Definition core_cm1.h:256
APSR_Type::@22::V
uint32_t V
Definition core_cm1.h:209
CONTROL_Type::@25::SPSEL
uint32_t SPSEL
Definition core_cm1.h:296
APSR_Type::@22::N
uint32_t N
Definition core_cm1.h:212
IPSR_Type::@23::_reserved0
uint32_t _reserved0
Definition core_cm1.h:239
xPSR_Type::@24::_reserved1
uint32_t _reserved1
Definition core_cm1.h:259
xPSR_Type::@24::_reserved0
uint32_t _reserved0
Definition core_cm1.h:257
APSR_Type::@22::Z
uint32_t Z
Definition core_cm1.h:211
xPSR_Type::@24::N
uint32_t N
Definition core_cm1.h:263
xPSR_Type::@24::C
uint32_t C
Definition core_cm1.h:261
CONTROL_Type::@25::_reserved1
uint32_t _reserved1
Definition core_cm1.h:297
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition core_armv81mml.h:499
SCB_Type
Structure type to access the System Control Block (SCB).
Definition core_armv81mml.h:535
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition core_armv81mml.h:1025
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition core_armv81mml.h:1050
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition core_armv81mml.h:352
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition core_armv81mml.h:460
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition core_armv81mml.h:391
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition core_armv81mml.h:409
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