DIB_Type Struct Reference
Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » Implementation Control Block register (ICB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » Implementation Control Block register (ICB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Memory System Control Registers (IMPLEMENTATION DEFINED) » Power Mode Control Registers » External Wakeup Interrupt Controller Registers » External Wakeup Interrupt Controller (EWIC) interrupt status access registers » Error Banking Registers (IMPLEMENTATION DEFINED) » Processor Configuration Information Registers (IMPLEMENTATION DEFINED) » Software Test Library Observation Registers » Trace Port Interface (TPI) » Floating Point Unit (FPU) » Core Debug Registers (CoreDebug) » Debug Control Block » Debug Identification Block
Structure type to access the Debug Identification Block Registers (DIB). More...
#include <core_armv81mml.h>
Public Attributes | |
| __OM uint32_t | DLAR |
| __IM uint32_t | DLSR |
| __IM uint32_t | DAUTHSTATUS |
| __IM uint32_t | DDEVARCH |
| __IM uint32_t | DDEVTYPE |
| uint32_t | RESERVED0 [2U] |
| uint32_t | RESERVED1 [3U] |
Detailed Description
Structure type to access the Debug Identification Block Registers (DIB).
Definition at line 3008 of file core_armv81mml.h.
The documentation for this struct was generated from the following files:
- /builds/Terstegge/yahal_with_examples/include/CPU/CMSIS/core_armv81mml.h
- /builds/Terstegge/yahal_with_examples/include/CPU/CMSIS/core_armv8mbl.h
- /builds/Terstegge/yahal_with_examples/include/CPU/CMSIS/core_armv8mml.h
- /builds/Terstegge/yahal_with_examples/include/CPU/CMSIS/core_cm23.h
- /builds/Terstegge/yahal_with_examples/include/CPU/CMSIS/core_cm33.h
- /builds/Terstegge/yahal_with_examples/include/CPU/CMSIS/core_cm35p.h
- /builds/Terstegge/yahal_with_examples/include/CPU/CMSIS/core_cm55.h
- /builds/Terstegge/yahal_with_examples/include/CPU/CMSIS/core_cm85.h
- /builds/Terstegge/yahal_with_examples/include/CPU/CMSIS/core_starmc1.h
- /builds/Terstegge/yahal_with_examples/include/CPU/cortex-m33fd/core_armv81mml.h
- /builds/Terstegge/yahal_with_examples/include/CPU/cortex-m33fd/core_armv8mbl.h
- /builds/Terstegge/yahal_with_examples/include/CPU/cortex-m33fd/core_armv8mml.h
- /builds/Terstegge/yahal_with_examples/include/CPU/cortex-m33fd/core_cm33.h
Generated by
1.12.0