STL_Type Struct Reference
Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » Implementation Control Block register (ICB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Memory System Control Registers (IMPLEMENTATION DEFINED) » Power Mode Control Registers » External Wakeup Interrupt Controller Registers » External Wakeup Interrupt Controller (EWIC) interrupt status access registers » Error Banking Registers (IMPLEMENTATION DEFINED) » Processor Configuration Information Registers (IMPLEMENTATION DEFINED) » Software Test Library Observation Registers
Structure type to access the Software Test Library Observation Registerss (STL). More...
#include <core_cm55.h>
Public Attributes | |
| __IM uint32_t | STLNVICPENDOR |
| __IM uint32_t | STLNVICACTVOR |
| uint32_t | RESERVED0 [2U] |
| __OM uint32_t | STLIDMPUSR |
| __IM uint32_t | STLIMPUOR |
| __IM uint32_t | STLD0MPUOR |
| __IM uint32_t | STLD1MPUOR |
Detailed Description
Structure type to access the Software Test Library Observation Registerss (STL).
Definition at line 1859 of file core_cm55.h.
The documentation for this struct was generated from the following file:
- /builds/Terstegge/yahal_with_examples/include/CPU/CMSIS/core_cm55.h
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