YAHAL
Yet Another Hardware Abstraction Library
Loading...
Searching...
No Matches
msp432p401r.h
1/******************************************************************************
2*
3* Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/
4*
5* Redistribution and use in source and binary forms, with or without
6* modification, are permitted provided that the following conditions
7* are met:
8*
9* Redistributions of source code must retain the above copyright
10* notice, this list of conditions and the following disclaimer.
11*
12* Redistributions in binary form must reproduce the above copyright
13* notice, this list of conditions and the following disclaimer in the
14* documentation and/or other materials provided with the
15* distribution.
16*
17* Neither the name of Texas Instruments Incorporated nor the names of
18* its contributors may be used to endorse or promote products derived
19* from this software without specific prior written permission.
20*
21* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32*
33* MSP432P401R Register Definitions
34*
35* This file includes CMSIS compliant component and register definitions
36*
37* For legacy components the definitions that are compatible with MSP430 code,
38* are included with msp432p401r_classic.h
39*
40* With CMSIS definitions, the register defines have been reformatted:
41* ModuleName[ModuleInstance]->RegisterName
42*
43* Writing to CMSIS bit fields can be done through register level
44* or via bitband area access:
45* - ADC14->CTL0 |= ADC14_CTL0_ENC;
46* - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ENC_OFS) = 1;
47*
48* File creation date: 2017-12-06
49*
50******************************************************************************/
51
52#ifndef __MSP432P401R_H__
53#define __MSP432P401R_H__
54
55/* Use standard integer types with explicit width */
56#include <stdint.h>
57
58#ifdef __cplusplus
59 extern "C" {
60#endif
61
62#define __MSP432_HEADER_VERSION__ 3230
63
64/* Remap MSP432 intrinsics to ARM equivalents */
65#include "msp_compatibility.h"
66
67/******************************************************************************
68* include MSP430 legacy definitions to make porting of code from MSP430 *
69* code base easier *
70* With fully CMSIS compliant code, NO_MSP_CLASSIC_DEFINES may be defined in *
71* your project to omit including the classic defines *
72******************************************************************************/
73#ifndef NO_MSP_CLASSIC_DEFINES
74#include "msp432p401r_classic.h"
75#endif
76
77
78#ifndef __CMSIS_CONFIG__
79#define __CMSIS_CONFIG__
80
90/******************************************************************************
91* Processor and Core Peripherals *
92******************************************************************************/
98/******************************************************************************
99* CMSIS-compatible Interrupt Number Definition *
100******************************************************************************/
101typedef enum IRQn
102{
103 /* Cortex-M4 Processor Exceptions Numbers */
104 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
105 HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */
106 MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
107 BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
108 UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
109 SVCall_IRQn = -5, /* 11 SV Call Interrupt */
110 DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
111 PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
112 SysTick_IRQn = -1, /* 15 System Tick Interrupt */
113 /* Peripheral Exceptions Numbers */
114 PSS_IRQn = 0, /* 16 PSS Interrupt */
115 CS_IRQn = 1, /* 17 CS Interrupt */
116 PCM_IRQn = 2, /* 18 PCM Interrupt */
117 WDT_A_IRQn = 3, /* 19 WDT_A Interrupt */
118 FPU_IRQn = 4, /* 20 FPU Interrupt */
119 FLCTL_IRQn = 5, /* 21 Flash Controller Interrupt*/
120 COMP_E0_IRQn = 6, /* 22 COMP_E0 Interrupt */
121 COMP_E1_IRQn = 7, /* 23 COMP_E1 Interrupt */
122 TA0_0_IRQn = 8, /* 24 TA0_0 Interrupt */
123 TA0_N_IRQn = 9, /* 25 TA0_N Interrupt */
124 TA1_0_IRQn = 10, /* 26 TA1_0 Interrupt */
125 TA1_N_IRQn = 11, /* 27 TA1_N Interrupt */
126 TA2_0_IRQn = 12, /* 28 TA2_0 Interrupt */
127 TA2_N_IRQn = 13, /* 29 TA2_N Interrupt */
128 TA3_0_IRQn = 14, /* 30 TA3_0 Interrupt */
129 TA3_N_IRQn = 15, /* 31 TA3_N Interrupt */
130 EUSCIA0_IRQn = 16, /* 32 EUSCIA0 Interrupt */
131 EUSCIA1_IRQn = 17, /* 33 EUSCIA1 Interrupt */
132 EUSCIA2_IRQn = 18, /* 34 EUSCIA2 Interrupt */
133 EUSCIA3_IRQn = 19, /* 35 EUSCIA3 Interrupt */
134 EUSCIB0_IRQn = 20, /* 36 EUSCIB0 Interrupt */
135 EUSCIB1_IRQn = 21, /* 37 EUSCIB1 Interrupt */
136 EUSCIB2_IRQn = 22, /* 38 EUSCIB2 Interrupt */
137 EUSCIB3_IRQn = 23, /* 39 EUSCIB3 Interrupt */
138 ADC14_IRQn = 24, /* 40 ADC14 Interrupt */
139 T32_INT1_IRQn = 25, /* 41 T32_INT1 Interrupt */
140 T32_INT2_IRQn = 26, /* 42 T32_INT2 Interrupt */
141 T32_INTC_IRQn = 27, /* 43 T32_INTC Interrupt */
142 AES256_IRQn = 28, /* 44 AES256 Interrupt */
143 RTC_C_IRQn = 29, /* 45 RTC_C Interrupt */
144 DMA_ERR_IRQn = 30, /* 46 DMA_ERR Interrupt */
145 DMA_INT3_IRQn = 31, /* 47 DMA_INT3 Interrupt */
146 DMA_INT2_IRQn = 32, /* 48 DMA_INT2 Interrupt */
147 DMA_INT1_IRQn = 33, /* 49 DMA_INT1 Interrupt */
148 DMA_INT0_IRQn = 34, /* 50 DMA_INT0 Interrupt */
149 PORT1_IRQn = 35, /* 51 Port1 Interrupt */
150 PORT2_IRQn = 36, /* 52 Port2 Interrupt */
151 PORT3_IRQn = 37, /* 53 Port3 Interrupt */
152 PORT4_IRQn = 38, /* 54 Port4 Interrupt */
153 PORT5_IRQn = 39, /* 55 Port5 Interrupt */
154 PORT6_IRQn = 40 /* 56 Port6 Interrupt */
155} IRQn_Type;
156
157/******************************************************************************
158* Processor and Core Peripheral Section *
159******************************************************************************/
160#define __CM4_REV 0x0001 /* Core revision r0p1 */
161#define __MPU_PRESENT 1 /* MPU present or not */
162#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Prio Levels */
163#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
164#define __FPU_PRESENT 1 /* FPU present or not */
165
166/******************************************************************************
167* Available Peripherals *
168******************************************************************************/
169#define __MCU_HAS_ADC14__
170#define __MCU_HAS_AES256__
171#define __MCU_HAS_CAPTIO0__
172#define __MCU_HAS_CAPTIO1__
173#define __MCU_HAS_COMP_E0__
174#define __MCU_HAS_COMP_E1__
175#define __MCU_HAS_CRC32__
176#define __MCU_HAS_CS__
177#define __MCU_HAS_DIO__
178#define __MCU_HAS_DMA__
179#define __MCU_HAS_EUSCI_A0__
180#define __MCU_HAS_EUSCI_A1__
181#define __MCU_HAS_EUSCI_A2__
182#define __MCU_HAS_EUSCI_A3__
183#define __MCU_HAS_EUSCI_B0__
184#define __MCU_HAS_EUSCI_B1__
185#define __MCU_HAS_EUSCI_B2__
186#define __MCU_HAS_EUSCI_B3__
187#define __MCU_HAS_FLCTL__
188#define __MCU_HAS_FL_BOOTOVER_MAILBOX__
189#define __MCU_HAS_PCM__
190#define __MCU_HAS_PMAP__
191#define __MCU_HAS_PSS__
192#define __MCU_HAS_REF_A__
193#define __MCU_HAS_RSTCTL__
194#define __MCU_HAS_RTC_C__
195#define __MCU_HAS_SYSCTL__
196#define __MCU_HAS_TIMER32__
197#define __MCU_HAS_TIMER_A0__
198#define __MCU_HAS_TIMER_A1__
199#define __MCU_HAS_TIMER_A2__
200#define __MCU_HAS_TIMER_A3__
201#define __MCU_HAS_TLV__
202#define __MCU_HAS_WDT_A__
204/* Definitions to show that specific ports are available */
205
206#define __MSP432_HAS_PORTA_R__
207#define __MSP432_HAS_PORTB_R__
208#define __MSP432_HAS_PORTC_R__
209#define __MSP432_HAS_PORTD_R__
210#define __MSP432_HAS_PORTE_R__
211#define __MSP432_HAS_PORTJ_R__
212
213#define __MSP432_HAS_PORT1_R__
214#define __MSP432_HAS_PORT2_R__
215#define __MSP432_HAS_PORT3_R__
216#define __MSP432_HAS_PORT4_R__
217#define __MSP432_HAS_PORT5_R__
218#define __MSP432_HAS_PORT6_R__
219#define __MSP432_HAS_PORT7_R__
220#define __MSP432_HAS_PORT8_R__
221#define __MSP432_HAS_PORT9_R__
222#define __MSP432_HAS_PORT10_R__
223
224 /* end of group MSP432P401R_CMSIS */
226
227/* Include CMSIS Cortex-M4 Core Peripheral Access Layer Header File */
228#ifdef __TI_ARM__
229/* disable the TI ULP advisor check for the core header file definitions */
230#pragma diag_push
231#pragma CHECK_ULP("none")
232#include "core_cm4.h"
233#pragma diag_pop
234#else
235#include "core_cm4.h"
236#endif
237
238/* System Header */
239#include "system_msp432p401r.h"
240
241/******************************************************************************
242* Definition of standard bits *
243******************************************************************************/
244#define BIT0 (uint16_t)(0x0001)
245#define BIT1 (uint16_t)(0x0002)
246#define BIT2 (uint16_t)(0x0004)
247#define BIT3 (uint16_t)(0x0008)
248#define BIT4 (uint16_t)(0x0010)
249#define BIT5 (uint16_t)(0x0020)
250#define BIT6 (uint16_t)(0x0040)
251#define BIT7 (uint16_t)(0x0080)
252#define BIT8 (uint16_t)(0x0100)
253#define BIT9 (uint16_t)(0x0200)
254#define BITA (uint16_t)(0x0400)
255#define BITB (uint16_t)(0x0800)
256#define BITC (uint16_t)(0x1000)
257#define BITD (uint16_t)(0x2000)
258#define BITE (uint16_t)(0x4000)
259#define BITF (uint16_t)(0x8000)
260#define BIT(x) ((uint16_t)1 << (x))
261
262/******************************************************************************
263* Device and peripheral memory map *
264******************************************************************************/
269#define FLASH_BASE ((uint32_t)0x00000000)
270#define SRAM_BASE ((uint32_t)0x20000000)
271#define PERIPH_BASE ((uint32_t)0x40000000)
272#define PERIPH_BASE2 ((uint32_t)0xE0000000)
274#define ADC14_BASE (PERIPH_BASE +0x00012000)
275#define AES256_BASE (PERIPH_BASE +0x00003C00)
276#define CAPTIO0_BASE (PERIPH_BASE +0x00005400)
277#define CAPTIO1_BASE (PERIPH_BASE +0x00005800)
278#define COMP_E0_BASE (PERIPH_BASE +0x00003400)
279#define COMP_E1_BASE (PERIPH_BASE +0x00003800)
280#define CRC32_BASE (PERIPH_BASE +0x00004000)
281#define CS_BASE (PERIPH_BASE +0x00010400)
282#define DIO_BASE (PERIPH_BASE +0x00004C00)
283#define DMA_BASE (PERIPH_BASE +0x0000E000)
284#define EUSCI_A0_BASE (PERIPH_BASE +0x00001000)
285#define EUSCI_A0_SPI_BASE (PERIPH_BASE +0x00001000)
286#define EUSCI_A1_BASE (PERIPH_BASE +0x00001400)
287#define EUSCI_A1_SPI_BASE (PERIPH_BASE +0x00001400)
288#define EUSCI_A2_BASE (PERIPH_BASE +0x00001800)
289#define EUSCI_A2_SPI_BASE (PERIPH_BASE +0x00001800)
290#define EUSCI_A3_BASE (PERIPH_BASE +0x00001C00)
291#define EUSCI_A3_SPI_BASE (PERIPH_BASE +0x00001C00)
292#define EUSCI_B0_BASE (PERIPH_BASE +0x00002000)
293#define EUSCI_B0_SPI_BASE (PERIPH_BASE +0x00002000)
294#define EUSCI_B1_BASE (PERIPH_BASE +0x00002400)
295#define EUSCI_B1_SPI_BASE (PERIPH_BASE +0x00002400)
296#define EUSCI_B2_BASE (PERIPH_BASE +0x00002800)
297#define EUSCI_B2_SPI_BASE (PERIPH_BASE +0x00002800)
298#define EUSCI_B3_BASE (PERIPH_BASE +0x00002C00)
299#define EUSCI_B3_SPI_BASE (PERIPH_BASE +0x00002C00)
300#define FLCTL_BASE (PERIPH_BASE +0x00011000)
301#define FL_BOOTOVER_MAILBOX_BASE ((uint32_t)0x00200000)
302#define PCM_BASE (PERIPH_BASE +0x00010000)
303#define PMAP_BASE (PERIPH_BASE +0x00005000)
304#define PSS_BASE (PERIPH_BASE +0x00010800)
305#define REF_A_BASE (PERIPH_BASE +0x00003000)
306#define RSTCTL_BASE (PERIPH_BASE2+0x00042000)
307#define RTC_C_BASE (PERIPH_BASE +0x00004400)
308#define RTC_C_BCD_BASE (PERIPH_BASE +0x00004400)
309#define SYSCTL_BASE (PERIPH_BASE2+0x00043000)
310#define TIMER32_BASE (PERIPH_BASE +0x0000C000)
311#define TIMER_A0_BASE (PERIPH_BASE +0x00000000)
312#define TIMER_A1_BASE (PERIPH_BASE +0x00000400)
313#define TIMER_A2_BASE (PERIPH_BASE +0x00000800)
314#define TIMER_A3_BASE (PERIPH_BASE +0x00000C00)
315#define TLV_BASE ((uint32_t)0x00201000)
316#define WDT_A_BASE (PERIPH_BASE +0x00004800) /* end of group MSP432P401R_MemoryMap */
320
321/******************************************************************************
322* Definitions for bit band access *
323******************************************************************************/
324#define BITBAND_SRAM_BASE ((uint32_t)(0x22000000))
325#define BITBAND_PERI_BASE ((uint32_t)(0x42000000))
326
327/* SRAM allows 32 bit bit band access */
328#define BITBAND_SRAM(x, b) (*((__IO uint32_t *) (BITBAND_SRAM_BASE + (((uint32_t)(volatile const uint32_t *)&(x)) - SRAM_BASE )*32 + (b)*4)))
329/* peripherals with 8 bit or 16 bit register access allow only 8 bit or 16 bit bit band access, so cast to 8 bit always */
330#define BITBAND_PERI(x, b) (*((__IO uint8_t *) (BITBAND_PERI_BASE + (((uint32_t)(volatile const uint32_t *)&(x)) - PERIPH_BASE)*32 + (b)*4)))
331
332/******************************************************************************
333* Peripheral register definitions *
334******************************************************************************/
340/* ------- Start of section using anonymous unions and disabling warnings ------- */
341#if defined (__CC_ARM)
342 #pragma push
343 #pragma anon_unions
344#elif defined (__ICCARM__)
345 #pragma language=extended
346#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
347 #pragma clang diagnostic push
348 #pragma clang diagnostic ignored "-Wc11-extensions"
349#elif defined (__GNUC__)
350 /* anonymous unions are enabled by default */
351#elif defined (__TI_ARM__)
352 /* anonymous unions are enabled by default */
353#else
354 #warning Not supported compiler type
355#endif
356
357
358/******************************************************************************
359* ADC14 Registers
360******************************************************************************/
364typedef struct {
365 __IO uint32_t CTL0;
366 __IO uint32_t CTL1;
367 __IO uint32_t LO0;
368 __IO uint32_t HI0;
369 __IO uint32_t LO1;
370 __IO uint32_t HI1;
371 __IO uint32_t MCTL[32];
372 __IO uint32_t MEM[32];
373 uint32_t RESERVED0[9];
374 __IO uint32_t IER0;
375 __IO uint32_t IER1;
376 __I uint32_t IFGR0;
377 __I uint32_t IFGR1;
378 __O uint32_t CLRIFGR0;
379 __IO uint32_t CLRIFGR1;
380 __IO uint32_t IV;
381} ADC14_Type;
382 /* end of group ADC14 */
384
385
386/******************************************************************************
387* AES256 Registers
388******************************************************************************/
392typedef struct {
393 __IO uint16_t CTL0;
394 __IO uint16_t CTL1;
395 __IO uint16_t STAT;
396 __O uint16_t KEY;
397 __O uint16_t DIN;
398 __O uint16_t DOUT;
399 __O uint16_t XDIN;
400 __O uint16_t XIN;
401} AES256_Type;
402 /* end of group AES256 */
404
405
406/******************************************************************************
407* CAPTIO Registers
408******************************************************************************/
412typedef struct {
413 uint16_t RESERVED0[7];
414 __IO uint16_t CTL;
415} CAPTIO_Type;
416 /* end of group CAPTIO */
418
419
420/******************************************************************************
421* COMP_E Registers
422******************************************************************************/
426typedef struct {
427 __IO uint16_t CTL0;
428 __IO uint16_t CTL1;
429 __IO uint16_t CTL2;
430 __IO uint16_t CTL3;
431 uint16_t RESERVED0[2];
432 __IO uint16_t INT;
433 __I uint16_t IV;
434} COMP_E_Type;
435 /* end of group COMP_E */
437
438
439/******************************************************************************
440* CRC32 Registers
441******************************************************************************/
445typedef struct {
446 __IO uint16_t DI32;
447 uint16_t RESERVED0;
448 __IO uint16_t DIRB32;
449 uint16_t RESERVED1;
450 __IO uint16_t INIRES32_LO;
451 __IO uint16_t INIRES32_HI;
452 __IO uint16_t RESR32_LO;
453 __IO uint16_t RESR32_HI;
454 __IO uint16_t DI16;
455 uint16_t RESERVED2;
456 __IO uint16_t DIRB16;
457 uint16_t RESERVED3;
458 __IO uint16_t INIRES16;
459 uint16_t RESERVED4[2];
460 __IO uint16_t RESR16;
461} CRC32_Type;
462 /* end of group CRC32 */
464
465
466/******************************************************************************
467* CS Registers
468******************************************************************************/
472typedef struct {
473 __IO uint32_t KEY;
474 __IO uint32_t CTL0;
475 __IO uint32_t CTL1;
476 __IO uint32_t CTL2;
477 __IO uint32_t CTL3;
478 uint32_t RESERVED0[7];
479 __IO uint32_t CLKEN;
480 __I uint32_t STAT;
481 uint32_t RESERVED1[2];
482 __IO uint32_t IE;
483 uint32_t RESERVED2;
484 __I uint32_t IFG;
485 uint32_t RESERVED3;
486 __O uint32_t CLRIFG;
487 uint32_t RESERVED4;
488 __O uint32_t SETIFG;
489 uint32_t RESERVED5;
490 __IO uint32_t DCOERCAL0;
491 __IO uint32_t DCOERCAL1;
492} CS_Type;
493 /* end of group CS */
495
496
497/******************************************************************************
498* DIO Registers
499******************************************************************************/
503typedef struct {
504 union {
505 __I uint16_t IN;
506 struct {
507 __I uint8_t IN_L;
508 __I uint8_t IN_H;
509 };
510 };
511 union {
512 __IO uint16_t OUT;
513 struct {
514 __IO uint8_t OUT_L;
515 __IO uint8_t OUT_H;
516 };
517 };
518 union {
519 __IO uint16_t DIR;
520 struct {
521 __IO uint8_t DIR_L;
522 __IO uint8_t DIR_H;
523 };
524 };
525 union {
526 __IO uint16_t REN;
527 struct {
528 __IO uint8_t REN_L;
529 __IO uint8_t REN_H;
530 };
531 };
532 union {
533 __IO uint16_t DS;
534 struct {
535 __IO uint8_t DS_L;
536 __IO uint8_t DS_H;
537 };
538 };
539 union {
540 __IO uint16_t SEL0;
541 struct {
542 __IO uint8_t SEL0_L;
543 __IO uint8_t SEL0_H;
544 };
545 };
546 union {
547 __IO uint16_t SEL1;
548 struct {
549 __IO uint8_t SEL1_L;
550 __IO uint8_t SEL1_H;
551 };
552 };
553 __I uint16_t IV_L;
554 uint16_t RESERVED0[3];
555 union {
556 __IO uint16_t SELC;
557 struct {
558 __IO uint8_t SELC_L;
559 __IO uint8_t SELC_H;
560 };
561 };
562 union {
563 __IO uint16_t IES;
564 struct {
565 __IO uint8_t IES_L;
566 __IO uint8_t IES_H;
567 };
568 };
569 union {
570 __IO uint16_t IE;
571 struct {
572 __IO uint8_t IE_L;
573 __IO uint8_t IE_H;
574 };
575 };
576 union {
577 __IO uint16_t IFG;
578 struct {
579 __IO uint8_t IFG_L;
580 __IO uint8_t IFG_H;
581 };
582 };
583 __I uint16_t IV_H;
584} DIO_PORT_Interruptable_Type;
585
586typedef struct {
587 union {
588 __I uint16_t IN;
589 struct {
590 __I uint8_t IN_L;
591 __I uint8_t IN_H;
592 };
593 };
594 union {
595 __IO uint16_t OUT;
596 struct {
597 __IO uint8_t OUT_L;
598 __IO uint8_t OUT_H;
599 };
600 };
601 union {
602 __IO uint16_t DIR;
603 struct {
604 __IO uint8_t DIR_L;
605 __IO uint8_t DIR_H;
606 };
607 };
608 union {
609 __IO uint16_t REN;
610 struct {
611 __IO uint8_t REN_L;
612 __IO uint8_t REN_H;
613 };
614 };
615 union {
616 __IO uint16_t DS;
617 struct {
618 __IO uint8_t DS_L;
619 __IO uint8_t DS_H;
620 };
621 };
622 union {
623 __IO uint16_t SEL0;
624 struct {
625 __IO uint8_t SEL0_L;
626 __IO uint8_t SEL0_H;
627 };
628 };
629 union {
630 __IO uint16_t SEL1;
631 struct {
632 __IO uint8_t SEL1_L;
633 __IO uint8_t SEL1_H;
634 };
635 };
636 uint16_t RESERVED0[4];
637 union {
638 __IO uint16_t SELC;
639 struct {
640 __IO uint8_t SELC_L;
641 __IO uint8_t SELC_H;
642 };
643 };
644} DIO_PORT_Not_Interruptable_Type;
645
646
647typedef struct {
648 __I uint8_t IN;
649 uint8_t RESERVED0;
650 __IO uint8_t OUT;
651 uint8_t RESERVED1;
652 __IO uint8_t DIR;
653 uint8_t RESERVED2;
654 __IO uint8_t REN;
655 uint8_t RESERVED3;
656 __IO uint8_t DS;
657 uint8_t RESERVED4;
658 __IO uint8_t SEL0;
659 uint8_t RESERVED5;
660 __IO uint8_t SEL1;
661 uint8_t RESERVED6;
662 __I uint16_t IV;
663 uint8_t RESERVED7[6];
664 __IO uint8_t SELC;
665 uint8_t RESERVED8;
666 __IO uint8_t IES;
667 uint8_t RESERVED9;
668 __IO uint8_t IE;
669 uint8_t RESERVED10;
670 __IO uint8_t IFG;
671 uint8_t RESERVED11;
672} DIO_PORT_Odd_Interruptable_Type;
673
674typedef struct {
675 uint8_t RESERVED0;
676 __I uint8_t IN;
677 uint8_t RESERVED1;
678 __IO uint8_t OUT;
679 uint8_t RESERVED2;
680 __IO uint8_t DIR;
681 uint8_t RESERVED3;
682 __IO uint8_t REN;
683 uint8_t RESERVED4;
684 __IO uint8_t DS;
685 uint8_t RESERVED5;
686 __IO uint8_t SEL0;
687 uint8_t RESERVED6;
688 __IO uint8_t SEL1;
689 uint8_t RESERVED7[9];
690 __IO uint8_t SELC;
691 uint8_t RESERVED8;
692 __IO uint8_t IES;
693 uint8_t RESERVED9;
694 __IO uint8_t IE;
695 uint8_t RESERVED10;
696 __IO uint8_t IFG;
697 __I uint16_t IV;
698} DIO_PORT_Even_Interruptable_Type;
699 /* end of group MSP432P401R_DIO */
701
702
703/******************************************************************************
704* DMA Registers
705******************************************************************************/
709typedef struct {
710 __I uint32_t DEVICE_CFG;
711 __IO uint32_t SW_CHTRIG;
712 uint32_t RESERVED0[2];
713 __IO uint32_t CH_SRCCFG[32];
714 uint32_t RESERVED1[28];
715 __IO uint32_t INT1_SRCCFG;
716 __IO uint32_t INT2_SRCCFG;
717 __IO uint32_t INT3_SRCCFG;
718 uint32_t RESERVED2;
719 __I uint32_t INT0_SRCFLG;
720 __O uint32_t INT0_CLRFLG;
721} DMA_Channel_Type;
722
723typedef struct {
724 __I uint32_t STAT;
725 __O uint32_t CFG;
726 __IO uint32_t CTLBASE;
727 __I uint32_t ALTBASE;
728 __I uint32_t WAITSTAT;
729 __O uint32_t SWREQ;
730 __IO uint32_t USEBURSTSET;
731 __O uint32_t USEBURSTCLR;
732 __IO uint32_t REQMASKSET;
733 __O uint32_t REQMASKCLR;
734 __IO uint32_t ENASET;
735 __O uint32_t ENACLR;
736 __IO uint32_t ALTSET;
737 __O uint32_t ALTCLR;
738 __IO uint32_t PRIOSET;
739 __O uint32_t PRIOCLR;
740 uint32_t RESERVED4[3];
741 __IO uint32_t ERRCLR;
742} DMA_Control_Type;
743 /* end of group DMA */
745
746
747/******************************************************************************
748* EUSCI_A Registers
749******************************************************************************/
753typedef struct {
754 __IO uint16_t CTLW0;
755 __IO uint16_t CTLW1;
756 uint16_t RESERVED0;
757 __IO uint16_t BRW;
758 __IO uint16_t MCTLW;
759 __IO uint16_t STATW;
760 __I uint16_t RXBUF;
761 __IO uint16_t TXBUF;
762 __IO uint16_t ABCTL;
763 __IO uint16_t IRCTL;
764 uint16_t RESERVED1[3];
765 __IO uint16_t IE;
766 __IO uint16_t IFG;
767 __I uint16_t IV;
768} EUSCI_A_Type;
769 /* end of group EUSCI_A */
771
775typedef struct {
776 __IO uint16_t CTLW0;
777 uint16_t RESERVED0[2];
778 __IO uint16_t BRW;
779 uint16_t RESERVED1;
780 __IO uint16_t STATW;
781 __I uint16_t RXBUF;
782 __IO uint16_t TXBUF;
783 uint16_t RESERVED2[5];
784 __IO uint16_t IE;
785 __IO uint16_t IFG;
786 __I uint16_t IV;
787} EUSCI_A_SPI_Type;
788 /* end of group EUSCI_A_SPI */
790
791
792/******************************************************************************
793* EUSCI_B Registers
794******************************************************************************/
798typedef struct {
799 __IO uint16_t CTLW0;
800 __IO uint16_t CTLW1;
801 uint16_t RESERVED0;
802 __IO uint16_t BRW;
803 __IO uint16_t STATW;
804 __IO uint16_t TBCNT;
805 __I uint16_t RXBUF;
806 __IO uint16_t TXBUF;
807 uint16_t RESERVED1[2];
808 __IO uint16_t I2COA0;
809 __IO uint16_t I2COA1;
810 __IO uint16_t I2COA2;
811 __IO uint16_t I2COA3;
812 __I uint16_t ADDRX;
813 __IO uint16_t ADDMASK;
814 __IO uint16_t I2CSA;
815 uint16_t RESERVED2[4];
816 __IO uint16_t IE;
817 __IO uint16_t IFG;
818 __I uint16_t IV;
819} EUSCI_B_Type;
820 /* end of group EUSCI_B */
822
826typedef struct {
827 __IO uint16_t CTLW0;
828 uint16_t RESERVED0[2];
829 __IO uint16_t BRW;
830 __IO uint16_t STATW;
831 uint16_t RESERVED1;
832 __I uint16_t RXBUF;
833 __IO uint16_t TXBUF;
834 uint16_t RESERVED2[13];
835 __IO uint16_t IE;
836 __IO uint16_t IFG;
837 __I uint16_t IV;
838} EUSCI_B_SPI_Type;
839 /* end of group EUSCI_B_SPI */
841
842
843/******************************************************************************
844* FLCTL Registers
845******************************************************************************/
849typedef struct {
850 __I uint32_t POWER_STAT;
851 uint32_t RESERVED0[3];
852 __IO uint32_t BANK0_RDCTL;
853 __IO uint32_t BANK1_RDCTL;
854 uint32_t RESERVED1[2];
855 __IO uint32_t RDBRST_CTLSTAT;
856 __IO uint32_t RDBRST_STARTADDR;
857 __IO uint32_t RDBRST_LEN;
858 uint32_t RESERVED2[4];
859 __IO uint32_t RDBRST_FAILADDR;
860 __IO uint32_t RDBRST_FAILCNT;
861 uint32_t RESERVED3[3];
862 __IO uint32_t PRG_CTLSTAT;
863 __IO uint32_t PRGBRST_CTLSTAT;
864 __IO uint32_t PRGBRST_STARTADDR;
865 uint32_t RESERVED4;
866 __IO uint32_t PRGBRST_DATA0_0;
867 __IO uint32_t PRGBRST_DATA0_1;
868 __IO uint32_t PRGBRST_DATA0_2;
869 __IO uint32_t PRGBRST_DATA0_3;
870 __IO uint32_t PRGBRST_DATA1_0;
871 __IO uint32_t PRGBRST_DATA1_1;
872 __IO uint32_t PRGBRST_DATA1_2;
873 __IO uint32_t PRGBRST_DATA1_3;
874 __IO uint32_t PRGBRST_DATA2_0;
875 __IO uint32_t PRGBRST_DATA2_1;
876 __IO uint32_t PRGBRST_DATA2_2;
877 __IO uint32_t PRGBRST_DATA2_3;
878 __IO uint32_t PRGBRST_DATA3_0;
879 __IO uint32_t PRGBRST_DATA3_1;
880 __IO uint32_t PRGBRST_DATA3_2;
881 __IO uint32_t PRGBRST_DATA3_3;
882 __IO uint32_t ERASE_CTLSTAT;
883 __IO uint32_t ERASE_SECTADDR;
884 uint32_t RESERVED5[2];
885 __IO uint32_t BANK0_INFO_WEPROT;
886 __IO uint32_t BANK0_MAIN_WEPROT;
887 uint32_t RESERVED6[2];
888 __IO uint32_t BANK1_INFO_WEPROT;
889 __IO uint32_t BANK1_MAIN_WEPROT;
890 uint32_t RESERVED7[2];
891 __IO uint32_t BMRK_CTLSTAT;
892 __IO uint32_t BMRK_IFETCH;
893 __IO uint32_t BMRK_DREAD;
894 __IO uint32_t BMRK_CMP;
895 uint32_t RESERVED8[4];
896 __IO uint32_t IFG;
897 __IO uint32_t IE;
898 __IO uint32_t CLRIFG;
899 __IO uint32_t SETIFG;
900 __I uint32_t READ_TIMCTL;
901 __I uint32_t READMARGIN_TIMCTL;
902 __I uint32_t PRGVER_TIMCTL;
903 __I uint32_t ERSVER_TIMCTL;
904 __I uint32_t LKGVER_TIMCTL;
905 __I uint32_t PROGRAM_TIMCTL;
906 __I uint32_t ERASE_TIMCTL;
907 __I uint32_t MASSERASE_TIMCTL;
908 __I uint32_t BURSTPRG_TIMCTL;
909} FLCTL_Type;
910 /* end of group FLCTL */
912
913
914/******************************************************************************
915* FL_BOOTOVER_MAILBOX Registers
916******************************************************************************/
920typedef struct {
921 __IO uint32_t SEC_ZONE_SECEN;
922 __IO uint32_t SEC_ZONE_START_ADDR;
923 __IO uint32_t SEC_ZONE_LENGTH;
924 __IO uint32_t SEC_ZONE_AESINIT_VECT[4];
925 __IO uint32_t SEC_ZONE_SECKEYS[8];
926 __IO uint32_t SEC_ZONE_UNENC_PWD[4];
927 __IO uint32_t SEC_ZONE_ENCUPDATE_EN;
928 __IO uint32_t SEC_ZONE_DATA_EN;
929 __IO uint32_t SEC_ZONE_ACK;
930 uint32_t RESERVED0[2];
931} SEC_ZONE_PARAMS_Type;
932 /* end of group SEC_ZONE_PARAMS */
934
938typedef struct {
939 __IO uint32_t SEC_ZONE_PAYLOADADDR;
940 __IO uint32_t SEC_ZONE_PAYLOADLEN;
941 __IO uint32_t SEC_ZONE_UPDATE_ACK;
942 uint32_t RESERVED0;
943} SEC_ZONE_UPDATE_Type;
944 /* end of group SEC_ZONE_UPDATE */
946
950typedef struct {
951 __IO uint32_t MB_START;
952 __IO uint32_t CMD;
953 uint32_t RESERVED0[2];
954 __IO uint32_t JTAG_SWD_LOCK_SECEN;
955 __IO uint32_t JTAG_SWD_LOCK_AES_INIT_VECT[4];
956 __IO uint32_t JTAG_SWD_LOCK_AES_SECKEYS[8];
957 __IO uint32_t JTAG_SWD_LOCK_UNENC_PWD[4];
958 __IO uint32_t JTAG_SWD_LOCK_ACK;
959 uint32_t RESERVED1[2];
960 SEC_ZONE_PARAMS_Type SEC_ZONE_PARAMS[4];
961 __IO uint32_t BSL_ENABLE;
962 __IO uint32_t BSL_START_ADDRESS;
963 __IO uint32_t BSL_PARAMETERS;
964 uint32_t RESERVED2[2];
965 __IO uint32_t BSL_ACK;
966 __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADADD;
967 __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADLEN;
968 __IO uint32_t JTAG_SWD_LOCK_DST_ADDR;
969 __IO uint32_t ENC_UPDATE_ACK;
970 uint32_t RESERVED3;
971 SEC_ZONE_UPDATE_Type SEC_ZONE_UPDATE[4];
972 uint32_t RESERVED4;
973 __IO uint32_t FACTORY_RESET_ENABLE;
974 __IO uint32_t FACTORY_RESET_PWDEN;
975 __IO uint32_t FACTORY_RESET_PWD[4];
976 __IO uint32_t FACTORY_RESET_PARAMS_ACK;
977 uint32_t RESERVED5;
978 __IO uint32_t FACTORY_RESET_PASSWORD[4];
979 __IO uint32_t FACTORY_RESET_ACK;
980 uint32_t RESERVED6[2];
981 __IO uint32_t MB_END;
982} FL_BOOTOVER_MAILBOX_Type;
983 /* end of group FL_BOOTOVER_MAILBOX */
985
986
987/******************************************************************************
988* PCM Registers
989******************************************************************************/
993typedef struct {
994 __IO uint32_t CTL0;
995 __IO uint32_t CTL1;
996 __IO uint32_t IE;
997 __I uint32_t IFG;
998 __O uint32_t CLRIFG;
999} PCM_Type;
1000 /* end of group PCM */
1002
1003
1004/******************************************************************************
1005* PMAP Registers
1006******************************************************************************/
1010typedef struct {
1011 __IO uint16_t KEYID;
1012 __IO uint16_t CTL;
1013} PMAP_COMMON_Type;
1014
1015typedef struct {
1016 union {
1017 __IO uint16_t PMAP_REGISTER[4];
1018 struct {
1019 __IO uint8_t PMAP_REGISTER0;
1020 __IO uint8_t PMAP_REGISTER1;
1021 __IO uint8_t PMAP_REGISTER2;
1022 __IO uint8_t PMAP_REGISTER3;
1023 __IO uint8_t PMAP_REGISTER4;
1024 __IO uint8_t PMAP_REGISTER5;
1025 __IO uint8_t PMAP_REGISTER6;
1026 __IO uint8_t PMAP_REGISTER7;
1027 };
1028 };
1029} PMAP_REGISTER_Type;
1030 /* end of group PMAP */
1032
1033
1034/******************************************************************************
1035* PSS Registers
1036******************************************************************************/
1040typedef struct {
1041 __IO uint32_t KEY;
1042 __IO uint32_t CTL0;
1043 uint32_t RESERVED0[11];
1044 __IO uint32_t IE;
1045 __I uint32_t IFG;
1046 __IO uint32_t CLRIFG;
1047} PSS_Type;
1048 /* end of group PSS */
1050
1051
1052/******************************************************************************
1053* REF_A Registers
1054******************************************************************************/
1058typedef struct {
1059 __IO uint16_t CTL0;
1060} REF_A_Type;
1061 /* end of group REF_A */
1063
1064
1065/******************************************************************************
1066* RSTCTL Registers
1067******************************************************************************/
1071typedef struct {
1072 __IO uint32_t RESET_REQ;
1073 __I uint32_t HARDRESET_STAT;
1074 __IO uint32_t HARDRESET_CLR;
1075 __IO uint32_t HARDRESET_SET;
1076 __I uint32_t SOFTRESET_STAT;
1077 __IO uint32_t SOFTRESET_CLR;
1078 __IO uint32_t SOFTRESET_SET;
1079 uint32_t RESERVED0[57];
1080 __I uint32_t PSSRESET_STAT;
1081 __IO uint32_t PSSRESET_CLR;
1082 __I uint32_t PCMRESET_STAT;
1083 __IO uint32_t PCMRESET_CLR;
1084 __I uint32_t PINRESET_STAT;
1085 __IO uint32_t PINRESET_CLR;
1086 __I uint32_t REBOOTRESET_STAT;
1087 __IO uint32_t REBOOTRESET_CLR;
1088 __I uint32_t CSRESET_STAT;
1089 __IO uint32_t CSRESET_CLR;
1090} RSTCTL_Type;
1091 /* end of group RSTCTL */
1093
1094
1095/******************************************************************************
1096* RTC_C Registers
1097******************************************************************************/
1101typedef struct {
1102 __IO uint16_t CTL0;
1103 __IO uint16_t CTL13;
1104 __IO uint16_t OCAL;
1105 __IO uint16_t TCMP;
1106 __IO uint16_t PS0CTL;
1107 __IO uint16_t PS1CTL;
1108 __IO uint16_t PS;
1109 __I uint16_t IV;
1110 __IO uint16_t TIM0;
1111 __IO uint16_t TIM1;
1112 __IO uint16_t DATE;
1113 __IO uint16_t YEAR;
1114 __IO uint16_t AMINHR;
1115 __IO uint16_t ADOWDAY;
1116 __IO uint16_t BIN2BCD;
1117 __IO uint16_t BCD2BIN;
1118} RTC_C_Type;
1119 /* end of group RTC_C */
1121
1125typedef struct {
1126 uint16_t RESERVED0[8];
1127 __IO uint16_t TIM0;
1128 __IO uint16_t TIM1;
1129 __IO uint16_t DATE;
1130 __IO uint16_t YEAR;
1131 __IO uint16_t AMINHR;
1132 __IO uint16_t ADOWDAY;
1133} RTC_C_BCD_Type;
1134 /* end of group RTC_C_BCD */
1136
1137
1138/******************************************************************************
1139* SYSCTL Registers
1140******************************************************************************/
1144typedef struct {
1145 __IO uint32_t REBOOT_CTL;
1146 __IO uint32_t NMI_CTLSTAT;
1147 __IO uint32_t WDTRESET_CTL;
1148 __IO uint32_t PERIHALT_CTL;
1149 __I uint32_t SRAM_SIZE;
1150 __IO uint32_t SRAM_BANKEN;
1151 __IO uint32_t SRAM_BANKRET;
1152 uint32_t RESERVED0;
1153 __I uint32_t FLASH_SIZE;
1154 uint32_t RESERVED1[3];
1155 __IO uint32_t DIO_GLTFLT_CTL;
1156 uint32_t RESERVED2[3];
1157 __IO uint32_t SECDATA_UNLOCK;
1158} SYSCTL_Type;
1159
1160typedef struct {
1161 __IO uint32_t MASTER_UNLOCK;
1162 __IO uint32_t BOOTOVER_REQ[2];
1163 __IO uint32_t BOOTOVER_ACK;
1164 __IO uint32_t RESET_REQ;
1165 __IO uint32_t RESET_STATOVER;
1166 uint32_t RESERVED7[2];
1167 __I uint32_t SYSTEM_STAT;
1168} SYSCTL_Boot_Type;
1169 /* end of group SYSCTL */
1171
1172
1173/******************************************************************************
1174* Timer32 Registers
1175******************************************************************************/
1179typedef struct {
1180 __IO uint32_t LOAD;
1181 __I uint32_t VALUE;
1182 __IO uint32_t CONTROL;
1183 __O uint32_t INTCLR;
1184 __I uint32_t RIS;
1185 __I uint32_t MIS;
1186 __IO uint32_t BGLOAD;
1187} Timer32_Type;
1188 /* end of group Timer32 */
1190
1191
1192/******************************************************************************
1193* Timer_A Registers
1194******************************************************************************/
1198typedef struct {
1199 __IO uint16_t CTL;
1200 __IO uint16_t CCTL[5];
1201 uint16_t RESERVED0[2];
1202 __IO uint16_t R;
1203 __IO uint16_t CCR[5];
1204 uint16_t RESERVED1[2];
1205 __IO uint16_t EX0;
1206 uint16_t RESERVED2[6];
1207 __I uint16_t IV;
1208} Timer_A_Type;
1209 /* end of group Timer_A */
1211
1212
1213/******************************************************************************
1214* TLV Registers
1215******************************************************************************/
1219typedef struct {
1220 __I uint32_t TLV_CHECKSUM;
1221 __I uint32_t DEVICE_INFO_TAG;
1222 __I uint32_t DEVICE_INFO_LEN;
1223 __I uint32_t DEVICE_ID;
1224 __I uint32_t HWREV;
1225 __I uint32_t BCREV;
1226 __I uint32_t ROM_DRVLIB_REV;
1227 __I uint32_t DIE_REC_TAG;
1228 __I uint32_t DIE_REC_LEN;
1229 __I uint32_t DIE_XPOS;
1230 __I uint32_t DIE_YPOS;
1231 __I uint32_t WAFER_ID;
1232 __I uint32_t LOT_ID;
1233 __I uint32_t RESERVED0;
1234 __I uint32_t RESERVED1;
1235 __I uint32_t RESERVED2;
1236 __I uint32_t TEST_RESULTS;
1237 __I uint32_t CS_CAL_TAG;
1238 __I uint32_t CS_CAL_LEN;
1239 __I uint32_t DCOIR_FCAL_RSEL04;
1240 __I uint32_t DCOIR_FCAL_RSEL5;
1241 __I uint32_t RESERVED3;
1242 __I uint32_t RESERVED4;
1243 __I uint32_t RESERVED5;
1244 __I uint32_t RESERVED6;
1245 __I uint32_t DCOIR_CONSTK_RSEL04;
1246 __I uint32_t DCOIR_CONSTK_RSEL5;
1247 __I uint32_t DCOER_FCAL_RSEL04;
1248 __I uint32_t DCOER_FCAL_RSEL5;
1249 __I uint32_t RESERVED7;
1250 __I uint32_t RESERVED8;
1251 __I uint32_t RESERVED9;
1252 __I uint32_t RESERVED10;
1253 __I uint32_t DCOER_CONSTK_RSEL04;
1254 __I uint32_t DCOER_CONSTK_RSEL5;
1255 __I uint32_t ADC14_CAL_TAG;
1256 __I uint32_t ADC14_CAL_LEN;
1257 __I uint32_t ADC_GAIN_FACTOR;
1258 __I uint32_t ADC_OFFSET;
1259 __I uint32_t RESERVED11;
1260 __I uint32_t RESERVED12;
1261 __I uint32_t RESERVED13;
1262 __I uint32_t RESERVED14;
1263 __I uint32_t RESERVED15;
1264 __I uint32_t RESERVED16;
1265 __I uint32_t RESERVED17;
1266 __I uint32_t RESERVED18;
1267 __I uint32_t RESERVED19;
1268 __I uint32_t RESERVED20;
1269 __I uint32_t RESERVED21;
1270 __I uint32_t RESERVED22;
1271 __I uint32_t RESERVED23;
1272 __I uint32_t RESERVED24;
1273 __I uint32_t RESERVED25;
1274 __I uint32_t RESERVED26;
1275 __I uint32_t ADC14_REF1P2V_TS30C;
1276 __I uint32_t ADC14_REF1P2V_TS85C;
1277 __I uint32_t ADC14_REF1P45V_TS30C;
1278 __I uint32_t ADC14_REF1P45V_TS85C;
1279 __I uint32_t ADC14_REF2P5V_TS30C;
1280 __I uint32_t ADC14_REF2P5V_TS85C;
1281 __I uint32_t REF_CAL_TAG;
1282 __I uint32_t REF_CAL_LEN;
1283 __I uint32_t REF_1P2V;
1284 __I uint32_t REF_1P45V;
1285 __I uint32_t REF_2P5V;
1286 __I uint32_t FLASH_INFO_TAG;
1287 __I uint32_t FLASH_INFO_LEN;
1288 __I uint32_t FLASH_MAX_PROG_PULSES;
1289 __I uint32_t FLASH_MAX_ERASE_PULSES;
1290 __I uint32_t RANDOM_NUM_TAG;
1291 __I uint32_t RANDOM_NUM_LEN;
1292 __I uint32_t RANDOM_NUM_1;
1293 __I uint32_t RANDOM_NUM_2;
1294 __I uint32_t RANDOM_NUM_3;
1295 __I uint32_t RANDOM_NUM_4;
1296 __I uint32_t BSL_CFG_TAG;
1297 __I uint32_t BSL_CFG_LEN;
1298 __I uint32_t BSL_PERIPHIF_SEL;
1299 __I uint32_t BSL_PORTIF_CFG_UART;
1300 __I uint32_t BSL_PORTIF_CFG_SPI;
1301 __I uint32_t BSL_PORTIF_CFG_I2C;
1302 __I uint32_t TLV_END;
1303} TLV_Type;
1304 /* end of group TLV */
1306
1307
1308/******************************************************************************
1309* WDT_A Registers
1310******************************************************************************/
1314typedef struct {
1315 uint16_t RESERVED0[6];
1316 __IO uint16_t CTL;
1317} WDT_A_Type;
1318 /* end of group WDT_A */
1320
1321
1322/* -------------------- End of section using anonymous unions ------------------- */
1323#if defined(__CC_ARM)
1324 #pragma pop
1325#elif defined(__ICCARM__)
1326 /* leave anonymous unions enabled */
1327#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
1328 #pragma clang diagnostic pop
1329#elif defined(__GNUC__)
1330 /* anonymous unions are enabled by default */
1331#elif defined(__TI_ARM__)
1332 /* anonymous unions are enabled by default */
1333#else
1334 #warning Not supported compiler type
1335#endif
1336 /* end of group MSP432P401R_Peripherals */
1338
1339/******************************************************************************
1340* Peripheral declaration *
1341******************************************************************************/
1346#define ADC14 ((ADC14_Type *) ADC14_BASE)
1347#define AES256 ((AES256_Type *) AES256_BASE)
1348#define CAPTIO0 ((CAPTIO_Type *) CAPTIO0_BASE)
1349#define CAPTIO1 ((CAPTIO_Type *) CAPTIO1_BASE)
1350#define COMP_E0 ((COMP_E_Type *) COMP_E0_BASE)
1351#define COMP_E1 ((COMP_E_Type *) COMP_E1_BASE)
1352#define CRC32 ((CRC32_Type *) CRC32_BASE)
1353#define CS ((CS_Type *) CS_BASE)
1354#define PA ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0000))
1355#define PB ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0020))
1356#define PC ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0040))
1357#define PD ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0060))
1358#define PE ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0080))
1359#define PJ ((DIO_PORT_Not_Interruptable_Type*) (DIO_BASE + 0x0120))
1360#define P1 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0000))
1361#define P2 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0000))
1362#define P3 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0020))
1363#define P4 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0020))
1364#define P5 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0040))
1365#define P6 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0040))
1366#define P7 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0060))
1367#define P8 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0060))
1368#define P9 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0080))
1369#define P10 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0080))
1370#define DMA_Channel ((DMA_Channel_Type *) DMA_BASE)
1371#define DMA_Control ((DMA_Control_Type *) (DMA_BASE + 0x1000))
1372#define EUSCI_A0 ((EUSCI_A_Type *) EUSCI_A0_BASE)
1373#define EUSCI_A0_SPI ((EUSCI_A_SPI_Type *) EUSCI_A0_SPI_BASE)
1374#define EUSCI_A1 ((EUSCI_A_Type *) EUSCI_A1_BASE)
1375#define EUSCI_A1_SPI ((EUSCI_A_SPI_Type *) EUSCI_A1_SPI_BASE)
1376#define EUSCI_A2 ((EUSCI_A_Type *) EUSCI_A2_BASE)
1377#define EUSCI_A2_SPI ((EUSCI_A_SPI_Type *) EUSCI_A2_SPI_BASE)
1378#define EUSCI_A3 ((EUSCI_A_Type *) EUSCI_A3_BASE)
1379#define EUSCI_A3_SPI ((EUSCI_A_SPI_Type *) EUSCI_A3_SPI_BASE)
1380#define EUSCI_B0 ((EUSCI_B_Type *) EUSCI_B0_BASE)
1381#define EUSCI_B0_SPI ((EUSCI_B_SPI_Type *) EUSCI_B0_SPI_BASE)
1382#define EUSCI_B1 ((EUSCI_B_Type *) EUSCI_B1_BASE)
1383#define EUSCI_B1_SPI ((EUSCI_B_SPI_Type *) EUSCI_B1_SPI_BASE)
1384#define EUSCI_B2 ((EUSCI_B_Type *) EUSCI_B2_BASE)
1385#define EUSCI_B2_SPI ((EUSCI_B_SPI_Type *) EUSCI_B2_SPI_BASE)
1386#define EUSCI_B3 ((EUSCI_B_Type *) EUSCI_B3_BASE)
1387#define EUSCI_B3_SPI ((EUSCI_B_SPI_Type *) EUSCI_B3_SPI_BASE)
1388#define FLCTL ((FLCTL_Type *) FLCTL_BASE)
1389#define FL_BOOTOVER_MAILBOX ((FL_BOOTOVER_MAILBOX_Type *) FL_BOOTOVER_MAILBOX_BASE)
1390#define PCM ((PCM_Type *) PCM_BASE)
1391#define PMAP ((PMAP_COMMON_Type*) PMAP_BASE)
1392#define P1MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0008))
1393#define P2MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0010))
1394#define P3MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0018))
1395#define P4MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0020))
1396#define P5MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0028))
1397#define P6MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0030))
1398#define P7MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0038))
1399#define PSS ((PSS_Type *) PSS_BASE)
1400#define REF_A ((REF_A_Type *) REF_A_BASE)
1401#define RSTCTL ((RSTCTL_Type *) RSTCTL_BASE)
1402#define RTC_C ((RTC_C_Type *) RTC_C_BASE)
1403#define RTC_C_BCD ((RTC_C_BCD_Type *) RTC_C_BCD_BASE)
1404#define SYSCTL ((SYSCTL_Type *) SYSCTL_BASE)
1405#define SYSCTL_Boot ((SYSCTL_Boot_Type *) (SYSCTL_BASE + 0x1000))
1406#define TIMER32_1 ((Timer32_Type *) TIMER32_BASE)
1407#define TIMER32_2 ((Timer32_Type *) (TIMER32_BASE + 0x00020))
1408#define TIMER_A0 ((Timer_A_Type *) TIMER_A0_BASE)
1409#define TIMER_A1 ((Timer_A_Type *) TIMER_A1_BASE)
1410#define TIMER_A2 ((Timer_A_Type *) TIMER_A2_BASE)
1411#define TIMER_A3 ((Timer_A_Type *) TIMER_A3_BASE)
1412#define TLV ((TLV_Type *) TLV_BASE)
1413#define WDT_A ((WDT_A_Type *) WDT_A_BASE)
1414
1415 /* end of group MSP432P401R_PeripheralDecl */
1417 /* end of group MSP432P401R_Definitions */
1419
1420#endif /* __CMSIS_CONFIG__ */
1421
1422/******************************************************************************
1423* Peripheral register control bits *
1424******************************************************************************/
1425
1426/******************************************************************************
1427* ADC14 Bits
1428******************************************************************************/
1429/* ADC14_CTL0[SC] Bits */
1430#define ADC14_CTL0_SC_OFS ( 0)
1431#define ADC14_CTL0_SC ((uint32_t)0x00000001)
1432/* ADC14_CTL0[ENC] Bits */
1433#define ADC14_CTL0_ENC_OFS ( 1)
1434#define ADC14_CTL0_ENC ((uint32_t)0x00000002)
1435/* ADC14_CTL0[ON] Bits */
1436#define ADC14_CTL0_ON_OFS ( 4)
1437#define ADC14_CTL0_ON ((uint32_t)0x00000010)
1438/* ADC14_CTL0[MSC] Bits */
1439#define ADC14_CTL0_MSC_OFS ( 7)
1440#define ADC14_CTL0_MSC ((uint32_t)0x00000080)
1441/* ADC14_CTL0[SHT0] Bits */
1442#define ADC14_CTL0_SHT0_OFS ( 8)
1443#define ADC14_CTL0_SHT0_MASK ((uint32_t)0x00000F00)
1444#define ADC14_CTL0_SHT00 ((uint32_t)0x00000100)
1445#define ADC14_CTL0_SHT01 ((uint32_t)0x00000200)
1446#define ADC14_CTL0_SHT02 ((uint32_t)0x00000400)
1447#define ADC14_CTL0_SHT03 ((uint32_t)0x00000800)
1448#define ADC14_CTL0_SHT0_0 ((uint32_t)0x00000000)
1449#define ADC14_CTL0_SHT0_1 ((uint32_t)0x00000100)
1450#define ADC14_CTL0_SHT0_2 ((uint32_t)0x00000200)
1451#define ADC14_CTL0_SHT0_3 ((uint32_t)0x00000300)
1452#define ADC14_CTL0_SHT0_4 ((uint32_t)0x00000400)
1453#define ADC14_CTL0_SHT0_5 ((uint32_t)0x00000500)
1454#define ADC14_CTL0_SHT0_6 ((uint32_t)0x00000600)
1455#define ADC14_CTL0_SHT0_7 ((uint32_t)0x00000700)
1456#define ADC14_CTL0_SHT0__4 ((uint32_t)0x00000000)
1457#define ADC14_CTL0_SHT0__8 ((uint32_t)0x00000100)
1458#define ADC14_CTL0_SHT0__16 ((uint32_t)0x00000200)
1459#define ADC14_CTL0_SHT0__32 ((uint32_t)0x00000300)
1460#define ADC14_CTL0_SHT0__64 ((uint32_t)0x00000400)
1461#define ADC14_CTL0_SHT0__96 ((uint32_t)0x00000500)
1462#define ADC14_CTL0_SHT0__128 ((uint32_t)0x00000600)
1463#define ADC14_CTL0_SHT0__192 ((uint32_t)0x00000700)
1464/* ADC14_CTL0[SHT1] Bits */
1465#define ADC14_CTL0_SHT1_OFS (12)
1466#define ADC14_CTL0_SHT1_MASK ((uint32_t)0x0000F000)
1467#define ADC14_CTL0_SHT10 ((uint32_t)0x00001000)
1468#define ADC14_CTL0_SHT11 ((uint32_t)0x00002000)
1469#define ADC14_CTL0_SHT12 ((uint32_t)0x00004000)
1470#define ADC14_CTL0_SHT13 ((uint32_t)0x00008000)
1471#define ADC14_CTL0_SHT1_0 ((uint32_t)0x00000000)
1472#define ADC14_CTL0_SHT1_1 ((uint32_t)0x00001000)
1473#define ADC14_CTL0_SHT1_2 ((uint32_t)0x00002000)
1474#define ADC14_CTL0_SHT1_3 ((uint32_t)0x00003000)
1475#define ADC14_CTL0_SHT1_4 ((uint32_t)0x00004000)
1476#define ADC14_CTL0_SHT1_5 ((uint32_t)0x00005000)
1477#define ADC14_CTL0_SHT1_6 ((uint32_t)0x00006000)
1478#define ADC14_CTL0_SHT1_7 ((uint32_t)0x00007000)
1479#define ADC14_CTL0_SHT1__4 ((uint32_t)0x00000000)
1480#define ADC14_CTL0_SHT1__8 ((uint32_t)0x00001000)
1481#define ADC14_CTL0_SHT1__16 ((uint32_t)0x00002000)
1482#define ADC14_CTL0_SHT1__32 ((uint32_t)0x00003000)
1483#define ADC14_CTL0_SHT1__64 ((uint32_t)0x00004000)
1484#define ADC14_CTL0_SHT1__96 ((uint32_t)0x00005000)
1485#define ADC14_CTL0_SHT1__128 ((uint32_t)0x00006000)
1486#define ADC14_CTL0_SHT1__192 ((uint32_t)0x00007000)
1487/* ADC14_CTL0[BUSY] Bits */
1488#define ADC14_CTL0_BUSY_OFS (16)
1489#define ADC14_CTL0_BUSY ((uint32_t)0x00010000)
1490/* ADC14_CTL0[CONSEQ] Bits */
1491#define ADC14_CTL0_CONSEQ_OFS (17)
1492#define ADC14_CTL0_CONSEQ_MASK ((uint32_t)0x00060000)
1493#define ADC14_CTL0_CONSEQ0 ((uint32_t)0x00020000)
1494#define ADC14_CTL0_CONSEQ1 ((uint32_t)0x00040000)
1495#define ADC14_CTL0_CONSEQ_0 ((uint32_t)0x00000000)
1496#define ADC14_CTL0_CONSEQ_1 ((uint32_t)0x00020000)
1497#define ADC14_CTL0_CONSEQ_2 ((uint32_t)0x00040000)
1498#define ADC14_CTL0_CONSEQ_3 ((uint32_t)0x00060000)
1499/* ADC14_CTL0[SSEL] Bits */
1500#define ADC14_CTL0_SSEL_OFS (19)
1501#define ADC14_CTL0_SSEL_MASK ((uint32_t)0x00380000)
1502#define ADC14_CTL0_SSEL0 ((uint32_t)0x00080000)
1503#define ADC14_CTL0_SSEL1 ((uint32_t)0x00100000)
1504#define ADC14_CTL0_SSEL2 ((uint32_t)0x00200000)
1505#define ADC14_CTL0_SSEL_0 ((uint32_t)0x00000000)
1506#define ADC14_CTL0_SSEL_1 ((uint32_t)0x00080000)
1507#define ADC14_CTL0_SSEL_2 ((uint32_t)0x00100000)
1508#define ADC14_CTL0_SSEL_3 ((uint32_t)0x00180000)
1509#define ADC14_CTL0_SSEL_4 ((uint32_t)0x00200000)
1510#define ADC14_CTL0_SSEL_5 ((uint32_t)0x00280000)
1511#define ADC14_CTL0_SSEL__MODCLK ((uint32_t)0x00000000)
1512#define ADC14_CTL0_SSEL__SYSCLK ((uint32_t)0x00080000)
1513#define ADC14_CTL0_SSEL__ACLK ((uint32_t)0x00100000)
1514#define ADC14_CTL0_SSEL__MCLK ((uint32_t)0x00180000)
1515#define ADC14_CTL0_SSEL__SMCLK ((uint32_t)0x00200000)
1516#define ADC14_CTL0_SSEL__HSMCLK ((uint32_t)0x00280000)
1517/* ADC14_CTL0[DIV] Bits */
1518#define ADC14_CTL0_DIV_OFS (22)
1519#define ADC14_CTL0_DIV_MASK ((uint32_t)0x01C00000)
1520#define ADC14_CTL0_DIV0 ((uint32_t)0x00400000)
1521#define ADC14_CTL0_DIV1 ((uint32_t)0x00800000)
1522#define ADC14_CTL0_DIV2 ((uint32_t)0x01000000)
1523#define ADC14_CTL0_DIV_0 ((uint32_t)0x00000000)
1524#define ADC14_CTL0_DIV_1 ((uint32_t)0x00400000)
1525#define ADC14_CTL0_DIV_2 ((uint32_t)0x00800000)
1526#define ADC14_CTL0_DIV_3 ((uint32_t)0x00C00000)
1527#define ADC14_CTL0_DIV_4 ((uint32_t)0x01000000)
1528#define ADC14_CTL0_DIV_5 ((uint32_t)0x01400000)
1529#define ADC14_CTL0_DIV_6 ((uint32_t)0x01800000)
1530#define ADC14_CTL0_DIV_7 ((uint32_t)0x01C00000)
1531#define ADC14_CTL0_DIV__1 ((uint32_t)0x00000000)
1532#define ADC14_CTL0_DIV__2 ((uint32_t)0x00400000)
1533#define ADC14_CTL0_DIV__3 ((uint32_t)0x00800000)
1534#define ADC14_CTL0_DIV__4 ((uint32_t)0x00C00000)
1535#define ADC14_CTL0_DIV__5 ((uint32_t)0x01000000)
1536#define ADC14_CTL0_DIV__6 ((uint32_t)0x01400000)
1537#define ADC14_CTL0_DIV__7 ((uint32_t)0x01800000)
1538#define ADC14_CTL0_DIV__8 ((uint32_t)0x01C00000)
1539/* ADC14_CTL0[ISSH] Bits */
1540#define ADC14_CTL0_ISSH_OFS (25)
1541#define ADC14_CTL0_ISSH ((uint32_t)0x02000000)
1542/* ADC14_CTL0[SHP] Bits */
1543#define ADC14_CTL0_SHP_OFS (26)
1544#define ADC14_CTL0_SHP ((uint32_t)0x04000000)
1545/* ADC14_CTL0[SHS] Bits */
1546#define ADC14_CTL0_SHS_OFS (27)
1547#define ADC14_CTL0_SHS_MASK ((uint32_t)0x38000000)
1548#define ADC14_CTL0_SHS0 ((uint32_t)0x08000000)
1549#define ADC14_CTL0_SHS1 ((uint32_t)0x10000000)
1550#define ADC14_CTL0_SHS2 ((uint32_t)0x20000000)
1551#define ADC14_CTL0_SHS_0 ((uint32_t)0x00000000)
1552#define ADC14_CTL0_SHS_1 ((uint32_t)0x08000000)
1553#define ADC14_CTL0_SHS_2 ((uint32_t)0x10000000)
1554#define ADC14_CTL0_SHS_3 ((uint32_t)0x18000000)
1555#define ADC14_CTL0_SHS_4 ((uint32_t)0x20000000)
1556#define ADC14_CTL0_SHS_5 ((uint32_t)0x28000000)
1557#define ADC14_CTL0_SHS_6 ((uint32_t)0x30000000)
1558#define ADC14_CTL0_SHS_7 ((uint32_t)0x38000000)
1559/* ADC14_CTL0[PDIV] Bits */
1560#define ADC14_CTL0_PDIV_OFS (30)
1561#define ADC14_CTL0_PDIV_MASK ((uint32_t)0xC0000000)
1562#define ADC14_CTL0_PDIV0 ((uint32_t)0x40000000)
1563#define ADC14_CTL0_PDIV1 ((uint32_t)0x80000000)
1564#define ADC14_CTL0_PDIV_0 ((uint32_t)0x00000000)
1565#define ADC14_CTL0_PDIV_1 ((uint32_t)0x40000000)
1566#define ADC14_CTL0_PDIV_2 ((uint32_t)0x80000000)
1567#define ADC14_CTL0_PDIV_3 ((uint32_t)0xC0000000)
1568#define ADC14_CTL0_PDIV__1 ((uint32_t)0x00000000)
1569#define ADC14_CTL0_PDIV__4 ((uint32_t)0x40000000)
1570#define ADC14_CTL0_PDIV__32 ((uint32_t)0x80000000)
1571#define ADC14_CTL0_PDIV__64 ((uint32_t)0xC0000000)
1572/* ADC14_CTL1[PWRMD] Bits */
1573#define ADC14_CTL1_PWRMD_OFS ( 0)
1574#define ADC14_CTL1_PWRMD_MASK ((uint32_t)0x00000003)
1575#define ADC14_CTL1_PWRMD0 ((uint32_t)0x00000001)
1576#define ADC14_CTL1_PWRMD1 ((uint32_t)0x00000002)
1577#define ADC14_CTL1_PWRMD_0 ((uint32_t)0x00000000)
1578 /* up to 1 Msps. */
1579#define ADC14_CTL1_PWRMD_2 ((uint32_t)0x00000002)
1580 /* rate must not exceed 200 ksps. */
1581/* ADC14_CTL1[REFBURST] Bits */
1582#define ADC14_CTL1_REFBURST_OFS ( 2)
1583#define ADC14_CTL1_REFBURST ((uint32_t)0x00000004)
1584/* ADC14_CTL1[DF] Bits */
1585#define ADC14_CTL1_DF_OFS ( 3)
1586#define ADC14_CTL1_DF ((uint32_t)0x00000008)
1587/* ADC14_CTL1[RES] Bits */
1588#define ADC14_CTL1_RES_OFS ( 4)
1589#define ADC14_CTL1_RES_MASK ((uint32_t)0x00000030)
1590#define ADC14_CTL1_RES0 ((uint32_t)0x00000010)
1591#define ADC14_CTL1_RES1 ((uint32_t)0x00000020)
1592#define ADC14_CTL1_RES_0 ((uint32_t)0x00000000)
1593#define ADC14_CTL1_RES_1 ((uint32_t)0x00000010)
1594#define ADC14_CTL1_RES_2 ((uint32_t)0x00000020)
1595#define ADC14_CTL1_RES_3 ((uint32_t)0x00000030)
1596#define ADC14_CTL1_RES__8BIT ((uint32_t)0x00000000)
1597#define ADC14_CTL1_RES__10BIT ((uint32_t)0x00000010)
1598#define ADC14_CTL1_RES__12BIT ((uint32_t)0x00000020)
1599#define ADC14_CTL1_RES__14BIT ((uint32_t)0x00000030)
1600/* ADC14_CTL1[CSTARTADD] Bits */
1601#define ADC14_CTL1_CSTARTADD_OFS (16)
1602#define ADC14_CTL1_CSTARTADD_MASK ((uint32_t)0x001F0000)
1603/* ADC14_CTL1[BATMAP] Bits */
1604#define ADC14_CTL1_BATMAP_OFS (22)
1605#define ADC14_CTL1_BATMAP ((uint32_t)0x00400000)
1606/* ADC14_CTL1[TCMAP] Bits */
1607#define ADC14_CTL1_TCMAP_OFS (23)
1608#define ADC14_CTL1_TCMAP ((uint32_t)0x00800000)
1609/* ADC14_CTL1[CH0MAP] Bits */
1610#define ADC14_CTL1_CH0MAP_OFS (24)
1611#define ADC14_CTL1_CH0MAP ((uint32_t)0x01000000)
1612/* ADC14_CTL1[CH1MAP] Bits */
1613#define ADC14_CTL1_CH1MAP_OFS (25)
1614#define ADC14_CTL1_CH1MAP ((uint32_t)0x02000000)
1615/* ADC14_CTL1[CH2MAP] Bits */
1616#define ADC14_CTL1_CH2MAP_OFS (26)
1617#define ADC14_CTL1_CH2MAP ((uint32_t)0x04000000)
1618/* ADC14_CTL1[CH3MAP] Bits */
1619#define ADC14_CTL1_CH3MAP_OFS (27)
1620#define ADC14_CTL1_CH3MAP ((uint32_t)0x08000000)
1621/* ADC14_LO0[LO0] Bits */
1622#define ADC14_LO0_LO0_OFS ( 0)
1623#define ADC14_LO0_LO0_MASK ((uint32_t)0x0000FFFF)
1624/* ADC14_HI0[HI0] Bits */
1625#define ADC14_HI0_HI0_OFS ( 0)
1626#define ADC14_HI0_HI0_MASK ((uint32_t)0x0000FFFF)
1627/* ADC14_LO1[LO1] Bits */
1628#define ADC14_LO1_LO1_OFS ( 0)
1629#define ADC14_LO1_LO1_MASK ((uint32_t)0x0000FFFF)
1630/* ADC14_HI1[HI1] Bits */
1631#define ADC14_HI1_HI1_OFS ( 0)
1632#define ADC14_HI1_HI1_MASK ((uint32_t)0x0000FFFF)
1633/* ADC14_MCTLN[INCH] Bits */
1634#define ADC14_MCTLN_INCH_OFS ( 0)
1635#define ADC14_MCTLN_INCH_MASK ((uint32_t)0x0000001F)
1636#define ADC14_MCTLN_INCH0 ((uint32_t)0x00000001)
1637#define ADC14_MCTLN_INCH1 ((uint32_t)0x00000002)
1638#define ADC14_MCTLN_INCH2 ((uint32_t)0x00000004)
1639#define ADC14_MCTLN_INCH3 ((uint32_t)0x00000008)
1640#define ADC14_MCTLN_INCH4 ((uint32_t)0x00000010)
1641#define ADC14_MCTLN_INCH_0 ((uint32_t)0x00000000)
1642#define ADC14_MCTLN_INCH_1 ((uint32_t)0x00000001)
1643#define ADC14_MCTLN_INCH_2 ((uint32_t)0x00000002)
1644#define ADC14_MCTLN_INCH_3 ((uint32_t)0x00000003)
1645#define ADC14_MCTLN_INCH_4 ((uint32_t)0x00000004)
1646#define ADC14_MCTLN_INCH_5 ((uint32_t)0x00000005)
1647#define ADC14_MCTLN_INCH_6 ((uint32_t)0x00000006)
1648#define ADC14_MCTLN_INCH_7 ((uint32_t)0x00000007)
1649#define ADC14_MCTLN_INCH_8 ((uint32_t)0x00000008)
1650#define ADC14_MCTLN_INCH_9 ((uint32_t)0x00000009)
1651#define ADC14_MCTLN_INCH_10 ((uint32_t)0x0000000A)
1652#define ADC14_MCTLN_INCH_11 ((uint32_t)0x0000000B)
1653#define ADC14_MCTLN_INCH_12 ((uint32_t)0x0000000C)
1654#define ADC14_MCTLN_INCH_13 ((uint32_t)0x0000000D)
1655#define ADC14_MCTLN_INCH_14 ((uint32_t)0x0000000E)
1656#define ADC14_MCTLN_INCH_15 ((uint32_t)0x0000000F)
1657#define ADC14_MCTLN_INCH_16 ((uint32_t)0x00000010)
1658#define ADC14_MCTLN_INCH_17 ((uint32_t)0x00000011)
1659#define ADC14_MCTLN_INCH_18 ((uint32_t)0x00000012)
1660#define ADC14_MCTLN_INCH_19 ((uint32_t)0x00000013)
1661#define ADC14_MCTLN_INCH_20 ((uint32_t)0x00000014)
1662#define ADC14_MCTLN_INCH_21 ((uint32_t)0x00000015)
1663#define ADC14_MCTLN_INCH_22 ((uint32_t)0x00000016)
1664#define ADC14_MCTLN_INCH_23 ((uint32_t)0x00000017)
1665#define ADC14_MCTLN_INCH_24 ((uint32_t)0x00000018)
1666#define ADC14_MCTLN_INCH_25 ((uint32_t)0x00000019)
1667#define ADC14_MCTLN_INCH_26 ((uint32_t)0x0000001A)
1668#define ADC14_MCTLN_INCH_27 ((uint32_t)0x0000001B)
1669#define ADC14_MCTLN_INCH_28 ((uint32_t)0x0000001C)
1670#define ADC14_MCTLN_INCH_29 ((uint32_t)0x0000001D)
1671#define ADC14_MCTLN_INCH_30 ((uint32_t)0x0000001E)
1672#define ADC14_MCTLN_INCH_31 ((uint32_t)0x0000001F)
1673/* ADC14_MCTLN[EOS] Bits */
1674#define ADC14_MCTLN_EOS_OFS ( 7)
1675#define ADC14_MCTLN_EOS ((uint32_t)0x00000080)
1676/* ADC14_MCTLN[VRSEL] Bits */
1677#define ADC14_MCTLN_VRSEL_OFS ( 8)
1678#define ADC14_MCTLN_VRSEL_MASK ((uint32_t)0x00000F00)
1679#define ADC14_MCTLN_VRSEL0 ((uint32_t)0x00000100)
1680#define ADC14_MCTLN_VRSEL1 ((uint32_t)0x00000200)
1681#define ADC14_MCTLN_VRSEL2 ((uint32_t)0x00000400)
1682#define ADC14_MCTLN_VRSEL3 ((uint32_t)0x00000800)
1683#define ADC14_MCTLN_VRSEL_0 ((uint32_t)0x00000000)
1684#define ADC14_MCTLN_VRSEL_1 ((uint32_t)0x00000100)
1685#define ADC14_MCTLN_VRSEL_14 ((uint32_t)0x00000E00)
1686#define ADC14_MCTLN_VRSEL_15 ((uint32_t)0x00000F00)
1687/* ADC14_MCTLN[DIF] Bits */
1688#define ADC14_MCTLN_DIF_OFS (13)
1689#define ADC14_MCTLN_DIF ((uint32_t)0x00002000)
1690/* ADC14_MCTLN[WINC] Bits */
1691#define ADC14_MCTLN_WINC_OFS (14)
1692#define ADC14_MCTLN_WINC ((uint32_t)0x00004000)
1693/* ADC14_MCTLN[WINCTH] Bits */
1694#define ADC14_MCTLN_WINCTH_OFS (15)
1695#define ADC14_MCTLN_WINCTH ((uint32_t)0x00008000)
1696/* ADC14_MEMN[CONVRES] Bits */
1697#define ADC14_MEMN_CONVRES_OFS ( 0)
1698#define ADC14_MEMN_CONVRES_MASK ((uint32_t)0x0000FFFF)
1699/* ADC14_IER0[IE0] Bits */
1700#define ADC14_IER0_IE0_OFS ( 0)
1701#define ADC14_IER0_IE0 ((uint32_t)0x00000001)
1702/* ADC14_IER0[IE1] Bits */
1703#define ADC14_IER0_IE1_OFS ( 1)
1704#define ADC14_IER0_IE1 ((uint32_t)0x00000002)
1705/* ADC14_IER0[IE2] Bits */
1706#define ADC14_IER0_IE2_OFS ( 2)
1707#define ADC14_IER0_IE2 ((uint32_t)0x00000004)
1708/* ADC14_IER0[IE3] Bits */
1709#define ADC14_IER0_IE3_OFS ( 3)
1710#define ADC14_IER0_IE3 ((uint32_t)0x00000008)
1711/* ADC14_IER0[IE4] Bits */
1712#define ADC14_IER0_IE4_OFS ( 4)
1713#define ADC14_IER0_IE4 ((uint32_t)0x00000010)
1714/* ADC14_IER0[IE5] Bits */
1715#define ADC14_IER0_IE5_OFS ( 5)
1716#define ADC14_IER0_IE5 ((uint32_t)0x00000020)
1717/* ADC14_IER0[IE6] Bits */
1718#define ADC14_IER0_IE6_OFS ( 6)
1719#define ADC14_IER0_IE6 ((uint32_t)0x00000040)
1720/* ADC14_IER0[IE7] Bits */
1721#define ADC14_IER0_IE7_OFS ( 7)
1722#define ADC14_IER0_IE7 ((uint32_t)0x00000080)
1723/* ADC14_IER0[IE8] Bits */
1724#define ADC14_IER0_IE8_OFS ( 8)
1725#define ADC14_IER0_IE8 ((uint32_t)0x00000100)
1726/* ADC14_IER0[IE9] Bits */
1727#define ADC14_IER0_IE9_OFS ( 9)
1728#define ADC14_IER0_IE9 ((uint32_t)0x00000200)
1729/* ADC14_IER0[IE10] Bits */
1730#define ADC14_IER0_IE10_OFS (10)
1731#define ADC14_IER0_IE10 ((uint32_t)0x00000400)
1732/* ADC14_IER0[IE11] Bits */
1733#define ADC14_IER0_IE11_OFS (11)
1734#define ADC14_IER0_IE11 ((uint32_t)0x00000800)
1735/* ADC14_IER0[IE12] Bits */
1736#define ADC14_IER0_IE12_OFS (12)
1737#define ADC14_IER0_IE12 ((uint32_t)0x00001000)
1738/* ADC14_IER0[IE13] Bits */
1739#define ADC14_IER0_IE13_OFS (13)
1740#define ADC14_IER0_IE13 ((uint32_t)0x00002000)
1741/* ADC14_IER0[IE14] Bits */
1742#define ADC14_IER0_IE14_OFS (14)
1743#define ADC14_IER0_IE14 ((uint32_t)0x00004000)
1744/* ADC14_IER0[IE15] Bits */
1745#define ADC14_IER0_IE15_OFS (15)
1746#define ADC14_IER0_IE15 ((uint32_t)0x00008000)
1747/* ADC14_IER0[IE16] Bits */
1748#define ADC14_IER0_IE16_OFS (16)
1749#define ADC14_IER0_IE16 ((uint32_t)0x00010000)
1750/* ADC14_IER0[IE17] Bits */
1751#define ADC14_IER0_IE17_OFS (17)
1752#define ADC14_IER0_IE17 ((uint32_t)0x00020000)
1753/* ADC14_IER0[IE19] Bits */
1754#define ADC14_IER0_IE19_OFS (19)
1755#define ADC14_IER0_IE19 ((uint32_t)0x00080000)
1756/* ADC14_IER0[IE18] Bits */
1757#define ADC14_IER0_IE18_OFS (18)
1758#define ADC14_IER0_IE18 ((uint32_t)0x00040000)
1759/* ADC14_IER0[IE20] Bits */
1760#define ADC14_IER0_IE20_OFS (20)
1761#define ADC14_IER0_IE20 ((uint32_t)0x00100000)
1762/* ADC14_IER0[IE21] Bits */
1763#define ADC14_IER0_IE21_OFS (21)
1764#define ADC14_IER0_IE21 ((uint32_t)0x00200000)
1765/* ADC14_IER0[IE22] Bits */
1766#define ADC14_IER0_IE22_OFS (22)
1767#define ADC14_IER0_IE22 ((uint32_t)0x00400000)
1768/* ADC14_IER0[IE23] Bits */
1769#define ADC14_IER0_IE23_OFS (23)
1770#define ADC14_IER0_IE23 ((uint32_t)0x00800000)
1771/* ADC14_IER0[IE24] Bits */
1772#define ADC14_IER0_IE24_OFS (24)
1773#define ADC14_IER0_IE24 ((uint32_t)0x01000000)
1774/* ADC14_IER0[IE25] Bits */
1775#define ADC14_IER0_IE25_OFS (25)
1776#define ADC14_IER0_IE25 ((uint32_t)0x02000000)
1777/* ADC14_IER0[IE26] Bits */
1778#define ADC14_IER0_IE26_OFS (26)
1779#define ADC14_IER0_IE26 ((uint32_t)0x04000000)
1780/* ADC14_IER0[IE27] Bits */
1781#define ADC14_IER0_IE27_OFS (27)
1782#define ADC14_IER0_IE27 ((uint32_t)0x08000000)
1783/* ADC14_IER0[IE28] Bits */
1784#define ADC14_IER0_IE28_OFS (28)
1785#define ADC14_IER0_IE28 ((uint32_t)0x10000000)
1786/* ADC14_IER0[IE29] Bits */
1787#define ADC14_IER0_IE29_OFS (29)
1788#define ADC14_IER0_IE29 ((uint32_t)0x20000000)
1789/* ADC14_IER0[IE30] Bits */
1790#define ADC14_IER0_IE30_OFS (30)
1791#define ADC14_IER0_IE30 ((uint32_t)0x40000000)
1792/* ADC14_IER0[IE31] Bits */
1793#define ADC14_IER0_IE31_OFS (31)
1794#define ADC14_IER0_IE31 ((uint32_t)0x80000000)
1795/* ADC14_IER1[INIE] Bits */
1796#define ADC14_IER1_INIE_OFS ( 1)
1797#define ADC14_IER1_INIE ((uint32_t)0x00000002)
1798/* ADC14_IER1[LOIE] Bits */
1799#define ADC14_IER1_LOIE_OFS ( 2)
1800#define ADC14_IER1_LOIE ((uint32_t)0x00000004)
1801/* ADC14_IER1[HIIE] Bits */
1802#define ADC14_IER1_HIIE_OFS ( 3)
1803#define ADC14_IER1_HIIE ((uint32_t)0x00000008)
1804/* ADC14_IER1[OVIE] Bits */
1805#define ADC14_IER1_OVIE_OFS ( 4)
1806#define ADC14_IER1_OVIE ((uint32_t)0x00000010)
1807/* ADC14_IER1[TOVIE] Bits */
1808#define ADC14_IER1_TOVIE_OFS ( 5)
1809#define ADC14_IER1_TOVIE ((uint32_t)0x00000020)
1810/* ADC14_IER1[RDYIE] Bits */
1811#define ADC14_IER1_RDYIE_OFS ( 6)
1812#define ADC14_IER1_RDYIE ((uint32_t)0x00000040)
1813/* ADC14_IFGR0[IFG0] Bits */
1814#define ADC14_IFGR0_IFG0_OFS ( 0)
1815#define ADC14_IFGR0_IFG0 ((uint32_t)0x00000001)
1816/* ADC14_IFGR0[IFG1] Bits */
1817#define ADC14_IFGR0_IFG1_OFS ( 1)
1818#define ADC14_IFGR0_IFG1 ((uint32_t)0x00000002)
1819/* ADC14_IFGR0[IFG2] Bits */
1820#define ADC14_IFGR0_IFG2_OFS ( 2)
1821#define ADC14_IFGR0_IFG2 ((uint32_t)0x00000004)
1822/* ADC14_IFGR0[IFG3] Bits */
1823#define ADC14_IFGR0_IFG3_OFS ( 3)
1824#define ADC14_IFGR0_IFG3 ((uint32_t)0x00000008)
1825/* ADC14_IFGR0[IFG4] Bits */
1826#define ADC14_IFGR0_IFG4_OFS ( 4)
1827#define ADC14_IFGR0_IFG4 ((uint32_t)0x00000010)
1828/* ADC14_IFGR0[IFG5] Bits */
1829#define ADC14_IFGR0_IFG5_OFS ( 5)
1830#define ADC14_IFGR0_IFG5 ((uint32_t)0x00000020)
1831/* ADC14_IFGR0[IFG6] Bits */
1832#define ADC14_IFGR0_IFG6_OFS ( 6)
1833#define ADC14_IFGR0_IFG6 ((uint32_t)0x00000040)
1834/* ADC14_IFGR0[IFG7] Bits */
1835#define ADC14_IFGR0_IFG7_OFS ( 7)
1836#define ADC14_IFGR0_IFG7 ((uint32_t)0x00000080)
1837/* ADC14_IFGR0[IFG8] Bits */
1838#define ADC14_IFGR0_IFG8_OFS ( 8)
1839#define ADC14_IFGR0_IFG8 ((uint32_t)0x00000100)
1840/* ADC14_IFGR0[IFG9] Bits */
1841#define ADC14_IFGR0_IFG9_OFS ( 9)
1842#define ADC14_IFGR0_IFG9 ((uint32_t)0x00000200)
1843/* ADC14_IFGR0[IFG10] Bits */
1844#define ADC14_IFGR0_IFG10_OFS (10)
1845#define ADC14_IFGR0_IFG10 ((uint32_t)0x00000400)
1846/* ADC14_IFGR0[IFG11] Bits */
1847#define ADC14_IFGR0_IFG11_OFS (11)
1848#define ADC14_IFGR0_IFG11 ((uint32_t)0x00000800)
1849/* ADC14_IFGR0[IFG12] Bits */
1850#define ADC14_IFGR0_IFG12_OFS (12)
1851#define ADC14_IFGR0_IFG12 ((uint32_t)0x00001000)
1852/* ADC14_IFGR0[IFG13] Bits */
1853#define ADC14_IFGR0_IFG13_OFS (13)
1854#define ADC14_IFGR0_IFG13 ((uint32_t)0x00002000)
1855/* ADC14_IFGR0[IFG14] Bits */
1856#define ADC14_IFGR0_IFG14_OFS (14)
1857#define ADC14_IFGR0_IFG14 ((uint32_t)0x00004000)
1858/* ADC14_IFGR0[IFG15] Bits */
1859#define ADC14_IFGR0_IFG15_OFS (15)
1860#define ADC14_IFGR0_IFG15 ((uint32_t)0x00008000)
1861/* ADC14_IFGR0[IFG16] Bits */
1862#define ADC14_IFGR0_IFG16_OFS (16)
1863#define ADC14_IFGR0_IFG16 ((uint32_t)0x00010000)
1864/* ADC14_IFGR0[IFG17] Bits */
1865#define ADC14_IFGR0_IFG17_OFS (17)
1866#define ADC14_IFGR0_IFG17 ((uint32_t)0x00020000)
1867/* ADC14_IFGR0[IFG18] Bits */
1868#define ADC14_IFGR0_IFG18_OFS (18)
1869#define ADC14_IFGR0_IFG18 ((uint32_t)0x00040000)
1870/* ADC14_IFGR0[IFG19] Bits */
1871#define ADC14_IFGR0_IFG19_OFS (19)
1872#define ADC14_IFGR0_IFG19 ((uint32_t)0x00080000)
1873/* ADC14_IFGR0[IFG20] Bits */
1874#define ADC14_IFGR0_IFG20_OFS (20)
1875#define ADC14_IFGR0_IFG20 ((uint32_t)0x00100000)
1876/* ADC14_IFGR0[IFG21] Bits */
1877#define ADC14_IFGR0_IFG21_OFS (21)
1878#define ADC14_IFGR0_IFG21 ((uint32_t)0x00200000)
1879/* ADC14_IFGR0[IFG22] Bits */
1880#define ADC14_IFGR0_IFG22_OFS (22)
1881#define ADC14_IFGR0_IFG22 ((uint32_t)0x00400000)
1882/* ADC14_IFGR0[IFG23] Bits */
1883#define ADC14_IFGR0_IFG23_OFS (23)
1884#define ADC14_IFGR0_IFG23 ((uint32_t)0x00800000)
1885/* ADC14_IFGR0[IFG24] Bits */
1886#define ADC14_IFGR0_IFG24_OFS (24)
1887#define ADC14_IFGR0_IFG24 ((uint32_t)0x01000000)
1888/* ADC14_IFGR0[IFG25] Bits */
1889#define ADC14_IFGR0_IFG25_OFS (25)
1890#define ADC14_IFGR0_IFG25 ((uint32_t)0x02000000)
1891/* ADC14_IFGR0[IFG26] Bits */
1892#define ADC14_IFGR0_IFG26_OFS (26)
1893#define ADC14_IFGR0_IFG26 ((uint32_t)0x04000000)
1894/* ADC14_IFGR0[IFG27] Bits */
1895#define ADC14_IFGR0_IFG27_OFS (27)
1896#define ADC14_IFGR0_IFG27 ((uint32_t)0x08000000)
1897/* ADC14_IFGR0[IFG28] Bits */
1898#define ADC14_IFGR0_IFG28_OFS (28)
1899#define ADC14_IFGR0_IFG28 ((uint32_t)0x10000000)
1900/* ADC14_IFGR0[IFG29] Bits */
1901#define ADC14_IFGR0_IFG29_OFS (29)
1902#define ADC14_IFGR0_IFG29 ((uint32_t)0x20000000)
1903/* ADC14_IFGR0[IFG30] Bits */
1904#define ADC14_IFGR0_IFG30_OFS (30)
1905#define ADC14_IFGR0_IFG30 ((uint32_t)0x40000000)
1906/* ADC14_IFGR0[IFG31] Bits */
1907#define ADC14_IFGR0_IFG31_OFS (31)
1908#define ADC14_IFGR0_IFG31 ((uint32_t)0x80000000)
1909/* ADC14_IFGR1[INIFG] Bits */
1910#define ADC14_IFGR1_INIFG_OFS ( 1)
1911#define ADC14_IFGR1_INIFG ((uint32_t)0x00000002)
1912/* ADC14_IFGR1[LOIFG] Bits */
1913#define ADC14_IFGR1_LOIFG_OFS ( 2)
1914#define ADC14_IFGR1_LOIFG ((uint32_t)0x00000004)
1915/* ADC14_IFGR1[HIIFG] Bits */
1916#define ADC14_IFGR1_HIIFG_OFS ( 3)
1917#define ADC14_IFGR1_HIIFG ((uint32_t)0x00000008)
1918/* ADC14_IFGR1[OVIFG] Bits */
1919#define ADC14_IFGR1_OVIFG_OFS ( 4)
1920#define ADC14_IFGR1_OVIFG ((uint32_t)0x00000010)
1921/* ADC14_IFGR1[TOVIFG] Bits */
1922#define ADC14_IFGR1_TOVIFG_OFS ( 5)
1923#define ADC14_IFGR1_TOVIFG ((uint32_t)0x00000020)
1924/* ADC14_IFGR1[RDYIFG] Bits */
1925#define ADC14_IFGR1_RDYIFG_OFS ( 6)
1926#define ADC14_IFGR1_RDYIFG ((uint32_t)0x00000040)
1927/* ADC14_CLRIFGR0[CLRIFG0] Bits */
1928#define ADC14_CLRIFGR0_CLRIFG0_OFS ( 0)
1929#define ADC14_CLRIFGR0_CLRIFG0 ((uint32_t)0x00000001)
1930/* ADC14_CLRIFGR0[CLRIFG1] Bits */
1931#define ADC14_CLRIFGR0_CLRIFG1_OFS ( 1)
1932#define ADC14_CLRIFGR0_CLRIFG1 ((uint32_t)0x00000002)
1933/* ADC14_CLRIFGR0[CLRIFG2] Bits */
1934#define ADC14_CLRIFGR0_CLRIFG2_OFS ( 2)
1935#define ADC14_CLRIFGR0_CLRIFG2 ((uint32_t)0x00000004)
1936/* ADC14_CLRIFGR0[CLRIFG3] Bits */
1937#define ADC14_CLRIFGR0_CLRIFG3_OFS ( 3)
1938#define ADC14_CLRIFGR0_CLRIFG3 ((uint32_t)0x00000008)
1939/* ADC14_CLRIFGR0[CLRIFG4] Bits */
1940#define ADC14_CLRIFGR0_CLRIFG4_OFS ( 4)
1941#define ADC14_CLRIFGR0_CLRIFG4 ((uint32_t)0x00000010)
1942/* ADC14_CLRIFGR0[CLRIFG5] Bits */
1943#define ADC14_CLRIFGR0_CLRIFG5_OFS ( 5)
1944#define ADC14_CLRIFGR0_CLRIFG5 ((uint32_t)0x00000020)
1945/* ADC14_CLRIFGR0[CLRIFG6] Bits */
1946#define ADC14_CLRIFGR0_CLRIFG6_OFS ( 6)
1947#define ADC14_CLRIFGR0_CLRIFG6 ((uint32_t)0x00000040)
1948/* ADC14_CLRIFGR0[CLRIFG7] Bits */
1949#define ADC14_CLRIFGR0_CLRIFG7_OFS ( 7)
1950#define ADC14_CLRIFGR0_CLRIFG7 ((uint32_t)0x00000080)
1951/* ADC14_CLRIFGR0[CLRIFG8] Bits */
1952#define ADC14_CLRIFGR0_CLRIFG8_OFS ( 8)
1953#define ADC14_CLRIFGR0_CLRIFG8 ((uint32_t)0x00000100)
1954/* ADC14_CLRIFGR0[CLRIFG9] Bits */
1955#define ADC14_CLRIFGR0_CLRIFG9_OFS ( 9)
1956#define ADC14_CLRIFGR0_CLRIFG9 ((uint32_t)0x00000200)
1957/* ADC14_CLRIFGR0[CLRIFG10] Bits */
1958#define ADC14_CLRIFGR0_CLRIFG10_OFS (10)
1959#define ADC14_CLRIFGR0_CLRIFG10 ((uint32_t)0x00000400)
1960/* ADC14_CLRIFGR0[CLRIFG11] Bits */
1961#define ADC14_CLRIFGR0_CLRIFG11_OFS (11)
1962#define ADC14_CLRIFGR0_CLRIFG11 ((uint32_t)0x00000800)
1963/* ADC14_CLRIFGR0[CLRIFG12] Bits */
1964#define ADC14_CLRIFGR0_CLRIFG12_OFS (12)
1965#define ADC14_CLRIFGR0_CLRIFG12 ((uint32_t)0x00001000)
1966/* ADC14_CLRIFGR0[CLRIFG13] Bits */
1967#define ADC14_CLRIFGR0_CLRIFG13_OFS (13)
1968#define ADC14_CLRIFGR0_CLRIFG13 ((uint32_t)0x00002000)
1969/* ADC14_CLRIFGR0[CLRIFG14] Bits */
1970#define ADC14_CLRIFGR0_CLRIFG14_OFS (14)
1971#define ADC14_CLRIFGR0_CLRIFG14 ((uint32_t)0x00004000)
1972/* ADC14_CLRIFGR0[CLRIFG15] Bits */
1973#define ADC14_CLRIFGR0_CLRIFG15_OFS (15)
1974#define ADC14_CLRIFGR0_CLRIFG15 ((uint32_t)0x00008000)
1975/* ADC14_CLRIFGR0[CLRIFG16] Bits */
1976#define ADC14_CLRIFGR0_CLRIFG16_OFS (16)
1977#define ADC14_CLRIFGR0_CLRIFG16 ((uint32_t)0x00010000)
1978/* ADC14_CLRIFGR0[CLRIFG17] Bits */
1979#define ADC14_CLRIFGR0_CLRIFG17_OFS (17)
1980#define ADC14_CLRIFGR0_CLRIFG17 ((uint32_t)0x00020000)
1981/* ADC14_CLRIFGR0[CLRIFG18] Bits */
1982#define ADC14_CLRIFGR0_CLRIFG18_OFS (18)
1983#define ADC14_CLRIFGR0_CLRIFG18 ((uint32_t)0x00040000)
1984/* ADC14_CLRIFGR0[CLRIFG19] Bits */
1985#define ADC14_CLRIFGR0_CLRIFG19_OFS (19)
1986#define ADC14_CLRIFGR0_CLRIFG19 ((uint32_t)0x00080000)
1987/* ADC14_CLRIFGR0[CLRIFG20] Bits */
1988#define ADC14_CLRIFGR0_CLRIFG20_OFS (20)
1989#define ADC14_CLRIFGR0_CLRIFG20 ((uint32_t)0x00100000)
1990/* ADC14_CLRIFGR0[CLRIFG21] Bits */
1991#define ADC14_CLRIFGR0_CLRIFG21_OFS (21)
1992#define ADC14_CLRIFGR0_CLRIFG21 ((uint32_t)0x00200000)
1993/* ADC14_CLRIFGR0[CLRIFG22] Bits */
1994#define ADC14_CLRIFGR0_CLRIFG22_OFS (22)
1995#define ADC14_CLRIFGR0_CLRIFG22 ((uint32_t)0x00400000)
1996/* ADC14_CLRIFGR0[CLRIFG23] Bits */
1997#define ADC14_CLRIFGR0_CLRIFG23_OFS (23)
1998#define ADC14_CLRIFGR0_CLRIFG23 ((uint32_t)0x00800000)
1999/* ADC14_CLRIFGR0[CLRIFG24] Bits */
2000#define ADC14_CLRIFGR0_CLRIFG24_OFS (24)
2001#define ADC14_CLRIFGR0_CLRIFG24 ((uint32_t)0x01000000)
2002/* ADC14_CLRIFGR0[CLRIFG25] Bits */
2003#define ADC14_CLRIFGR0_CLRIFG25_OFS (25)
2004#define ADC14_CLRIFGR0_CLRIFG25 ((uint32_t)0x02000000)
2005/* ADC14_CLRIFGR0[CLRIFG26] Bits */
2006#define ADC14_CLRIFGR0_CLRIFG26_OFS (26)
2007#define ADC14_CLRIFGR0_CLRIFG26 ((uint32_t)0x04000000)
2008/* ADC14_CLRIFGR0[CLRIFG27] Bits */
2009#define ADC14_CLRIFGR0_CLRIFG27_OFS (27)
2010#define ADC14_CLRIFGR0_CLRIFG27 ((uint32_t)0x08000000)
2011/* ADC14_CLRIFGR0[CLRIFG28] Bits */
2012#define ADC14_CLRIFGR0_CLRIFG28_OFS (28)
2013#define ADC14_CLRIFGR0_CLRIFG28 ((uint32_t)0x10000000)
2014/* ADC14_CLRIFGR0[CLRIFG29] Bits */
2015#define ADC14_CLRIFGR0_CLRIFG29_OFS (29)
2016#define ADC14_CLRIFGR0_CLRIFG29 ((uint32_t)0x20000000)
2017/* ADC14_CLRIFGR0[CLRIFG30] Bits */
2018#define ADC14_CLRIFGR0_CLRIFG30_OFS (30)
2019#define ADC14_CLRIFGR0_CLRIFG30 ((uint32_t)0x40000000)
2020/* ADC14_CLRIFGR0[CLRIFG31] Bits */
2021#define ADC14_CLRIFGR0_CLRIFG31_OFS (31)
2022#define ADC14_CLRIFGR0_CLRIFG31 ((uint32_t)0x80000000)
2023/* ADC14_CLRIFGR1[CLRINIFG] Bits */
2024#define ADC14_CLRIFGR1_CLRINIFG_OFS ( 1)
2025#define ADC14_CLRIFGR1_CLRINIFG ((uint32_t)0x00000002)
2026/* ADC14_CLRIFGR1[CLRLOIFG] Bits */
2027#define ADC14_CLRIFGR1_CLRLOIFG_OFS ( 2)
2028#define ADC14_CLRIFGR1_CLRLOIFG ((uint32_t)0x00000004)
2029/* ADC14_CLRIFGR1[CLRHIIFG] Bits */
2030#define ADC14_CLRIFGR1_CLRHIIFG_OFS ( 3)
2031#define ADC14_CLRIFGR1_CLRHIIFG ((uint32_t)0x00000008)
2032/* ADC14_CLRIFGR1[CLROVIFG] Bits */
2033#define ADC14_CLRIFGR1_CLROVIFG_OFS ( 4)
2034#define ADC14_CLRIFGR1_CLROVIFG ((uint32_t)0x00000010)
2035/* ADC14_CLRIFGR1[CLRTOVIFG] Bits */
2036#define ADC14_CLRIFGR1_CLRTOVIFG_OFS ( 5)
2037#define ADC14_CLRIFGR1_CLRTOVIFG ((uint32_t)0x00000020)
2038/* ADC14_CLRIFGR1[CLRRDYIFG] Bits */
2039#define ADC14_CLRIFGR1_CLRRDYIFG_OFS ( 6)
2040#define ADC14_CLRIFGR1_CLRRDYIFG ((uint32_t)0x00000040)
2042/******************************************************************************
2043* AES256 Bits
2044******************************************************************************/
2045/* AES256_CTL0[OP] Bits */
2046#define AES256_CTL0_OP_OFS ( 0)
2047#define AES256_CTL0_OP_MASK ((uint16_t)0x0003)
2048#define AES256_CTL0_OP0 ((uint16_t)0x0001)
2049#define AES256_CTL0_OP1 ((uint16_t)0x0002)
2050#define AES256_CTL0_OP_0 ((uint16_t)0x0000)
2051#define AES256_CTL0_OP_1 ((uint16_t)0x0001)
2052#define AES256_CTL0_OP_2 ((uint16_t)0x0002)
2053#define AES256_CTL0_OP_3 ((uint16_t)0x0003)
2054/* AES256_CTL0[KL] Bits */
2055#define AES256_CTL0_KL_OFS ( 2)
2056#define AES256_CTL0_KL_MASK ((uint16_t)0x000C)
2057#define AES256_CTL0_KL0 ((uint16_t)0x0004)
2058#define AES256_CTL0_KL1 ((uint16_t)0x0008)
2059#define AES256_CTL0_KL_0 ((uint16_t)0x0000)
2060#define AES256_CTL0_KL_1 ((uint16_t)0x0004)
2061#define AES256_CTL0_KL_2 ((uint16_t)0x0008)
2062#define AES256_CTL0_KL__128BIT ((uint16_t)0x0000)
2063#define AES256_CTL0_KL__192BIT ((uint16_t)0x0004)
2064#define AES256_CTL0_KL__256BIT ((uint16_t)0x0008)
2065/* AES256_CTL0[CM] Bits */
2066#define AES256_CTL0_CM_OFS ( 5)
2067#define AES256_CTL0_CM_MASK ((uint16_t)0x0060)
2068#define AES256_CTL0_CM0 ((uint16_t)0x0020)
2069#define AES256_CTL0_CM1 ((uint16_t)0x0040)
2070#define AES256_CTL0_CM_0 ((uint16_t)0x0000)
2071#define AES256_CTL0_CM_1 ((uint16_t)0x0020)
2072#define AES256_CTL0_CM_2 ((uint16_t)0x0040)
2073#define AES256_CTL0_CM_3 ((uint16_t)0x0060)
2074#define AES256_CTL0_CM__ECB ((uint16_t)0x0000)
2075#define AES256_CTL0_CM__CBC ((uint16_t)0x0020)
2076#define AES256_CTL0_CM__OFB ((uint16_t)0x0040)
2077#define AES256_CTL0_CM__CFB ((uint16_t)0x0060)
2078/* AES256_CTL0[SWRST] Bits */
2079#define AES256_CTL0_SWRST_OFS ( 7)
2080#define AES256_CTL0_SWRST ((uint16_t)0x0080)
2081/* AES256_CTL0[RDYIFG] Bits */
2082#define AES256_CTL0_RDYIFG_OFS ( 8)
2083#define AES256_CTL0_RDYIFG ((uint16_t)0x0100)
2084/* AES256_CTL0[ERRFG] Bits */
2085#define AES256_CTL0_ERRFG_OFS (11)
2086#define AES256_CTL0_ERRFG ((uint16_t)0x0800)
2087/* AES256_CTL0[RDYIE] Bits */
2088#define AES256_CTL0_RDYIE_OFS (12)
2089#define AES256_CTL0_RDYIE ((uint16_t)0x1000)
2090/* AES256_CTL0[CMEN] Bits */
2091#define AES256_CTL0_CMEN_OFS (15)
2092#define AES256_CTL0_CMEN ((uint16_t)0x8000)
2093/* AES256_CTL1[BLKCNT] Bits */
2094#define AES256_CTL1_BLKCNT_OFS ( 0)
2095#define AES256_CTL1_BLKCNT_MASK ((uint16_t)0x00FF)
2096#define AES256_CTL1_BLKCNT0 ((uint16_t)0x0001)
2097#define AES256_CTL1_BLKCNT1 ((uint16_t)0x0002)
2098#define AES256_CTL1_BLKCNT2 ((uint16_t)0x0004)
2099#define AES256_CTL1_BLKCNT3 ((uint16_t)0x0008)
2100#define AES256_CTL1_BLKCNT4 ((uint16_t)0x0010)
2101#define AES256_CTL1_BLKCNT5 ((uint16_t)0x0020)
2102#define AES256_CTL1_BLKCNT6 ((uint16_t)0x0040)
2103#define AES256_CTL1_BLKCNT7 ((uint16_t)0x0080)
2104/* AES256_STAT[BUSY] Bits */
2105#define AES256_STAT_BUSY_OFS ( 0)
2106#define AES256_STAT_BUSY ((uint16_t)0x0001)
2107/* AES256_STAT[KEYWR] Bits */
2108#define AES256_STAT_KEYWR_OFS ( 1)
2109#define AES256_STAT_KEYWR ((uint16_t)0x0002)
2110/* AES256_STAT[DINWR] Bits */
2111#define AES256_STAT_DINWR_OFS ( 2)
2112#define AES256_STAT_DINWR ((uint16_t)0x0004)
2113/* AES256_STAT[DOUTRD] Bits */
2114#define AES256_STAT_DOUTRD_OFS ( 3)
2115#define AES256_STAT_DOUTRD ((uint16_t)0x0008)
2116/* AES256_STAT[KEYCNT] Bits */
2117#define AES256_STAT_KEYCNT_OFS ( 4)
2118#define AES256_STAT_KEYCNT_MASK ((uint16_t)0x00F0)
2119#define AES256_STAT_KEYCNT0 ((uint16_t)0x0010)
2120#define AES256_STAT_KEYCNT1 ((uint16_t)0x0020)
2121#define AES256_STAT_KEYCNT2 ((uint16_t)0x0040)
2122#define AES256_STAT_KEYCNT3 ((uint16_t)0x0080)
2123/* AES256_STAT[DINCNT] Bits */
2124#define AES256_STAT_DINCNT_OFS ( 8)
2125#define AES256_STAT_DINCNT_MASK ((uint16_t)0x0F00)
2126#define AES256_STAT_DINCNT0 ((uint16_t)0x0100)
2127#define AES256_STAT_DINCNT1 ((uint16_t)0x0200)
2128#define AES256_STAT_DINCNT2 ((uint16_t)0x0400)
2129#define AES256_STAT_DINCNT3 ((uint16_t)0x0800)
2130/* AES256_STAT[DOUTCNT] Bits */
2131#define AES256_STAT_DOUTCNT_OFS (12)
2132#define AES256_STAT_DOUTCNT_MASK ((uint16_t)0xF000)
2133#define AES256_STAT_DOUTCNT0 ((uint16_t)0x1000)
2134#define AES256_STAT_DOUTCNT1 ((uint16_t)0x2000)
2135#define AES256_STAT_DOUTCNT2 ((uint16_t)0x4000)
2136#define AES256_STAT_DOUTCNT3 ((uint16_t)0x8000)
2137/* AES256_KEY[KEY0] Bits */
2138#define AES256_KEY_KEY0_OFS ( 0)
2139#define AES256_KEY_KEY0_MASK ((uint16_t)0x00FF)
2140#define AES256_KEY_KEY00 ((uint16_t)0x0001)
2141#define AES256_KEY_KEY01 ((uint16_t)0x0002)
2142#define AES256_KEY_KEY02 ((uint16_t)0x0004)
2143#define AES256_KEY_KEY03 ((uint16_t)0x0008)
2144#define AES256_KEY_KEY04 ((uint16_t)0x0010)
2145#define AES256_KEY_KEY05 ((uint16_t)0x0020)
2146#define AES256_KEY_KEY06 ((uint16_t)0x0040)
2147#define AES256_KEY_KEY07 ((uint16_t)0x0080)
2148/* AES256_KEY[KEY1] Bits */
2149#define AES256_KEY_KEY1_OFS ( 8)
2150#define AES256_KEY_KEY1_MASK ((uint16_t)0xFF00)
2151#define AES256_KEY_KEY10 ((uint16_t)0x0100)
2152#define AES256_KEY_KEY11 ((uint16_t)0x0200)
2153#define AES256_KEY_KEY12 ((uint16_t)0x0400)
2154#define AES256_KEY_KEY13 ((uint16_t)0x0800)
2155#define AES256_KEY_KEY14 ((uint16_t)0x1000)
2156#define AES256_KEY_KEY15 ((uint16_t)0x2000)
2157#define AES256_KEY_KEY16 ((uint16_t)0x4000)
2158#define AES256_KEY_KEY17 ((uint16_t)0x8000)
2159/* AES256_DIN[DIN0] Bits */
2160#define AES256_DIN_DIN0_OFS ( 0)
2161#define AES256_DIN_DIN0_MASK ((uint16_t)0x00FF)
2162#define AES256_DIN_DIN00 ((uint16_t)0x0001)
2163#define AES256_DIN_DIN01 ((uint16_t)0x0002)
2164#define AES256_DIN_DIN02 ((uint16_t)0x0004)
2165#define AES256_DIN_DIN03 ((uint16_t)0x0008)
2166#define AES256_DIN_DIN04 ((uint16_t)0x0010)
2167#define AES256_DIN_DIN05 ((uint16_t)0x0020)
2168#define AES256_DIN_DIN06 ((uint16_t)0x0040)
2169#define AES256_DIN_DIN07 ((uint16_t)0x0080)
2170/* AES256_DIN[DIN1] Bits */
2171#define AES256_DIN_DIN1_OFS ( 8)
2172#define AES256_DIN_DIN1_MASK ((uint16_t)0xFF00)
2173#define AES256_DIN_DIN10 ((uint16_t)0x0100)
2174#define AES256_DIN_DIN11 ((uint16_t)0x0200)
2175#define AES256_DIN_DIN12 ((uint16_t)0x0400)
2176#define AES256_DIN_DIN13 ((uint16_t)0x0800)
2177#define AES256_DIN_DIN14 ((uint16_t)0x1000)
2178#define AES256_DIN_DIN15 ((uint16_t)0x2000)
2179#define AES256_DIN_DIN16 ((uint16_t)0x4000)
2180#define AES256_DIN_DIN17 ((uint16_t)0x8000)
2181/* AES256_DOUT[DOUT0] Bits */
2182#define AES256_DOUT_DOUT0_OFS ( 0)
2183#define AES256_DOUT_DOUT0_MASK ((uint16_t)0x00FF)
2184#define AES256_DOUT_DOUT00 ((uint16_t)0x0001)
2185#define AES256_DOUT_DOUT01 ((uint16_t)0x0002)
2186#define AES256_DOUT_DOUT02 ((uint16_t)0x0004)
2187#define AES256_DOUT_DOUT03 ((uint16_t)0x0008)
2188#define AES256_DOUT_DOUT04 ((uint16_t)0x0010)
2189#define AES256_DOUT_DOUT05 ((uint16_t)0x0020)
2190#define AES256_DOUT_DOUT06 ((uint16_t)0x0040)
2191#define AES256_DOUT_DOUT07 ((uint16_t)0x0080)
2192/* AES256_DOUT[DOUT1] Bits */
2193#define AES256_DOUT_DOUT1_OFS ( 8)
2194#define AES256_DOUT_DOUT1_MASK ((uint16_t)0xFF00)
2195#define AES256_DOUT_DOUT10 ((uint16_t)0x0100)
2196#define AES256_DOUT_DOUT11 ((uint16_t)0x0200)
2197#define AES256_DOUT_DOUT12 ((uint16_t)0x0400)
2198#define AES256_DOUT_DOUT13 ((uint16_t)0x0800)
2199#define AES256_DOUT_DOUT14 ((uint16_t)0x1000)
2200#define AES256_DOUT_DOUT15 ((uint16_t)0x2000)
2201#define AES256_DOUT_DOUT16 ((uint16_t)0x4000)
2202#define AES256_DOUT_DOUT17 ((uint16_t)0x8000)
2203/* AES256_XDIN[XDIN0] Bits */
2204#define AES256_XDIN_XDIN0_OFS ( 0)
2205#define AES256_XDIN_XDIN0_MASK ((uint16_t)0x00FF)
2206#define AES256_XDIN_XDIN00 ((uint16_t)0x0001)
2207#define AES256_XDIN_XDIN01 ((uint16_t)0x0002)
2208#define AES256_XDIN_XDIN02 ((uint16_t)0x0004)
2209#define AES256_XDIN_XDIN03 ((uint16_t)0x0008)
2210#define AES256_XDIN_XDIN04 ((uint16_t)0x0010)
2211#define AES256_XDIN_XDIN05 ((uint16_t)0x0020)
2212#define AES256_XDIN_XDIN06 ((uint16_t)0x0040)
2213#define AES256_XDIN_XDIN07 ((uint16_t)0x0080)
2214/* AES256_XDIN[XDIN1] Bits */
2215#define AES256_XDIN_XDIN1_OFS ( 8)
2216#define AES256_XDIN_XDIN1_MASK ((uint16_t)0xFF00)
2217#define AES256_XDIN_XDIN10 ((uint16_t)0x0100)
2218#define AES256_XDIN_XDIN11 ((uint16_t)0x0200)
2219#define AES256_XDIN_XDIN12 ((uint16_t)0x0400)
2220#define AES256_XDIN_XDIN13 ((uint16_t)0x0800)
2221#define AES256_XDIN_XDIN14 ((uint16_t)0x1000)
2222#define AES256_XDIN_XDIN15 ((uint16_t)0x2000)
2223#define AES256_XDIN_XDIN16 ((uint16_t)0x4000)
2224#define AES256_XDIN_XDIN17 ((uint16_t)0x8000)
2225/* AES256_XIN[XIN0] Bits */
2226#define AES256_XIN_XIN0_OFS ( 0)
2227#define AES256_XIN_XIN0_MASK ((uint16_t)0x00FF)
2228#define AES256_XIN_XIN00 ((uint16_t)0x0001)
2229#define AES256_XIN_XIN01 ((uint16_t)0x0002)
2230#define AES256_XIN_XIN02 ((uint16_t)0x0004)
2231#define AES256_XIN_XIN03 ((uint16_t)0x0008)
2232#define AES256_XIN_XIN04 ((uint16_t)0x0010)
2233#define AES256_XIN_XIN05 ((uint16_t)0x0020)
2234#define AES256_XIN_XIN06 ((uint16_t)0x0040)
2235#define AES256_XIN_XIN07 ((uint16_t)0x0080)
2236/* AES256_XIN[XIN1] Bits */
2237#define AES256_XIN_XIN1_OFS ( 8)
2238#define AES256_XIN_XIN1_MASK ((uint16_t)0xFF00)
2239#define AES256_XIN_XIN10 ((uint16_t)0x0100)
2240#define AES256_XIN_XIN11 ((uint16_t)0x0200)
2241#define AES256_XIN_XIN12 ((uint16_t)0x0400)
2242#define AES256_XIN_XIN13 ((uint16_t)0x0800)
2243#define AES256_XIN_XIN14 ((uint16_t)0x1000)
2244#define AES256_XIN_XIN15 ((uint16_t)0x2000)
2245#define AES256_XIN_XIN16 ((uint16_t)0x4000)
2246#define AES256_XIN_XIN17 ((uint16_t)0x8000)
2248/******************************************************************************
2249* CAPTIO Bits
2250******************************************************************************/
2251/* CAPTIO_CTL[PISEL] Bits */
2252#define CAPTIO_CTL_PISEL_OFS ( 1)
2253#define CAPTIO_CTL_PISEL_MASK ((uint16_t)0x000E)
2254#define CAPTIO_CTL_PISEL0 ((uint16_t)0x0002)
2255#define CAPTIO_CTL_PISEL1 ((uint16_t)0x0004)
2256#define CAPTIO_CTL_PISEL2 ((uint16_t)0x0008)
2257#define CAPTIO_CTL_PISEL_0 ((uint16_t)0x0000)
2258#define CAPTIO_CTL_PISEL_1 ((uint16_t)0x0002)
2259#define CAPTIO_CTL_PISEL_2 ((uint16_t)0x0004)
2260#define CAPTIO_CTL_PISEL_3 ((uint16_t)0x0006)
2261#define CAPTIO_CTL_PISEL_4 ((uint16_t)0x0008)
2262#define CAPTIO_CTL_PISEL_5 ((uint16_t)0x000A)
2263#define CAPTIO_CTL_PISEL_6 ((uint16_t)0x000C)
2264#define CAPTIO_CTL_PISEL_7 ((uint16_t)0x000E)
2265/* CAPTIO_CTL[POSEL] Bits */
2266#define CAPTIO_CTL_POSEL_OFS ( 4)
2267#define CAPTIO_CTL_POSEL_MASK ((uint16_t)0x00F0)
2268#define CAPTIO_CTL_POSEL0 ((uint16_t)0x0010)
2269#define CAPTIO_CTL_POSEL1 ((uint16_t)0x0020)
2270#define CAPTIO_CTL_POSEL2 ((uint16_t)0x0040)
2271#define CAPTIO_CTL_POSEL3 ((uint16_t)0x0080)
2272#define CAPTIO_CTL_POSEL_0 ((uint16_t)0x0000)
2273#define CAPTIO_CTL_POSEL_1 ((uint16_t)0x0010)
2274#define CAPTIO_CTL_POSEL_2 ((uint16_t)0x0020)
2275#define CAPTIO_CTL_POSEL_3 ((uint16_t)0x0030)
2276#define CAPTIO_CTL_POSEL_4 ((uint16_t)0x0040)
2277#define CAPTIO_CTL_POSEL_5 ((uint16_t)0x0050)
2278#define CAPTIO_CTL_POSEL_6 ((uint16_t)0x0060)
2279#define CAPTIO_CTL_POSEL_7 ((uint16_t)0x0070)
2280#define CAPTIO_CTL_POSEL_8 ((uint16_t)0x0080)
2281#define CAPTIO_CTL_POSEL_9 ((uint16_t)0x0090)
2282#define CAPTIO_CTL_POSEL_10 ((uint16_t)0x00A0)
2283#define CAPTIO_CTL_POSEL_11 ((uint16_t)0x00B0)
2284#define CAPTIO_CTL_POSEL_12 ((uint16_t)0x00C0)
2285#define CAPTIO_CTL_POSEL_13 ((uint16_t)0x00D0)
2286#define CAPTIO_CTL_POSEL_14 ((uint16_t)0x00E0)
2287#define CAPTIO_CTL_POSEL_15 ((uint16_t)0x00F0)
2288#define CAPTIO_CTL_POSEL__PJ ((uint16_t)0x0000)
2289#define CAPTIO_CTL_POSEL__P1 ((uint16_t)0x0010)
2290#define CAPTIO_CTL_POSEL__P2 ((uint16_t)0x0020)
2291#define CAPTIO_CTL_POSEL__P3 ((uint16_t)0x0030)
2292#define CAPTIO_CTL_POSEL__P4 ((uint16_t)0x0040)
2293#define CAPTIO_CTL_POSEL__P5 ((uint16_t)0x0050)
2294#define CAPTIO_CTL_POSEL__P6 ((uint16_t)0x0060)
2295#define CAPTIO_CTL_POSEL__P7 ((uint16_t)0x0070)
2296#define CAPTIO_CTL_POSEL__P8 ((uint16_t)0x0080)
2297#define CAPTIO_CTL_POSEL__P9 ((uint16_t)0x0090)
2298#define CAPTIO_CTL_POSEL__P10 ((uint16_t)0x00A0)
2299#define CAPTIO_CTL_POSEL__P11 ((uint16_t)0x00B0)
2300#define CAPTIO_CTL_POSEL__P12 ((uint16_t)0x00C0)
2301#define CAPTIO_CTL_POSEL__P13 ((uint16_t)0x00D0)
2302#define CAPTIO_CTL_POSEL__P14 ((uint16_t)0x00E0)
2303#define CAPTIO_CTL_POSEL__P15 ((uint16_t)0x00F0)
2304/* CAPTIO_CTL[EN] Bits */
2305#define CAPTIO_CTL_EN_OFS ( 8)
2306#define CAPTIO_CTL_EN ((uint16_t)0x0100)
2307/* CAPTIO_CTL[STATE] Bits */
2308#define CAPTIO_CTL_STATE_OFS ( 9)
2309#define CAPTIO_CTL_STATE ((uint16_t)0x0200)
2311/******************************************************************************
2312* COMP_E Bits
2313******************************************************************************/
2314/* COMP_E_CTL0[IPSEL] Bits */
2315#define COMP_E_CTL0_IPSEL_OFS ( 0)
2316#define COMP_E_CTL0_IPSEL_MASK ((uint16_t)0x000F)
2317#define COMP_E_CTL0_IPSEL0 ((uint16_t)0x0001)
2318#define COMP_E_CTL0_IPSEL1 ((uint16_t)0x0002)
2319#define COMP_E_CTL0_IPSEL2 ((uint16_t)0x0004)
2320#define COMP_E_CTL0_IPSEL3 ((uint16_t)0x0008)
2321#define COMP_E_CTL0_IPSEL_0 ((uint16_t)0x0000)
2322#define COMP_E_CTL0_IPSEL_1 ((uint16_t)0x0001)
2323#define COMP_E_CTL0_IPSEL_2 ((uint16_t)0x0002)
2324#define COMP_E_CTL0_IPSEL_3 ((uint16_t)0x0003)
2325#define COMP_E_CTL0_IPSEL_4 ((uint16_t)0x0004)
2326#define COMP_E_CTL0_IPSEL_5 ((uint16_t)0x0005)
2327#define COMP_E_CTL0_IPSEL_6 ((uint16_t)0x0006)
2328#define COMP_E_CTL0_IPSEL_7 ((uint16_t)0x0007)
2329#define COMP_E_CTL0_IPSEL_8 ((uint16_t)0x0008)
2330#define COMP_E_CTL0_IPSEL_9 ((uint16_t)0x0009)
2331#define COMP_E_CTL0_IPSEL_10 ((uint16_t)0x000A)
2332#define COMP_E_CTL0_IPSEL_11 ((uint16_t)0x000B)
2333#define COMP_E_CTL0_IPSEL_12 ((uint16_t)0x000C)
2334#define COMP_E_CTL0_IPSEL_13 ((uint16_t)0x000D)
2335#define COMP_E_CTL0_IPSEL_14 ((uint16_t)0x000E)
2336#define COMP_E_CTL0_IPSEL_15 ((uint16_t)0x000F)
2337/* COMP_E_CTL0[IPEN] Bits */
2338#define COMP_E_CTL0_IPEN_OFS ( 7)
2339#define COMP_E_CTL0_IPEN ((uint16_t)0x0080)
2340/* COMP_E_CTL0[IMSEL] Bits */
2341#define COMP_E_CTL0_IMSEL_OFS ( 8)
2342#define COMP_E_CTL0_IMSEL_MASK ((uint16_t)0x0F00)
2343#define COMP_E_CTL0_IMSEL0 ((uint16_t)0x0100)
2344#define COMP_E_CTL0_IMSEL1 ((uint16_t)0x0200)
2345#define COMP_E_CTL0_IMSEL2 ((uint16_t)0x0400)
2346#define COMP_E_CTL0_IMSEL3 ((uint16_t)0x0800)
2347#define COMP_E_CTL0_IMSEL_0 ((uint16_t)0x0000)
2348#define COMP_E_CTL0_IMSEL_1 ((uint16_t)0x0100)
2349#define COMP_E_CTL0_IMSEL_2 ((uint16_t)0x0200)
2350#define COMP_E_CTL0_IMSEL_3 ((uint16_t)0x0300)
2351#define COMP_E_CTL0_IMSEL_4 ((uint16_t)0x0400)
2352#define COMP_E_CTL0_IMSEL_5 ((uint16_t)0x0500)
2353#define COMP_E_CTL0_IMSEL_6 ((uint16_t)0x0600)
2354#define COMP_E_CTL0_IMSEL_7 ((uint16_t)0x0700)
2355#define COMP_E_CTL0_IMSEL_8 ((uint16_t)0x0800)
2356#define COMP_E_CTL0_IMSEL_9 ((uint16_t)0x0900)
2357#define COMP_E_CTL0_IMSEL_10 ((uint16_t)0x0A00)
2358#define COMP_E_CTL0_IMSEL_11 ((uint16_t)0x0B00)
2359#define COMP_E_CTL0_IMSEL_12 ((uint16_t)0x0C00)
2360#define COMP_E_CTL0_IMSEL_13 ((uint16_t)0x0D00)
2361#define COMP_E_CTL0_IMSEL_14 ((uint16_t)0x0E00)
2362#define COMP_E_CTL0_IMSEL_15 ((uint16_t)0x0F00)
2363/* COMP_E_CTL0[IMEN] Bits */
2364#define COMP_E_CTL0_IMEN_OFS (15)
2365#define COMP_E_CTL0_IMEN ((uint16_t)0x8000)
2366/* COMP_E_CTL1[OUT] Bits */
2367#define COMP_E_CTL1_OUT_OFS ( 0)
2368#define COMP_E_CTL1_OUT ((uint16_t)0x0001)
2369/* COMP_E_CTL1[OUTPOL] Bits */
2370#define COMP_E_CTL1_OUTPOL_OFS ( 1)
2371#define COMP_E_CTL1_OUTPOL ((uint16_t)0x0002)
2372/* COMP_E_CTL1[F] Bits */
2373#define COMP_E_CTL1_F_OFS ( 2)
2374#define COMP_E_CTL1_F ((uint16_t)0x0004)
2375/* COMP_E_CTL1[IES] Bits */
2376#define COMP_E_CTL1_IES_OFS ( 3)
2377#define COMP_E_CTL1_IES ((uint16_t)0x0008)
2378/* COMP_E_CTL1[SHORT] Bits */
2379#define COMP_E_CTL1_SHORT_OFS ( 4)
2380#define COMP_E_CTL1_SHORT ((uint16_t)0x0010)
2381/* COMP_E_CTL1[EX] Bits */
2382#define COMP_E_CTL1_EX_OFS ( 5)
2383#define COMP_E_CTL1_EX ((uint16_t)0x0020)
2384/* COMP_E_CTL1[FDLY] Bits */
2385#define COMP_E_CTL1_FDLY_OFS ( 6)
2386#define COMP_E_CTL1_FDLY_MASK ((uint16_t)0x00C0)
2387#define COMP_E_CTL1_FDLY0 ((uint16_t)0x0040)
2388#define COMP_E_CTL1_FDLY1 ((uint16_t)0x0080)
2389#define COMP_E_CTL1_FDLY_0 ((uint16_t)0x0000)
2390#define COMP_E_CTL1_FDLY_1 ((uint16_t)0x0040)
2391#define COMP_E_CTL1_FDLY_2 ((uint16_t)0x0080)
2392#define COMP_E_CTL1_FDLY_3 ((uint16_t)0x00C0)
2393/* COMP_E_CTL1[PWRMD] Bits */
2394#define COMP_E_CTL1_PWRMD_OFS ( 8)
2395#define COMP_E_CTL1_PWRMD_MASK ((uint16_t)0x0300)
2396#define COMP_E_CTL1_PWRMD0 ((uint16_t)0x0100)
2397#define COMP_E_CTL1_PWRMD1 ((uint16_t)0x0200)
2398#define COMP_E_CTL1_PWRMD_0 ((uint16_t)0x0000)
2399#define COMP_E_CTL1_PWRMD_1 ((uint16_t)0x0100)
2400#define COMP_E_CTL1_PWRMD_2 ((uint16_t)0x0200)
2401/* COMP_E_CTL1[ON] Bits */
2402#define COMP_E_CTL1_ON_OFS (10)
2403#define COMP_E_CTL1_ON ((uint16_t)0x0400)
2404/* COMP_E_CTL1[MRVL] Bits */
2405#define COMP_E_CTL1_MRVL_OFS (11)
2406#define COMP_E_CTL1_MRVL ((uint16_t)0x0800)
2407/* COMP_E_CTL1[MRVS] Bits */
2408#define COMP_E_CTL1_MRVS_OFS (12)
2409#define COMP_E_CTL1_MRVS ((uint16_t)0x1000)
2410/* COMP_E_CTL2[REF0] Bits */
2411#define COMP_E_CTL2_REF0_OFS ( 0)
2412#define COMP_E_CTL2_REF0_MASK ((uint16_t)0x001F)
2413#define COMP_E_CTL2_REF00 ((uint16_t)0x0001)
2414#define COMP_E_CTL2_REF01 ((uint16_t)0x0002)
2415#define COMP_E_CTL2_REF02 ((uint16_t)0x0004)
2416#define COMP_E_CTL2_REF03 ((uint16_t)0x0008)
2417#define COMP_E_CTL2_REF04 ((uint16_t)0x0010)
2418#define COMP_E_CTL2_REF0_0 ((uint16_t)0x0000)
2419#define COMP_E_CTL2_REF0_1 ((uint16_t)0x0001)
2420#define COMP_E_CTL2_REF0_2 ((uint16_t)0x0002)
2421#define COMP_E_CTL2_REF0_3 ((uint16_t)0x0003)
2422#define COMP_E_CTL2_REF0_4 ((uint16_t)0x0004)
2423#define COMP_E_CTL2_REF0_5 ((uint16_t)0x0005)
2424#define COMP_E_CTL2_REF0_6 ((uint16_t)0x0006)
2425#define COMP_E_CTL2_REF0_7 ((uint16_t)0x0007)
2426#define COMP_E_CTL2_REF0_8 ((uint16_t)0x0008)
2427#define COMP_E_CTL2_REF0_9 ((uint16_t)0x0009)
2428#define COMP_E_CTL2_REF0_10 ((uint16_t)0x000A)
2429#define COMP_E_CTL2_REF0_11 ((uint16_t)0x000B)
2430#define COMP_E_CTL2_REF0_12 ((uint16_t)0x000C)
2431#define COMP_E_CTL2_REF0_13 ((uint16_t)0x000D)
2432#define COMP_E_CTL2_REF0_14 ((uint16_t)0x000E)
2433#define COMP_E_CTL2_REF0_15 ((uint16_t)0x000F)
2434#define COMP_E_CTL2_REF0_16 ((uint16_t)0x0010)
2435#define COMP_E_CTL2_REF0_17 ((uint16_t)0x0011)
2436#define COMP_E_CTL2_REF0_18 ((uint16_t)0x0012)
2437#define COMP_E_CTL2_REF0_19 ((uint16_t)0x0013)
2438#define COMP_E_CTL2_REF0_20 ((uint16_t)0x0014)
2439#define COMP_E_CTL2_REF0_21 ((uint16_t)0x0015)
2440#define COMP_E_CTL2_REF0_22 ((uint16_t)0x0016)
2441#define COMP_E_CTL2_REF0_23 ((uint16_t)0x0017)
2442#define COMP_E_CTL2_REF0_24 ((uint16_t)0x0018)
2443#define COMP_E_CTL2_REF0_25 ((uint16_t)0x0019)
2444#define COMP_E_CTL2_REF0_26 ((uint16_t)0x001A)
2445#define COMP_E_CTL2_REF0_27 ((uint16_t)0x001B)
2446#define COMP_E_CTL2_REF0_28 ((uint16_t)0x001C)
2447#define COMP_E_CTL2_REF0_29 ((uint16_t)0x001D)
2448#define COMP_E_CTL2_REF0_30 ((uint16_t)0x001E)
2449#define COMP_E_CTL2_REF0_31 ((uint16_t)0x001F)
2450/* COMP_E_CTL2[RSEL] Bits */
2451#define COMP_E_CTL2_RSEL_OFS ( 5)
2452#define COMP_E_CTL2_RSEL ((uint16_t)0x0020)
2453/* COMP_E_CTL2[RS] Bits */
2454#define COMP_E_CTL2_RS_OFS ( 6)
2455#define COMP_E_CTL2_RS_MASK ((uint16_t)0x00C0)
2456#define COMP_E_CTL2_RS0 ((uint16_t)0x0040)
2457#define COMP_E_CTL2_RS1 ((uint16_t)0x0080)
2458#define COMP_E_CTL2_RS_0 ((uint16_t)0x0000)
2459#define COMP_E_CTL2_RS_1 ((uint16_t)0x0040)
2460#define COMP_E_CTL2_RS_2 ((uint16_t)0x0080)
2461#define COMP_E_CTL2_RS_3 ((uint16_t)0x00C0)
2462/* COMP_E_CTL2[REF1] Bits */
2463#define COMP_E_CTL2_REF1_OFS ( 8)
2464#define COMP_E_CTL2_REF1_MASK ((uint16_t)0x1F00)
2465#define COMP_E_CTL2_REF10 ((uint16_t)0x0100)
2466#define COMP_E_CTL2_REF11 ((uint16_t)0x0200)
2467#define COMP_E_CTL2_REF12 ((uint16_t)0x0400)
2468#define COMP_E_CTL2_REF13 ((uint16_t)0x0800)
2469#define COMP_E_CTL2_REF14 ((uint16_t)0x1000)
2470#define COMP_E_CTL2_REF1_0 ((uint16_t)0x0000)
2471#define COMP_E_CTL2_REF1_1 ((uint16_t)0x0100)
2472#define COMP_E_CTL2_REF1_2 ((uint16_t)0x0200)
2473#define COMP_E_CTL2_REF1_3 ((uint16_t)0x0300)
2474#define COMP_E_CTL2_REF1_4 ((uint16_t)0x0400)
2475#define COMP_E_CTL2_REF1_5 ((uint16_t)0x0500)
2476#define COMP_E_CTL2_REF1_6 ((uint16_t)0x0600)
2477#define COMP_E_CTL2_REF1_7 ((uint16_t)0x0700)
2478#define COMP_E_CTL2_REF1_8 ((uint16_t)0x0800)
2479#define COMP_E_CTL2_REF1_9 ((uint16_t)0x0900)
2480#define COMP_E_CTL2_REF1_10 ((uint16_t)0x0A00)
2481#define COMP_E_CTL2_REF1_11 ((uint16_t)0x0B00)
2482#define COMP_E_CTL2_REF1_12 ((uint16_t)0x0C00)
2483#define COMP_E_CTL2_REF1_13 ((uint16_t)0x0D00)
2484#define COMP_E_CTL2_REF1_14 ((uint16_t)0x0E00)
2485#define COMP_E_CTL2_REF1_15 ((uint16_t)0x0F00)
2486#define COMP_E_CTL2_REF1_16 ((uint16_t)0x1000)
2487#define COMP_E_CTL2_REF1_17 ((uint16_t)0x1100)
2488#define COMP_E_CTL2_REF1_18 ((uint16_t)0x1200)
2489#define COMP_E_CTL2_REF1_19 ((uint16_t)0x1300)
2490#define COMP_E_CTL2_REF1_20 ((uint16_t)0x1400)
2491#define COMP_E_CTL2_REF1_21 ((uint16_t)0x1500)
2492#define COMP_E_CTL2_REF1_22 ((uint16_t)0x1600)
2493#define COMP_E_CTL2_REF1_23 ((uint16_t)0x1700)
2494#define COMP_E_CTL2_REF1_24 ((uint16_t)0x1800)
2495#define COMP_E_CTL2_REF1_25 ((uint16_t)0x1900)
2496#define COMP_E_CTL2_REF1_26 ((uint16_t)0x1A00)
2497#define COMP_E_CTL2_REF1_27 ((uint16_t)0x1B00)
2498#define COMP_E_CTL2_REF1_28 ((uint16_t)0x1C00)
2499#define COMP_E_CTL2_REF1_29 ((uint16_t)0x1D00)
2500#define COMP_E_CTL2_REF1_30 ((uint16_t)0x1E00)
2501#define COMP_E_CTL2_REF1_31 ((uint16_t)0x1F00)
2502/* COMP_E_CTL2[REFL] Bits */
2503#define COMP_E_CTL2_REFL_OFS (13)
2504#define COMP_E_CTL2_REFL_MASK ((uint16_t)0x6000)
2505#define COMP_E_CTL2_REFL0 ((uint16_t)0x2000)
2506#define COMP_E_CTL2_REFL1 ((uint16_t)0x4000)
2507#define COMP_E_CTL2_CEREFL_0 ((uint16_t)0x0000)
2508#define COMP_E_CTL2_CEREFL_1 ((uint16_t)0x2000)
2509#define COMP_E_CTL2_CEREFL_2 ((uint16_t)0x4000)
2510#define COMP_E_CTL2_CEREFL_3 ((uint16_t)0x6000)
2511#define COMP_E_CTL2_REFL__OFF ((uint16_t)0x0000)
2512#define COMP_E_CTL2_REFL__1P2V ((uint16_t)0x2000)
2513#define COMP_E_CTL2_REFL__2P0V ((uint16_t)0x4000)
2514#define COMP_E_CTL2_REFL__2P5V ((uint16_t)0x6000)
2515/* COMP_E_CTL2[REFACC] Bits */
2516#define COMP_E_CTL2_REFACC_OFS (15)
2517#define COMP_E_CTL2_REFACC ((uint16_t)0x8000)
2518/* COMP_E_CTL3[PD0] Bits */
2519#define COMP_E_CTL3_PD0_OFS ( 0)
2520#define COMP_E_CTL3_PD0 ((uint16_t)0x0001)
2521/* COMP_E_CTL3[PD1] Bits */
2522#define COMP_E_CTL3_PD1_OFS ( 1)
2523#define COMP_E_CTL3_PD1 ((uint16_t)0x0002)
2524/* COMP_E_CTL3[PD2] Bits */
2525#define COMP_E_CTL3_PD2_OFS ( 2)
2526#define COMP_E_CTL3_PD2 ((uint16_t)0x0004)
2527/* COMP_E_CTL3[PD3] Bits */
2528#define COMP_E_CTL3_PD3_OFS ( 3)
2529#define COMP_E_CTL3_PD3 ((uint16_t)0x0008)
2530/* COMP_E_CTL3[PD4] Bits */
2531#define COMP_E_CTL3_PD4_OFS ( 4)
2532#define COMP_E_CTL3_PD4 ((uint16_t)0x0010)
2533/* COMP_E_CTL3[PD5] Bits */
2534#define COMP_E_CTL3_PD5_OFS ( 5)
2535#define COMP_E_CTL3_PD5 ((uint16_t)0x0020)
2536/* COMP_E_CTL3[PD6] Bits */
2537#define COMP_E_CTL3_PD6_OFS ( 6)
2538#define COMP_E_CTL3_PD6 ((uint16_t)0x0040)
2539/* COMP_E_CTL3[PD7] Bits */
2540#define COMP_E_CTL3_PD7_OFS ( 7)
2541#define COMP_E_CTL3_PD7 ((uint16_t)0x0080)
2542/* COMP_E_CTL3[PD8] Bits */
2543#define COMP_E_CTL3_PD8_OFS ( 8)
2544#define COMP_E_CTL3_PD8 ((uint16_t)0x0100)
2545/* COMP_E_CTL3[PD9] Bits */
2546#define COMP_E_CTL3_PD9_OFS ( 9)
2547#define COMP_E_CTL3_PD9 ((uint16_t)0x0200)
2548/* COMP_E_CTL3[PD10] Bits */
2549#define COMP_E_CTL3_PD10_OFS (10)
2550#define COMP_E_CTL3_PD10 ((uint16_t)0x0400)
2551/* COMP_E_CTL3[PD11] Bits */
2552#define COMP_E_CTL3_PD11_OFS (11)
2553#define COMP_E_CTL3_PD11 ((uint16_t)0x0800)
2554/* COMP_E_CTL3[PD12] Bits */
2555#define COMP_E_CTL3_PD12_OFS (12)
2556#define COMP_E_CTL3_PD12 ((uint16_t)0x1000)
2557/* COMP_E_CTL3[PD13] Bits */
2558#define COMP_E_CTL3_PD13_OFS (13)
2559#define COMP_E_CTL3_PD13 ((uint16_t)0x2000)
2560/* COMP_E_CTL3[PD14] Bits */
2561#define COMP_E_CTL3_PD14_OFS (14)
2562#define COMP_E_CTL3_PD14 ((uint16_t)0x4000)
2563/* COMP_E_CTL3[PD15] Bits */
2564#define COMP_E_CTL3_PD15_OFS (15)
2565#define COMP_E_CTL3_PD15 ((uint16_t)0x8000)
2566/* COMP_E_INT[IFG] Bits */
2567#define COMP_E_INT_IFG_OFS ( 0)
2568#define COMP_E_INT_IFG ((uint16_t)0x0001)
2569/* COMP_E_INT[IIFG] Bits */
2570#define COMP_E_INT_IIFG_OFS ( 1)
2571#define COMP_E_INT_IIFG ((uint16_t)0x0002)
2572/* COMP_E_INT[RDYIFG] Bits */
2573#define COMP_E_INT_RDYIFG_OFS ( 4)
2574#define COMP_E_INT_RDYIFG ((uint16_t)0x0010)
2575/* COMP_E_INT[IE] Bits */
2576#define COMP_E_INT_IE_OFS ( 8)
2577#define COMP_E_INT_IE ((uint16_t)0x0100)
2578/* COMP_E_INT[IIE] Bits */
2579#define COMP_E_INT_IIE_OFS ( 9)
2580#define COMP_E_INT_IIE ((uint16_t)0x0200)
2581/* COMP_E_INT[RDYIE] Bits */
2582#define COMP_E_INT_RDYIE_OFS (12)
2583#define COMP_E_INT_RDYIE ((uint16_t)0x1000)
2585/******************************************************************************
2586* COREDEBUG Bits
2587******************************************************************************/
2588
2589
2590/******************************************************************************
2591* CRC32 Bits
2592******************************************************************************/
2593
2594/******************************************************************************
2595* CS Bits
2596******************************************************************************/
2597/* CS_KEY[KEY] Bits */
2598#define CS_KEY_KEY_OFS ( 0)
2599#define CS_KEY_KEY_MASK ((uint32_t)0x0000FFFF)
2600/* CS_CTL0[DCOTUNE] Bits */
2601#define CS_CTL0_DCOTUNE_OFS ( 0)
2602#define CS_CTL0_DCOTUNE_MASK ((uint32_t)0x000003FF)
2603/* CS_CTL0[DCORSEL] Bits */
2604#define CS_CTL0_DCORSEL_OFS (16)
2605#define CS_CTL0_DCORSEL_MASK ((uint32_t)0x00070000)
2606#define CS_CTL0_DCORSEL0 ((uint32_t)0x00010000)
2607#define CS_CTL0_DCORSEL1 ((uint32_t)0x00020000)
2608#define CS_CTL0_DCORSEL2 ((uint32_t)0x00040000)
2609#define CS_CTL0_DCORSEL_0 ((uint32_t)0x00000000)
2610#define CS_CTL0_DCORSEL_1 ((uint32_t)0x00010000)
2611#define CS_CTL0_DCORSEL_2 ((uint32_t)0x00020000)
2612#define CS_CTL0_DCORSEL_3 ((uint32_t)0x00030000)
2613#define CS_CTL0_DCORSEL_4 ((uint32_t)0x00040000)
2614#define CS_CTL0_DCORSEL_5 ((uint32_t)0x00050000)
2615/* CS_CTL0[DCORES] Bits */
2616#define CS_CTL0_DCORES_OFS (22)
2617#define CS_CTL0_DCORES ((uint32_t)0x00400000)
2618/* CS_CTL0[DCOEN] Bits */
2619#define CS_CTL0_DCOEN_OFS (23)
2620#define CS_CTL0_DCOEN ((uint32_t)0x00800000)
2621/* CS_CTL1[SELM] Bits */
2622#define CS_CTL1_SELM_OFS ( 0)
2623#define CS_CTL1_SELM_MASK ((uint32_t)0x00000007)
2624#define CS_CTL1_SELM0 ((uint32_t)0x00000001)
2625#define CS_CTL1_SELM1 ((uint32_t)0x00000002)
2626#define CS_CTL1_SELM2 ((uint32_t)0x00000004)
2627#define CS_CTL1_SELM_0 ((uint32_t)0x00000000)
2628#define CS_CTL1_SELM_1 ((uint32_t)0x00000001)
2629#define CS_CTL1_SELM_2 ((uint32_t)0x00000002)
2630#define CS_CTL1_SELM_3 ((uint32_t)0x00000003)
2631#define CS_CTL1_SELM_4 ((uint32_t)0x00000004)
2632#define CS_CTL1_SELM_5 ((uint32_t)0x00000005)
2633#define CS_CTL1_SELM_6 ((uint32_t)0x00000006)
2634#define CS_CTL1_SELM__LFXTCLK ((uint32_t)0x00000000)
2635#define CS_CTL1_SELM__VLOCLK ((uint32_t)0x00000001)
2636#define CS_CTL1_SELM__REFOCLK ((uint32_t)0x00000002)
2637#define CS_CTL1_SELM__DCOCLK ((uint32_t)0x00000003)
2638#define CS_CTL1_SELM__MODOSC ((uint32_t)0x00000004)
2639#define CS_CTL1_SELM__HFXTCLK ((uint32_t)0x00000005)
2640#define CS_CTL1_SELM__HFXT2CLK ((uint32_t)0x00000006)
2641/* CS_CTL1[SELS] Bits */
2642#define CS_CTL1_SELS_OFS ( 4)
2643#define CS_CTL1_SELS_MASK ((uint32_t)0x00000070)
2644#define CS_CTL1_SELS0 ((uint32_t)0x00000010)
2645#define CS_CTL1_SELS1 ((uint32_t)0x00000020)
2646#define CS_CTL1_SELS2 ((uint32_t)0x00000040)
2647#define CS_CTL1_SELS_0 ((uint32_t)0x00000000)
2648#define CS_CTL1_SELS_1 ((uint32_t)0x00000010)
2649#define CS_CTL1_SELS_2 ((uint32_t)0x00000020)
2650#define CS_CTL1_SELS_3 ((uint32_t)0x00000030)
2651#define CS_CTL1_SELS_4 ((uint32_t)0x00000040)
2652#define CS_CTL1_SELS_5 ((uint32_t)0x00000050)
2653#define CS_CTL1_SELS_6 ((uint32_t)0x00000060)
2654#define CS_CTL1_SELS__LFXTCLK ((uint32_t)0x00000000)
2655#define CS_CTL1_SELS__VLOCLK ((uint32_t)0x00000010)
2656#define CS_CTL1_SELS__REFOCLK ((uint32_t)0x00000020)
2657#define CS_CTL1_SELS__DCOCLK ((uint32_t)0x00000030)
2658#define CS_CTL1_SELS__MODOSC ((uint32_t)0x00000040)
2659#define CS_CTL1_SELS__HFXTCLK ((uint32_t)0x00000050)
2660#define CS_CTL1_SELS__HFXT2CLK ((uint32_t)0x00000060)
2661/* CS_CTL1[SELA] Bits */
2662#define CS_CTL1_SELA_OFS ( 8)
2663#define CS_CTL1_SELA_MASK ((uint32_t)0x00000700)
2664#define CS_CTL1_SELA0 ((uint32_t)0x00000100)
2665#define CS_CTL1_SELA1 ((uint32_t)0x00000200)
2666#define CS_CTL1_SELA2 ((uint32_t)0x00000400)
2667#define CS_CTL1_SELA_0 ((uint32_t)0x00000000)
2668#define CS_CTL1_SELA_1 ((uint32_t)0x00000100)
2669#define CS_CTL1_SELA_2 ((uint32_t)0x00000200)
2670#define CS_CTL1_SELA__LFXTCLK ((uint32_t)0x00000000)
2671#define CS_CTL1_SELA__VLOCLK ((uint32_t)0x00000100)
2672#define CS_CTL1_SELA__REFOCLK ((uint32_t)0x00000200)
2673/* CS_CTL1[SELB] Bits */
2674#define CS_CTL1_SELB_OFS (12)
2675#define CS_CTL1_SELB ((uint32_t)0x00001000)
2676/* CS_CTL1[DIVM] Bits */
2677#define CS_CTL1_DIVM_OFS (16)
2678#define CS_CTL1_DIVM_MASK ((uint32_t)0x00070000)
2679#define CS_CTL1_DIVM0 ((uint32_t)0x00010000)
2680#define CS_CTL1_DIVM1 ((uint32_t)0x00020000)
2681#define CS_CTL1_DIVM2 ((uint32_t)0x00040000)
2682#define CS_CTL1_DIVM_0 ((uint32_t)0x00000000)
2683#define CS_CTL1_DIVM_1 ((uint32_t)0x00010000)
2684#define CS_CTL1_DIVM_2 ((uint32_t)0x00020000)
2685#define CS_CTL1_DIVM_3 ((uint32_t)0x00030000)
2686#define CS_CTL1_DIVM_4 ((uint32_t)0x00040000)
2687#define CS_CTL1_DIVM_5 ((uint32_t)0x00050000)
2688#define CS_CTL1_DIVM_6 ((uint32_t)0x00060000)
2689#define CS_CTL1_DIVM_7 ((uint32_t)0x00070000)
2690#define CS_CTL1_DIVM__1 ((uint32_t)0x00000000)
2691#define CS_CTL1_DIVM__2 ((uint32_t)0x00010000)
2692#define CS_CTL1_DIVM__4 ((uint32_t)0x00020000)
2693#define CS_CTL1_DIVM__8 ((uint32_t)0x00030000)
2694#define CS_CTL1_DIVM__16 ((uint32_t)0x00040000)
2695#define CS_CTL1_DIVM__32 ((uint32_t)0x00050000)
2696#define CS_CTL1_DIVM__64 ((uint32_t)0x00060000)
2697#define CS_CTL1_DIVM__128 ((uint32_t)0x00070000)
2698/* CS_CTL1[DIVHS] Bits */
2699#define CS_CTL1_DIVHS_OFS (20)
2700#define CS_CTL1_DIVHS_MASK ((uint32_t)0x00700000)
2701#define CS_CTL1_DIVHS0 ((uint32_t)0x00100000)
2702#define CS_CTL1_DIVHS1 ((uint32_t)0x00200000)
2703#define CS_CTL1_DIVHS2 ((uint32_t)0x00400000)
2704#define CS_CTL1_DIVHS_0 ((uint32_t)0x00000000)
2705#define CS_CTL1_DIVHS_1 ((uint32_t)0x00100000)
2706#define CS_CTL1_DIVHS_2 ((uint32_t)0x00200000)
2707#define CS_CTL1_DIVHS_3 ((uint32_t)0x00300000)
2708#define CS_CTL1_DIVHS_4 ((uint32_t)0x00400000)
2709#define CS_CTL1_DIVHS_5 ((uint32_t)0x00500000)
2710#define CS_CTL1_DIVHS_6 ((uint32_t)0x00600000)
2711#define CS_CTL1_DIVHS_7 ((uint32_t)0x00700000)
2712#define CS_CTL1_DIVHS__1 ((uint32_t)0x00000000)
2713#define CS_CTL1_DIVHS__2 ((uint32_t)0x00100000)
2714#define CS_CTL1_DIVHS__4 ((uint32_t)0x00200000)
2715#define CS_CTL1_DIVHS__8 ((uint32_t)0x00300000)
2716#define CS_CTL1_DIVHS__16 ((uint32_t)0x00400000)
2717#define CS_CTL1_DIVHS__32 ((uint32_t)0x00500000)
2718#define CS_CTL1_DIVHS__64 ((uint32_t)0x00600000)
2719#define CS_CTL1_DIVHS__128 ((uint32_t)0x00700000)
2720/* CS_CTL1[DIVA] Bits */
2721#define CS_CTL1_DIVA_OFS (24)
2722#define CS_CTL1_DIVA_MASK ((uint32_t)0x07000000)
2723#define CS_CTL1_DIVA0 ((uint32_t)0x01000000)
2724#define CS_CTL1_DIVA1 ((uint32_t)0x02000000)
2725#define CS_CTL1_DIVA2 ((uint32_t)0x04000000)
2726#define CS_CTL1_DIVA_0 ((uint32_t)0x00000000)
2727#define CS_CTL1_DIVA_1 ((uint32_t)0x01000000)
2728#define CS_CTL1_DIVA_2 ((uint32_t)0x02000000)
2729#define CS_CTL1_DIVA_3 ((uint32_t)0x03000000)
2730#define CS_CTL1_DIVA_4 ((uint32_t)0x04000000)
2731#define CS_CTL1_DIVA_5 ((uint32_t)0x05000000)
2732#define CS_CTL1_DIVA_6 ((uint32_t)0x06000000)
2733#define CS_CTL1_DIVA_7 ((uint32_t)0x07000000)
2734#define CS_CTL1_DIVA__1 ((uint32_t)0x00000000)
2735#define CS_CTL1_DIVA__2 ((uint32_t)0x01000000)
2736#define CS_CTL1_DIVA__4 ((uint32_t)0x02000000)
2737#define CS_CTL1_DIVA__8 ((uint32_t)0x03000000)
2738#define CS_CTL1_DIVA__16 ((uint32_t)0x04000000)
2739#define CS_CTL1_DIVA__32 ((uint32_t)0x05000000)
2740#define CS_CTL1_DIVA__64 ((uint32_t)0x06000000)
2741#define CS_CTL1_DIVA__128 ((uint32_t)0x07000000)
2742/* CS_CTL1[DIVS] Bits */
2743#define CS_CTL1_DIVS_OFS (28)
2744#define CS_CTL1_DIVS_MASK ((uint32_t)0x70000000)
2745#define CS_CTL1_DIVS0 ((uint32_t)0x10000000)
2746#define CS_CTL1_DIVS1 ((uint32_t)0x20000000)
2747#define CS_CTL1_DIVS2 ((uint32_t)0x40000000)
2748#define CS_CTL1_DIVS_0 ((uint32_t)0x00000000)
2749#define CS_CTL1_DIVS_1 ((uint32_t)0x10000000)
2750#define CS_CTL1_DIVS_2 ((uint32_t)0x20000000)
2751#define CS_CTL1_DIVS_3 ((uint32_t)0x30000000)
2752#define CS_CTL1_DIVS_4 ((uint32_t)0x40000000)
2753#define CS_CTL1_DIVS_5 ((uint32_t)0x50000000)
2754#define CS_CTL1_DIVS_6 ((uint32_t)0x60000000)
2755#define CS_CTL1_DIVS_7 ((uint32_t)0x70000000)
2756#define CS_CTL1_DIVS__1 ((uint32_t)0x00000000)
2757#define CS_CTL1_DIVS__2 ((uint32_t)0x10000000)
2758#define CS_CTL1_DIVS__4 ((uint32_t)0x20000000)
2759#define CS_CTL1_DIVS__8 ((uint32_t)0x30000000)
2760#define CS_CTL1_DIVS__16 ((uint32_t)0x40000000)
2761#define CS_CTL1_DIVS__32 ((uint32_t)0x50000000)
2762#define CS_CTL1_DIVS__64 ((uint32_t)0x60000000)
2763#define CS_CTL1_DIVS__128 ((uint32_t)0x70000000)
2764/* CS_CTL2[LFXTDRIVE] Bits */
2765#define CS_CTL2_LFXTDRIVE_OFS ( 0)
2766#define CS_CTL2_LFXTDRIVE_MASK ((uint32_t)0x00000003)
2767#define CS_CTL2_LFXTDRIVE0 ((uint32_t)0x00000001)
2768#define CS_CTL2_LFXTDRIVE1 ((uint32_t)0x00000002)
2769#define CS_CTL2_LFXTDRIVE_0 ((uint32_t)0x00000000)
2770#define CS_CTL2_LFXTDRIVE_1 ((uint32_t)0x00000001)
2771#define CS_CTL2_LFXTDRIVE_2 ((uint32_t)0x00000002)
2772#define CS_CTL2_LFXTDRIVE_3 ((uint32_t)0x00000003)
2773/* CS_CTL2[LFXT_EN] Bits */
2774#define CS_CTL2_LFXT_EN_OFS ( 8)
2775#define CS_CTL2_LFXT_EN ((uint32_t)0x00000100)
2776/* CS_CTL2[LFXTBYPASS] Bits */
2777#define CS_CTL2_LFXTBYPASS_OFS ( 9)
2778#define CS_CTL2_LFXTBYPASS ((uint32_t)0x00000200)
2779/* CS_CTL2[HFXTDRIVE] Bits */
2780#define CS_CTL2_HFXTDRIVE_OFS (16)
2781#define CS_CTL2_HFXTDRIVE ((uint32_t)0x00010000)
2782/* CS_CTL2[HFXTFREQ] Bits */
2783#define CS_CTL2_HFXTFREQ_OFS (20)
2784#define CS_CTL2_HFXTFREQ_MASK ((uint32_t)0x00700000)
2785#define CS_CTL2_HFXTFREQ0 ((uint32_t)0x00100000)
2786#define CS_CTL2_HFXTFREQ1 ((uint32_t)0x00200000)
2787#define CS_CTL2_HFXTFREQ2 ((uint32_t)0x00400000)
2788#define CS_CTL2_HFXTFREQ_0 ((uint32_t)0x00000000)
2789#define CS_CTL2_HFXTFREQ_1 ((uint32_t)0x00100000)
2790#define CS_CTL2_HFXTFREQ_2 ((uint32_t)0x00200000)
2791#define CS_CTL2_HFXTFREQ_3 ((uint32_t)0x00300000)
2792#define CS_CTL2_HFXTFREQ_4 ((uint32_t)0x00400000)
2793#define CS_CTL2_HFXTFREQ_5 ((uint32_t)0x00500000)
2794#define CS_CTL2_HFXTFREQ_6 ((uint32_t)0x00600000)
2795#define CS_CTL2_HFXTFREQ_7 ((uint32_t)0x00700000)
2796/* CS_CTL2[HFXT_EN] Bits */
2797#define CS_CTL2_HFXT_EN_OFS (24)
2798#define CS_CTL2_HFXT_EN ((uint32_t)0x01000000)
2799/* CS_CTL2[HFXTBYPASS] Bits */
2800#define CS_CTL2_HFXTBYPASS_OFS (25)
2801#define CS_CTL2_HFXTBYPASS ((uint32_t)0x02000000)
2802/* CS_CTL3[FCNTLF] Bits */
2803#define CS_CTL3_FCNTLF_OFS ( 0)
2804#define CS_CTL3_FCNTLF_MASK ((uint32_t)0x00000003)
2805#define CS_CTL3_FCNTLF0 ((uint32_t)0x00000001)
2806#define CS_CTL3_FCNTLF1 ((uint32_t)0x00000002)
2807#define CS_CTL3_FCNTLF_0 ((uint32_t)0x00000000)
2808#define CS_CTL3_FCNTLF_1 ((uint32_t)0x00000001)
2809#define CS_CTL3_FCNTLF_2 ((uint32_t)0x00000002)
2810#define CS_CTL3_FCNTLF_3 ((uint32_t)0x00000003)
2811#define CS_CTL3_FCNTLF__4096 ((uint32_t)0x00000000)
2812#define CS_CTL3_FCNTLF__8192 ((uint32_t)0x00000001)
2813#define CS_CTL3_FCNTLF__16384 ((uint32_t)0x00000002)
2814#define CS_CTL3_FCNTLF__32768 ((uint32_t)0x00000003)
2815/* CS_CTL3[RFCNTLF] Bits */
2816#define CS_CTL3_RFCNTLF_OFS ( 2)
2817#define CS_CTL3_RFCNTLF ((uint32_t)0x00000004)
2818/* CS_CTL3[FCNTLF_EN] Bits */
2819#define CS_CTL3_FCNTLF_EN_OFS ( 3)
2820#define CS_CTL3_FCNTLF_EN ((uint32_t)0x00000008)
2821/* CS_CTL3[FCNTHF] Bits */
2822#define CS_CTL3_FCNTHF_OFS ( 4)
2823#define CS_CTL3_FCNTHF_MASK ((uint32_t)0x00000030)
2824#define CS_CTL3_FCNTHF0 ((uint32_t)0x00000010)
2825#define CS_CTL3_FCNTHF1 ((uint32_t)0x00000020)
2826#define CS_CTL3_FCNTHF_0 ((uint32_t)0x00000000)
2827#define CS_CTL3_FCNTHF_1 ((uint32_t)0x00000010)
2828#define CS_CTL3_FCNTHF_2 ((uint32_t)0x00000020)
2829#define CS_CTL3_FCNTHF_3 ((uint32_t)0x00000030)
2830#define CS_CTL3_FCNTHF__2048 ((uint32_t)0x00000000)
2831#define CS_CTL3_FCNTHF__4096 ((uint32_t)0x00000010)
2832#define CS_CTL3_FCNTHF__8192 ((uint32_t)0x00000020)
2833#define CS_CTL3_FCNTHF__16384 ((uint32_t)0x00000030)
2834/* CS_CTL3[RFCNTHF] Bits */
2835#define CS_CTL3_RFCNTHF_OFS ( 6)
2836#define CS_CTL3_RFCNTHF ((uint32_t)0x00000040)
2837/* CS_CTL3[FCNTHF_EN] Bits */
2838#define CS_CTL3_FCNTHF_EN_OFS ( 7)
2839#define CS_CTL3_FCNTHF_EN ((uint32_t)0x00000080)
2840/* CS_CLKEN[ACLK_EN] Bits */
2841#define CS_CLKEN_ACLK_EN_OFS ( 0)
2842#define CS_CLKEN_ACLK_EN ((uint32_t)0x00000001)
2843/* CS_CLKEN[MCLK_EN] Bits */
2844#define CS_CLKEN_MCLK_EN_OFS ( 1)
2845#define CS_CLKEN_MCLK_EN ((uint32_t)0x00000002)
2846/* CS_CLKEN[HSMCLK_EN] Bits */
2847#define CS_CLKEN_HSMCLK_EN_OFS ( 2)
2848#define CS_CLKEN_HSMCLK_EN ((uint32_t)0x00000004)
2849/* CS_CLKEN[SMCLK_EN] Bits */
2850#define CS_CLKEN_SMCLK_EN_OFS ( 3)
2851#define CS_CLKEN_SMCLK_EN ((uint32_t)0x00000008)
2852/* CS_CLKEN[VLO_EN] Bits */
2853#define CS_CLKEN_VLO_EN_OFS ( 8)
2854#define CS_CLKEN_VLO_EN ((uint32_t)0x00000100)
2855/* CS_CLKEN[REFO_EN] Bits */
2856#define CS_CLKEN_REFO_EN_OFS ( 9)
2857#define CS_CLKEN_REFO_EN ((uint32_t)0x00000200)
2858/* CS_CLKEN[MODOSC_EN] Bits */
2859#define CS_CLKEN_MODOSC_EN_OFS (10)
2860#define CS_CLKEN_MODOSC_EN ((uint32_t)0x00000400)
2861/* CS_CLKEN[REFOFSEL] Bits */
2862#define CS_CLKEN_REFOFSEL_OFS (15)
2863#define CS_CLKEN_REFOFSEL ((uint32_t)0x00008000)
2864/* CS_STAT[DCO_ON] Bits */
2865#define CS_STAT_DCO_ON_OFS ( 0)
2866#define CS_STAT_DCO_ON ((uint32_t)0x00000001)
2867/* CS_STAT[DCOBIAS_ON] Bits */
2868#define CS_STAT_DCOBIAS_ON_OFS ( 1)
2869#define CS_STAT_DCOBIAS_ON ((uint32_t)0x00000002)
2870/* CS_STAT[HFXT_ON] Bits */
2871#define CS_STAT_HFXT_ON_OFS ( 2)
2872#define CS_STAT_HFXT_ON ((uint32_t)0x00000004)
2873/* CS_STAT[MODOSC_ON] Bits */
2874#define CS_STAT_MODOSC_ON_OFS ( 4)
2875#define CS_STAT_MODOSC_ON ((uint32_t)0x00000010)
2876/* CS_STAT[VLO_ON] Bits */
2877#define CS_STAT_VLO_ON_OFS ( 5)
2878#define CS_STAT_VLO_ON ((uint32_t)0x00000020)
2879/* CS_STAT[LFXT_ON] Bits */
2880#define CS_STAT_LFXT_ON_OFS ( 6)
2881#define CS_STAT_LFXT_ON ((uint32_t)0x00000040)
2882/* CS_STAT[REFO_ON] Bits */
2883#define CS_STAT_REFO_ON_OFS ( 7)
2884#define CS_STAT_REFO_ON ((uint32_t)0x00000080)
2885/* CS_STAT[ACLK_ON] Bits */
2886#define CS_STAT_ACLK_ON_OFS (16)
2887#define CS_STAT_ACLK_ON ((uint32_t)0x00010000)
2888/* CS_STAT[MCLK_ON] Bits */
2889#define CS_STAT_MCLK_ON_OFS (17)
2890#define CS_STAT_MCLK_ON ((uint32_t)0x00020000)
2891/* CS_STAT[HSMCLK_ON] Bits */
2892#define CS_STAT_HSMCLK_ON_OFS (18)
2893#define CS_STAT_HSMCLK_ON ((uint32_t)0x00040000)
2894/* CS_STAT[SMCLK_ON] Bits */
2895#define CS_STAT_SMCLK_ON_OFS (19)
2896#define CS_STAT_SMCLK_ON ((uint32_t)0x00080000)
2897/* CS_STAT[MODCLK_ON] Bits */
2898#define CS_STAT_MODCLK_ON_OFS (20)
2899#define CS_STAT_MODCLK_ON ((uint32_t)0x00100000)
2900/* CS_STAT[VLOCLK_ON] Bits */
2901#define CS_STAT_VLOCLK_ON_OFS (21)
2902#define CS_STAT_VLOCLK_ON ((uint32_t)0x00200000)
2903/* CS_STAT[LFXTCLK_ON] Bits */
2904#define CS_STAT_LFXTCLK_ON_OFS (22)
2905#define CS_STAT_LFXTCLK_ON ((uint32_t)0x00400000)
2906/* CS_STAT[REFOCLK_ON] Bits */
2907#define CS_STAT_REFOCLK_ON_OFS (23)
2908#define CS_STAT_REFOCLK_ON ((uint32_t)0x00800000)
2909/* CS_STAT[ACLK_READY] Bits */
2910#define CS_STAT_ACLK_READY_OFS (24)
2911#define CS_STAT_ACLK_READY ((uint32_t)0x01000000)
2912/* CS_STAT[MCLK_READY] Bits */
2913#define CS_STAT_MCLK_READY_OFS (25)
2914#define CS_STAT_MCLK_READY ((uint32_t)0x02000000)
2915/* CS_STAT[HSMCLK_READY] Bits */
2916#define CS_STAT_HSMCLK_READY_OFS (26)
2917#define CS_STAT_HSMCLK_READY ((uint32_t)0x04000000)
2918/* CS_STAT[SMCLK_READY] Bits */
2919#define CS_STAT_SMCLK_READY_OFS (27)
2920#define CS_STAT_SMCLK_READY ((uint32_t)0x08000000)
2921/* CS_STAT[BCLK_READY] Bits */
2922#define CS_STAT_BCLK_READY_OFS (28)
2923#define CS_STAT_BCLK_READY ((uint32_t)0x10000000)
2924/* CS_IE[LFXTIE] Bits */
2925#define CS_IE_LFXTIE_OFS ( 0)
2926#define CS_IE_LFXTIE ((uint32_t)0x00000001)
2927/* CS_IE[HFXTIE] Bits */
2928#define CS_IE_HFXTIE_OFS ( 1)
2929#define CS_IE_HFXTIE ((uint32_t)0x00000002)
2930/* CS_IE[DCOR_OPNIE] Bits */
2931#define CS_IE_DCOR_OPNIE_OFS ( 6)
2932#define CS_IE_DCOR_OPNIE ((uint32_t)0x00000040)
2933/* CS_IE[FCNTLFIE] Bits */
2934#define CS_IE_FCNTLFIE_OFS ( 8)
2935#define CS_IE_FCNTLFIE ((uint32_t)0x00000100)
2936/* CS_IE[FCNTHFIE] Bits */
2937#define CS_IE_FCNTHFIE_OFS ( 9)
2938#define CS_IE_FCNTHFIE ((uint32_t)0x00000200)
2939/* CS_IFG[LFXTIFG] Bits */
2940#define CS_IFG_LFXTIFG_OFS ( 0)
2941#define CS_IFG_LFXTIFG ((uint32_t)0x00000001)
2942/* CS_IFG[HFXTIFG] Bits */
2943#define CS_IFG_HFXTIFG_OFS ( 1)
2944#define CS_IFG_HFXTIFG ((uint32_t)0x00000002)
2945/* CS_IFG[DCOR_SHTIFG] Bits */
2946#define CS_IFG_DCOR_SHTIFG_OFS ( 5)
2947#define CS_IFG_DCOR_SHTIFG ((uint32_t)0x00000020)
2948/* CS_IFG[DCOR_OPNIFG] Bits */
2949#define CS_IFG_DCOR_OPNIFG_OFS ( 6)
2950#define CS_IFG_DCOR_OPNIFG ((uint32_t)0x00000040)
2951/* CS_IFG[FCNTLFIFG] Bits */
2952#define CS_IFG_FCNTLFIFG_OFS ( 8)
2953#define CS_IFG_FCNTLFIFG ((uint32_t)0x00000100)
2954/* CS_IFG[FCNTHFIFG] Bits */
2955#define CS_IFG_FCNTHFIFG_OFS ( 9)
2956#define CS_IFG_FCNTHFIFG ((uint32_t)0x00000200)
2957/* CS_CLRIFG[CLR_LFXTIFG] Bits */
2958#define CS_CLRIFG_CLR_LFXTIFG_OFS ( 0)
2959#define CS_CLRIFG_CLR_LFXTIFG ((uint32_t)0x00000001)
2960/* CS_CLRIFG[CLR_HFXTIFG] Bits */
2961#define CS_CLRIFG_CLR_HFXTIFG_OFS ( 1)
2962#define CS_CLRIFG_CLR_HFXTIFG ((uint32_t)0x00000002)
2963/* CS_CLRIFG[CLR_DCOR_OPNIFG] Bits */
2964#define CS_CLRIFG_CLR_DCOR_OPNIFG_OFS ( 6)
2965#define CS_CLRIFG_CLR_DCOR_OPNIFG ((uint32_t)0x00000040)
2966/* CS_CLRIFG[CLR_FCNTLFIFG] Bits */
2967#define CS_CLRIFG_CLR_FCNTLFIFG_OFS ( 8)
2968#define CS_CLRIFG_CLR_FCNTLFIFG ((uint32_t)0x00000100)
2969/* CS_CLRIFG[CLR_FCNTHFIFG] Bits */
2970#define CS_CLRIFG_CLR_FCNTHFIFG_OFS ( 9)
2971#define CS_CLRIFG_CLR_FCNTHFIFG ((uint32_t)0x00000200)
2972/* CS_SETIFG[SET_LFXTIFG] Bits */
2973#define CS_SETIFG_SET_LFXTIFG_OFS ( 0)
2974#define CS_SETIFG_SET_LFXTIFG ((uint32_t)0x00000001)
2975/* CS_SETIFG[SET_HFXTIFG] Bits */
2976#define CS_SETIFG_SET_HFXTIFG_OFS ( 1)
2977#define CS_SETIFG_SET_HFXTIFG ((uint32_t)0x00000002)
2978/* CS_SETIFG[SET_DCOR_OPNIFG] Bits */
2979#define CS_SETIFG_SET_DCOR_OPNIFG_OFS ( 6)
2980#define CS_SETIFG_SET_DCOR_OPNIFG ((uint32_t)0x00000040)
2981/* CS_SETIFG[SET_FCNTHFIFG] Bits */
2982#define CS_SETIFG_SET_FCNTHFIFG_OFS ( 9)
2983#define CS_SETIFG_SET_FCNTHFIFG ((uint32_t)0x00000200)
2984/* CS_SETIFG[SET_FCNTLFIFG] Bits */
2985#define CS_SETIFG_SET_FCNTLFIFG_OFS ( 8)
2986#define CS_SETIFG_SET_FCNTLFIFG ((uint32_t)0x00000100)
2987/* CS_DCOERCAL0[DCO_TCCAL] Bits */
2988#define CS_DCOERCAL0_DCO_TCCAL_OFS ( 0)
2989#define CS_DCOERCAL0_DCO_TCCAL_MASK ((uint32_t)0x00000003)
2990/* CS_DCOERCAL0[DCO_FCAL_RSEL04] Bits */
2991#define CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS (16)
2992#define CS_DCOERCAL0_DCO_FCAL_RSEL04_MASK ((uint32_t)0x03FF0000)
2993/* CS_DCOERCAL1[DCO_FCAL_RSEL5] Bits */
2994#define CS_DCOERCAL1_DCO_FCAL_RSEL5_OFS ( 0)
2995#define CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK ((uint32_t)0x000003FF)
2996/* Pre-defined bitfield values */
2997#define CS_KEY_VAL ((uint32_t)0x0000695A)
2999/******************************************************************************
3000* DIO Bits
3001******************************************************************************/
3002/* DIO_IV[IV] Bits */
3003#define DIO_PORT_IV_OFS ( 0)
3004#define DIO_PORT_IV_MASK ((uint16_t)0x001F)
3005#define DIO_PORT_IV0 ((uint16_t)0x0001)
3006#define DIO_PORT_IV1 ((uint16_t)0x0002)
3007#define DIO_PORT_IV2 ((uint16_t)0x0004)
3008#define DIO_PORT_IV3 ((uint16_t)0x0008)
3009#define DIO_PORT_IV4 ((uint16_t)0x0010)
3010#define DIO_PORT_IV_0 ((uint16_t)0x0000)
3011#define DIO_PORT_IV_2 ((uint16_t)0x0002)
3012 /* Priority: Highest */
3013#define DIO_PORT_IV_4 ((uint16_t)0x0004)
3014#define DIO_PORT_IV_6 ((uint16_t)0x0006)
3015#define DIO_PORT_IV_8 ((uint16_t)0x0008)
3016#define DIO_PORT_IV_10 ((uint16_t)0x000A)
3017#define DIO_PORT_IV_12 ((uint16_t)0x000C)
3018#define DIO_PORT_IV_14 ((uint16_t)0x000E)
3019#define DIO_PORT_IV_16 ((uint16_t)0x0010)
3020 /* Priority: Lowest */
3021#define DIO_PORT_IV__NONE ((uint16_t)0x0000)
3022#define DIO_PORT_IV__IFG0 ((uint16_t)0x0002)
3023 /* Priority: Highest */
3024#define DIO_PORT_IV__IFG1 ((uint16_t)0x0004)
3025#define DIO_PORT_IV__IFG2 ((uint16_t)0x0006)
3026#define DIO_PORT_IV__IFG3 ((uint16_t)0x0008)
3027#define DIO_PORT_IV__IFG4 ((uint16_t)0x000A)
3028#define DIO_PORT_IV__IFG5 ((uint16_t)0x000C)
3029#define DIO_PORT_IV__IFG6 ((uint16_t)0x000E)
3030#define DIO_PORT_IV__IFG7 ((uint16_t)0x0010)
3031 /* Priority: Lowest */
3032
3033
3034/******************************************************************************
3035* DMA Bits
3036******************************************************************************/
3037/* DMA_DEVICE_CFG[NUM_DMA_CHANNELS] Bits */
3038#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_OFS ( 0)
3039#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_MASK ((uint32_t)0x000000FF)
3040/* DMA_DEVICE_CFG[NUM_SRC_PER_CHANNEL] Bits */
3041#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_OFS ( 8)
3042#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_MASK ((uint32_t)0x0000FF00)
3043/* DMA_SW_CHTRIG[CH0] Bits */
3044#define DMA_SW_CHTRIG_CH0_OFS ( 0)
3045#define DMA_SW_CHTRIG_CH0 ((uint32_t)0x00000001)
3046/* DMA_SW_CHTRIG[CH1] Bits */
3047#define DMA_SW_CHTRIG_CH1_OFS ( 1)
3048#define DMA_SW_CHTRIG_CH1 ((uint32_t)0x00000002)
3049/* DMA_SW_CHTRIG[CH2] Bits */
3050#define DMA_SW_CHTRIG_CH2_OFS ( 2)
3051#define DMA_SW_CHTRIG_CH2 ((uint32_t)0x00000004)
3052/* DMA_SW_CHTRIG[CH3] Bits */
3053#define DMA_SW_CHTRIG_CH3_OFS ( 3)
3054#define DMA_SW_CHTRIG_CH3 ((uint32_t)0x00000008)
3055/* DMA_SW_CHTRIG[CH4] Bits */
3056#define DMA_SW_CHTRIG_CH4_OFS ( 4)
3057#define DMA_SW_CHTRIG_CH4 ((uint32_t)0x00000010)
3058/* DMA_SW_CHTRIG[CH5] Bits */
3059#define DMA_SW_CHTRIG_CH5_OFS ( 5)
3060#define DMA_SW_CHTRIG_CH5 ((uint32_t)0x00000020)
3061/* DMA_SW_CHTRIG[CH6] Bits */
3062#define DMA_SW_CHTRIG_CH6_OFS ( 6)
3063#define DMA_SW_CHTRIG_CH6 ((uint32_t)0x00000040)
3064/* DMA_SW_CHTRIG[CH7] Bits */
3065#define DMA_SW_CHTRIG_CH7_OFS ( 7)
3066#define DMA_SW_CHTRIG_CH7 ((uint32_t)0x00000080)
3067/* DMA_SW_CHTRIG[CH8] Bits */
3068#define DMA_SW_CHTRIG_CH8_OFS ( 8)
3069#define DMA_SW_CHTRIG_CH8 ((uint32_t)0x00000100)
3070/* DMA_SW_CHTRIG[CH9] Bits */
3071#define DMA_SW_CHTRIG_CH9_OFS ( 9)
3072#define DMA_SW_CHTRIG_CH9 ((uint32_t)0x00000200)
3073/* DMA_SW_CHTRIG[CH10] Bits */
3074#define DMA_SW_CHTRIG_CH10_OFS (10)
3075#define DMA_SW_CHTRIG_CH10 ((uint32_t)0x00000400)
3076/* DMA_SW_CHTRIG[CH11] Bits */
3077#define DMA_SW_CHTRIG_CH11_OFS (11)
3078#define DMA_SW_CHTRIG_CH11 ((uint32_t)0x00000800)
3079/* DMA_SW_CHTRIG[CH12] Bits */
3080#define DMA_SW_CHTRIG_CH12_OFS (12)
3081#define DMA_SW_CHTRIG_CH12 ((uint32_t)0x00001000)
3082/* DMA_SW_CHTRIG[CH13] Bits */
3083#define DMA_SW_CHTRIG_CH13_OFS (13)
3084#define DMA_SW_CHTRIG_CH13 ((uint32_t)0x00002000)
3085/* DMA_SW_CHTRIG[CH14] Bits */
3086#define DMA_SW_CHTRIG_CH14_OFS (14)
3087#define DMA_SW_CHTRIG_CH14 ((uint32_t)0x00004000)
3088/* DMA_SW_CHTRIG[CH15] Bits */
3089#define DMA_SW_CHTRIG_CH15_OFS (15)
3090#define DMA_SW_CHTRIG_CH15 ((uint32_t)0x00008000)
3091/* DMA_SW_CHTRIG[CH16] Bits */
3092#define DMA_SW_CHTRIG_CH16_OFS (16)
3093#define DMA_SW_CHTRIG_CH16 ((uint32_t)0x00010000)
3094/* DMA_SW_CHTRIG[CH17] Bits */
3095#define DMA_SW_CHTRIG_CH17_OFS (17)
3096#define DMA_SW_CHTRIG_CH17 ((uint32_t)0x00020000)
3097/* DMA_SW_CHTRIG[CH18] Bits */
3098#define DMA_SW_CHTRIG_CH18_OFS (18)
3099#define DMA_SW_CHTRIG_CH18 ((uint32_t)0x00040000)
3100/* DMA_SW_CHTRIG[CH19] Bits */
3101#define DMA_SW_CHTRIG_CH19_OFS (19)
3102#define DMA_SW_CHTRIG_CH19 ((uint32_t)0x00080000)
3103/* DMA_SW_CHTRIG[CH20] Bits */
3104#define DMA_SW_CHTRIG_CH20_OFS (20)
3105#define DMA_SW_CHTRIG_CH20 ((uint32_t)0x00100000)
3106/* DMA_SW_CHTRIG[CH21] Bits */
3107#define DMA_SW_CHTRIG_CH21_OFS (21)
3108#define DMA_SW_CHTRIG_CH21 ((uint32_t)0x00200000)
3109/* DMA_SW_CHTRIG[CH22] Bits */
3110#define DMA_SW_CHTRIG_CH22_OFS (22)
3111#define DMA_SW_CHTRIG_CH22 ((uint32_t)0x00400000)
3112/* DMA_SW_CHTRIG[CH23] Bits */
3113#define DMA_SW_CHTRIG_CH23_OFS (23)
3114#define DMA_SW_CHTRIG_CH23 ((uint32_t)0x00800000)
3115/* DMA_SW_CHTRIG[CH24] Bits */
3116#define DMA_SW_CHTRIG_CH24_OFS (24)
3117#define DMA_SW_CHTRIG_CH24 ((uint32_t)0x01000000)
3118/* DMA_SW_CHTRIG[CH25] Bits */
3119#define DMA_SW_CHTRIG_CH25_OFS (25)
3120#define DMA_SW_CHTRIG_CH25 ((uint32_t)0x02000000)
3121/* DMA_SW_CHTRIG[CH26] Bits */
3122#define DMA_SW_CHTRIG_CH26_OFS (26)
3123#define DMA_SW_CHTRIG_CH26 ((uint32_t)0x04000000)
3124/* DMA_SW_CHTRIG[CH27] Bits */
3125#define DMA_SW_CHTRIG_CH27_OFS (27)
3126#define DMA_SW_CHTRIG_CH27 ((uint32_t)0x08000000)
3127/* DMA_SW_CHTRIG[CH28] Bits */
3128#define DMA_SW_CHTRIG_CH28_OFS (28)
3129#define DMA_SW_CHTRIG_CH28 ((uint32_t)0x10000000)
3130/* DMA_SW_CHTRIG[CH29] Bits */
3131#define DMA_SW_CHTRIG_CH29_OFS (29)
3132#define DMA_SW_CHTRIG_CH29 ((uint32_t)0x20000000)
3133/* DMA_SW_CHTRIG[CH30] Bits */
3134#define DMA_SW_CHTRIG_CH30_OFS (30)
3135#define DMA_SW_CHTRIG_CH30 ((uint32_t)0x40000000)
3136/* DMA_SW_CHTRIG[CH31] Bits */
3137#define DMA_SW_CHTRIG_CH31_OFS (31)
3138#define DMA_SW_CHTRIG_CH31 ((uint32_t)0x80000000)
3139/* DMA_CHN_SRCCFG[DMA_SRC] Bits */
3140#define DMA_CHN_SRCCFG_DMA_SRC_OFS ( 0)
3141#define DMA_CHN_SRCCFG_DMA_SRC_MASK ((uint32_t)0x000000FF)
3142/* DMA_INT1_SRCCFG[INT_SRC] Bits */
3143#define DMA_INT1_SRCCFG_INT_SRC_OFS ( 0)
3144#define DMA_INT1_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F)
3145/* DMA_INT1_SRCCFG[EN] Bits */
3146#define DMA_INT1_SRCCFG_EN_OFS ( 5)
3147#define DMA_INT1_SRCCFG_EN ((uint32_t)0x00000020)
3148/* DMA_INT2_SRCCFG[INT_SRC] Bits */
3149#define DMA_INT2_SRCCFG_INT_SRC_OFS ( 0)
3150#define DMA_INT2_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F)
3151/* DMA_INT2_SRCCFG[EN] Bits */
3152#define DMA_INT2_SRCCFG_EN_OFS ( 5)
3153#define DMA_INT2_SRCCFG_EN ((uint32_t)0x00000020)
3154/* DMA_INT3_SRCCFG[INT_SRC] Bits */
3155#define DMA_INT3_SRCCFG_INT_SRC_OFS ( 0)
3156#define DMA_INT3_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F)
3157/* DMA_INT3_SRCCFG[EN] Bits */
3158#define DMA_INT3_SRCCFG_EN_OFS ( 5)
3159#define DMA_INT3_SRCCFG_EN ((uint32_t)0x00000020)
3160/* DMA_INT0_SRCFLG[CH0] Bits */
3161#define DMA_INT0_SRCFLG_CH0_OFS ( 0)
3162#define DMA_INT0_SRCFLG_CH0 ((uint32_t)0x00000001)
3163/* DMA_INT0_SRCFLG[CH1] Bits */
3164#define DMA_INT0_SRCFLG_CH1_OFS ( 1)
3165#define DMA_INT0_SRCFLG_CH1 ((uint32_t)0x00000002)
3166/* DMA_INT0_SRCFLG[CH2] Bits */
3167#define DMA_INT0_SRCFLG_CH2_OFS ( 2)
3168#define DMA_INT0_SRCFLG_CH2 ((uint32_t)0x00000004)
3169/* DMA_INT0_SRCFLG[CH3] Bits */
3170#define DMA_INT0_SRCFLG_CH3_OFS ( 3)
3171#define DMA_INT0_SRCFLG_CH3 ((uint32_t)0x00000008)
3172/* DMA_INT0_SRCFLG[CH4] Bits */
3173#define DMA_INT0_SRCFLG_CH4_OFS ( 4)
3174#define DMA_INT0_SRCFLG_CH4 ((uint32_t)0x00000010)
3175/* DMA_INT0_SRCFLG[CH5] Bits */
3176#define DMA_INT0_SRCFLG_CH5_OFS ( 5)
3177#define DMA_INT0_SRCFLG_CH5 ((uint32_t)0x00000020)
3178/* DMA_INT0_SRCFLG[CH6] Bits */
3179#define DMA_INT0_SRCFLG_CH6_OFS ( 6)
3180#define DMA_INT0_SRCFLG_CH6 ((uint32_t)0x00000040)
3181/* DMA_INT0_SRCFLG[CH7] Bits */
3182#define DMA_INT0_SRCFLG_CH7_OFS ( 7)
3183#define DMA_INT0_SRCFLG_CH7 ((uint32_t)0x00000080)
3184/* DMA_INT0_SRCFLG[CH8] Bits */
3185#define DMA_INT0_SRCFLG_CH8_OFS ( 8)
3186#define DMA_INT0_SRCFLG_CH8 ((uint32_t)0x00000100)
3187/* DMA_INT0_SRCFLG[CH9] Bits */
3188#define DMA_INT0_SRCFLG_CH9_OFS ( 9)
3189#define DMA_INT0_SRCFLG_CH9 ((uint32_t)0x00000200)
3190/* DMA_INT0_SRCFLG[CH10] Bits */
3191#define DMA_INT0_SRCFLG_CH10_OFS (10)
3192#define DMA_INT0_SRCFLG_CH10 ((uint32_t)0x00000400)
3193/* DMA_INT0_SRCFLG[CH11] Bits */
3194#define DMA_INT0_SRCFLG_CH11_OFS (11)
3195#define DMA_INT0_SRCFLG_CH11 ((uint32_t)0x00000800)
3196/* DMA_INT0_SRCFLG[CH12] Bits */
3197#define DMA_INT0_SRCFLG_CH12_OFS (12)
3198#define DMA_INT0_SRCFLG_CH12 ((uint32_t)0x00001000)
3199/* DMA_INT0_SRCFLG[CH13] Bits */
3200#define DMA_INT0_SRCFLG_CH13_OFS (13)
3201#define DMA_INT0_SRCFLG_CH13 ((uint32_t)0x00002000)
3202/* DMA_INT0_SRCFLG[CH14] Bits */
3203#define DMA_INT0_SRCFLG_CH14_OFS (14)
3204#define DMA_INT0_SRCFLG_CH14 ((uint32_t)0x00004000)
3205/* DMA_INT0_SRCFLG[CH15] Bits */
3206#define DMA_INT0_SRCFLG_CH15_OFS (15)
3207#define DMA_INT0_SRCFLG_CH15 ((uint32_t)0x00008000)
3208/* DMA_INT0_SRCFLG[CH16] Bits */
3209#define DMA_INT0_SRCFLG_CH16_OFS (16)
3210#define DMA_INT0_SRCFLG_CH16 ((uint32_t)0x00010000)
3211/* DMA_INT0_SRCFLG[CH17] Bits */
3212#define DMA_INT0_SRCFLG_CH17_OFS (17)
3213#define DMA_INT0_SRCFLG_CH17 ((uint32_t)0x00020000)
3214/* DMA_INT0_SRCFLG[CH18] Bits */
3215#define DMA_INT0_SRCFLG_CH18_OFS (18)
3216#define DMA_INT0_SRCFLG_CH18 ((uint32_t)0x00040000)
3217/* DMA_INT0_SRCFLG[CH19] Bits */
3218#define DMA_INT0_SRCFLG_CH19_OFS (19)
3219#define DMA_INT0_SRCFLG_CH19 ((uint32_t)0x00080000)
3220/* DMA_INT0_SRCFLG[CH20] Bits */
3221#define DMA_INT0_SRCFLG_CH20_OFS (20)
3222#define DMA_INT0_SRCFLG_CH20 ((uint32_t)0x00100000)
3223/* DMA_INT0_SRCFLG[CH21] Bits */
3224#define DMA_INT0_SRCFLG_CH21_OFS (21)
3225#define DMA_INT0_SRCFLG_CH21 ((uint32_t)0x00200000)
3226/* DMA_INT0_SRCFLG[CH22] Bits */
3227#define DMA_INT0_SRCFLG_CH22_OFS (22)
3228#define DMA_INT0_SRCFLG_CH22 ((uint32_t)0x00400000)
3229/* DMA_INT0_SRCFLG[CH23] Bits */
3230#define DMA_INT0_SRCFLG_CH23_OFS (23)
3231#define DMA_INT0_SRCFLG_CH23 ((uint32_t)0x00800000)
3232/* DMA_INT0_SRCFLG[CH24] Bits */
3233#define DMA_INT0_SRCFLG_CH24_OFS (24)
3234#define DMA_INT0_SRCFLG_CH24 ((uint32_t)0x01000000)
3235/* DMA_INT0_SRCFLG[CH25] Bits */
3236#define DMA_INT0_SRCFLG_CH25_OFS (25)
3237#define DMA_INT0_SRCFLG_CH25 ((uint32_t)0x02000000)
3238/* DMA_INT0_SRCFLG[CH26] Bits */
3239#define DMA_INT0_SRCFLG_CH26_OFS (26)
3240#define DMA_INT0_SRCFLG_CH26 ((uint32_t)0x04000000)
3241/* DMA_INT0_SRCFLG[CH27] Bits */
3242#define DMA_INT0_SRCFLG_CH27_OFS (27)
3243#define DMA_INT0_SRCFLG_CH27 ((uint32_t)0x08000000)
3244/* DMA_INT0_SRCFLG[CH28] Bits */
3245#define DMA_INT0_SRCFLG_CH28_OFS (28)
3246#define DMA_INT0_SRCFLG_CH28 ((uint32_t)0x10000000)
3247/* DMA_INT0_SRCFLG[CH29] Bits */
3248#define DMA_INT0_SRCFLG_CH29_OFS (29)
3249#define DMA_INT0_SRCFLG_CH29 ((uint32_t)0x20000000)
3250/* DMA_INT0_SRCFLG[CH30] Bits */
3251#define DMA_INT0_SRCFLG_CH30_OFS (30)
3252#define DMA_INT0_SRCFLG_CH30 ((uint32_t)0x40000000)
3253/* DMA_INT0_SRCFLG[CH31] Bits */
3254#define DMA_INT0_SRCFLG_CH31_OFS (31)
3255#define DMA_INT0_SRCFLG_CH31 ((uint32_t)0x80000000)
3256/* DMA_INT0_CLRFLG[CH0] Bits */
3257#define DMA_INT0_CLRFLG_CH0_OFS ( 0)
3258#define DMA_INT0_CLRFLG_CH0 ((uint32_t)0x00000001)
3259/* DMA_INT0_CLRFLG[CH1] Bits */
3260#define DMA_INT0_CLRFLG_CH1_OFS ( 1)
3261#define DMA_INT0_CLRFLG_CH1 ((uint32_t)0x00000002)
3262/* DMA_INT0_CLRFLG[CH2] Bits */
3263#define DMA_INT0_CLRFLG_CH2_OFS ( 2)
3264#define DMA_INT0_CLRFLG_CH2 ((uint32_t)0x00000004)
3265/* DMA_INT0_CLRFLG[CH3] Bits */
3266#define DMA_INT0_CLRFLG_CH3_OFS ( 3)
3267#define DMA_INT0_CLRFLG_CH3 ((uint32_t)0x00000008)
3268/* DMA_INT0_CLRFLG[CH4] Bits */
3269#define DMA_INT0_CLRFLG_CH4_OFS ( 4)
3270#define DMA_INT0_CLRFLG_CH4 ((uint32_t)0x00000010)
3271/* DMA_INT0_CLRFLG[CH5] Bits */
3272#define DMA_INT0_CLRFLG_CH5_OFS ( 5)
3273#define DMA_INT0_CLRFLG_CH5 ((uint32_t)0x00000020)
3274/* DMA_INT0_CLRFLG[CH6] Bits */
3275#define DMA_INT0_CLRFLG_CH6_OFS ( 6)
3276#define DMA_INT0_CLRFLG_CH6 ((uint32_t)0x00000040)
3277/* DMA_INT0_CLRFLG[CH7] Bits */
3278#define DMA_INT0_CLRFLG_CH7_OFS ( 7)
3279#define DMA_INT0_CLRFLG_CH7 ((uint32_t)0x00000080)
3280/* DMA_INT0_CLRFLG[CH8] Bits */
3281#define DMA_INT0_CLRFLG_CH8_OFS ( 8)
3282#define DMA_INT0_CLRFLG_CH8 ((uint32_t)0x00000100)
3283/* DMA_INT0_CLRFLG[CH9] Bits */
3284#define DMA_INT0_CLRFLG_CH9_OFS ( 9)
3285#define DMA_INT0_CLRFLG_CH9 ((uint32_t)0x00000200)
3286/* DMA_INT0_CLRFLG[CH10] Bits */
3287#define DMA_INT0_CLRFLG_CH10_OFS (10)
3288#define DMA_INT0_CLRFLG_CH10 ((uint32_t)0x00000400)
3289/* DMA_INT0_CLRFLG[CH11] Bits */
3290#define DMA_INT0_CLRFLG_CH11_OFS (11)
3291#define DMA_INT0_CLRFLG_CH11 ((uint32_t)0x00000800)
3292/* DMA_INT0_CLRFLG[CH12] Bits */
3293#define DMA_INT0_CLRFLG_CH12_OFS (12)
3294#define DMA_INT0_CLRFLG_CH12 ((uint32_t)0x00001000)
3295/* DMA_INT0_CLRFLG[CH13] Bits */
3296#define DMA_INT0_CLRFLG_CH13_OFS (13)
3297#define DMA_INT0_CLRFLG_CH13 ((uint32_t)0x00002000)
3298/* DMA_INT0_CLRFLG[CH14] Bits */
3299#define DMA_INT0_CLRFLG_CH14_OFS (14)
3300#define DMA_INT0_CLRFLG_CH14 ((uint32_t)0x00004000)
3301/* DMA_INT0_CLRFLG[CH15] Bits */
3302#define DMA_INT0_CLRFLG_CH15_OFS (15)
3303#define DMA_INT0_CLRFLG_CH15 ((uint32_t)0x00008000)
3304/* DMA_INT0_CLRFLG[CH16] Bits */
3305#define DMA_INT0_CLRFLG_CH16_OFS (16)
3306#define DMA_INT0_CLRFLG_CH16 ((uint32_t)0x00010000)
3307/* DMA_INT0_CLRFLG[CH17] Bits */
3308#define DMA_INT0_CLRFLG_CH17_OFS (17)
3309#define DMA_INT0_CLRFLG_CH17 ((uint32_t)0x00020000)
3310/* DMA_INT0_CLRFLG[CH18] Bits */
3311#define DMA_INT0_CLRFLG_CH18_OFS (18)
3312#define DMA_INT0_CLRFLG_CH18 ((uint32_t)0x00040000)
3313/* DMA_INT0_CLRFLG[CH19] Bits */
3314#define DMA_INT0_CLRFLG_CH19_OFS (19)
3315#define DMA_INT0_CLRFLG_CH19 ((uint32_t)0x00080000)
3316/* DMA_INT0_CLRFLG[CH20] Bits */
3317#define DMA_INT0_CLRFLG_CH20_OFS (20)
3318#define DMA_INT0_CLRFLG_CH20 ((uint32_t)0x00100000)
3319/* DMA_INT0_CLRFLG[CH21] Bits */
3320#define DMA_INT0_CLRFLG_CH21_OFS (21)
3321#define DMA_INT0_CLRFLG_CH21 ((uint32_t)0x00200000)
3322/* DMA_INT0_CLRFLG[CH22] Bits */
3323#define DMA_INT0_CLRFLG_CH22_OFS (22)
3324#define DMA_INT0_CLRFLG_CH22 ((uint32_t)0x00400000)
3325/* DMA_INT0_CLRFLG[CH23] Bits */
3326#define DMA_INT0_CLRFLG_CH23_OFS (23)
3327#define DMA_INT0_CLRFLG_CH23 ((uint32_t)0x00800000)
3328/* DMA_INT0_CLRFLG[CH24] Bits */
3329#define DMA_INT0_CLRFLG_CH24_OFS (24)
3330#define DMA_INT0_CLRFLG_CH24 ((uint32_t)0x01000000)
3331/* DMA_INT0_CLRFLG[CH25] Bits */
3332#define DMA_INT0_CLRFLG_CH25_OFS (25)
3333#define DMA_INT0_CLRFLG_CH25 ((uint32_t)0x02000000)
3334/* DMA_INT0_CLRFLG[CH26] Bits */
3335#define DMA_INT0_CLRFLG_CH26_OFS (26)
3336#define DMA_INT0_CLRFLG_CH26 ((uint32_t)0x04000000)
3337/* DMA_INT0_CLRFLG[CH27] Bits */
3338#define DMA_INT0_CLRFLG_CH27_OFS (27)
3339#define DMA_INT0_CLRFLG_CH27 ((uint32_t)0x08000000)
3340/* DMA_INT0_CLRFLG[CH28] Bits */
3341#define DMA_INT0_CLRFLG_CH28_OFS (28)
3342#define DMA_INT0_CLRFLG_CH28 ((uint32_t)0x10000000)
3343/* DMA_INT0_CLRFLG[CH29] Bits */
3344#define DMA_INT0_CLRFLG_CH29_OFS (29)
3345#define DMA_INT0_CLRFLG_CH29 ((uint32_t)0x20000000)
3346/* DMA_INT0_CLRFLG[CH30] Bits */
3347#define DMA_INT0_CLRFLG_CH30_OFS (30)
3348#define DMA_INT0_CLRFLG_CH30 ((uint32_t)0x40000000)
3349/* DMA_INT0_CLRFLG[CH31] Bits */
3350#define DMA_INT0_CLRFLG_CH31_OFS (31)
3351#define DMA_INT0_CLRFLG_CH31 ((uint32_t)0x80000000)
3352/* DMA_STAT[MASTEN] Bits */
3353#define DMA_STAT_MASTEN_OFS ( 0)
3354#define DMA_STAT_MASTEN ((uint32_t)0x00000001)
3355/* DMA_STAT[STATE] Bits */
3356#define DMA_STAT_STATE_OFS ( 4)
3357#define DMA_STAT_STATE_MASK ((uint32_t)0x000000F0)
3358#define DMA_STAT_STATE0 ((uint32_t)0x00000010)
3359#define DMA_STAT_STATE1 ((uint32_t)0x00000020)
3360#define DMA_STAT_STATE2 ((uint32_t)0x00000040)
3361#define DMA_STAT_STATE3 ((uint32_t)0x00000080)
3362#define DMA_STAT_STATE_0 ((uint32_t)0x00000000)
3363#define DMA_STAT_STATE_1 ((uint32_t)0x00000010)
3364#define DMA_STAT_STATE_2 ((uint32_t)0x00000020)
3365#define DMA_STAT_STATE_3 ((uint32_t)0x00000030)
3366#define DMA_STAT_STATE_4 ((uint32_t)0x00000040)
3367#define DMA_STAT_STATE_5 ((uint32_t)0x00000050)
3368#define DMA_STAT_STATE_6 ((uint32_t)0x00000060)
3369#define DMA_STAT_STATE_7 ((uint32_t)0x00000070)
3370#define DMA_STAT_STATE_8 ((uint32_t)0x00000080)
3371#define DMA_STAT_STATE_9 ((uint32_t)0x00000090)
3372#define DMA_STAT_STATE_10 ((uint32_t)0x000000A0)
3373#define DMA_STAT_STATE_11 ((uint32_t)0x000000B0)
3374#define DMA_STAT_STATE_12 ((uint32_t)0x000000C0)
3375#define DMA_STAT_STATE_13 ((uint32_t)0x000000D0)
3376#define DMA_STAT_STATE_14 ((uint32_t)0x000000E0)
3377#define DMA_STAT_STATE_15 ((uint32_t)0x000000F0)
3378/* DMA_STAT[DMACHANS] Bits */
3379#define DMA_STAT_DMACHANS_OFS (16)
3380#define DMA_STAT_DMACHANS_MASK ((uint32_t)0x001F0000)
3381#define DMA_STAT_DMACHANS0 ((uint32_t)0x00010000)
3382#define DMA_STAT_DMACHANS1 ((uint32_t)0x00020000)
3383#define DMA_STAT_DMACHANS2 ((uint32_t)0x00040000)
3384#define DMA_STAT_DMACHANS3 ((uint32_t)0x00080000)
3385#define DMA_STAT_DMACHANS4 ((uint32_t)0x00100000)
3386#define DMA_STAT_DMACHANS_0 ((uint32_t)0x00000000)
3387#define DMA_STAT_DMACHANS_1 ((uint32_t)0x00010000)
3388#define DMA_STAT_DMACHANS_30 ((uint32_t)0x001E0000)
3389#define DMA_STAT_DMACHANS_31 ((uint32_t)0x001F0000)
3390/* DMA_STAT[TESTSTAT] Bits */
3391#define DMA_STAT_TESTSTAT_OFS (28)
3392#define DMA_STAT_TESTSTAT_MASK ((uint32_t)0xF0000000)
3393#define DMA_STAT_TESTSTAT0 ((uint32_t)0x10000000)
3394#define DMA_STAT_TESTSTAT1 ((uint32_t)0x20000000)
3395#define DMA_STAT_TESTSTAT2 ((uint32_t)0x40000000)
3396#define DMA_STAT_TESTSTAT3 ((uint32_t)0x80000000)
3397#define DMA_STAT_TESTSTAT_0 ((uint32_t)0x00000000)
3398#define DMA_STAT_TESTSTAT_1 ((uint32_t)0x10000000)
3399/* DMA_CFG[MASTEN] Bits */
3400#define DMA_CFG_MASTEN_OFS ( 0)
3401#define DMA_CFG_MASTEN ((uint32_t)0x00000001)
3402/* DMA_CFG[CHPROTCTRL] Bits */
3403#define DMA_CFG_CHPROTCTRL_OFS ( 5)
3404#define DMA_CFG_CHPROTCTRL_MASK ((uint32_t)0x000000E0)
3405/* DMA_CTLBASE[ADDR] Bits */
3406#define DMA_CTLBASE_ADDR_OFS ( 5)
3407#define DMA_CTLBASE_ADDR_MASK ((uint32_t)0xFFFFFFE0)
3408/* DMA_ERRCLR[ERRCLR] Bits */
3409#define DMA_ERRCLR_ERRCLR_OFS ( 0)
3410#define DMA_ERRCLR_ERRCLR ((uint32_t)0x00000001)
3411/* DMA channel definitions and memory structure alignment */
3412#define __MCU_NUM_DMA_CHANNELS__ 8
3413#define DMA_CHANNEL_CONTROL_STRUCT_SIZE 0x10
3414#define DMA_CONTROL_MEMORY_ALIGNMENT (__MCU_NUM_DMA_CHANNELS__ * DMA_CHANNEL_CONTROL_STRUCT_SIZE)
3415
3416/* UDMA_STAT Control Bits */
3417#define UDMA_STAT_DMACHANS_M ((uint32_t)0x001F0000)
3418#define UDMA_STAT_STATE_M ((uint32_t)0x000000F0)
3419#define UDMA_STAT_STATE_IDLE ((uint32_t)0x00000000)
3420#define UDMA_STAT_STATE_RD_CTRL ((uint32_t)0x00000010)
3421#define UDMA_STAT_STATE_RD_SRCENDP ((uint32_t)0x00000020)
3422#define UDMA_STAT_STATE_RD_DSTENDP ((uint32_t)0x00000030)
3423#define UDMA_STAT_STATE_RD_SRCDAT ((uint32_t)0x00000040)
3424#define UDMA_STAT_STATE_WR_DSTDAT ((uint32_t)0x00000050)
3425#define UDMA_STAT_STATE_WAIT ((uint32_t)0x00000060)
3426#define UDMA_STAT_STATE_WR_CTRL ((uint32_t)0x00000070)
3427#define UDMA_STAT_STATE_STALL ((uint32_t)0x00000080)
3428#define UDMA_STAT_STATE_DONE ((uint32_t)0x00000090)
3429#define UDMA_STAT_STATE_UNDEF ((uint32_t)0x000000A0)
3430#define UDMA_STAT_MASTEN ((uint32_t)0x00000001)
3431#define UDMA_STAT_DMACHANS_S (16)
3432
3433/* UDMA_CFG Control Bits */
3434#define UDMA_CFG_MASTEN ((uint32_t)0x00000001)
3436/* UDMA_CTLBASE Control Bits */
3437#define UDMA_CTLBASE_ADDR_M ((uint32_t)0xFFFFFC00)
3438#define UDMA_CTLBASE_ADDR_S (10)
3439
3440/* UDMA_ALTBASE Control Bits */
3441#define UDMA_ALTBASE_ADDR_M ((uint32_t)0xFFFFFFFF)
3442#define UDMA_ALTBASE_ADDR_S ( 0)
3443
3444/* UDMA_WAITSTAT Control Bits */
3445#define UDMA_WAITSTAT_WAITREQ_M ((uint32_t)0xFFFFFFFF)
3447/* UDMA_SWREQ Control Bits */
3448#define UDMA_SWREQ_M ((uint32_t)0xFFFFFFFF)
3450/* UDMA_USEBURSTSET Control Bits */
3451#define UDMA_USEBURSTSET_SET_M ((uint32_t)0xFFFFFFFF)
3453/* UDMA_USEBURSTCLR Control Bits */
3454#define UDMA_USEBURSTCLR_CLR_M ((uint32_t)0xFFFFFFFF)
3456/* UDMA_REQMASKSET Control Bits */
3457#define UDMA_REQMASKSET_SET_M ((uint32_t)0xFFFFFFFF)
3459/* UDMA_REQMASKCLR Control Bits */
3460#define UDMA_REQMASKCLR_CLR_M ((uint32_t)0xFFFFFFFF)
3462/* UDMA_ENASET Control Bits */
3463#define UDMA_ENASET_SET_M ((uint32_t)0xFFFFFFFF)
3465/* UDMA_ENACLR Control Bits */
3466#define UDMA_ENACLR_CLR_M ((uint32_t)0xFFFFFFFF)
3468/* UDMA_ALTSET Control Bits */
3469#define UDMA_ALTSET_SET_M ((uint32_t)0xFFFFFFFF)
3471/* UDMA_ALTCLR Control Bits */
3472#define UDMA_ALTCLR_CLR_M ((uint32_t)0xFFFFFFFF)
3474/* UDMA_PRIOSET Control Bits */
3475#define UDMA_PRIOSET_SET_M ((uint32_t)0xFFFFFFFF)
3477/* UDMA_PRIOCLR Control Bits */
3478#define UDMA_PRIOCLR_CLR_M ((uint32_t)0xFFFFFFFF)
3480/* UDMA_ERRCLR Control Bits */
3481#define UDMA_ERRCLR_ERRCLR ((uint32_t)0x00000001)
3483/* UDMA_CHASGN Control Bits */
3484#define UDMA_CHASGN_M ((uint32_t)0xFFFFFFFF)
3485#define UDMA_CHASGN_PRIMARY ((uint32_t)0x00000000)
3486#define UDMA_CHASGN_SECONDARY ((uint32_t)0x00000001)
3488/* Micro Direct Memory Access (uDMA) offsets */
3489#define UDMA_O_SRCENDP ((uint32_t)0x00000000)
3490#define UDMA_O_DSTENDP ((uint32_t)0x00000004)
3491#define UDMA_O_CHCTL ((uint32_t)0x00000008)
3493/* UDMA_O_SRCENDP Control Bits */
3494#define UDMA_SRCENDP_ADDR_M ((uint32_t)0xFFFFFFFF)
3495#define UDMA_SRCENDP_ADDR_S ( 0)
3496
3497/* UDMA_O_DSTENDP Control Bits */
3498#define UDMA_DSTENDP_ADDR_M ((uint32_t)0xFFFFFFFF)
3499#define UDMA_DSTENDP_ADDR_S ( 0)
3500
3501/* UDMA_O_CHCTL Control Bits */
3502#define UDMA_CHCTL_DSTINC_M ((uint32_t)0xC0000000)
3503#define UDMA_CHCTL_DSTINC_8 ((uint32_t)0x00000000)
3504#define UDMA_CHCTL_DSTINC_16 ((uint32_t)0x40000000)
3505#define UDMA_CHCTL_DSTINC_32 ((uint32_t)0x80000000)
3506#define UDMA_CHCTL_DSTINC_NONE ((uint32_t)0xC0000000)
3507#define UDMA_CHCTL_DSTSIZE_M ((uint32_t)0x30000000)
3508#define UDMA_CHCTL_DSTSIZE_8 ((uint32_t)0x00000000)
3509#define UDMA_CHCTL_DSTSIZE_16 ((uint32_t)0x10000000)
3510#define UDMA_CHCTL_DSTSIZE_32 ((uint32_t)0x20000000)
3511#define UDMA_CHCTL_SRCINC_M ((uint32_t)0x0C000000)
3512#define UDMA_CHCTL_SRCINC_8 ((uint32_t)0x00000000)
3513#define UDMA_CHCTL_SRCINC_16 ((uint32_t)0x04000000)
3514#define UDMA_CHCTL_SRCINC_32 ((uint32_t)0x08000000)
3515#define UDMA_CHCTL_SRCINC_NONE ((uint32_t)0x0C000000)
3516#define UDMA_CHCTL_SRCSIZE_M ((uint32_t)0x03000000)
3517#define UDMA_CHCTL_SRCSIZE_8 ((uint32_t)0x00000000)
3518#define UDMA_CHCTL_SRCSIZE_16 ((uint32_t)0x01000000)
3519#define UDMA_CHCTL_SRCSIZE_32 ((uint32_t)0x02000000)
3520#define UDMA_CHCTL_ARBSIZE_M ((uint32_t)0x0003C000)
3521#define UDMA_CHCTL_ARBSIZE_1 ((uint32_t)0x00000000)
3522#define UDMA_CHCTL_ARBSIZE_2 ((uint32_t)0x00004000)
3523#define UDMA_CHCTL_ARBSIZE_4 ((uint32_t)0x00008000)
3524#define UDMA_CHCTL_ARBSIZE_8 ((uint32_t)0x0000C000)
3525#define UDMA_CHCTL_ARBSIZE_16 ((uint32_t)0x00010000)
3526#define UDMA_CHCTL_ARBSIZE_32 ((uint32_t)0x00014000)
3527#define UDMA_CHCTL_ARBSIZE_64 ((uint32_t)0x00018000)
3528#define UDMA_CHCTL_ARBSIZE_128 ((uint32_t)0x0001C000)
3529#define UDMA_CHCTL_ARBSIZE_256 ((uint32_t)0x00020000)
3530#define UDMA_CHCTL_ARBSIZE_512 ((uint32_t)0x00024000)
3531#define UDMA_CHCTL_ARBSIZE_1024 ((uint32_t)0x00028000)
3532#define UDMA_CHCTL_XFERSIZE_M ((uint32_t)0x00003FF0)
3533#define UDMA_CHCTL_NXTUSEBURST ((uint32_t)0x00000008)
3534#define UDMA_CHCTL_XFERMODE_M ((uint32_t)0x00000007)
3535#define UDMA_CHCTL_XFERMODE_STOP ((uint32_t)0x00000000)
3536#define UDMA_CHCTL_XFERMODE_BASIC ((uint32_t)0x00000001)
3537#define UDMA_CHCTL_XFERMODE_AUTO ((uint32_t)0x00000002)
3538#define UDMA_CHCTL_XFERMODE_PINGPONG ((uint32_t)0x00000003)
3539#define UDMA_CHCTL_XFERMODE_MEM_SG ((uint32_t)0x00000004)
3540#define UDMA_CHCTL_XFERMODE_MEM_SGA ((uint32_t)0x00000005)
3541#define UDMA_CHCTL_XFERMODE_PER_SG ((uint32_t)0x00000006)
3542#define UDMA_CHCTL_XFERMODE_PER_SGA ((uint32_t)0x00000007)
3544#define UDMA_CHCTL_XFERSIZE_S ( 4)
3545
3546
3547/******************************************************************************
3548* DWT Bits
3549******************************************************************************/
3550
3551
3552/******************************************************************************
3553* EUSCI_A Bits
3554******************************************************************************/
3555/* EUSCI_A_CTLW0[SWRST] Bits */
3556#define EUSCI_A_CTLW0_SWRST_OFS ( 0)
3557#define EUSCI_A_CTLW0_SWRST ((uint16_t)0x0001)
3558/* EUSCI_A_CTLW0[TXBRK] Bits */
3559#define EUSCI_A_CTLW0_TXBRK_OFS ( 1)
3560#define EUSCI_A_CTLW0_TXBRK ((uint16_t)0x0002)
3561/* EUSCI_A_CTLW0[TXADDR] Bits */
3562#define EUSCI_A_CTLW0_TXADDR_OFS ( 2)
3563#define EUSCI_A_CTLW0_TXADDR ((uint16_t)0x0004)
3564/* EUSCI_A_CTLW0[DORM] Bits */
3565#define EUSCI_A_CTLW0_DORM_OFS ( 3)
3566#define EUSCI_A_CTLW0_DORM ((uint16_t)0x0008)
3567/* EUSCI_A_CTLW0[BRKIE] Bits */
3568#define EUSCI_A_CTLW0_BRKIE_OFS ( 4)
3569#define EUSCI_A_CTLW0_BRKIE ((uint16_t)0x0010)
3570/* EUSCI_A_CTLW0[RXEIE] Bits */
3571#define EUSCI_A_CTLW0_RXEIE_OFS ( 5)
3572#define EUSCI_A_CTLW0_RXEIE ((uint16_t)0x0020)
3573/* EUSCI_A_CTLW0[SSEL] Bits */
3574#define EUSCI_A_CTLW0_SSEL_OFS ( 6)
3575#define EUSCI_A_CTLW0_SSEL_MASK ((uint16_t)0x00C0)
3576#define EUSCI_A_CTLW0_SSEL0 ((uint16_t)0x0040)
3577#define EUSCI_A_CTLW0_SSEL1 ((uint16_t)0x0080)
3578#define EUSCI_A_CTLW0_UCSSEL_0 ((uint16_t)0x0000)
3579#define EUSCI_A_CTLW0_UCSSEL_1 ((uint16_t)0x0040)
3580#define EUSCI_A_CTLW0_UCSSEL_2 ((uint16_t)0x0080)
3581#define EUSCI_A_CTLW0_SSEL__UCLK ((uint16_t)0x0000)
3582#define EUSCI_A_CTLW0_SSEL__ACLK ((uint16_t)0x0040)
3583#define EUSCI_A_CTLW0_SSEL__SMCLK ((uint16_t)0x0080)
3584/* EUSCI_A_CTLW0[SYNC] Bits */
3585#define EUSCI_A_CTLW0_SYNC_OFS ( 8)
3586#define EUSCI_A_CTLW0_SYNC ((uint16_t)0x0100)
3587/* EUSCI_A_CTLW0[MODE] Bits */
3588#define EUSCI_A_CTLW0_MODE_OFS ( 9)
3589#define EUSCI_A_CTLW0_MODE_MASK ((uint16_t)0x0600)
3590#define EUSCI_A_CTLW0_MODE0 ((uint16_t)0x0200)
3591#define EUSCI_A_CTLW0_MODE1 ((uint16_t)0x0400)
3592#define EUSCI_A_CTLW0_MODE_0 ((uint16_t)0x0000)
3593#define EUSCI_A_CTLW0_MODE_1 ((uint16_t)0x0200)
3594#define EUSCI_A_CTLW0_MODE_2 ((uint16_t)0x0400)
3595#define EUSCI_A_CTLW0_MODE_3 ((uint16_t)0x0600)
3596/* EUSCI_A_CTLW0[SPB] Bits */
3597#define EUSCI_A_CTLW0_SPB_OFS (11)
3598#define EUSCI_A_CTLW0_SPB ((uint16_t)0x0800)
3599/* EUSCI_A_CTLW0[SEVENBIT] Bits */
3600#define EUSCI_A_CTLW0_SEVENBIT_OFS (12)
3601#define EUSCI_A_CTLW0_SEVENBIT ((uint16_t)0x1000)
3602/* EUSCI_A_CTLW0[MSB] Bits */
3603#define EUSCI_A_CTLW0_MSB_OFS (13)
3604#define EUSCI_A_CTLW0_MSB ((uint16_t)0x2000)
3605/* EUSCI_A_CTLW0[PAR] Bits */
3606#define EUSCI_A_CTLW0_PAR_OFS (14)
3607#define EUSCI_A_CTLW0_PAR ((uint16_t)0x4000)
3608/* EUSCI_A_CTLW0[PEN] Bits */
3609#define EUSCI_A_CTLW0_PEN_OFS (15)
3610#define EUSCI_A_CTLW0_PEN ((uint16_t)0x8000)
3611/* EUSCI_A_CTLW0[STEM] Bits */
3612#define EUSCI_A_CTLW0_STEM_OFS ( 1)
3613#define EUSCI_A_CTLW0_STEM ((uint16_t)0x0002)
3614/* EUSCI_A_CTLW0[MST] Bits */
3615#define EUSCI_A_CTLW0_MST_OFS (11)
3616#define EUSCI_A_CTLW0_MST ((uint16_t)0x0800)
3617/* EUSCI_A_CTLW0[CKPL] Bits */
3618#define EUSCI_A_CTLW0_CKPL_OFS (14)
3619#define EUSCI_A_CTLW0_CKPL ((uint16_t)0x4000)
3620/* EUSCI_A_CTLW0[CKPH] Bits */
3621#define EUSCI_A_CTLW0_CKPH_OFS (15)
3622#define EUSCI_A_CTLW0_CKPH ((uint16_t)0x8000)
3623/* EUSCI_A_CTLW1[GLIT] Bits */
3624#define EUSCI_A_CTLW1_GLIT_OFS ( 0)
3625#define EUSCI_A_CTLW1_GLIT_MASK ((uint16_t)0x0003)
3626#define EUSCI_A_CTLW1_GLIT0 ((uint16_t)0x0001)
3627#define EUSCI_A_CTLW1_GLIT1 ((uint16_t)0x0002)
3628#define EUSCI_A_CTLW1_GLIT_0 ((uint16_t)0x0000)
3629#define EUSCI_A_CTLW1_GLIT_1 ((uint16_t)0x0001)
3630#define EUSCI_A_CTLW1_GLIT_2 ((uint16_t)0x0002)
3631#define EUSCI_A_CTLW1_GLIT_3 ((uint16_t)0x0003)
3632/* EUSCI_A_MCTLW[OS16] Bits */
3633#define EUSCI_A_MCTLW_OS16_OFS ( 0)
3634#define EUSCI_A_MCTLW_OS16 ((uint16_t)0x0001)
3635/* EUSCI_A_MCTLW[BRF] Bits */
3636#define EUSCI_A_MCTLW_BRF_OFS ( 4)
3637#define EUSCI_A_MCTLW_BRF_MASK ((uint16_t)0x00F0)
3638/* EUSCI_A_MCTLW[BRS] Bits */
3639#define EUSCI_A_MCTLW_BRS_OFS ( 8)
3640#define EUSCI_A_MCTLW_BRS_MASK ((uint16_t)0xFF00)
3641/* EUSCI_A_STATW[BUSY] Bits */
3642#define EUSCI_A_STATW_BUSY_OFS ( 0)
3643#define EUSCI_A_STATW_BUSY ((uint16_t)0x0001)
3644/* EUSCI_A_STATW[ADDR_IDLE] Bits */
3645#define EUSCI_A_STATW_ADDR_IDLE_OFS ( 1)
3646#define EUSCI_A_STATW_ADDR_IDLE ((uint16_t)0x0002)
3647/* EUSCI_A_STATW[RXERR] Bits */
3648#define EUSCI_A_STATW_RXERR_OFS ( 2)
3649#define EUSCI_A_STATW_RXERR ((uint16_t)0x0004)
3650/* EUSCI_A_STATW[BRK] Bits */
3651#define EUSCI_A_STATW_BRK_OFS ( 3)
3652#define EUSCI_A_STATW_BRK ((uint16_t)0x0008)
3653/* EUSCI_A_STATW[PE] Bits */
3654#define EUSCI_A_STATW_PE_OFS ( 4)
3655#define EUSCI_A_STATW_PE ((uint16_t)0x0010)
3656/* EUSCI_A_STATW[OE] Bits */
3657#define EUSCI_A_STATW_OE_OFS ( 5)
3658#define EUSCI_A_STATW_OE ((uint16_t)0x0020)
3659/* EUSCI_A_STATW[FE] Bits */
3660#define EUSCI_A_STATW_FE_OFS ( 6)
3661#define EUSCI_A_STATW_FE ((uint16_t)0x0040)
3662/* EUSCI_A_STATW[LISTEN] Bits */
3663#define EUSCI_A_STATW_LISTEN_OFS ( 7)
3664#define EUSCI_A_STATW_LISTEN ((uint16_t)0x0080)
3665/* EUSCI_A_STATW[SPI_BUSY] Bits */
3666#define EUSCI_A_STATW_SPI_BUSY_OFS ( 0)
3667#define EUSCI_A_STATW_SPI_BUSY ((uint16_t)0x0001)
3668/* EUSCI_A_RXBUF[RXBUF] Bits */
3669#define EUSCI_A_RXBUF_RXBUF_OFS ( 0)
3670#define EUSCI_A_RXBUF_RXBUF_MASK ((uint16_t)0x00FF)
3671/* EUSCI_A_TXBUF[TXBUF] Bits */
3672#define EUSCI_A_TXBUF_TXBUF_OFS ( 0)
3673#define EUSCI_A_TXBUF_TXBUF_MASK ((uint16_t)0x00FF)
3674/* EUSCI_A_ABCTL[ABDEN] Bits */
3675#define EUSCI_A_ABCTL_ABDEN_OFS ( 0)
3676#define EUSCI_A_ABCTL_ABDEN ((uint16_t)0x0001)
3677/* EUSCI_A_ABCTL[BTOE] Bits */
3678#define EUSCI_A_ABCTL_BTOE_OFS ( 2)
3679#define EUSCI_A_ABCTL_BTOE ((uint16_t)0x0004)
3680/* EUSCI_A_ABCTL[STOE] Bits */
3681#define EUSCI_A_ABCTL_STOE_OFS ( 3)
3682#define EUSCI_A_ABCTL_STOE ((uint16_t)0x0008)
3683/* EUSCI_A_ABCTL[DELIM] Bits */
3684#define EUSCI_A_ABCTL_DELIM_OFS ( 4)
3685#define EUSCI_A_ABCTL_DELIM_MASK ((uint16_t)0x0030)
3686#define EUSCI_A_ABCTL_DELIM0 ((uint16_t)0x0010)
3687#define EUSCI_A_ABCTL_DELIM1 ((uint16_t)0x0020)
3688#define EUSCI_A_ABCTL_DELIM_0 ((uint16_t)0x0000)
3689#define EUSCI_A_ABCTL_DELIM_1 ((uint16_t)0x0010)
3690#define EUSCI_A_ABCTL_DELIM_2 ((uint16_t)0x0020)
3691#define EUSCI_A_ABCTL_DELIM_3 ((uint16_t)0x0030)
3692/* EUSCI_A_IRCTL[IREN] Bits */
3693#define EUSCI_A_IRCTL_IREN_OFS ( 0)
3694#define EUSCI_A_IRCTL_IREN ((uint16_t)0x0001)
3695/* EUSCI_A_IRCTL[IRTXCLK] Bits */
3696#define EUSCI_A_IRCTL_IRTXCLK_OFS ( 1)
3697#define EUSCI_A_IRCTL_IRTXCLK ((uint16_t)0x0002)
3698/* EUSCI_A_IRCTL[IRTXPL] Bits */
3699#define EUSCI_A_IRCTL_IRTXPL_OFS ( 2)
3700#define EUSCI_A_IRCTL_IRTXPL_MASK ((uint16_t)0x00FC)
3701/* EUSCI_A_IRCTL[IRRXFE] Bits */
3702#define EUSCI_A_IRCTL_IRRXFE_OFS ( 8)
3703#define EUSCI_A_IRCTL_IRRXFE ((uint16_t)0x0100)
3704/* EUSCI_A_IRCTL[IRRXPL] Bits */
3705#define EUSCI_A_IRCTL_IRRXPL_OFS ( 9)
3706#define EUSCI_A_IRCTL_IRRXPL ((uint16_t)0x0200)
3707/* EUSCI_A_IRCTL[IRRXFL] Bits */
3708#define EUSCI_A_IRCTL_IRRXFL_OFS (10)
3709#define EUSCI_A_IRCTL_IRRXFL_MASK ((uint16_t)0x3C00)
3710/* EUSCI_A_IE[RXIE] Bits */
3711#define EUSCI_A_IE_RXIE_OFS ( 0)
3712#define EUSCI_A_IE_RXIE ((uint16_t)0x0001)
3713/* EUSCI_A_IE[TXIE] Bits */
3714#define EUSCI_A_IE_TXIE_OFS ( 1)
3715#define EUSCI_A_IE_TXIE ((uint16_t)0x0002)
3716/* EUSCI_A_IE[STTIE] Bits */
3717#define EUSCI_A_IE_STTIE_OFS ( 2)
3718#define EUSCI_A_IE_STTIE ((uint16_t)0x0004)
3719/* EUSCI_A_IE[TXCPTIE] Bits */
3720#define EUSCI_A_IE_TXCPTIE_OFS ( 3)
3721#define EUSCI_A_IE_TXCPTIE ((uint16_t)0x0008)
3722/* EUSCI_A_IFG[RXIFG] Bits */
3723#define EUSCI_A_IFG_RXIFG_OFS ( 0)
3724#define EUSCI_A_IFG_RXIFG ((uint16_t)0x0001)
3725/* EUSCI_A_IFG[TXIFG] Bits */
3726#define EUSCI_A_IFG_TXIFG_OFS ( 1)
3727#define EUSCI_A_IFG_TXIFG ((uint16_t)0x0002)
3728/* EUSCI_A_IFG[STTIFG] Bits */
3729#define EUSCI_A_IFG_STTIFG_OFS ( 2)
3730#define EUSCI_A_IFG_STTIFG ((uint16_t)0x0004)
3731/* EUSCI_A_IFG[TXCPTIFG] Bits */
3732#define EUSCI_A_IFG_TXCPTIFG_OFS ( 3)
3733#define EUSCI_A_IFG_TXCPTIFG ((uint16_t)0x0008)
3734/* legacy definitions for backward compatibility to version 2100 */
3735#define EUSCI_A__RXIE_OFS EUSCI_A_IE_RXIE_OFS
3736#define EUSCI_A__RXIE EUSCI_A_IE_RXIE
3737#define EUSCI_A__TXIE_OFS EUSCI_A_IE_TXIE_OFS
3738#define EUSCI_A__TXIE EUSCI_A_IE_TXIE
3741/******************************************************************************
3742* EUSCI_B Bits
3743******************************************************************************/
3744/* EUSCI_B_CTLW0[SWRST] Bits */
3745#define EUSCI_B_CTLW0_SWRST_OFS ( 0)
3746#define EUSCI_B_CTLW0_SWRST ((uint16_t)0x0001)
3747/* EUSCI_B_CTLW0[TXSTT] Bits */
3748#define EUSCI_B_CTLW0_TXSTT_OFS ( 1)
3749#define EUSCI_B_CTLW0_TXSTT ((uint16_t)0x0002)
3750/* EUSCI_B_CTLW0[TXSTP] Bits */
3751#define EUSCI_B_CTLW0_TXSTP_OFS ( 2)
3752#define EUSCI_B_CTLW0_TXSTP ((uint16_t)0x0004)
3753/* EUSCI_B_CTLW0[TXNACK] Bits */
3754#define EUSCI_B_CTLW0_TXNACK_OFS ( 3)
3755#define EUSCI_B_CTLW0_TXNACK ((uint16_t)0x0008)
3756/* EUSCI_B_CTLW0[TR] Bits */
3757#define EUSCI_B_CTLW0_TR_OFS ( 4)
3758#define EUSCI_B_CTLW0_TR ((uint16_t)0x0010)
3759/* EUSCI_B_CTLW0[TXACK] Bits */
3760#define EUSCI_B_CTLW0_TXACK_OFS ( 5)
3761#define EUSCI_B_CTLW0_TXACK ((uint16_t)0x0020)
3762/* EUSCI_B_CTLW0[SSEL] Bits */
3763#define EUSCI_B_CTLW0_SSEL_OFS ( 6)
3764#define EUSCI_B_CTLW0_SSEL_MASK ((uint16_t)0x00C0)
3765#define EUSCI_B_CTLW0_SSEL0 ((uint16_t)0x0040)
3766#define EUSCI_B_CTLW0_SSEL1 ((uint16_t)0x0080)
3767#define EUSCI_B_CTLW0_UCSSEL_0 ((uint16_t)0x0000)
3768#define EUSCI_B_CTLW0_UCSSEL_1 ((uint16_t)0x0040)
3769#define EUSCI_B_CTLW0_UCSSEL_2 ((uint16_t)0x0080)
3770#define EUSCI_B_CTLW0_UCSSEL_3 ((uint16_t)0x00C0)
3771#define EUSCI_B_CTLW0_SSEL__UCLKI ((uint16_t)0x0000)
3772#define EUSCI_B_CTLW0_SSEL__ACLK ((uint16_t)0x0040)
3773#define EUSCI_B_CTLW0_SSEL__SMCLK ((uint16_t)0x0080)
3774/* EUSCI_B_CTLW0[SYNC] Bits */
3775#define EUSCI_B_CTLW0_SYNC_OFS ( 8)
3776#define EUSCI_B_CTLW0_SYNC ((uint16_t)0x0100)
3777/* EUSCI_B_CTLW0[MODE] Bits */
3778#define EUSCI_B_CTLW0_MODE_OFS ( 9)
3779#define EUSCI_B_CTLW0_MODE_MASK ((uint16_t)0x0600)
3780#define EUSCI_B_CTLW0_MODE0 ((uint16_t)0x0200)
3781#define EUSCI_B_CTLW0_MODE1 ((uint16_t)0x0400)
3782#define EUSCI_B_CTLW0_MODE_0 ((uint16_t)0x0000)
3783#define EUSCI_B_CTLW0_MODE_1 ((uint16_t)0x0200)
3784#define EUSCI_B_CTLW0_MODE_2 ((uint16_t)0x0400)
3785#define EUSCI_B_CTLW0_MODE_3 ((uint16_t)0x0600)
3786/* EUSCI_B_CTLW0[MST] Bits */
3787#define EUSCI_B_CTLW0_MST_OFS (11)
3788#define EUSCI_B_CTLW0_MST ((uint16_t)0x0800)
3789/* EUSCI_B_CTLW0[MM] Bits */
3790#define EUSCI_B_CTLW0_MM_OFS (13)
3791#define EUSCI_B_CTLW0_MM ((uint16_t)0x2000)
3792/* EUSCI_B_CTLW0[SLA10] Bits */
3793#define EUSCI_B_CTLW0_SLA10_OFS (14)
3794#define EUSCI_B_CTLW0_SLA10 ((uint16_t)0x4000)
3795/* EUSCI_B_CTLW0[A10] Bits */
3796#define EUSCI_B_CTLW0_A10_OFS (15)
3797#define EUSCI_B_CTLW0_A10 ((uint16_t)0x8000)
3798/* EUSCI_B_CTLW0[STEM] Bits */
3799#define EUSCI_B_CTLW0_STEM_OFS ( 1)
3800#define EUSCI_B_CTLW0_STEM ((uint16_t)0x0002)
3801/* EUSCI_B_CTLW0[SEVENBIT] Bits */
3802#define EUSCI_B_CTLW0_SEVENBIT_OFS (12)
3803#define EUSCI_B_CTLW0_SEVENBIT ((uint16_t)0x1000)
3804/* EUSCI_B_CTLW0[MSB] Bits */
3805#define EUSCI_B_CTLW0_MSB_OFS (13)
3806#define EUSCI_B_CTLW0_MSB ((uint16_t)0x2000)
3807/* EUSCI_B_CTLW0[CKPL] Bits */
3808#define EUSCI_B_CTLW0_CKPL_OFS (14)
3809#define EUSCI_B_CTLW0_CKPL ((uint16_t)0x4000)
3810/* EUSCI_B_CTLW0[CKPH] Bits */
3811#define EUSCI_B_CTLW0_CKPH_OFS (15)
3812#define EUSCI_B_CTLW0_CKPH ((uint16_t)0x8000)
3813/* EUSCI_B_CTLW1[GLIT] Bits */
3814#define EUSCI_B_CTLW1_GLIT_OFS ( 0)
3815#define EUSCI_B_CTLW1_GLIT_MASK ((uint16_t)0x0003)
3816#define EUSCI_B_CTLW1_GLIT0 ((uint16_t)0x0001)
3817#define EUSCI_B_CTLW1_GLIT1 ((uint16_t)0x0002)
3818#define EUSCI_B_CTLW1_GLIT_0 ((uint16_t)0x0000)
3819#define EUSCI_B_CTLW1_GLIT_1 ((uint16_t)0x0001)
3820#define EUSCI_B_CTLW1_GLIT_2 ((uint16_t)0x0002)
3821#define EUSCI_B_CTLW1_GLIT_3 ((uint16_t)0x0003)
3822/* EUSCI_B_CTLW1[ASTP] Bits */
3823#define EUSCI_B_CTLW1_ASTP_OFS ( 2)
3824#define EUSCI_B_CTLW1_ASTP_MASK ((uint16_t)0x000C)
3825#define EUSCI_B_CTLW1_ASTP0 ((uint16_t)0x0004)
3826#define EUSCI_B_CTLW1_ASTP1 ((uint16_t)0x0008)
3827#define EUSCI_B_CTLW1_ASTP_0 ((uint16_t)0x0000)
3828 /* sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */
3829#define EUSCI_B_CTLW1_ASTP_1 ((uint16_t)0x0004)
3830 /* UCBxTBCNT */
3831#define EUSCI_B_CTLW1_ASTP_2 ((uint16_t)0x0008)
3832 /* reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the */
3833 /* threshold */
3834/* EUSCI_B_CTLW1[SWACK] Bits */
3835#define EUSCI_B_CTLW1_SWACK_OFS ( 4)
3836#define EUSCI_B_CTLW1_SWACK ((uint16_t)0x0010)
3837/* EUSCI_B_CTLW1[STPNACK] Bits */
3838#define EUSCI_B_CTLW1_STPNACK_OFS ( 5)
3839#define EUSCI_B_CTLW1_STPNACK ((uint16_t)0x0020)
3840/* EUSCI_B_CTLW1[CLTO] Bits */
3841#define EUSCI_B_CTLW1_CLTO_OFS ( 6)
3842#define EUSCI_B_CTLW1_CLTO_MASK ((uint16_t)0x00C0)
3843#define EUSCI_B_CTLW1_CLTO0 ((uint16_t)0x0040)
3844#define EUSCI_B_CTLW1_CLTO1 ((uint16_t)0x0080)
3845#define EUSCI_B_CTLW1_CLTO_0 ((uint16_t)0x0000)
3846#define EUSCI_B_CTLW1_CLTO_1 ((uint16_t)0x0040)
3847#define EUSCI_B_CTLW1_CLTO_2 ((uint16_t)0x0080)
3848#define EUSCI_B_CTLW1_CLTO_3 ((uint16_t)0x00C0)
3849/* EUSCI_B_CTLW1[ETXINT] Bits */
3850#define EUSCI_B_CTLW1_ETXINT_OFS ( 8)
3851#define EUSCI_B_CTLW1_ETXINT ((uint16_t)0x0100)
3852/* EUSCI_B_STATW[BBUSY] Bits */
3853#define EUSCI_B_STATW_BBUSY_OFS ( 4)
3854#define EUSCI_B_STATW_BBUSY ((uint16_t)0x0010)
3855/* EUSCI_B_STATW[GC] Bits */
3856#define EUSCI_B_STATW_GC_OFS ( 5)
3857#define EUSCI_B_STATW_GC ((uint16_t)0x0020)
3858/* EUSCI_B_STATW[SCLLOW] Bits */
3859#define EUSCI_B_STATW_SCLLOW_OFS ( 6)
3860#define EUSCI_B_STATW_SCLLOW ((uint16_t)0x0040)
3861/* EUSCI_B_STATW[BCNT] Bits */
3862#define EUSCI_B_STATW_BCNT_OFS ( 8)
3863#define EUSCI_B_STATW_BCNT_MASK ((uint16_t)0xFF00)
3864/* EUSCI_B_STATW[SPI_BUSY] Bits */
3865#define EUSCI_B_STATW_SPI_BUSY_OFS ( 0)
3866#define EUSCI_B_STATW_SPI_BUSY ((uint16_t)0x0001)
3867/* EUSCI_B_STATW[OE] Bits */
3868#define EUSCI_B_STATW_OE_OFS ( 5)
3869#define EUSCI_B_STATW_OE ((uint16_t)0x0020)
3870/* EUSCI_B_STATW[FE] Bits */
3871#define EUSCI_B_STATW_FE_OFS ( 6)
3872#define EUSCI_B_STATW_FE ((uint16_t)0x0040)
3873/* EUSCI_B_STATW[LISTEN] Bits */
3874#define EUSCI_B_STATW_LISTEN_OFS ( 7)
3875#define EUSCI_B_STATW_LISTEN ((uint16_t)0x0080)
3876/* EUSCI_B_TBCNT[TBCNT] Bits */
3877#define EUSCI_B_TBCNT_TBCNT_OFS ( 0)
3878#define EUSCI_B_TBCNT_TBCNT_MASK ((uint16_t)0x00FF)
3879/* EUSCI_B_RXBUF[RXBUF] Bits */
3880#define EUSCI_B_RXBUF_RXBUF_OFS ( 0)
3881#define EUSCI_B_RXBUF_RXBUF_MASK ((uint16_t)0x00FF)
3882/* EUSCI_B_TXBUF[TXBUF] Bits */
3883#define EUSCI_B_TXBUF_TXBUF_OFS ( 0)
3884#define EUSCI_B_TXBUF_TXBUF_MASK ((uint16_t)0x00FF)
3885/* EUSCI_B_I2COA0[I2COA0] Bits */
3886#define EUSCI_B_I2COA0_I2COA0_OFS ( 0)
3887#define EUSCI_B_I2COA0_I2COA0_MASK ((uint16_t)0x03FF)
3888/* EUSCI_B_I2COA0[OAEN] Bits */
3889#define EUSCI_B_I2COA0_OAEN_OFS (10)
3890#define EUSCI_B_I2COA0_OAEN ((uint16_t)0x0400)
3891/* EUSCI_B_I2COA0[GCEN] Bits */
3892#define EUSCI_B_I2COA0_GCEN_OFS (15)
3893#define EUSCI_B_I2COA0_GCEN ((uint16_t)0x8000)
3894/* EUSCI_B_I2COA1[I2COA1] Bits */
3895#define EUSCI_B_I2COA1_I2COA1_OFS ( 0)
3896#define EUSCI_B_I2COA1_I2COA1_MASK ((uint16_t)0x03FF)
3897/* EUSCI_B_I2COA1[OAEN] Bits */
3898#define EUSCI_B_I2COA1_OAEN_OFS (10)
3899#define EUSCI_B_I2COA1_OAEN ((uint16_t)0x0400)
3900/* EUSCI_B_I2COA2[I2COA2] Bits */
3901#define EUSCI_B_I2COA2_I2COA2_OFS ( 0)
3902#define EUSCI_B_I2COA2_I2COA2_MASK ((uint16_t)0x03FF)
3903/* EUSCI_B_I2COA2[OAEN] Bits */
3904#define EUSCI_B_I2COA2_OAEN_OFS (10)
3905#define EUSCI_B_I2COA2_OAEN ((uint16_t)0x0400)
3906/* EUSCI_B_I2COA3[I2COA3] Bits */
3907#define EUSCI_B_I2COA3_I2COA3_OFS ( 0)
3908#define EUSCI_B_I2COA3_I2COA3_MASK ((uint16_t)0x03FF)
3909/* EUSCI_B_I2COA3[OAEN] Bits */
3910#define EUSCI_B_I2COA3_OAEN_OFS (10)
3911#define EUSCI_B_I2COA3_OAEN ((uint16_t)0x0400)
3912/* EUSCI_B_ADDRX[ADDRX] Bits */
3913#define EUSCI_B_ADDRX_ADDRX_OFS ( 0)
3914#define EUSCI_B_ADDRX_ADDRX_MASK ((uint16_t)0x03FF)
3915#define EUSCI_B_ADDRX_ADDRX0 ((uint16_t)0x0001)
3916#define EUSCI_B_ADDRX_ADDRX1 ((uint16_t)0x0002)
3917#define EUSCI_B_ADDRX_ADDRX2 ((uint16_t)0x0004)
3918#define EUSCI_B_ADDRX_ADDRX3 ((uint16_t)0x0008)
3919#define EUSCI_B_ADDRX_ADDRX4 ((uint16_t)0x0010)
3920#define EUSCI_B_ADDRX_ADDRX5 ((uint16_t)0x0020)
3921#define EUSCI_B_ADDRX_ADDRX6 ((uint16_t)0x0040)
3922#define EUSCI_B_ADDRX_ADDRX7 ((uint16_t)0x0080)
3923#define EUSCI_B_ADDRX_ADDRX8 ((uint16_t)0x0100)
3924#define EUSCI_B_ADDRX_ADDRX9 ((uint16_t)0x0200)
3925/* EUSCI_B_ADDMASK[ADDMASK] Bits */
3926#define EUSCI_B_ADDMASK_ADDMASK_OFS ( 0)
3927#define EUSCI_B_ADDMASK_ADDMASK_MASK ((uint16_t)0x03FF)
3928/* EUSCI_B_I2CSA[I2CSA] Bits */
3929#define EUSCI_B_I2CSA_I2CSA_OFS ( 0)
3930#define EUSCI_B_I2CSA_I2CSA_MASK ((uint16_t)0x03FF)
3931/* EUSCI_B_IE[RXIE0] Bits */
3932#define EUSCI_B_IE_RXIE0_OFS ( 0)
3933#define EUSCI_B_IE_RXIE0 ((uint16_t)0x0001)
3934/* EUSCI_B_IE[TXIE0] Bits */
3935#define EUSCI_B_IE_TXIE0_OFS ( 1)
3936#define EUSCI_B_IE_TXIE0 ((uint16_t)0x0002)
3937/* EUSCI_B_IE[STTIE] Bits */
3938#define EUSCI_B_IE_STTIE_OFS ( 2)
3939#define EUSCI_B_IE_STTIE ((uint16_t)0x0004)
3940/* EUSCI_B_IE[STPIE] Bits */
3941#define EUSCI_B_IE_STPIE_OFS ( 3)
3942#define EUSCI_B_IE_STPIE ((uint16_t)0x0008)
3943/* EUSCI_B_IE[ALIE] Bits */
3944#define EUSCI_B_IE_ALIE_OFS ( 4)
3945#define EUSCI_B_IE_ALIE ((uint16_t)0x0010)
3946/* EUSCI_B_IE[NACKIE] Bits */
3947#define EUSCI_B_IE_NACKIE_OFS ( 5)
3948#define EUSCI_B_IE_NACKIE ((uint16_t)0x0020)
3949/* EUSCI_B_IE[BCNTIE] Bits */
3950#define EUSCI_B_IE_BCNTIE_OFS ( 6)
3951#define EUSCI_B_IE_BCNTIE ((uint16_t)0x0040)
3952/* EUSCI_B_IE[CLTOIE] Bits */
3953#define EUSCI_B_IE_CLTOIE_OFS ( 7)
3954#define EUSCI_B_IE_CLTOIE ((uint16_t)0x0080)
3955/* EUSCI_B_IE[RXIE1] Bits */
3956#define EUSCI_B_IE_RXIE1_OFS ( 8)
3957#define EUSCI_B_IE_RXIE1 ((uint16_t)0x0100)
3958/* EUSCI_B_IE[TXIE1] Bits */
3959#define EUSCI_B_IE_TXIE1_OFS ( 9)
3960#define EUSCI_B_IE_TXIE1 ((uint16_t)0x0200)
3961/* EUSCI_B_IE[RXIE2] Bits */
3962#define EUSCI_B_IE_RXIE2_OFS (10)
3963#define EUSCI_B_IE_RXIE2 ((uint16_t)0x0400)
3964/* EUSCI_B_IE[TXIE2] Bits */
3965#define EUSCI_B_IE_TXIE2_OFS (11)
3966#define EUSCI_B_IE_TXIE2 ((uint16_t)0x0800)
3967/* EUSCI_B_IE[RXIE3] Bits */
3968#define EUSCI_B_IE_RXIE3_OFS (12)
3969#define EUSCI_B_IE_RXIE3 ((uint16_t)0x1000)
3970/* EUSCI_B_IE[TXIE3] Bits */
3971#define EUSCI_B_IE_TXIE3_OFS (13)
3972#define EUSCI_B_IE_TXIE3 ((uint16_t)0x2000)
3973/* EUSCI_B_IE[BIT9IE] Bits */
3974#define EUSCI_B_IE_BIT9IE_OFS (14)
3975#define EUSCI_B_IE_BIT9IE ((uint16_t)0x4000)
3976/* EUSCI_B_IE[RXIE] Bits */
3977#define EUSCI_B_IE_RXIE_OFS ( 0)
3978#define EUSCI_B_IE_RXIE ((uint16_t)0x0001)
3979/* EUSCI_B_IE[TXIE] Bits */
3980#define EUSCI_B_IE_TXIE_OFS ( 1)
3981#define EUSCI_B_IE_TXIE ((uint16_t)0x0002)
3982/* EUSCI_B_IFG[RXIFG0] Bits */
3983#define EUSCI_B_IFG_RXIFG0_OFS ( 0)
3984#define EUSCI_B_IFG_RXIFG0 ((uint16_t)0x0001)
3985/* EUSCI_B_IFG[TXIFG0] Bits */
3986#define EUSCI_B_IFG_TXIFG0_OFS ( 1)
3987#define EUSCI_B_IFG_TXIFG0 ((uint16_t)0x0002)
3988/* EUSCI_B_IFG[STTIFG] Bits */
3989#define EUSCI_B_IFG_STTIFG_OFS ( 2)
3990#define EUSCI_B_IFG_STTIFG ((uint16_t)0x0004)
3991/* EUSCI_B_IFG[STPIFG] Bits */
3992#define EUSCI_B_IFG_STPIFG_OFS ( 3)
3993#define EUSCI_B_IFG_STPIFG ((uint16_t)0x0008)
3994/* EUSCI_B_IFG[ALIFG] Bits */
3995#define EUSCI_B_IFG_ALIFG_OFS ( 4)
3996#define EUSCI_B_IFG_ALIFG ((uint16_t)0x0010)
3997/* EUSCI_B_IFG[NACKIFG] Bits */
3998#define EUSCI_B_IFG_NACKIFG_OFS ( 5)
3999#define EUSCI_B_IFG_NACKIFG ((uint16_t)0x0020)
4000/* EUSCI_B_IFG[BCNTIFG] Bits */
4001#define EUSCI_B_IFG_BCNTIFG_OFS ( 6)
4002#define EUSCI_B_IFG_BCNTIFG ((uint16_t)0x0040)
4003/* EUSCI_B_IFG[CLTOIFG] Bits */
4004#define EUSCI_B_IFG_CLTOIFG_OFS ( 7)
4005#define EUSCI_B_IFG_CLTOIFG ((uint16_t)0x0080)
4006/* EUSCI_B_IFG[RXIFG1] Bits */
4007#define EUSCI_B_IFG_RXIFG1_OFS ( 8)
4008#define EUSCI_B_IFG_RXIFG1 ((uint16_t)0x0100)
4009/* EUSCI_B_IFG[TXIFG1] Bits */
4010#define EUSCI_B_IFG_TXIFG1_OFS ( 9)
4011#define EUSCI_B_IFG_TXIFG1 ((uint16_t)0x0200)
4012/* EUSCI_B_IFG[RXIFG2] Bits */
4013#define EUSCI_B_IFG_RXIFG2_OFS (10)
4014#define EUSCI_B_IFG_RXIFG2 ((uint16_t)0x0400)
4015/* EUSCI_B_IFG[TXIFG2] Bits */
4016#define EUSCI_B_IFG_TXIFG2_OFS (11)
4017#define EUSCI_B_IFG_TXIFG2 ((uint16_t)0x0800)
4018/* EUSCI_B_IFG[RXIFG3] Bits */
4019#define EUSCI_B_IFG_RXIFG3_OFS (12)
4020#define EUSCI_B_IFG_RXIFG3 ((uint16_t)0x1000)
4021/* EUSCI_B_IFG[TXIFG3] Bits */
4022#define EUSCI_B_IFG_TXIFG3_OFS (13)
4023#define EUSCI_B_IFG_TXIFG3 ((uint16_t)0x2000)
4024/* EUSCI_B_IFG[BIT9IFG] Bits */
4025#define EUSCI_B_IFG_BIT9IFG_OFS (14)
4026#define EUSCI_B_IFG_BIT9IFG ((uint16_t)0x4000)
4027/* EUSCI_B_IFG[RXIFG] Bits */
4028#define EUSCI_B_IFG_RXIFG_OFS ( 0)
4029#define EUSCI_B_IFG_RXIFG ((uint16_t)0x0001)
4030/* EUSCI_B_IFG[TXIFG] Bits */
4031#define EUSCI_B_IFG_TXIFG_OFS ( 1)
4032#define EUSCI_B_IFG_TXIFG ((uint16_t)0x0002)
4033/* legacy definitions for backward compatibility to version 2100 */
4034#define EUSCI_B__RXIE_OFS EUSCI_B_IE_RXIE_OFS
4035#define EUSCI_B__RXIE EUSCI_B_IE_RXIE
4036#define EUSCI_B__TXIE_OFS EUSCI_B_IE_TXIE_OFS
4037#define EUSCI_B__TXIE EUSCI_B_IE_TXIE
4040/******************************************************************************
4041* FLCTL Bits
4042******************************************************************************/
4043/* FLCTL_POWER_STAT[PSTAT] Bits */
4044#define FLCTL_POWER_STAT_PSTAT_OFS ( 0)
4045#define FLCTL_POWER_STAT_PSTAT_MASK ((uint32_t)0x00000007)
4046#define FLCTL_POWER_STAT_PSTAT0 ((uint32_t)0x00000001)
4047#define FLCTL_POWER_STAT_PSTAT1 ((uint32_t)0x00000002)
4048#define FLCTL_POWER_STAT_PSTAT2 ((uint32_t)0x00000004)
4049#define FLCTL_POWER_STAT_PSTAT_0 ((uint32_t)0x00000000)
4050#define FLCTL_POWER_STAT_PSTAT_1 ((uint32_t)0x00000001)
4051#define FLCTL_POWER_STAT_PSTAT_2 ((uint32_t)0x00000002)
4052#define FLCTL_POWER_STAT_PSTAT_3 ((uint32_t)0x00000003)
4053#define FLCTL_POWER_STAT_PSTAT_4 ((uint32_t)0x00000004)
4054#define FLCTL_POWER_STAT_PSTAT_5 ((uint32_t)0x00000005)
4055#define FLCTL_POWER_STAT_PSTAT_6 ((uint32_t)0x00000006)
4056#define FLCTL_POWER_STAT_PSTAT_7 ((uint32_t)0x00000007)
4057/* FLCTL_POWER_STAT[LDOSTAT] Bits */
4058#define FLCTL_POWER_STAT_LDOSTAT_OFS ( 3)
4059#define FLCTL_POWER_STAT_LDOSTAT ((uint32_t)0x00000008)
4060/* FLCTL_POWER_STAT[VREFSTAT] Bits */
4061#define FLCTL_POWER_STAT_VREFSTAT_OFS ( 4)
4062#define FLCTL_POWER_STAT_VREFSTAT ((uint32_t)0x00000010)
4063/* FLCTL_POWER_STAT[IREFSTAT] Bits */
4064#define FLCTL_POWER_STAT_IREFSTAT_OFS ( 5)
4065#define FLCTL_POWER_STAT_IREFSTAT ((uint32_t)0x00000020)
4066/* FLCTL_POWER_STAT[TRIMSTAT] Bits */
4067#define FLCTL_POWER_STAT_TRIMSTAT_OFS ( 6)
4068#define FLCTL_POWER_STAT_TRIMSTAT ((uint32_t)0x00000040)
4069/* FLCTL_POWER_STAT[RD_2T] Bits */
4070#define FLCTL_POWER_STAT_RD_2T_OFS ( 7)
4071#define FLCTL_POWER_STAT_RD_2T ((uint32_t)0x00000080)
4072/* FLCTL_BANK0_RDCTL[RD_MODE] Bits */
4073#define FLCTL_BANK0_RDCTL_RD_MODE_OFS ( 0)
4074#define FLCTL_BANK0_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F)
4075#define FLCTL_BANK0_RDCTL_RD_MODE0 ((uint32_t)0x00000001)
4076#define FLCTL_BANK0_RDCTL_RD_MODE1 ((uint32_t)0x00000002)
4077#define FLCTL_BANK0_RDCTL_RD_MODE2 ((uint32_t)0x00000004)
4078#define FLCTL_BANK0_RDCTL_RD_MODE3 ((uint32_t)0x00000008)
4079#define FLCTL_BANK0_RDCTL_RD_MODE_0 ((uint32_t)0x00000000)
4080#define FLCTL_BANK0_RDCTL_RD_MODE_1 ((uint32_t)0x00000001)
4081#define FLCTL_BANK0_RDCTL_RD_MODE_2 ((uint32_t)0x00000002)
4082#define FLCTL_BANK0_RDCTL_RD_MODE_3 ((uint32_t)0x00000003)
4083#define FLCTL_BANK0_RDCTL_RD_MODE_4 ((uint32_t)0x00000004)
4084#define FLCTL_BANK0_RDCTL_RD_MODE_5 ((uint32_t)0x00000005)
4085#define FLCTL_BANK0_RDCTL_RD_MODE_9 ((uint32_t)0x00000009)
4086#define FLCTL_BANK0_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A)
4087/* FLCTL_BANK0_RDCTL[BUFI] Bits */
4088#define FLCTL_BANK0_RDCTL_BUFI_OFS ( 4)
4089#define FLCTL_BANK0_RDCTL_BUFI ((uint32_t)0x00000010)
4090/* FLCTL_BANK0_RDCTL[BUFD] Bits */
4091#define FLCTL_BANK0_RDCTL_BUFD_OFS ( 5)
4092#define FLCTL_BANK0_RDCTL_BUFD ((uint32_t)0x00000020)
4093/* FLCTL_BANK0_RDCTL[WAIT] Bits */
4094#define FLCTL_BANK0_RDCTL_WAIT_OFS (12)
4095#define FLCTL_BANK0_RDCTL_WAIT_MASK ((uint32_t)0x0000F000)
4096#define FLCTL_BANK0_RDCTL_WAIT0 ((uint32_t)0x00001000)
4097#define FLCTL_BANK0_RDCTL_WAIT1 ((uint32_t)0x00002000)
4098#define FLCTL_BANK0_RDCTL_WAIT2 ((uint32_t)0x00004000)
4099#define FLCTL_BANK0_RDCTL_WAIT3 ((uint32_t)0x00008000)
4100#define FLCTL_BANK0_RDCTL_WAIT_0 ((uint32_t)0x00000000)
4101#define FLCTL_BANK0_RDCTL_WAIT_1 ((uint32_t)0x00001000)
4102#define FLCTL_BANK0_RDCTL_WAIT_2 ((uint32_t)0x00002000)
4103#define FLCTL_BANK0_RDCTL_WAIT_3 ((uint32_t)0x00003000)
4104#define FLCTL_BANK0_RDCTL_WAIT_4 ((uint32_t)0x00004000)
4105#define FLCTL_BANK0_RDCTL_WAIT_5 ((uint32_t)0x00005000)
4106#define FLCTL_BANK0_RDCTL_WAIT_6 ((uint32_t)0x00006000)
4107#define FLCTL_BANK0_RDCTL_WAIT_7 ((uint32_t)0x00007000)
4108#define FLCTL_BANK0_RDCTL_WAIT_8 ((uint32_t)0x00008000)
4109#define FLCTL_BANK0_RDCTL_WAIT_9 ((uint32_t)0x00009000)
4110#define FLCTL_BANK0_RDCTL_WAIT_10 ((uint32_t)0x0000A000)
4111#define FLCTL_BANK0_RDCTL_WAIT_11 ((uint32_t)0x0000B000)
4112#define FLCTL_BANK0_RDCTL_WAIT_12 ((uint32_t)0x0000C000)
4113#define FLCTL_BANK0_RDCTL_WAIT_13 ((uint32_t)0x0000D000)
4114#define FLCTL_BANK0_RDCTL_WAIT_14 ((uint32_t)0x0000E000)
4115#define FLCTL_BANK0_RDCTL_WAIT_15 ((uint32_t)0x0000F000)
4116/* FLCTL_BANK0_RDCTL[RD_MODE_STATUS] Bits */
4117#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_OFS (16)
4118#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000)
4119#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000)
4120#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000)
4121#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000)
4122#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000)
4123#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000)
4124#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000)
4125#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000)
4126#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000)
4127#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000)
4128#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000)
4129#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000)
4130#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000)
4131/* FLCTL_BANK1_RDCTL[RD_MODE] Bits */
4132#define FLCTL_BANK1_RDCTL_RD_MODE_OFS ( 0)
4133#define FLCTL_BANK1_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F)
4134#define FLCTL_BANK1_RDCTL_RD_MODE0 ((uint32_t)0x00000001)
4135#define FLCTL_BANK1_RDCTL_RD_MODE1 ((uint32_t)0x00000002)
4136#define FLCTL_BANK1_RDCTL_RD_MODE2 ((uint32_t)0x00000004)
4137#define FLCTL_BANK1_RDCTL_RD_MODE3 ((uint32_t)0x00000008)
4138#define FLCTL_BANK1_RDCTL_RD_MODE_0 ((uint32_t)0x00000000)
4139#define FLCTL_BANK1_RDCTL_RD_MODE_1 ((uint32_t)0x00000001)
4140#define FLCTL_BANK1_RDCTL_RD_MODE_2 ((uint32_t)0x00000002)
4141#define FLCTL_BANK1_RDCTL_RD_MODE_3 ((uint32_t)0x00000003)
4142#define FLCTL_BANK1_RDCTL_RD_MODE_4 ((uint32_t)0x00000004)
4143#define FLCTL_BANK1_RDCTL_RD_MODE_5 ((uint32_t)0x00000005)
4144#define FLCTL_BANK1_RDCTL_RD_MODE_9 ((uint32_t)0x00000009)
4145#define FLCTL_BANK1_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A)
4146/* FLCTL_BANK1_RDCTL[BUFI] Bits */
4147#define FLCTL_BANK1_RDCTL_BUFI_OFS ( 4)
4148#define FLCTL_BANK1_RDCTL_BUFI ((uint32_t)0x00000010)
4149/* FLCTL_BANK1_RDCTL[BUFD] Bits */
4150#define FLCTL_BANK1_RDCTL_BUFD_OFS ( 5)
4151#define FLCTL_BANK1_RDCTL_BUFD ((uint32_t)0x00000020)
4152/* FLCTL_BANK1_RDCTL[RD_MODE_STATUS] Bits */
4153#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_OFS (16)
4154#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000)
4155#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000)
4156#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000)
4157#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000)
4158#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000)
4159#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000)
4160#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000)
4161#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000)
4162#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000)
4163#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000)
4164#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000)
4165#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000)
4166#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000)
4167/* FLCTL_BANK1_RDCTL[WAIT] Bits */
4168#define FLCTL_BANK1_RDCTL_WAIT_OFS (12)
4169#define FLCTL_BANK1_RDCTL_WAIT_MASK ((uint32_t)0x0000F000)
4170#define FLCTL_BANK1_RDCTL_WAIT0 ((uint32_t)0x00001000)
4171#define FLCTL_BANK1_RDCTL_WAIT1 ((uint32_t)0x00002000)
4172#define FLCTL_BANK1_RDCTL_WAIT2 ((uint32_t)0x00004000)
4173#define FLCTL_BANK1_RDCTL_WAIT3 ((uint32_t)0x00008000)
4174#define FLCTL_BANK1_RDCTL_WAIT_0 ((uint32_t)0x00000000)
4175#define FLCTL_BANK1_RDCTL_WAIT_1 ((uint32_t)0x00001000)
4176#define FLCTL_BANK1_RDCTL_WAIT_2 ((uint32_t)0x00002000)
4177#define FLCTL_BANK1_RDCTL_WAIT_3 ((uint32_t)0x00003000)
4178#define FLCTL_BANK1_RDCTL_WAIT_4 ((uint32_t)0x00004000)
4179#define FLCTL_BANK1_RDCTL_WAIT_5 ((uint32_t)0x00005000)
4180#define FLCTL_BANK1_RDCTL_WAIT_6 ((uint32_t)0x00006000)
4181#define FLCTL_BANK1_RDCTL_WAIT_7 ((uint32_t)0x00007000)
4182#define FLCTL_BANK1_RDCTL_WAIT_8 ((uint32_t)0x00008000)
4183#define FLCTL_BANK1_RDCTL_WAIT_9 ((uint32_t)0x00009000)
4184#define FLCTL_BANK1_RDCTL_WAIT_10 ((uint32_t)0x0000A000)
4185#define FLCTL_BANK1_RDCTL_WAIT_11 ((uint32_t)0x0000B000)
4186#define FLCTL_BANK1_RDCTL_WAIT_12 ((uint32_t)0x0000C000)
4187#define FLCTL_BANK1_RDCTL_WAIT_13 ((uint32_t)0x0000D000)
4188#define FLCTL_BANK1_RDCTL_WAIT_14 ((uint32_t)0x0000E000)
4189#define FLCTL_BANK1_RDCTL_WAIT_15 ((uint32_t)0x0000F000)
4190/* FLCTL_RDBRST_CTLSTAT[START] Bits */
4191#define FLCTL_RDBRST_CTLSTAT_START_OFS ( 0)
4192#define FLCTL_RDBRST_CTLSTAT_START ((uint32_t)0x00000001)
4193/* FLCTL_RDBRST_CTLSTAT[MEM_TYPE] Bits */
4194#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_OFS ( 1)
4195#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_MASK ((uint32_t)0x00000006)
4196#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE0 ((uint32_t)0x00000002)
4197#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE1 ((uint32_t)0x00000004)
4198#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0 ((uint32_t)0x00000000)
4199#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1 ((uint32_t)0x00000002)
4200#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_2 ((uint32_t)0x00000004)
4201#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_3 ((uint32_t)0x00000006)
4202/* FLCTL_RDBRST_CTLSTAT[STOP_FAIL] Bits */
4203#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL_OFS ( 3)
4204#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL ((uint32_t)0x00000008)
4205/* FLCTL_RDBRST_CTLSTAT[DATA_CMP] Bits */
4206#define FLCTL_RDBRST_CTLSTAT_DATA_CMP_OFS ( 4)
4207#define FLCTL_RDBRST_CTLSTAT_DATA_CMP ((uint32_t)0x00000010)
4208/* FLCTL_RDBRST_CTLSTAT[TEST_EN] Bits */
4209#define FLCTL_RDBRST_CTLSTAT_TEST_EN_OFS ( 6)
4210#define FLCTL_RDBRST_CTLSTAT_TEST_EN ((uint32_t)0x00000040)
4211/* FLCTL_RDBRST_CTLSTAT[BRST_STAT] Bits */
4212#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_OFS (16)
4213#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_MASK ((uint32_t)0x00030000)
4214#define FLCTL_RDBRST_CTLSTAT_BRST_STAT0 ((uint32_t)0x00010000)
4215#define FLCTL_RDBRST_CTLSTAT_BRST_STAT1 ((uint32_t)0x00020000)
4216#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_0 ((uint32_t)0x00000000)
4217#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_1 ((uint32_t)0x00010000)
4218#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_2 ((uint32_t)0x00020000)
4219#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_3 ((uint32_t)0x00030000)
4220 /* explicitly cleared by SW) */
4221/* FLCTL_RDBRST_CTLSTAT[CMP_ERR] Bits */
4222#define FLCTL_RDBRST_CTLSTAT_CMP_ERR_OFS (18)
4223#define FLCTL_RDBRST_CTLSTAT_CMP_ERR ((uint32_t)0x00040000)
4224/* FLCTL_RDBRST_CTLSTAT[ADDR_ERR] Bits */
4225#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR_OFS (19)
4226#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00080000)
4227/* FLCTL_RDBRST_CTLSTAT[CLR_STAT] Bits */
4228#define FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS (23)
4229#define FLCTL_RDBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000)
4230/* FLCTL_RDBRST_STARTADDR[START_ADDRESS] Bits */
4231#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0)
4232#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x001FFFFF)
4233/* FLCTL_RDBRST_LEN[BURST_LENGTH] Bits */
4234#define FLCTL_RDBRST_LEN_BURST_LENGTH_OFS ( 0)
4235#define FLCTL_RDBRST_LEN_BURST_LENGTH_MASK ((uint32_t)0x001FFFFF)
4236/* FLCTL_RDBRST_FAILADDR[FAIL_ADDRESS] Bits */
4237#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_OFS ( 0)
4238#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_MASK ((uint32_t)0x001FFFFF)
4239/* FLCTL_RDBRST_FAILCNT[FAIL_COUNT] Bits */
4240#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_OFS ( 0)
4241#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_MASK ((uint32_t)0x0001FFFF)
4242/* FLCTL_PRG_CTLSTAT[ENABLE] Bits */
4243#define FLCTL_PRG_CTLSTAT_ENABLE_OFS ( 0)
4244#define FLCTL_PRG_CTLSTAT_ENABLE ((uint32_t)0x00000001)
4245/* FLCTL_PRG_CTLSTAT[MODE] Bits */
4246#define FLCTL_PRG_CTLSTAT_MODE_OFS ( 1)
4247#define FLCTL_PRG_CTLSTAT_MODE ((uint32_t)0x00000002)
4248/* FLCTL_PRG_CTLSTAT[VER_PRE] Bits */
4249#define FLCTL_PRG_CTLSTAT_VER_PRE_OFS ( 2)
4250#define FLCTL_PRG_CTLSTAT_VER_PRE ((uint32_t)0x00000004)
4251/* FLCTL_PRG_CTLSTAT[VER_PST] Bits */
4252#define FLCTL_PRG_CTLSTAT_VER_PST_OFS ( 3)
4253#define FLCTL_PRG_CTLSTAT_VER_PST ((uint32_t)0x00000008)
4254/* FLCTL_PRG_CTLSTAT[STATUS] Bits */
4255#define FLCTL_PRG_CTLSTAT_STATUS_OFS (16)
4256#define FLCTL_PRG_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000)
4257#define FLCTL_PRG_CTLSTAT_STATUS0 ((uint32_t)0x00010000)
4258#define FLCTL_PRG_CTLSTAT_STATUS1 ((uint32_t)0x00020000)
4259#define FLCTL_PRG_CTLSTAT_STATUS_0 ((uint32_t)0x00000000)
4260#define FLCTL_PRG_CTLSTAT_STATUS_1 ((uint32_t)0x00010000)
4261#define FLCTL_PRG_CTLSTAT_STATUS_2 ((uint32_t)0x00020000)
4262#define FLCTL_PRG_CTLSTAT_STATUS_3 ((uint32_t)0x00030000)
4263/* FLCTL_PRG_CTLSTAT[BNK_ACT] Bits */
4264#define FLCTL_PRG_CTLSTAT_BNK_ACT_OFS (18)
4265#define FLCTL_PRG_CTLSTAT_BNK_ACT ((uint32_t)0x00040000)
4266/* FLCTL_PRGBRST_CTLSTAT[START] Bits */
4267#define FLCTL_PRGBRST_CTLSTAT_START_OFS ( 0)
4268#define FLCTL_PRGBRST_CTLSTAT_START ((uint32_t)0x00000001)
4269/* FLCTL_PRGBRST_CTLSTAT[TYPE] Bits */
4270#define FLCTL_PRGBRST_CTLSTAT_TYPE_OFS ( 1)
4271#define FLCTL_PRGBRST_CTLSTAT_TYPE_MASK ((uint32_t)0x00000006)
4272#define FLCTL_PRGBRST_CTLSTAT_TYPE0 ((uint32_t)0x00000002)
4273#define FLCTL_PRGBRST_CTLSTAT_TYPE1 ((uint32_t)0x00000004)
4274#define FLCTL_PRGBRST_CTLSTAT_TYPE_0 ((uint32_t)0x00000000)
4275#define FLCTL_PRGBRST_CTLSTAT_TYPE_1 ((uint32_t)0x00000002)
4276#define FLCTL_PRGBRST_CTLSTAT_TYPE_2 ((uint32_t)0x00000004)
4277#define FLCTL_PRGBRST_CTLSTAT_TYPE_3 ((uint32_t)0x00000006)
4278/* FLCTL_PRGBRST_CTLSTAT[LEN] Bits */
4279#define FLCTL_PRGBRST_CTLSTAT_LEN_OFS ( 3)
4280#define FLCTL_PRGBRST_CTLSTAT_LEN_MASK ((uint32_t)0x00000038)
4281#define FLCTL_PRGBRST_CTLSTAT_LEN0 ((uint32_t)0x00000008)
4282#define FLCTL_PRGBRST_CTLSTAT_LEN1 ((uint32_t)0x00000010)
4283#define FLCTL_PRGBRST_CTLSTAT_LEN2 ((uint32_t)0x00000020)
4284#define FLCTL_PRGBRST_CTLSTAT_LEN_0 ((uint32_t)0x00000000)
4285#define FLCTL_PRGBRST_CTLSTAT_LEN_1 ((uint32_t)0x00000008)
4286 /* FLCTL_PRGBRST_STARTADDR Register */
4287#define FLCTL_PRGBRST_CTLSTAT_LEN_2 ((uint32_t)0x00000010)
4288 /* Register */
4289#define FLCTL_PRGBRST_CTLSTAT_LEN_3 ((uint32_t)0x00000018)
4290 /* Register */
4291#define FLCTL_PRGBRST_CTLSTAT_LEN_4 ((uint32_t)0x00000020)
4292 /* Register */
4293/* FLCTL_PRGBRST_CTLSTAT[AUTO_PRE] Bits */
4294#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS ( 6)
4295#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE ((uint32_t)0x00000040)
4296/* FLCTL_PRGBRST_CTLSTAT[AUTO_PST] Bits */
4297#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS ( 7)
4298#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST ((uint32_t)0x00000080)
4299/* FLCTL_PRGBRST_CTLSTAT[BURST_STATUS] Bits */
4300#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_OFS (16)
4301#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK ((uint32_t)0x00070000)
4302#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS0 ((uint32_t)0x00010000)
4303#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS1 ((uint32_t)0x00020000)
4304#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS2 ((uint32_t)0x00040000)
4305#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0 ((uint32_t)0x00000000)
4306#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_1 ((uint32_t)0x00010000)
4307#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_2 ((uint32_t)0x00020000)
4308#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_3 ((uint32_t)0x00030000)
4309#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_4 ((uint32_t)0x00040000)
4310#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_5 ((uint32_t)0x00050000)
4311#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_6 ((uint32_t)0x00060000)
4312#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_7 ((uint32_t)0x00070000)
4313 /* explicitly cleared by SW) */
4314/* FLCTL_PRGBRST_CTLSTAT[PRE_ERR] Bits */
4315#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR_OFS (19)
4316#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR ((uint32_t)0x00080000)
4317/* FLCTL_PRGBRST_CTLSTAT[PST_ERR] Bits */
4318#define FLCTL_PRGBRST_CTLSTAT_PST_ERR_OFS (20)
4319#define FLCTL_PRGBRST_CTLSTAT_PST_ERR ((uint32_t)0x00100000)
4320/* FLCTL_PRGBRST_CTLSTAT[ADDR_ERR] Bits */
4321#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR_OFS (21)
4322#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00200000)
4323/* FLCTL_PRGBRST_CTLSTAT[CLR_STAT] Bits */
4324#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS (23)
4325#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000)
4326/* FLCTL_PRGBRST_STARTADDR[START_ADDRESS] Bits */
4327#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0)
4328#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x003FFFFF)
4329/* FLCTL_ERASE_CTLSTAT[START] Bits */
4330#define FLCTL_ERASE_CTLSTAT_START_OFS ( 0)
4331#define FLCTL_ERASE_CTLSTAT_START ((uint32_t)0x00000001)
4332/* FLCTL_ERASE_CTLSTAT[MODE] Bits */
4333#define FLCTL_ERASE_CTLSTAT_MODE_OFS ( 1)
4334#define FLCTL_ERASE_CTLSTAT_MODE ((uint32_t)0x00000002)
4335/* FLCTL_ERASE_CTLSTAT[TYPE] Bits */
4336#define FLCTL_ERASE_CTLSTAT_TYPE_OFS ( 2)
4337#define FLCTL_ERASE_CTLSTAT_TYPE_MASK ((uint32_t)0x0000000C)
4338#define FLCTL_ERASE_CTLSTAT_TYPE0 ((uint32_t)0x00000004)
4339#define FLCTL_ERASE_CTLSTAT_TYPE1 ((uint32_t)0x00000008)
4340#define FLCTL_ERASE_CTLSTAT_TYPE_0 ((uint32_t)0x00000000)
4341#define FLCTL_ERASE_CTLSTAT_TYPE_1 ((uint32_t)0x00000004)
4342#define FLCTL_ERASE_CTLSTAT_TYPE_2 ((uint32_t)0x00000008)
4343#define FLCTL_ERASE_CTLSTAT_TYPE_3 ((uint32_t)0x0000000C)
4344/* FLCTL_ERASE_CTLSTAT[STATUS] Bits */
4345#define FLCTL_ERASE_CTLSTAT_STATUS_OFS (16)
4346#define FLCTL_ERASE_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000)
4347#define FLCTL_ERASE_CTLSTAT_STATUS0 ((uint32_t)0x00010000)
4348#define FLCTL_ERASE_CTLSTAT_STATUS1 ((uint32_t)0x00020000)
4349#define FLCTL_ERASE_CTLSTAT_STATUS_0 ((uint32_t)0x00000000)
4350#define FLCTL_ERASE_CTLSTAT_STATUS_1 ((uint32_t)0x00010000)
4351#define FLCTL_ERASE_CTLSTAT_STATUS_2 ((uint32_t)0x00020000)
4352#define FLCTL_ERASE_CTLSTAT_STATUS_3 ((uint32_t)0x00030000)
4353 /* unless explicitly cleared by SW) */
4354/* FLCTL_ERASE_CTLSTAT[ADDR_ERR] Bits */
4355#define FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS (18)
4356#define FLCTL_ERASE_CTLSTAT_ADDR_ERR ((uint32_t)0x00040000)
4357 /* address */
4358/* FLCTL_ERASE_CTLSTAT[CLR_STAT] Bits */
4359#define FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS (19)
4360#define FLCTL_ERASE_CTLSTAT_CLR_STAT ((uint32_t)0x00080000)
4361/* FLCTL_ERASE_SECTADDR[SECT_ADDRESS] Bits */
4362#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_OFS ( 0)
4363#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_MASK ((uint32_t)0x003FFFFF)
4364/* FLCTL_BANK0_INFO_WEPROT[PROT0] Bits */
4365#define FLCTL_BANK0_INFO_WEPROT_PROT0_OFS ( 0)
4366#define FLCTL_BANK0_INFO_WEPROT_PROT0 ((uint32_t)0x00000001)
4367/* FLCTL_BANK0_INFO_WEPROT[PROT1] Bits */
4368#define FLCTL_BANK0_INFO_WEPROT_PROT1_OFS ( 1)
4369#define FLCTL_BANK0_INFO_WEPROT_PROT1 ((uint32_t)0x00000002)
4370/* FLCTL_BANK0_MAIN_WEPROT[PROT0] Bits */
4371#define FLCTL_BANK0_MAIN_WEPROT_PROT0_OFS ( 0)
4372#define FLCTL_BANK0_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001)
4373/* FLCTL_BANK0_MAIN_WEPROT[PROT1] Bits */
4374#define FLCTL_BANK0_MAIN_WEPROT_PROT1_OFS ( 1)
4375#define FLCTL_BANK0_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002)
4376/* FLCTL_BANK0_MAIN_WEPROT[PROT2] Bits */
4377#define FLCTL_BANK0_MAIN_WEPROT_PROT2_OFS ( 2)
4378#define FLCTL_BANK0_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004)
4379/* FLCTL_BANK0_MAIN_WEPROT[PROT3] Bits */
4380#define FLCTL_BANK0_MAIN_WEPROT_PROT3_OFS ( 3)
4381#define FLCTL_BANK0_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008)
4382/* FLCTL_BANK0_MAIN_WEPROT[PROT4] Bits */
4383#define FLCTL_BANK0_MAIN_WEPROT_PROT4_OFS ( 4)
4384#define FLCTL_BANK0_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010)
4385/* FLCTL_BANK0_MAIN_WEPROT[PROT5] Bits */
4386#define FLCTL_BANK0_MAIN_WEPROT_PROT5_OFS ( 5)
4387#define FLCTL_BANK0_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020)
4388/* FLCTL_BANK0_MAIN_WEPROT[PROT6] Bits */
4389#define FLCTL_BANK0_MAIN_WEPROT_PROT6_OFS ( 6)
4390#define FLCTL_BANK0_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040)
4391/* FLCTL_BANK0_MAIN_WEPROT[PROT7] Bits */
4392#define FLCTL_BANK0_MAIN_WEPROT_PROT7_OFS ( 7)
4393#define FLCTL_BANK0_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080)
4394/* FLCTL_BANK0_MAIN_WEPROT[PROT8] Bits */
4395#define FLCTL_BANK0_MAIN_WEPROT_PROT8_OFS ( 8)
4396#define FLCTL_BANK0_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100)
4397/* FLCTL_BANK0_MAIN_WEPROT[PROT9] Bits */
4398#define FLCTL_BANK0_MAIN_WEPROT_PROT9_OFS ( 9)
4399#define FLCTL_BANK0_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200)
4400/* FLCTL_BANK0_MAIN_WEPROT[PROT10] Bits */
4401#define FLCTL_BANK0_MAIN_WEPROT_PROT10_OFS (10)
4402#define FLCTL_BANK0_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400)
4403/* FLCTL_BANK0_MAIN_WEPROT[PROT11] Bits */
4404#define FLCTL_BANK0_MAIN_WEPROT_PROT11_OFS (11)
4405#define FLCTL_BANK0_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800)
4406/* FLCTL_BANK0_MAIN_WEPROT[PROT12] Bits */
4407#define FLCTL_BANK0_MAIN_WEPROT_PROT12_OFS (12)
4408#define FLCTL_BANK0_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000)
4409/* FLCTL_BANK0_MAIN_WEPROT[PROT13] Bits */
4410#define FLCTL_BANK0_MAIN_WEPROT_PROT13_OFS (13)
4411#define FLCTL_BANK0_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000)
4412/* FLCTL_BANK0_MAIN_WEPROT[PROT14] Bits */
4413#define FLCTL_BANK0_MAIN_WEPROT_PROT14_OFS (14)
4414#define FLCTL_BANK0_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000)
4415/* FLCTL_BANK0_MAIN_WEPROT[PROT15] Bits */
4416#define FLCTL_BANK0_MAIN_WEPROT_PROT15_OFS (15)
4417#define FLCTL_BANK0_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000)
4418/* FLCTL_BANK0_MAIN_WEPROT[PROT16] Bits */
4419#define FLCTL_BANK0_MAIN_WEPROT_PROT16_OFS (16)
4420#define FLCTL_BANK0_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000)
4421/* FLCTL_BANK0_MAIN_WEPROT[PROT17] Bits */
4422#define FLCTL_BANK0_MAIN_WEPROT_PROT17_OFS (17)
4423#define FLCTL_BANK0_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000)
4424/* FLCTL_BANK0_MAIN_WEPROT[PROT18] Bits */
4425#define FLCTL_BANK0_MAIN_WEPROT_PROT18_OFS (18)
4426#define FLCTL_BANK0_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000)
4427/* FLCTL_BANK0_MAIN_WEPROT[PROT19] Bits */
4428#define FLCTL_BANK0_MAIN_WEPROT_PROT19_OFS (19)
4429#define FLCTL_BANK0_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000)
4430/* FLCTL_BANK0_MAIN_WEPROT[PROT20] Bits */
4431#define FLCTL_BANK0_MAIN_WEPROT_PROT20_OFS (20)
4432#define FLCTL_BANK0_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000)
4433/* FLCTL_BANK0_MAIN_WEPROT[PROT21] Bits */
4434#define FLCTL_BANK0_MAIN_WEPROT_PROT21_OFS (21)
4435#define FLCTL_BANK0_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000)
4436/* FLCTL_BANK0_MAIN_WEPROT[PROT22] Bits */
4437#define FLCTL_BANK0_MAIN_WEPROT_PROT22_OFS (22)
4438#define FLCTL_BANK0_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000)
4439/* FLCTL_BANK0_MAIN_WEPROT[PROT23] Bits */
4440#define FLCTL_BANK0_MAIN_WEPROT_PROT23_OFS (23)
4441#define FLCTL_BANK0_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000)
4442/* FLCTL_BANK0_MAIN_WEPROT[PROT24] Bits */
4443#define FLCTL_BANK0_MAIN_WEPROT_PROT24_OFS (24)
4444#define FLCTL_BANK0_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000)
4445/* FLCTL_BANK0_MAIN_WEPROT[PROT25] Bits */
4446#define FLCTL_BANK0_MAIN_WEPROT_PROT25_OFS (25)
4447#define FLCTL_BANK0_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000)
4448/* FLCTL_BANK0_MAIN_WEPROT[PROT26] Bits */
4449#define FLCTL_BANK0_MAIN_WEPROT_PROT26_OFS (26)
4450#define FLCTL_BANK0_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000)
4451/* FLCTL_BANK0_MAIN_WEPROT[PROT27] Bits */
4452#define FLCTL_BANK0_MAIN_WEPROT_PROT27_OFS (27)
4453#define FLCTL_BANK0_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000)
4454/* FLCTL_BANK0_MAIN_WEPROT[PROT28] Bits */
4455#define FLCTL_BANK0_MAIN_WEPROT_PROT28_OFS (28)
4456#define FLCTL_BANK0_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000)
4457/* FLCTL_BANK0_MAIN_WEPROT[PROT29] Bits */
4458#define FLCTL_BANK0_MAIN_WEPROT_PROT29_OFS (29)
4459#define FLCTL_BANK0_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000)
4460/* FLCTL_BANK0_MAIN_WEPROT[PROT30] Bits */
4461#define FLCTL_BANK0_MAIN_WEPROT_PROT30_OFS (30)
4462#define FLCTL_BANK0_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000)
4463/* FLCTL_BANK0_MAIN_WEPROT[PROT31] Bits */
4464#define FLCTL_BANK0_MAIN_WEPROT_PROT31_OFS (31)
4465#define FLCTL_BANK0_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000)
4466/* FLCTL_BANK1_INFO_WEPROT[PROT0] Bits */
4467#define FLCTL_BANK1_INFO_WEPROT_PROT0_OFS ( 0)
4468#define FLCTL_BANK1_INFO_WEPROT_PROT0 ((uint32_t)0x00000001)
4469/* FLCTL_BANK1_INFO_WEPROT[PROT1] Bits */
4470#define FLCTL_BANK1_INFO_WEPROT_PROT1_OFS ( 1)
4471#define FLCTL_BANK1_INFO_WEPROT_PROT1 ((uint32_t)0x00000002)
4472/* FLCTL_BANK1_MAIN_WEPROT[PROT0] Bits */
4473#define FLCTL_BANK1_MAIN_WEPROT_PROT0_OFS ( 0)
4474#define FLCTL_BANK1_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001)
4475/* FLCTL_BANK1_MAIN_WEPROT[PROT1] Bits */
4476#define FLCTL_BANK1_MAIN_WEPROT_PROT1_OFS ( 1)
4477#define FLCTL_BANK1_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002)
4478/* FLCTL_BANK1_MAIN_WEPROT[PROT2] Bits */
4479#define FLCTL_BANK1_MAIN_WEPROT_PROT2_OFS ( 2)
4480#define FLCTL_BANK1_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004)
4481/* FLCTL_BANK1_MAIN_WEPROT[PROT3] Bits */
4482#define FLCTL_BANK1_MAIN_WEPROT_PROT3_OFS ( 3)
4483#define FLCTL_BANK1_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008)
4484/* FLCTL_BANK1_MAIN_WEPROT[PROT4] Bits */
4485#define FLCTL_BANK1_MAIN_WEPROT_PROT4_OFS ( 4)
4486#define FLCTL_BANK1_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010)
4487/* FLCTL_BANK1_MAIN_WEPROT[PROT5] Bits */
4488#define FLCTL_BANK1_MAIN_WEPROT_PROT5_OFS ( 5)
4489#define FLCTL_BANK1_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020)
4490/* FLCTL_BANK1_MAIN_WEPROT[PROT6] Bits */
4491#define FLCTL_BANK1_MAIN_WEPROT_PROT6_OFS ( 6)
4492#define FLCTL_BANK1_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040)
4493/* FLCTL_BANK1_MAIN_WEPROT[PROT7] Bits */
4494#define FLCTL_BANK1_MAIN_WEPROT_PROT7_OFS ( 7)
4495#define FLCTL_BANK1_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080)
4496/* FLCTL_BANK1_MAIN_WEPROT[PROT8] Bits */
4497#define FLCTL_BANK1_MAIN_WEPROT_PROT8_OFS ( 8)
4498#define FLCTL_BANK1_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100)
4499/* FLCTL_BANK1_MAIN_WEPROT[PROT9] Bits */
4500#define FLCTL_BANK1_MAIN_WEPROT_PROT9_OFS ( 9)
4501#define FLCTL_BANK1_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200)
4502/* FLCTL_BANK1_MAIN_WEPROT[PROT10] Bits */
4503#define FLCTL_BANK1_MAIN_WEPROT_PROT10_OFS (10)
4504#define FLCTL_BANK1_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400)
4505/* FLCTL_BANK1_MAIN_WEPROT[PROT11] Bits */
4506#define FLCTL_BANK1_MAIN_WEPROT_PROT11_OFS (11)
4507#define FLCTL_BANK1_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800)
4508/* FLCTL_BANK1_MAIN_WEPROT[PROT12] Bits */
4509#define FLCTL_BANK1_MAIN_WEPROT_PROT12_OFS (12)
4510#define FLCTL_BANK1_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000)
4511/* FLCTL_BANK1_MAIN_WEPROT[PROT13] Bits */
4512#define FLCTL_BANK1_MAIN_WEPROT_PROT13_OFS (13)
4513#define FLCTL_BANK1_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000)
4514/* FLCTL_BANK1_MAIN_WEPROT[PROT14] Bits */
4515#define FLCTL_BANK1_MAIN_WEPROT_PROT14_OFS (14)
4516#define FLCTL_BANK1_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000)
4517/* FLCTL_BANK1_MAIN_WEPROT[PROT15] Bits */
4518#define FLCTL_BANK1_MAIN_WEPROT_PROT15_OFS (15)
4519#define FLCTL_BANK1_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000)
4520/* FLCTL_BANK1_MAIN_WEPROT[PROT16] Bits */
4521#define FLCTL_BANK1_MAIN_WEPROT_PROT16_OFS (16)
4522#define FLCTL_BANK1_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000)
4523/* FLCTL_BANK1_MAIN_WEPROT[PROT17] Bits */
4524#define FLCTL_BANK1_MAIN_WEPROT_PROT17_OFS (17)
4525#define FLCTL_BANK1_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000)
4526/* FLCTL_BANK1_MAIN_WEPROT[PROT18] Bits */
4527#define FLCTL_BANK1_MAIN_WEPROT_PROT18_OFS (18)
4528#define FLCTL_BANK1_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000)
4529/* FLCTL_BANK1_MAIN_WEPROT[PROT19] Bits */
4530#define FLCTL_BANK1_MAIN_WEPROT_PROT19_OFS (19)
4531#define FLCTL_BANK1_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000)
4532/* FLCTL_BANK1_MAIN_WEPROT[PROT20] Bits */
4533#define FLCTL_BANK1_MAIN_WEPROT_PROT20_OFS (20)
4534#define FLCTL_BANK1_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000)
4535/* FLCTL_BANK1_MAIN_WEPROT[PROT21] Bits */
4536#define FLCTL_BANK1_MAIN_WEPROT_PROT21_OFS (21)
4537#define FLCTL_BANK1_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000)
4538/* FLCTL_BANK1_MAIN_WEPROT[PROT22] Bits */
4539#define FLCTL_BANK1_MAIN_WEPROT_PROT22_OFS (22)
4540#define FLCTL_BANK1_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000)
4541/* FLCTL_BANK1_MAIN_WEPROT[PROT23] Bits */
4542#define FLCTL_BANK1_MAIN_WEPROT_PROT23_OFS (23)
4543#define FLCTL_BANK1_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000)
4544/* FLCTL_BANK1_MAIN_WEPROT[PROT24] Bits */
4545#define FLCTL_BANK1_MAIN_WEPROT_PROT24_OFS (24)
4546#define FLCTL_BANK1_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000)
4547/* FLCTL_BANK1_MAIN_WEPROT[PROT25] Bits */
4548#define FLCTL_BANK1_MAIN_WEPROT_PROT25_OFS (25)
4549#define FLCTL_BANK1_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000)
4550/* FLCTL_BANK1_MAIN_WEPROT[PROT26] Bits */
4551#define FLCTL_BANK1_MAIN_WEPROT_PROT26_OFS (26)
4552#define FLCTL_BANK1_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000)
4553/* FLCTL_BANK1_MAIN_WEPROT[PROT27] Bits */
4554#define FLCTL_BANK1_MAIN_WEPROT_PROT27_OFS (27)
4555#define FLCTL_BANK1_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000)
4556/* FLCTL_BANK1_MAIN_WEPROT[PROT28] Bits */
4557#define FLCTL_BANK1_MAIN_WEPROT_PROT28_OFS (28)
4558#define FLCTL_BANK1_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000)
4559/* FLCTL_BANK1_MAIN_WEPROT[PROT29] Bits */
4560#define FLCTL_BANK1_MAIN_WEPROT_PROT29_OFS (29)
4561#define FLCTL_BANK1_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000)
4562/* FLCTL_BANK1_MAIN_WEPROT[PROT30] Bits */
4563#define FLCTL_BANK1_MAIN_WEPROT_PROT30_OFS (30)
4564#define FLCTL_BANK1_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000)
4565/* FLCTL_BANK1_MAIN_WEPROT[PROT31] Bits */
4566#define FLCTL_BANK1_MAIN_WEPROT_PROT31_OFS (31)
4567#define FLCTL_BANK1_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000)
4568/* FLCTL_BMRK_CTLSTAT[I_BMRK] Bits */
4569#define FLCTL_BMRK_CTLSTAT_I_BMRK_OFS ( 0)
4570#define FLCTL_BMRK_CTLSTAT_I_BMRK ((uint32_t)0x00000001)
4571/* FLCTL_BMRK_CTLSTAT[D_BMRK] Bits */
4572#define FLCTL_BMRK_CTLSTAT_D_BMRK_OFS ( 1)
4573#define FLCTL_BMRK_CTLSTAT_D_BMRK ((uint32_t)0x00000002)
4574/* FLCTL_BMRK_CTLSTAT[CMP_EN] Bits */
4575#define FLCTL_BMRK_CTLSTAT_CMP_EN_OFS ( 2)
4576#define FLCTL_BMRK_CTLSTAT_CMP_EN ((uint32_t)0x00000004)
4577/* FLCTL_BMRK_CTLSTAT[CMP_SEL] Bits */
4578#define FLCTL_BMRK_CTLSTAT_CMP_SEL_OFS ( 3)
4579#define FLCTL_BMRK_CTLSTAT_CMP_SEL ((uint32_t)0x00000008)
4580/* FLCTL_IFG[RDBRST] Bits */
4581#define FLCTL_IFG_RDBRST_OFS ( 0)
4582#define FLCTL_IFG_RDBRST ((uint32_t)0x00000001)
4583/* FLCTL_IFG[AVPRE] Bits */
4584#define FLCTL_IFG_AVPRE_OFS ( 1)
4585#define FLCTL_IFG_AVPRE ((uint32_t)0x00000002)
4586/* FLCTL_IFG[AVPST] Bits */
4587#define FLCTL_IFG_AVPST_OFS ( 2)
4588#define FLCTL_IFG_AVPST ((uint32_t)0x00000004)
4589/* FLCTL_IFG[PRG] Bits */
4590#define FLCTL_IFG_PRG_OFS ( 3)
4591#define FLCTL_IFG_PRG ((uint32_t)0x00000008)
4592/* FLCTL_IFG[PRGB] Bits */
4593#define FLCTL_IFG_PRGB_OFS ( 4)
4594#define FLCTL_IFG_PRGB ((uint32_t)0x00000010)
4595/* FLCTL_IFG[ERASE] Bits */
4596#define FLCTL_IFG_ERASE_OFS ( 5)
4597#define FLCTL_IFG_ERASE ((uint32_t)0x00000020)
4598/* FLCTL_IFG[BMRK] Bits */
4599#define FLCTL_IFG_BMRK_OFS ( 8)
4600#define FLCTL_IFG_BMRK ((uint32_t)0x00000100)
4601/* FLCTL_IFG[PRG_ERR] Bits */
4602#define FLCTL_IFG_PRG_ERR_OFS ( 9)
4603#define FLCTL_IFG_PRG_ERR ((uint32_t)0x00000200)
4604/* FLCTL_IE[RDBRST] Bits */
4605#define FLCTL_IE_RDBRST_OFS ( 0)
4606#define FLCTL_IE_RDBRST ((uint32_t)0x00000001)
4607/* FLCTL_IE[AVPRE] Bits */
4608#define FLCTL_IE_AVPRE_OFS ( 1)
4609#define FLCTL_IE_AVPRE ((uint32_t)0x00000002)
4610/* FLCTL_IE[AVPST] Bits */
4611#define FLCTL_IE_AVPST_OFS ( 2)
4612#define FLCTL_IE_AVPST ((uint32_t)0x00000004)
4613/* FLCTL_IE[PRG] Bits */
4614#define FLCTL_IE_PRG_OFS ( 3)
4615#define FLCTL_IE_PRG ((uint32_t)0x00000008)
4616/* FLCTL_IE[PRGB] Bits */
4617#define FLCTL_IE_PRGB_OFS ( 4)
4618#define FLCTL_IE_PRGB ((uint32_t)0x00000010)
4619/* FLCTL_IE[ERASE] Bits */
4620#define FLCTL_IE_ERASE_OFS ( 5)
4621#define FLCTL_IE_ERASE ((uint32_t)0x00000020)
4622/* FLCTL_IE[BMRK] Bits */
4623#define FLCTL_IE_BMRK_OFS ( 8)
4624#define FLCTL_IE_BMRK ((uint32_t)0x00000100)
4625/* FLCTL_IE[PRG_ERR] Bits */
4626#define FLCTL_IE_PRG_ERR_OFS ( 9)
4627#define FLCTL_IE_PRG_ERR ((uint32_t)0x00000200)
4628/* FLCTL_CLRIFG[RDBRST] Bits */
4629#define FLCTL_CLRIFG_RDBRST_OFS ( 0)
4630#define FLCTL_CLRIFG_RDBRST ((uint32_t)0x00000001)
4631/* FLCTL_CLRIFG[AVPRE] Bits */
4632#define FLCTL_CLRIFG_AVPRE_OFS ( 1)
4633#define FLCTL_CLRIFG_AVPRE ((uint32_t)0x00000002)
4634/* FLCTL_CLRIFG[AVPST] Bits */
4635#define FLCTL_CLRIFG_AVPST_OFS ( 2)
4636#define FLCTL_CLRIFG_AVPST ((uint32_t)0x00000004)
4637/* FLCTL_CLRIFG[PRG] Bits */
4638#define FLCTL_CLRIFG_PRG_OFS ( 3)
4639#define FLCTL_CLRIFG_PRG ((uint32_t)0x00000008)
4640/* FLCTL_CLRIFG[PRGB] Bits */
4641#define FLCTL_CLRIFG_PRGB_OFS ( 4)
4642#define FLCTL_CLRIFG_PRGB ((uint32_t)0x00000010)
4643/* FLCTL_CLRIFG[ERASE] Bits */
4644#define FLCTL_CLRIFG_ERASE_OFS ( 5)
4645#define FLCTL_CLRIFG_ERASE ((uint32_t)0x00000020)
4646/* FLCTL_CLRIFG[BMRK] Bits */
4647#define FLCTL_CLRIFG_BMRK_OFS ( 8)
4648#define FLCTL_CLRIFG_BMRK ((uint32_t)0x00000100)
4649/* FLCTL_CLRIFG[PRG_ERR] Bits */
4650#define FLCTL_CLRIFG_PRG_ERR_OFS ( 9)
4651#define FLCTL_CLRIFG_PRG_ERR ((uint32_t)0x00000200)
4652/* FLCTL_SETIFG[RDBRST] Bits */
4653#define FLCTL_SETIFG_RDBRST_OFS ( 0)
4654#define FLCTL_SETIFG_RDBRST ((uint32_t)0x00000001)
4655/* FLCTL_SETIFG[AVPRE] Bits */
4656#define FLCTL_SETIFG_AVPRE_OFS ( 1)
4657#define FLCTL_SETIFG_AVPRE ((uint32_t)0x00000002)
4658/* FLCTL_SETIFG[AVPST] Bits */
4659#define FLCTL_SETIFG_AVPST_OFS ( 2)
4660#define FLCTL_SETIFG_AVPST ((uint32_t)0x00000004)
4661/* FLCTL_SETIFG[PRG] Bits */
4662#define FLCTL_SETIFG_PRG_OFS ( 3)
4663#define FLCTL_SETIFG_PRG ((uint32_t)0x00000008)
4664/* FLCTL_SETIFG[PRGB] Bits */
4665#define FLCTL_SETIFG_PRGB_OFS ( 4)
4666#define FLCTL_SETIFG_PRGB ((uint32_t)0x00000010)
4667/* FLCTL_SETIFG[ERASE] Bits */
4668#define FLCTL_SETIFG_ERASE_OFS ( 5)
4669#define FLCTL_SETIFG_ERASE ((uint32_t)0x00000020)
4670/* FLCTL_SETIFG[BMRK] Bits */
4671#define FLCTL_SETIFG_BMRK_OFS ( 8)
4672#define FLCTL_SETIFG_BMRK ((uint32_t)0x00000100)
4673/* FLCTL_SETIFG[PRG_ERR] Bits */
4674#define FLCTL_SETIFG_PRG_ERR_OFS ( 9)
4675#define FLCTL_SETIFG_PRG_ERR ((uint32_t)0x00000200)
4676/* FLCTL_READ_TIMCTL[SETUP] Bits */
4677#define FLCTL_READ_TIMCTL_SETUP_OFS ( 0)
4678#define FLCTL_READ_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF)
4679/* FLCTL_READ_TIMCTL[IREF_BOOST1] Bits */
4680#define FLCTL_READ_TIMCTL_IREF_BOOST1_OFS (12)
4681#define FLCTL_READ_TIMCTL_IREF_BOOST1_MASK ((uint32_t)0x0000F000)
4682/* FLCTL_READ_TIMCTL[SETUP_LONG] Bits */
4683#define FLCTL_READ_TIMCTL_SETUP_LONG_OFS (16)
4684#define FLCTL_READ_TIMCTL_SETUP_LONG_MASK ((uint32_t)0x00FF0000)
4685/* FLCTL_READMARGIN_TIMCTL[SETUP] Bits */
4686#define FLCTL_READMARGIN_TIMCTL_SETUP_OFS ( 0)
4687#define FLCTL_READMARGIN_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF)
4688/* FLCTL_PRGVER_TIMCTL[SETUP] Bits */
4689#define FLCTL_PRGVER_TIMCTL_SETUP_OFS ( 0)
4690#define FLCTL_PRGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF)
4691/* FLCTL_PRGVER_TIMCTL[ACTIVE] Bits */
4692#define FLCTL_PRGVER_TIMCTL_ACTIVE_OFS ( 8)
4693#define FLCTL_PRGVER_TIMCTL_ACTIVE_MASK ((uint32_t)0x00000F00)
4694/* FLCTL_PRGVER_TIMCTL[HOLD] Bits */
4695#define FLCTL_PRGVER_TIMCTL_HOLD_OFS (12)
4696#define FLCTL_PRGVER_TIMCTL_HOLD_MASK ((uint32_t)0x0000F000)
4697/* FLCTL_ERSVER_TIMCTL[SETUP] Bits */
4698#define FLCTL_ERSVER_TIMCTL_SETUP_OFS ( 0)
4699#define FLCTL_ERSVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF)
4700/* FLCTL_LKGVER_TIMCTL[SETUP] Bits */
4701#define FLCTL_LKGVER_TIMCTL_SETUP_OFS ( 0)
4702#define FLCTL_LKGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF)
4703/* FLCTL_PROGRAM_TIMCTL[SETUP] Bits */
4704#define FLCTL_PROGRAM_TIMCTL_SETUP_OFS ( 0)
4705#define FLCTL_PROGRAM_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF)
4706/* FLCTL_PROGRAM_TIMCTL[ACTIVE] Bits */
4707#define FLCTL_PROGRAM_TIMCTL_ACTIVE_OFS ( 8)
4708#define FLCTL_PROGRAM_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00)
4709/* FLCTL_PROGRAM_TIMCTL[HOLD] Bits */
4710#define FLCTL_PROGRAM_TIMCTL_HOLD_OFS (28)
4711#define FLCTL_PROGRAM_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000)
4712/* FLCTL_ERASE_TIMCTL[SETUP] Bits */
4713#define FLCTL_ERASE_TIMCTL_SETUP_OFS ( 0)
4714#define FLCTL_ERASE_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF)
4715/* FLCTL_ERASE_TIMCTL[ACTIVE] Bits */
4716#define FLCTL_ERASE_TIMCTL_ACTIVE_OFS ( 8)
4717#define FLCTL_ERASE_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00)
4718/* FLCTL_ERASE_TIMCTL[HOLD] Bits */
4719#define FLCTL_ERASE_TIMCTL_HOLD_OFS (28)
4720#define FLCTL_ERASE_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000)
4721/* FLCTL_MASSERASE_TIMCTL[BOOST_ACTIVE] Bits */
4722#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS ( 0)
4723#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_MASK ((uint32_t)0x000000FF)
4724/* FLCTL_MASSERASE_TIMCTL[BOOST_HOLD] Bits */
4725#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_OFS ( 8)
4726#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_MASK ((uint32_t)0x0000FF00)
4727/* FLCTL_BURSTPRG_TIMCTL[ACTIVE] Bits */
4728#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_OFS ( 8)
4729#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00)
4731/******************************************************************************
4732* FL_BOOTOVER_MAILBOX Bits
4733******************************************************************************/
4734
4735/******************************************************************************
4736* FPB Bits
4737******************************************************************************/
4738
4739
4740/******************************************************************************
4741* FPU Bits
4742******************************************************************************/
4743
4744
4745/******************************************************************************
4746* ITM Bits
4747******************************************************************************/
4748
4749
4750/******************************************************************************
4751* MPU Bits
4752******************************************************************************/
4753
4754/* Pre-defined bitfield values */
4755
4756/* MPU_RASR_SIZE Bitfield Bits */
4757#define MPU_RASR_SIZE__32B ((uint32_t)0x00000008)
4758#define MPU_RASR_SIZE__64B ((uint32_t)0x0000000A)
4759#define MPU_RASR_SIZE__128B ((uint32_t)0x0000000C)
4760#define MPU_RASR_SIZE__256B ((uint32_t)0x0000000E)
4761#define MPU_RASR_SIZE__512B ((uint32_t)0x00000010)
4762#define MPU_RASR_SIZE__1K ((uint32_t)0x00000012)
4763#define MPU_RASR_SIZE__2K ((uint32_t)0x00000014)
4764#define MPU_RASR_SIZE__4K ((uint32_t)0x00000016)
4765#define MPU_RASR_SIZE__8K ((uint32_t)0x00000018)
4766#define MPU_RASR_SIZE__16K ((uint32_t)0x0000001A)
4767#define MPU_RASR_SIZE__32K ((uint32_t)0x0000001C)
4768#define MPU_RASR_SIZE__64K ((uint32_t)0x0000001E)
4769#define MPU_RASR_SIZE__128K ((uint32_t)0x00000020)
4770#define MPU_RASR_SIZE__256K ((uint32_t)0x00000022)
4771#define MPU_RASR_SIZE__512K ((uint32_t)0x00000024)
4772#define MPU_RASR_SIZE__1M ((uint32_t)0x00000026)
4773#define MPU_RASR_SIZE__2M ((uint32_t)0x00000028)
4774#define MPU_RASR_SIZE__4M ((uint32_t)0x0000002A)
4775#define MPU_RASR_SIZE__8M ((uint32_t)0x0000002C)
4776#define MPU_RASR_SIZE__16M ((uint32_t)0x0000002E)
4777#define MPU_RASR_SIZE__32M ((uint32_t)0x00000030)
4778#define MPU_RASR_SIZE__64M ((uint32_t)0x00000032)
4779#define MPU_RASR_SIZE__128M ((uint32_t)0x00000034)
4780#define MPU_RASR_SIZE__256M ((uint32_t)0x00000036)
4781#define MPU_RASR_SIZE__512M ((uint32_t)0x00000038)
4782#define MPU_RASR_SIZE__1G ((uint32_t)0x0000003A)
4783#define MPU_RASR_SIZE__2G ((uint32_t)0x0000003C)
4784#define MPU_RASR_SIZE__4G ((uint32_t)0x0000003E)
4786/* MPU_RASR_AP Bitfield Bits */
4787#define MPU_RASR_AP_PRV_NO_USR_NO ((uint32_t)0x00000000)
4788#define MPU_RASR_AP_PRV_RW_USR_NO ((uint32_t)0x01000000)
4789#define MPU_RASR_AP_PRV_RW_USR_RO ((uint32_t)0x02000000)
4790#define MPU_RASR_AP_PRV_RW_USR_RW ((uint32_t)0x03000000)
4791#define MPU_RASR_AP_PRV_RO_USR_NO ((uint32_t)0x05000000)
4792#define MPU_RASR_AP_PRV_RO_USR_RO ((uint32_t)0x06000000)
4794/* MPU_RASR_XN Bitfield Bits */
4795#define MPU_RASR_AP_EXEC ((uint32_t)0x00000000)
4796#define MPU_RASR_AP_NOEXEC ((uint32_t)0x10000000)
4799/******************************************************************************
4800* NVIC Bits
4801******************************************************************************/
4802
4803/* NVIC_IPR0[NVIC_IPR0_PRI_0] Bits */
4804#define NVIC_IPR0_PRI_0_OFS ( 0)
4805#define NVIC_IPR0_PRI_0_M ((uint32_t)0x000000ff) /* */
4806/* NVIC_IPR0[NVIC_IPR0_PRI_1] Bits */
4807#define NVIC_IPR0_PRI_1_OFS ( 8)
4808#define NVIC_IPR0_PRI_1_M ((uint32_t)0x0000ff00) /* */
4809/* NVIC_IPR0[NVIC_IPR0_PRI_2] Bits */
4810#define NVIC_IPR0_PRI_2_OFS (16)
4811#define NVIC_IPR0_PRI_2_M ((uint32_t)0x00ff0000) /* */
4812/* NVIC_IPR0[NVIC_IPR0_PRI_3] Bits */
4813#define NVIC_IPR0_PRI_3_OFS (24)
4814#define NVIC_IPR0_PRI_3_M ((uint32_t)0xff000000) /* */
4815/* NVIC_IPR1[NVIC_IPR1_PRI_4] Bits */
4816#define NVIC_IPR1_PRI_4_OFS ( 0)
4817#define NVIC_IPR1_PRI_4_M ((uint32_t)0x000000ff) /* */
4818/* NVIC_IPR1[NVIC_IPR1_PRI_5] Bits */
4819#define NVIC_IPR1_PRI_5_OFS ( 8)
4820#define NVIC_IPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */
4821/* NVIC_IPR1[NVIC_IPR1_PRI_6] Bits */
4822#define NVIC_IPR1_PRI_6_OFS (16)
4823#define NVIC_IPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */
4824/* NVIC_IPR1[NVIC_IPR1_PRI_7] Bits */
4825#define NVIC_IPR1_PRI_7_OFS (24)
4826#define NVIC_IPR1_PRI_7_M ((uint32_t)0xff000000) /* */
4827/* NVIC_IPR2[NVIC_IPR2_PRI_8] Bits */
4828#define NVIC_IPR2_PRI_8_OFS ( 0)
4829#define NVIC_IPR2_PRI_8_M ((uint32_t)0x000000ff) /* */
4830/* NVIC_IPR2[NVIC_IPR2_PRI_9] Bits */
4831#define NVIC_IPR2_PRI_9_OFS ( 8)
4832#define NVIC_IPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */
4833/* NVIC_IPR2[NVIC_IPR2_PRI_10] Bits */
4834#define NVIC_IPR2_PRI_10_OFS (16)
4835#define NVIC_IPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */
4836/* NVIC_IPR2[NVIC_IPR2_PRI_11] Bits */
4837#define NVIC_IPR2_PRI_11_OFS (24)
4838#define NVIC_IPR2_PRI_11_M ((uint32_t)0xff000000) /* */
4839/* NVIC_IPR3[NVIC_IPR3_PRI_12] Bits */
4840#define NVIC_IPR3_PRI_12_OFS ( 0)
4841#define NVIC_IPR3_PRI_12_M ((uint32_t)0x000000ff) /* */
4842/* NVIC_IPR3[NVIC_IPR3_PRI_13] Bits */
4843#define NVIC_IPR3_PRI_13_OFS ( 8)
4844#define NVIC_IPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */
4845/* NVIC_IPR3[NVIC_IPR3_PRI_14] Bits */
4846#define NVIC_IPR3_PRI_14_OFS (16)
4847#define NVIC_IPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */
4848/* NVIC_IPR3[NVIC_IPR3_PRI_15] Bits */
4849#define NVIC_IPR3_PRI_15_OFS (24)
4850#define NVIC_IPR3_PRI_15_M ((uint32_t)0xff000000) /* */
4851/* NVIC_IPR4[NVIC_IPR4_PRI_16] Bits */
4852#define NVIC_IPR4_PRI_16_OFS ( 0)
4853#define NVIC_IPR4_PRI_16_M ((uint32_t)0x000000ff) /* */
4854/* NVIC_IPR4[NVIC_IPR4_PRI_17] Bits */
4855#define NVIC_IPR4_PRI_17_OFS ( 8)
4856#define NVIC_IPR4_PRI_17_M ((uint32_t)0x0000ff00) /* */
4857/* NVIC_IPR4[NVIC_IPR4_PRI_18] Bits */
4858#define NVIC_IPR4_PRI_18_OFS (16)
4859#define NVIC_IPR4_PRI_18_M ((uint32_t)0x00ff0000) /* */
4860/* NVIC_IPR4[NVIC_IPR4_PRI_19] Bits */
4861#define NVIC_IPR4_PRI_19_OFS (24)
4862#define NVIC_IPR4_PRI_19_M ((uint32_t)0xff000000) /* */
4863/* NVIC_IPR5[NVIC_IPR5_PRI_20] Bits */
4864#define NVIC_IPR5_PRI_20_OFS ( 0)
4865#define NVIC_IPR5_PRI_20_M ((uint32_t)0x000000ff) /* */
4866/* NVIC_IPR5[NVIC_IPR5_PRI_21] Bits */
4867#define NVIC_IPR5_PRI_21_OFS ( 8)
4868#define NVIC_IPR5_PRI_21_M ((uint32_t)0x0000ff00) /* */
4869/* NVIC_IPR5[NVIC_IPR5_PRI_22] Bits */
4870#define NVIC_IPR5_PRI_22_OFS (16)
4871#define NVIC_IPR5_PRI_22_M ((uint32_t)0x00ff0000) /* */
4872/* NVIC_IPR5[NVIC_IPR5_PRI_23] Bits */
4873#define NVIC_IPR5_PRI_23_OFS (24)
4874#define NVIC_IPR5_PRI_23_M ((uint32_t)0xff000000) /* */
4875/* NVIC_IPR6[NVIC_IPR6_PRI_24] Bits */
4876#define NVIC_IPR6_PRI_24_OFS ( 0)
4877#define NVIC_IPR6_PRI_24_M ((uint32_t)0x000000ff) /* */
4878/* NVIC_IPR6[NVIC_IPR6_PRI_25] Bits */
4879#define NVIC_IPR6_PRI_25_OFS ( 8)
4880#define NVIC_IPR6_PRI_25_M ((uint32_t)0x0000ff00) /* */
4881/* NVIC_IPR6[NVIC_IPR6_PRI_26] Bits */
4882#define NVIC_IPR6_PRI_26_OFS (16)
4883#define NVIC_IPR6_PRI_26_M ((uint32_t)0x00ff0000) /* */
4884/* NVIC_IPR6[NVIC_IPR6_PRI_27] Bits */
4885#define NVIC_IPR6_PRI_27_OFS (24)
4886#define NVIC_IPR6_PRI_27_M ((uint32_t)0xff000000) /* */
4887/* NVIC_IPR7[NVIC_IPR7_PRI_28] Bits */
4888#define NVIC_IPR7_PRI_28_OFS ( 0)
4889#define NVIC_IPR7_PRI_28_M ((uint32_t)0x000000ff) /* */
4890/* NVIC_IPR7[NVIC_IPR7_PRI_29] Bits */
4891#define NVIC_IPR7_PRI_29_OFS ( 8)
4892#define NVIC_IPR7_PRI_29_M ((uint32_t)0x0000ff00) /* */
4893/* NVIC_IPR7[NVIC_IPR7_PRI_30] Bits */
4894#define NVIC_IPR7_PRI_30_OFS (16)
4895#define NVIC_IPR7_PRI_30_M ((uint32_t)0x00ff0000) /* */
4896/* NVIC_IPR7[NVIC_IPR7_PRI_31] Bits */
4897#define NVIC_IPR7_PRI_31_OFS (24)
4898#define NVIC_IPR7_PRI_31_M ((uint32_t)0xff000000) /* */
4899/* NVIC_IPR8[NVIC_IPR8_PRI_32] Bits */
4900#define NVIC_IPR8_PRI_32_OFS ( 0)
4901#define NVIC_IPR8_PRI_32_M ((uint32_t)0x000000ff) /* */
4902/* NVIC_IPR8[NVIC_IPR8_PRI_33] Bits */
4903#define NVIC_IPR8_PRI_33_OFS ( 8)
4904#define NVIC_IPR8_PRI_33_M ((uint32_t)0x0000ff00) /* */
4905/* NVIC_IPR8[NVIC_IPR8_PRI_34] Bits */
4906#define NVIC_IPR8_PRI_34_OFS (16)
4907#define NVIC_IPR8_PRI_34_M ((uint32_t)0x00ff0000) /* */
4908/* NVIC_IPR8[NVIC_IPR8_PRI_35] Bits */
4909#define NVIC_IPR8_PRI_35_OFS (24)
4910#define NVIC_IPR8_PRI_35_M ((uint32_t)0xff000000) /* */
4911/* NVIC_IPR9[NVIC_IPR9_PRI_36] Bits */
4912#define NVIC_IPR9_PRI_36_OFS ( 0)
4913#define NVIC_IPR9_PRI_36_M ((uint32_t)0x000000ff) /* */
4914/* NVIC_IPR9[NVIC_IPR9_PRI_37] Bits */
4915#define NVIC_IPR9_PRI_37_OFS ( 8)
4916#define NVIC_IPR9_PRI_37_M ((uint32_t)0x0000ff00) /* */
4917/* NVIC_IPR9[NVIC_IPR9_PRI_38] Bits */
4918#define NVIC_IPR9_PRI_38_OFS (16)
4919#define NVIC_IPR9_PRI_38_M ((uint32_t)0x00ff0000) /* */
4920/* NVIC_IPR9[NVIC_IPR9_PRI_39] Bits */
4921#define NVIC_IPR9_PRI_39_OFS (24)
4922#define NVIC_IPR9_PRI_39_M ((uint32_t)0xff000000) /* */
4923/* NVIC_IPR10[NVIC_IPR10_PRI_40] Bits */
4924#define NVIC_IPR10_PRI_40_OFS ( 0)
4925#define NVIC_IPR10_PRI_40_M ((uint32_t)0x000000ff) /* */
4926/* NVIC_IPR10[NVIC_IPR10_PRI_41] Bits */
4927#define NVIC_IPR10_PRI_41_OFS ( 8)
4928#define NVIC_IPR10_PRI_41_M ((uint32_t)0x0000ff00) /* */
4929/* NVIC_IPR10[NVIC_IPR10_PRI_42] Bits */
4930#define NVIC_IPR10_PRI_42_OFS (16)
4931#define NVIC_IPR10_PRI_42_M ((uint32_t)0x00ff0000) /* */
4932/* NVIC_IPR10[NVIC_IPR10_PRI_43] Bits */
4933#define NVIC_IPR10_PRI_43_OFS (24)
4934#define NVIC_IPR10_PRI_43_M ((uint32_t)0xff000000) /* */
4935/* NVIC_IPR11[NVIC_IPR11_PRI_44] Bits */
4936#define NVIC_IPR11_PRI_44_OFS ( 0)
4937#define NVIC_IPR11_PRI_44_M ((uint32_t)0x000000ff) /* */
4938/* NVIC_IPR11[NVIC_IPR11_PRI_45] Bits */
4939#define NVIC_IPR11_PRI_45_OFS ( 8)
4940#define NVIC_IPR11_PRI_45_M ((uint32_t)0x0000ff00) /* */
4941/* NVIC_IPR11[NVIC_IPR11_PRI_46] Bits */
4942#define NVIC_IPR11_PRI_46_OFS (16)
4943#define NVIC_IPR11_PRI_46_M ((uint32_t)0x00ff0000) /* */
4944/* NVIC_IPR11[NVIC_IPR11_PRI_47] Bits */
4945#define NVIC_IPR11_PRI_47_OFS (24)
4946#define NVIC_IPR11_PRI_47_M ((uint32_t)0xff000000) /* */
4947/* NVIC_IPR12[NVIC_IPR12_PRI_48] Bits */
4948#define NVIC_IPR12_PRI_48_OFS ( 0)
4949#define NVIC_IPR12_PRI_48_M ((uint32_t)0x000000ff) /* */
4950/* NVIC_IPR12[NVIC_IPR12_PRI_49] Bits */
4951#define NVIC_IPR12_PRI_49_OFS ( 8)
4952#define NVIC_IPR12_PRI_49_M ((uint32_t)0x0000ff00) /* */
4953/* NVIC_IPR12[NVIC_IPR12_PRI_50] Bits */
4954#define NVIC_IPR12_PRI_50_OFS (16)
4955#define NVIC_IPR12_PRI_50_M ((uint32_t)0x00ff0000) /* */
4956/* NVIC_IPR12[NVIC_IPR12_PRI_51] Bits */
4957#define NVIC_IPR12_PRI_51_OFS (24)
4958#define NVIC_IPR12_PRI_51_M ((uint32_t)0xff000000) /* */
4959/* NVIC_IPR13[NVIC_IPR13_PRI_52] Bits */
4960#define NVIC_IPR13_PRI_52_OFS ( 0)
4961#define NVIC_IPR13_PRI_52_M ((uint32_t)0x000000ff) /* */
4962/* NVIC_IPR13[NVIC_IPR13_PRI_53] Bits */
4963#define NVIC_IPR13_PRI_53_OFS ( 8)
4964#define NVIC_IPR13_PRI_53_M ((uint32_t)0x0000ff00) /* */
4965/* NVIC_IPR13[NVIC_IPR13_PRI_54] Bits */
4966#define NVIC_IPR13_PRI_54_OFS (16)
4967#define NVIC_IPR13_PRI_54_M ((uint32_t)0x00ff0000) /* */
4968/* NVIC_IPR13[NVIC_IPR13_PRI_55] Bits */
4969#define NVIC_IPR13_PRI_55_OFS (24)
4970#define NVIC_IPR13_PRI_55_M ((uint32_t)0xff000000) /* */
4971/* NVIC_IPR14[NVIC_IPR14_PRI_56] Bits */
4972#define NVIC_IPR14_PRI_56_OFS ( 0)
4973#define NVIC_IPR14_PRI_56_M ((uint32_t)0x000000ff) /* */
4974/* NVIC_IPR14[NVIC_IPR14_PRI_57] Bits */
4975#define NVIC_IPR14_PRI_57_OFS ( 8)
4976#define NVIC_IPR14_PRI_57_M ((uint32_t)0x0000ff00) /* */
4977/* NVIC_IPR14[NVIC_IPR14_PRI_58] Bits */
4978#define NVIC_IPR14_PRI_58_OFS (16)
4979#define NVIC_IPR14_PRI_58_M ((uint32_t)0x00ff0000) /* */
4980/* NVIC_IPR14[NVIC_IPR14_PRI_59] Bits */
4981#define NVIC_IPR14_PRI_59_OFS (24)
4982#define NVIC_IPR14_PRI_59_M ((uint32_t)0xff000000) /* */
4983/* NVIC_IPR15[NVIC_IPR15_PRI_60] Bits */
4984#define NVIC_IPR15_PRI_60_OFS ( 0)
4985#define NVIC_IPR15_PRI_60_M ((uint32_t)0x000000ff) /* */
4986/* NVIC_IPR15[NVIC_IPR15_PRI_61] Bits */
4987#define NVIC_IPR15_PRI_61_OFS ( 8)
4988#define NVIC_IPR15_PRI_61_M ((uint32_t)0x0000ff00) /* */
4989/* NVIC_IPR15[NVIC_IPR15_PRI_62] Bits */
4990#define NVIC_IPR15_PRI_62_OFS (16)
4991#define NVIC_IPR15_PRI_62_M ((uint32_t)0x00ff0000) /* */
4992/* NVIC_IPR15[NVIC_IPR15_PRI_63] Bits */
4993#define NVIC_IPR15_PRI_63_OFS (24)
4994#define NVIC_IPR15_PRI_63_M ((uint32_t)0xff000000) /* */
4995
4996
4997/******************************************************************************
4998* PCM Bits
4999******************************************************************************/
5000/* PCM_CTL0[AMR] Bits */
5001#define PCM_CTL0_AMR_OFS ( 0)
5002#define PCM_CTL0_AMR_MASK ((uint32_t)0x0000000F)
5003#define PCM_CTL0_AMR0 ((uint32_t)0x00000001)
5004#define PCM_CTL0_AMR1 ((uint32_t)0x00000002)
5005#define PCM_CTL0_AMR2 ((uint32_t)0x00000004)
5006#define PCM_CTL0_AMR3 ((uint32_t)0x00000008)
5007#define PCM_CTL0_AMR_0 ((uint32_t)0x00000000)
5008#define PCM_CTL0_AMR_1 ((uint32_t)0x00000001)
5009#define PCM_CTL0_AMR_4 ((uint32_t)0x00000004)
5010#define PCM_CTL0_AMR_5 ((uint32_t)0x00000005)
5011#define PCM_CTL0_AMR_8 ((uint32_t)0x00000008)
5012#define PCM_CTL0_AMR_9 ((uint32_t)0x00000009)
5013#define PCM_CTL0_AMR__AM_LDO_VCORE0 ((uint32_t)0x00000000)
5014#define PCM_CTL0_AMR__AM_LDO_VCORE1 ((uint32_t)0x00000001)
5015#define PCM_CTL0_AMR__AM_DCDC_VCORE0 ((uint32_t)0x00000004)
5016#define PCM_CTL0_AMR__AM_DCDC_VCORE1 ((uint32_t)0x00000005)
5017#define PCM_CTL0_AMR__AM_LF_VCORE0 ((uint32_t)0x00000008)
5018#define PCM_CTL0_AMR__AM_LF_VCORE1 ((uint32_t)0x00000009)
5019/* PCM_CTL0[LPMR] Bits */
5020#define PCM_CTL0_LPMR_OFS ( 4)
5021#define PCM_CTL0_LPMR_MASK ((uint32_t)0x000000F0)
5022#define PCM_CTL0_LPMR0 ((uint32_t)0x00000010)
5023#define PCM_CTL0_LPMR1 ((uint32_t)0x00000020)
5024#define PCM_CTL0_LPMR2 ((uint32_t)0x00000040)
5025#define PCM_CTL0_LPMR3 ((uint32_t)0x00000080)
5026#define PCM_CTL0_LPMR_0 ((uint32_t)0x00000000)
5027 /* entered. */
5028#define PCM_CTL0_LPMR_10 ((uint32_t)0x000000A0)
5029#define PCM_CTL0_LPMR_12 ((uint32_t)0x000000C0)
5030#define PCM_CTL0_LPMR__LPM3 ((uint32_t)0x00000000)
5031 /* entered. */
5032#define PCM_CTL0_LPMR__LPM35 ((uint32_t)0x000000A0)
5033#define PCM_CTL0_LPMR__LPM45 ((uint32_t)0x000000C0)
5034/* PCM_CTL0[CPM] Bits */
5035#define PCM_CTL0_CPM_OFS ( 8)
5036#define PCM_CTL0_CPM_MASK ((uint32_t)0x00003F00)
5037#define PCM_CTL0_CPM0 ((uint32_t)0x00000100)
5038#define PCM_CTL0_CPM1 ((uint32_t)0x00000200)
5039#define PCM_CTL0_CPM2 ((uint32_t)0x00000400)
5040#define PCM_CTL0_CPM3 ((uint32_t)0x00000800)
5041#define PCM_CTL0_CPM4 ((uint32_t)0x00001000)
5042#define PCM_CTL0_CPM5 ((uint32_t)0x00002000)
5043#define PCM_CTL0_CPM_0 ((uint32_t)0x00000000)
5044#define PCM_CTL0_CPM_1 ((uint32_t)0x00000100)
5045#define PCM_CTL0_CPM_4 ((uint32_t)0x00000400)
5046#define PCM_CTL0_CPM_5 ((uint32_t)0x00000500)
5047#define PCM_CTL0_CPM_8 ((uint32_t)0x00000800)
5048#define PCM_CTL0_CPM_9 ((uint32_t)0x00000900)
5049#define PCM_CTL0_CPM_16 ((uint32_t)0x00001000)
5050#define PCM_CTL0_CPM_17 ((uint32_t)0x00001100)
5051#define PCM_CTL0_CPM_20 ((uint32_t)0x00001400)
5052#define PCM_CTL0_CPM_21 ((uint32_t)0x00001500)
5053#define PCM_CTL0_CPM_24 ((uint32_t)0x00001800)
5054#define PCM_CTL0_CPM_25 ((uint32_t)0x00001900)
5055#define PCM_CTL0_CPM_32 ((uint32_t)0x00002000)
5056#define PCM_CTL0_CPM__AM_LDO_VCORE0 ((uint32_t)0x00000000)
5057#define PCM_CTL0_CPM__AM_LDO_VCORE1 ((uint32_t)0x00000100)
5058#define PCM_CTL0_CPM__AM_DCDC_VCORE0 ((uint32_t)0x00000400)
5059#define PCM_CTL0_CPM__AM_DCDC_VCORE1 ((uint32_t)0x00000500)
5060#define PCM_CTL0_CPM__AM_LF_VCORE0 ((uint32_t)0x00000800)
5061#define PCM_CTL0_CPM__AM_LF_VCORE1 ((uint32_t)0x00000900)
5062#define PCM_CTL0_CPM__LPM0_LDO_VCORE0 ((uint32_t)0x00001000)
5063#define PCM_CTL0_CPM__LPM0_LDO_VCORE1 ((uint32_t)0x00001100)
5064#define PCM_CTL0_CPM__LPM0_DCDC_VCORE0 ((uint32_t)0x00001400)
5065#define PCM_CTL0_CPM__LPM0_DCDC_VCORE1 ((uint32_t)0x00001500)
5066#define PCM_CTL0_CPM__LPM0_LF_VCORE0 ((uint32_t)0x00001800)
5067#define PCM_CTL0_CPM__LPM0_LF_VCORE1 ((uint32_t)0x00001900)
5068#define PCM_CTL0_CPM__LPM3 ((uint32_t)0x00002000)
5069/* PCM_CTL0[KEY] Bits */
5070#define PCM_CTL0_KEY_OFS (16)
5071#define PCM_CTL0_KEY_MASK ((uint32_t)0xFFFF0000)
5072/* PCM_CTL1[LOCKLPM5] Bits */
5073#define PCM_CTL1_LOCKLPM5_OFS ( 0)
5074#define PCM_CTL1_LOCKLPM5 ((uint32_t)0x00000001)
5075/* PCM_CTL1[LOCKBKUP] Bits */
5076#define PCM_CTL1_LOCKBKUP_OFS ( 1)
5077#define PCM_CTL1_LOCKBKUP ((uint32_t)0x00000002)
5078/* PCM_CTL1[FORCE_LPM_ENTRY] Bits */
5079#define PCM_CTL1_FORCE_LPM_ENTRY_OFS ( 2)
5080#define PCM_CTL1_FORCE_LPM_ENTRY ((uint32_t)0x00000004)
5081/* PCM_CTL1[PMR_BUSY] Bits */
5082#define PCM_CTL1_PMR_BUSY_OFS ( 8)
5083#define PCM_CTL1_PMR_BUSY ((uint32_t)0x00000100)
5084/* PCM_CTL1[KEY] Bits */
5085#define PCM_CTL1_KEY_OFS (16)
5086#define PCM_CTL1_KEY_MASK ((uint32_t)0xFFFF0000)
5087/* PCM_IE[LPM_INVALID_TR_IE] Bits */
5088#define PCM_IE_LPM_INVALID_TR_IE_OFS ( 0)
5089#define PCM_IE_LPM_INVALID_TR_IE ((uint32_t)0x00000001)
5090/* PCM_IE[LPM_INVALID_CLK_IE] Bits */
5091#define PCM_IE_LPM_INVALID_CLK_IE_OFS ( 1)
5092#define PCM_IE_LPM_INVALID_CLK_IE ((uint32_t)0x00000002)
5093/* PCM_IE[AM_INVALID_TR_IE] Bits */
5094#define PCM_IE_AM_INVALID_TR_IE_OFS ( 2)
5095#define PCM_IE_AM_INVALID_TR_IE ((uint32_t)0x00000004)
5096/* PCM_IE[DCDC_ERROR_IE] Bits */
5097#define PCM_IE_DCDC_ERROR_IE_OFS ( 6)
5098#define PCM_IE_DCDC_ERROR_IE ((uint32_t)0x00000040)
5099/* PCM_IFG[LPM_INVALID_TR_IFG] Bits */
5100#define PCM_IFG_LPM_INVALID_TR_IFG_OFS ( 0)
5101#define PCM_IFG_LPM_INVALID_TR_IFG ((uint32_t)0x00000001)
5102/* PCM_IFG[LPM_INVALID_CLK_IFG] Bits */
5103#define PCM_IFG_LPM_INVALID_CLK_IFG_OFS ( 1)
5104#define PCM_IFG_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002)
5105/* PCM_IFG[AM_INVALID_TR_IFG] Bits */
5106#define PCM_IFG_AM_INVALID_TR_IFG_OFS ( 2)
5107#define PCM_IFG_AM_INVALID_TR_IFG ((uint32_t)0x00000004)
5108/* PCM_IFG[DCDC_ERROR_IFG] Bits */
5109#define PCM_IFG_DCDC_ERROR_IFG_OFS ( 6)
5110#define PCM_IFG_DCDC_ERROR_IFG ((uint32_t)0x00000040)
5111/* PCM_CLRIFG[CLR_LPM_INVALID_TR_IFG] Bits */
5112#define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG_OFS ( 0)
5113#define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG ((uint32_t)0x00000001)
5114/* PCM_CLRIFG[CLR_LPM_INVALID_CLK_IFG] Bits */
5115#define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG_OFS ( 1)
5116#define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002)
5117/* PCM_CLRIFG[CLR_AM_INVALID_TR_IFG] Bits */
5118#define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG_OFS ( 2)
5119#define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG ((uint32_t)0x00000004)
5120/* PCM_CLRIFG[CLR_DCDC_ERROR_IFG] Bits */
5121#define PCM_CLRIFG_CLR_DCDC_ERROR_IFG_OFS ( 6)
5122#define PCM_CLRIFG_CLR_DCDC_ERROR_IFG ((uint32_t)0x00000040)
5123/* Pre-defined bitfield values */
5124#define PCM_CTL0_KEY_VAL ((uint32_t)0x695A0000)
5125#define PCM_CTL1_KEY_VAL ((uint32_t)0x695A0000)
5128/******************************************************************************
5129* PMAP Bits
5130******************************************************************************/
5131/* PMAP_CTL[LOCKED] Bits */
5132#define PMAP_CTL_LOCKED_OFS ( 0)
5133#define PMAP_CTL_LOCKED ((uint16_t)0x0001)
5134/* PMAP_CTL[PRECFG] Bits */
5135#define PMAP_CTL_PRECFG_OFS ( 1)
5136#define PMAP_CTL_PRECFG ((uint16_t)0x0002)
5137/* Pre-defined bitfield values */
5138#define PMAP_NONE 0
5139#define PMAP_UCA0CLK 1
5140#define PMAP_UCA0RXD 2
5141#define PMAP_UCA0SOMI 2
5142#define PMAP_UCA0TXD 3
5143#define PMAP_UCA0SIMO 3
5144#define PMAP_UCB0CLK 4
5145#define PMAP_UCB0SDA 5
5146#define PMAP_UCB0SIMO 5
5147#define PMAP_UCB0SCL 6
5148#define PMAP_UCB0SOMI 6
5149#define PMAP_UCA1STE 7
5150#define PMAP_UCA1CLK 8
5151#define PMAP_UCA1RXD 9
5152#define PMAP_UCA1SOMI 9
5153#define PMAP_UCA1TXD 10
5154#define PMAP_UCA1SIMO 10
5155#define PMAP_UCA2STE 11
5156#define PMAP_UCA2CLK 12
5157#define PMAP_UCA2RXD 13
5158#define PMAP_UCA2SOMI 13
5159#define PMAP_UCA2TXD 14
5160#define PMAP_UCA2SIMO 14
5161#define PMAP_UCB2STE 15
5162#define PMAP_UCB2CLK 16
5163#define PMAP_UCB2SDA 17
5164#define PMAP_UCB2SIMO 17
5165#define PMAP_UCB2SCL 18
5166#define PMAP_UCB2SOMI 18
5167#define PMAP_TA0CCR0A 19
5168#define PMAP_TA0CCR1A 20
5169#define PMAP_TA0CCR2A 21
5170#define PMAP_TA0CCR3A 22
5171#define PMAP_TA0CCR4A 23
5172#define PMAP_TA1CCR1A 24
5173#define PMAP_TA1CCR2A 25
5174#define PMAP_TA1CCR3A 26
5175#define PMAP_TA1CCR4A 27
5176#define PMAP_TA0CLK 28
5177#define PMAP_CE0OUT 28
5178#define PMAP_TA1CLK 29
5179#define PMAP_CE1OUT 29
5180#define PMAP_DMAE0 30
5181#define PMAP_SMCLK 30
5182#define PMAP_ANALOG 31
5183
5184#define PMAP_KEYID_VAL ((uint16_t)0x2D52)
5187/******************************************************************************
5188* PSS Bits
5189******************************************************************************/
5190/* PSS_KEY[KEY] Bits */
5191#define PSS_KEY_KEY_OFS ( 0)
5192#define PSS_KEY_KEY_MASK ((uint32_t)0x0000FFFF)
5193/* PSS_CTL0[SVSMHOFF] Bits */
5194#define PSS_CTL0_SVSMHOFF_OFS ( 0)
5195#define PSS_CTL0_SVSMHOFF ((uint32_t)0x00000001)
5196/* PSS_CTL0[SVSMHLP] Bits */
5197#define PSS_CTL0_SVSMHLP_OFS ( 1)
5198#define PSS_CTL0_SVSMHLP ((uint32_t)0x00000002)
5199/* PSS_CTL0[SVSMHS] Bits */
5200#define PSS_CTL0_SVSMHS_OFS ( 2)
5201#define PSS_CTL0_SVSMHS ((uint32_t)0x00000004)
5202/* PSS_CTL0[SVSMHTH] Bits */
5203#define PSS_CTL0_SVSMHTH_OFS ( 3)
5204#define PSS_CTL0_SVSMHTH_MASK ((uint32_t)0x00000038)
5205/* PSS_CTL0[SVMHOE] Bits */
5206#define PSS_CTL0_SVMHOE_OFS ( 6)
5207#define PSS_CTL0_SVMHOE ((uint32_t)0x00000040)
5208/* PSS_CTL0[SVMHOUTPOLAL] Bits */
5209#define PSS_CTL0_SVMHOUTPOLAL_OFS ( 7)
5210#define PSS_CTL0_SVMHOUTPOLAL ((uint32_t)0x00000080)
5211/* PSS_CTL0[DCDC_FORCE] Bits */
5212#define PSS_CTL0_DCDC_FORCE_OFS (10)
5213#define PSS_CTL0_DCDC_FORCE ((uint32_t)0x00000400)
5214/* PSS_CTL0[VCORETRAN] Bits */
5215#define PSS_CTL0_VCORETRAN_OFS (12)
5216#define PSS_CTL0_VCORETRAN_MASK ((uint32_t)0x00003000)
5217#define PSS_CTL0_VCORETRAN0 ((uint32_t)0x00001000)
5218#define PSS_CTL0_VCORETRAN1 ((uint32_t)0x00002000)
5219#define PSS_CTL0_VCORETRAN_0 ((uint32_t)0x00000000)
5220#define PSS_CTL0_VCORETRAN_1 ((uint32_t)0x00001000)
5221#define PSS_CTL0_VCORETRAN_2 ((uint32_t)0x00002000)
5222#define PSS_CTL0_VCORETRAN_3 ((uint32_t)0x00003000)
5223#define PSS_CTL0_VCORETRAN__32 ((uint32_t)0x00000000)
5224#define PSS_CTL0_VCORETRAN__64 ((uint32_t)0x00001000)
5225#define PSS_CTL0_VCORETRAN__128 ((uint32_t)0x00002000)
5226#define PSS_CTL0_VCORETRAN__256 ((uint32_t)0x00003000)
5227/* PSS_IE[SVSMHIE] Bits */
5228#define PSS_IE_SVSMHIE_OFS ( 1)
5229#define PSS_IE_SVSMHIE ((uint32_t)0x00000002)
5230/* PSS_IFG[SVSMHIFG] Bits */
5231#define PSS_IFG_SVSMHIFG_OFS ( 1)
5232#define PSS_IFG_SVSMHIFG ((uint32_t)0x00000002)
5233/* PSS_CLRIFG[CLRSVSMHIFG] Bits */
5234#define PSS_CLRIFG_CLRSVSMHIFG_OFS ( 1)
5235#define PSS_CLRIFG_CLRSVSMHIFG ((uint32_t)0x00000002)
5236/* Pre-defined bitfield values */
5237#define PSS_KEY_KEY_VAL ((uint32_t)0x0000695A)
5240/******************************************************************************
5241* REF_A Bits
5242******************************************************************************/
5243/* REF_A_CTL0[ON] Bits */
5244#define REF_A_CTL0_ON_OFS ( 0)
5245#define REF_A_CTL0_ON ((uint16_t)0x0001)
5246/* REF_A_CTL0[OUT] Bits */
5247#define REF_A_CTL0_OUT_OFS ( 1)
5248#define REF_A_CTL0_OUT ((uint16_t)0x0002)
5249/* REF_A_CTL0[TCOFF] Bits */
5250#define REF_A_CTL0_TCOFF_OFS ( 3)
5251#define REF_A_CTL0_TCOFF ((uint16_t)0x0008)
5252/* REF_A_CTL0[VSEL] Bits */
5253#define REF_A_CTL0_VSEL_OFS ( 4)
5254#define REF_A_CTL0_VSEL_MASK ((uint16_t)0x0030)
5255#define REF_A_CTL0_VSEL0 ((uint16_t)0x0010)
5256#define REF_A_CTL0_VSEL1 ((uint16_t)0x0020)
5257#define REF_A_CTL0_VSEL_0 ((uint16_t)0x0000)
5258#define REF_A_CTL0_VSEL_1 ((uint16_t)0x0010)
5259#define REF_A_CTL0_VSEL_3 ((uint16_t)0x0030)
5260/* REF_A_CTL0[GENOT] Bits */
5261#define REF_A_CTL0_GENOT_OFS ( 6)
5262#define REF_A_CTL0_GENOT ((uint16_t)0x0040)
5263/* REF_A_CTL0[BGOT] Bits */
5264#define REF_A_CTL0_BGOT_OFS ( 7)
5265#define REF_A_CTL0_BGOT ((uint16_t)0x0080)
5266/* REF_A_CTL0[GENACT] Bits */
5267#define REF_A_CTL0_GENACT_OFS ( 8)
5268#define REF_A_CTL0_GENACT ((uint16_t)0x0100)
5269/* REF_A_CTL0[BGACT] Bits */
5270#define REF_A_CTL0_BGACT_OFS ( 9)
5271#define REF_A_CTL0_BGACT ((uint16_t)0x0200)
5272/* REF_A_CTL0[GENBUSY] Bits */
5273#define REF_A_CTL0_GENBUSY_OFS (10)
5274#define REF_A_CTL0_GENBUSY ((uint16_t)0x0400)
5275/* REF_A_CTL0[BGMODE] Bits */
5276#define REF_A_CTL0_BGMODE_OFS (11)
5277#define REF_A_CTL0_BGMODE ((uint16_t)0x0800)
5278/* REF_A_CTL0[GENRDY] Bits */
5279#define REF_A_CTL0_GENRDY_OFS (12)
5280#define REF_A_CTL0_GENRDY ((uint16_t)0x1000)
5281/* REF_A_CTL0[BGRDY] Bits */
5282#define REF_A_CTL0_BGRDY_OFS (13)
5283#define REF_A_CTL0_BGRDY ((uint16_t)0x2000)
5285/******************************************************************************
5286* RSTCTL Bits
5287******************************************************************************/
5288/* RSTCTL_RESET_REQ[SOFT_REQ] Bits */
5289#define RSTCTL_RESET_REQ_SOFT_REQ_OFS ( 0)
5290#define RSTCTL_RESET_REQ_SOFT_REQ ((uint32_t)0x00000001)
5291/* RSTCTL_RESET_REQ[HARD_REQ] Bits */
5292#define RSTCTL_RESET_REQ_HARD_REQ_OFS ( 1)
5293#define RSTCTL_RESET_REQ_HARD_REQ ((uint32_t)0x00000002)
5294/* RSTCTL_RESET_REQ[RSTKEY] Bits */
5295#define RSTCTL_RESET_REQ_RSTKEY_OFS ( 8)
5296#define RSTCTL_RESET_REQ_RSTKEY_MASK ((uint32_t)0x0000FF00)
5297/* RSTCTL_HARDRESET_STAT[SRC0] Bits */
5298#define RSTCTL_HARDRESET_STAT_SRC0_OFS ( 0)
5299#define RSTCTL_HARDRESET_STAT_SRC0 ((uint32_t)0x00000001)
5300/* RSTCTL_HARDRESET_STAT[SRC1] Bits */
5301#define RSTCTL_HARDRESET_STAT_SRC1_OFS ( 1)
5302#define RSTCTL_HARDRESET_STAT_SRC1 ((uint32_t)0x00000002)
5303/* RSTCTL_HARDRESET_STAT[SRC2] Bits */
5304#define RSTCTL_HARDRESET_STAT_SRC2_OFS ( 2)
5305#define RSTCTL_HARDRESET_STAT_SRC2 ((uint32_t)0x00000004)
5306/* RSTCTL_HARDRESET_STAT[SRC3] Bits */
5307#define RSTCTL_HARDRESET_STAT_SRC3_OFS ( 3)
5308#define RSTCTL_HARDRESET_STAT_SRC3 ((uint32_t)0x00000008)
5309/* RSTCTL_HARDRESET_STAT[SRC4] Bits */
5310#define RSTCTL_HARDRESET_STAT_SRC4_OFS ( 4)
5311#define RSTCTL_HARDRESET_STAT_SRC4 ((uint32_t)0x00000010)
5312/* RSTCTL_HARDRESET_STAT[SRC5] Bits */
5313#define RSTCTL_HARDRESET_STAT_SRC5_OFS ( 5)
5314#define RSTCTL_HARDRESET_STAT_SRC5 ((uint32_t)0x00000020)
5315/* RSTCTL_HARDRESET_STAT[SRC6] Bits */
5316#define RSTCTL_HARDRESET_STAT_SRC6_OFS ( 6)
5317#define RSTCTL_HARDRESET_STAT_SRC6 ((uint32_t)0x00000040)
5318/* RSTCTL_HARDRESET_STAT[SRC7] Bits */
5319#define RSTCTL_HARDRESET_STAT_SRC7_OFS ( 7)
5320#define RSTCTL_HARDRESET_STAT_SRC7 ((uint32_t)0x00000080)
5321/* RSTCTL_HARDRESET_STAT[SRC8] Bits */
5322#define RSTCTL_HARDRESET_STAT_SRC8_OFS ( 8)
5323#define RSTCTL_HARDRESET_STAT_SRC8 ((uint32_t)0x00000100)
5324/* RSTCTL_HARDRESET_STAT[SRC9] Bits */
5325#define RSTCTL_HARDRESET_STAT_SRC9_OFS ( 9)
5326#define RSTCTL_HARDRESET_STAT_SRC9 ((uint32_t)0x00000200)
5327/* RSTCTL_HARDRESET_STAT[SRC10] Bits */
5328#define RSTCTL_HARDRESET_STAT_SRC10_OFS (10)
5329#define RSTCTL_HARDRESET_STAT_SRC10 ((uint32_t)0x00000400)
5330/* RSTCTL_HARDRESET_STAT[SRC11] Bits */
5331#define RSTCTL_HARDRESET_STAT_SRC11_OFS (11)
5332#define RSTCTL_HARDRESET_STAT_SRC11 ((uint32_t)0x00000800)
5333/* RSTCTL_HARDRESET_STAT[SRC12] Bits */
5334#define RSTCTL_HARDRESET_STAT_SRC12_OFS (12)
5335#define RSTCTL_HARDRESET_STAT_SRC12 ((uint32_t)0x00001000)
5336/* RSTCTL_HARDRESET_STAT[SRC13] Bits */
5337#define RSTCTL_HARDRESET_STAT_SRC13_OFS (13)
5338#define RSTCTL_HARDRESET_STAT_SRC13 ((uint32_t)0x00002000)
5339/* RSTCTL_HARDRESET_STAT[SRC14] Bits */
5340#define RSTCTL_HARDRESET_STAT_SRC14_OFS (14)
5341#define RSTCTL_HARDRESET_STAT_SRC14 ((uint32_t)0x00004000)
5342/* RSTCTL_HARDRESET_STAT[SRC15] Bits */
5343#define RSTCTL_HARDRESET_STAT_SRC15_OFS (15)
5344#define RSTCTL_HARDRESET_STAT_SRC15 ((uint32_t)0x00008000)
5345/* RSTCTL_HARDRESET_CLR[SRC0] Bits */
5346#define RSTCTL_HARDRESET_CLR_SRC0_OFS ( 0)
5347#define RSTCTL_HARDRESET_CLR_SRC0 ((uint32_t)0x00000001)
5348/* RSTCTL_HARDRESET_CLR[SRC1] Bits */
5349#define RSTCTL_HARDRESET_CLR_SRC1_OFS ( 1)
5350#define RSTCTL_HARDRESET_CLR_SRC1 ((uint32_t)0x00000002)
5351/* RSTCTL_HARDRESET_CLR[SRC2] Bits */
5352#define RSTCTL_HARDRESET_CLR_SRC2_OFS ( 2)
5353#define RSTCTL_HARDRESET_CLR_SRC2 ((uint32_t)0x00000004)
5354/* RSTCTL_HARDRESET_CLR[SRC3] Bits */
5355#define RSTCTL_HARDRESET_CLR_SRC3_OFS ( 3)
5356#define RSTCTL_HARDRESET_CLR_SRC3 ((uint32_t)0x00000008)
5357/* RSTCTL_HARDRESET_CLR[SRC4] Bits */
5358#define RSTCTL_HARDRESET_CLR_SRC4_OFS ( 4)
5359#define RSTCTL_HARDRESET_CLR_SRC4 ((uint32_t)0x00000010)
5360/* RSTCTL_HARDRESET_CLR[SRC5] Bits */
5361#define RSTCTL_HARDRESET_CLR_SRC5_OFS ( 5)
5362#define RSTCTL_HARDRESET_CLR_SRC5 ((uint32_t)0x00000020)
5363/* RSTCTL_HARDRESET_CLR[SRC6] Bits */
5364#define RSTCTL_HARDRESET_CLR_SRC6_OFS ( 6)
5365#define RSTCTL_HARDRESET_CLR_SRC6 ((uint32_t)0x00000040)
5366/* RSTCTL_HARDRESET_CLR[SRC7] Bits */
5367#define RSTCTL_HARDRESET_CLR_SRC7_OFS ( 7)
5368#define RSTCTL_HARDRESET_CLR_SRC7 ((uint32_t)0x00000080)
5369/* RSTCTL_HARDRESET_CLR[SRC8] Bits */
5370#define RSTCTL_HARDRESET_CLR_SRC8_OFS ( 8)
5371#define RSTCTL_HARDRESET_CLR_SRC8 ((uint32_t)0x00000100)
5372/* RSTCTL_HARDRESET_CLR[SRC9] Bits */
5373#define RSTCTL_HARDRESET_CLR_SRC9_OFS ( 9)
5374#define RSTCTL_HARDRESET_CLR_SRC9 ((uint32_t)0x00000200)
5375/* RSTCTL_HARDRESET_CLR[SRC10] Bits */
5376#define RSTCTL_HARDRESET_CLR_SRC10_OFS (10)
5377#define RSTCTL_HARDRESET_CLR_SRC10 ((uint32_t)0x00000400)
5378/* RSTCTL_HARDRESET_CLR[SRC11] Bits */
5379#define RSTCTL_HARDRESET_CLR_SRC11_OFS (11)
5380#define RSTCTL_HARDRESET_CLR_SRC11 ((uint32_t)0x00000800)
5381/* RSTCTL_HARDRESET_CLR[SRC12] Bits */
5382#define RSTCTL_HARDRESET_CLR_SRC12_OFS (12)
5383#define RSTCTL_HARDRESET_CLR_SRC12 ((uint32_t)0x00001000)
5384/* RSTCTL_HARDRESET_CLR[SRC13] Bits */
5385#define RSTCTL_HARDRESET_CLR_SRC13_OFS (13)
5386#define RSTCTL_HARDRESET_CLR_SRC13 ((uint32_t)0x00002000)
5387/* RSTCTL_HARDRESET_CLR[SRC14] Bits */
5388#define RSTCTL_HARDRESET_CLR_SRC14_OFS (14)
5389#define RSTCTL_HARDRESET_CLR_SRC14 ((uint32_t)0x00004000)
5390/* RSTCTL_HARDRESET_CLR[SRC15] Bits */
5391#define RSTCTL_HARDRESET_CLR_SRC15_OFS (15)
5392#define RSTCTL_HARDRESET_CLR_SRC15 ((uint32_t)0x00008000)
5393/* RSTCTL_HARDRESET_SET[SRC0] Bits */
5394#define RSTCTL_HARDRESET_SET_SRC0_OFS ( 0)
5395#define RSTCTL_HARDRESET_SET_SRC0 ((uint32_t)0x00000001)
5396 /* initiates a Hard Reset) */
5397/* RSTCTL_HARDRESET_SET[SRC1] Bits */
5398#define RSTCTL_HARDRESET_SET_SRC1_OFS ( 1)
5399#define RSTCTL_HARDRESET_SET_SRC1 ((uint32_t)0x00000002)
5400 /* initiates a Hard Reset) */
5401/* RSTCTL_HARDRESET_SET[SRC2] Bits */
5402#define RSTCTL_HARDRESET_SET_SRC2_OFS ( 2)
5403#define RSTCTL_HARDRESET_SET_SRC2 ((uint32_t)0x00000004)
5404 /* initiates a Hard Reset) */
5405/* RSTCTL_HARDRESET_SET[SRC3] Bits */
5406#define RSTCTL_HARDRESET_SET_SRC3_OFS ( 3)
5407#define RSTCTL_HARDRESET_SET_SRC3 ((uint32_t)0x00000008)
5408 /* initiates a Hard Reset) */
5409/* RSTCTL_HARDRESET_SET[SRC4] Bits */
5410#define RSTCTL_HARDRESET_SET_SRC4_OFS ( 4)
5411#define RSTCTL_HARDRESET_SET_SRC4 ((uint32_t)0x00000010)
5412 /* initiates a Hard Reset) */
5413/* RSTCTL_HARDRESET_SET[SRC5] Bits */
5414#define RSTCTL_HARDRESET_SET_SRC5_OFS ( 5)
5415#define RSTCTL_HARDRESET_SET_SRC5 ((uint32_t)0x00000020)
5416 /* initiates a Hard Reset) */
5417/* RSTCTL_HARDRESET_SET[SRC6] Bits */
5418#define RSTCTL_HARDRESET_SET_SRC6_OFS ( 6)
5419#define RSTCTL_HARDRESET_SET_SRC6 ((uint32_t)0x00000040)
5420 /* initiates a Hard Reset) */
5421/* RSTCTL_HARDRESET_SET[SRC7] Bits */
5422#define RSTCTL_HARDRESET_SET_SRC7_OFS ( 7)
5423#define RSTCTL_HARDRESET_SET_SRC7 ((uint32_t)0x00000080)
5424 /* initiates a Hard Reset) */
5425/* RSTCTL_HARDRESET_SET[SRC8] Bits */
5426#define RSTCTL_HARDRESET_SET_SRC8_OFS ( 8)
5427#define RSTCTL_HARDRESET_SET_SRC8 ((uint32_t)0x00000100)
5428 /* initiates a Hard Reset) */
5429/* RSTCTL_HARDRESET_SET[SRC9] Bits */
5430#define RSTCTL_HARDRESET_SET_SRC9_OFS ( 9)
5431#define RSTCTL_HARDRESET_SET_SRC9 ((uint32_t)0x00000200)
5432 /* initiates a Hard Reset) */
5433/* RSTCTL_HARDRESET_SET[SRC10] Bits */
5434#define RSTCTL_HARDRESET_SET_SRC10_OFS (10)
5435#define RSTCTL_HARDRESET_SET_SRC10 ((uint32_t)0x00000400)
5436 /* initiates a Hard Reset) */
5437/* RSTCTL_HARDRESET_SET[SRC11] Bits */
5438#define RSTCTL_HARDRESET_SET_SRC11_OFS (11)
5439#define RSTCTL_HARDRESET_SET_SRC11 ((uint32_t)0x00000800)
5440 /* initiates a Hard Reset) */
5441/* RSTCTL_HARDRESET_SET[SRC12] Bits */
5442#define RSTCTL_HARDRESET_SET_SRC12_OFS (12)
5443#define RSTCTL_HARDRESET_SET_SRC12 ((uint32_t)0x00001000)
5444 /* initiates a Hard Reset) */
5445/* RSTCTL_HARDRESET_SET[SRC13] Bits */
5446#define RSTCTL_HARDRESET_SET_SRC13_OFS (13)
5447#define RSTCTL_HARDRESET_SET_SRC13 ((uint32_t)0x00002000)
5448 /* initiates a Hard Reset) */
5449/* RSTCTL_HARDRESET_SET[SRC14] Bits */
5450#define RSTCTL_HARDRESET_SET_SRC14_OFS (14)
5451#define RSTCTL_HARDRESET_SET_SRC14 ((uint32_t)0x00004000)
5452 /* initiates a Hard Reset) */
5453/* RSTCTL_HARDRESET_SET[SRC15] Bits */
5454#define RSTCTL_HARDRESET_SET_SRC15_OFS (15)
5455#define RSTCTL_HARDRESET_SET_SRC15 ((uint32_t)0x00008000)
5456 /* initiates a Hard Reset) */
5457/* RSTCTL_SOFTRESET_STAT[SRC0] Bits */
5458#define RSTCTL_SOFTRESET_STAT_SRC0_OFS ( 0)
5459#define RSTCTL_SOFTRESET_STAT_SRC0 ((uint32_t)0x00000001)
5460/* RSTCTL_SOFTRESET_STAT[SRC1] Bits */
5461#define RSTCTL_SOFTRESET_STAT_SRC1_OFS ( 1)
5462#define RSTCTL_SOFTRESET_STAT_SRC1 ((uint32_t)0x00000002)
5463/* RSTCTL_SOFTRESET_STAT[SRC2] Bits */
5464#define RSTCTL_SOFTRESET_STAT_SRC2_OFS ( 2)
5465#define RSTCTL_SOFTRESET_STAT_SRC2 ((uint32_t)0x00000004)
5466/* RSTCTL_SOFTRESET_STAT[SRC3] Bits */
5467#define RSTCTL_SOFTRESET_STAT_SRC3_OFS ( 3)
5468#define RSTCTL_SOFTRESET_STAT_SRC3 ((uint32_t)0x00000008)
5469/* RSTCTL_SOFTRESET_STAT[SRC4] Bits */
5470#define RSTCTL_SOFTRESET_STAT_SRC4_OFS ( 4)
5471#define RSTCTL_SOFTRESET_STAT_SRC4 ((uint32_t)0x00000010)
5472/* RSTCTL_SOFTRESET_STAT[SRC5] Bits */
5473#define RSTCTL_SOFTRESET_STAT_SRC5_OFS ( 5)
5474#define RSTCTL_SOFTRESET_STAT_SRC5 ((uint32_t)0x00000020)
5475/* RSTCTL_SOFTRESET_STAT[SRC6] Bits */
5476#define RSTCTL_SOFTRESET_STAT_SRC6_OFS ( 6)
5477#define RSTCTL_SOFTRESET_STAT_SRC6 ((uint32_t)0x00000040)
5478/* RSTCTL_SOFTRESET_STAT[SRC7] Bits */
5479#define RSTCTL_SOFTRESET_STAT_SRC7_OFS ( 7)
5480#define RSTCTL_SOFTRESET_STAT_SRC7 ((uint32_t)0x00000080)
5481/* RSTCTL_SOFTRESET_STAT[SRC8] Bits */
5482#define RSTCTL_SOFTRESET_STAT_SRC8_OFS ( 8)
5483#define RSTCTL_SOFTRESET_STAT_SRC8 ((uint32_t)0x00000100)
5484/* RSTCTL_SOFTRESET_STAT[SRC9] Bits */
5485#define RSTCTL_SOFTRESET_STAT_SRC9_OFS ( 9)
5486#define RSTCTL_SOFTRESET_STAT_SRC9 ((uint32_t)0x00000200)
5487/* RSTCTL_SOFTRESET_STAT[SRC10] Bits */
5488#define RSTCTL_SOFTRESET_STAT_SRC10_OFS (10)
5489#define RSTCTL_SOFTRESET_STAT_SRC10 ((uint32_t)0x00000400)
5490/* RSTCTL_SOFTRESET_STAT[SRC11] Bits */
5491#define RSTCTL_SOFTRESET_STAT_SRC11_OFS (11)
5492#define RSTCTL_SOFTRESET_STAT_SRC11 ((uint32_t)0x00000800)
5493/* RSTCTL_SOFTRESET_STAT[SRC12] Bits */
5494#define RSTCTL_SOFTRESET_STAT_SRC12_OFS (12)
5495#define RSTCTL_SOFTRESET_STAT_SRC12 ((uint32_t)0x00001000)
5496/* RSTCTL_SOFTRESET_STAT[SRC13] Bits */
5497#define RSTCTL_SOFTRESET_STAT_SRC13_OFS (13)
5498#define RSTCTL_SOFTRESET_STAT_SRC13 ((uint32_t)0x00002000)
5499/* RSTCTL_SOFTRESET_STAT[SRC14] Bits */
5500#define RSTCTL_SOFTRESET_STAT_SRC14_OFS (14)
5501#define RSTCTL_SOFTRESET_STAT_SRC14 ((uint32_t)0x00004000)
5502/* RSTCTL_SOFTRESET_STAT[SRC15] Bits */
5503#define RSTCTL_SOFTRESET_STAT_SRC15_OFS (15)
5504#define RSTCTL_SOFTRESET_STAT_SRC15 ((uint32_t)0x00008000)
5505/* RSTCTL_SOFTRESET_CLR[SRC0] Bits */
5506#define RSTCTL_SOFTRESET_CLR_SRC0_OFS ( 0)
5507#define RSTCTL_SOFTRESET_CLR_SRC0 ((uint32_t)0x00000001)
5508/* RSTCTL_SOFTRESET_CLR[SRC1] Bits */
5509#define RSTCTL_SOFTRESET_CLR_SRC1_OFS ( 1)
5510#define RSTCTL_SOFTRESET_CLR_SRC1 ((uint32_t)0x00000002)
5511/* RSTCTL_SOFTRESET_CLR[SRC2] Bits */
5512#define RSTCTL_SOFTRESET_CLR_SRC2_OFS ( 2)
5513#define RSTCTL_SOFTRESET_CLR_SRC2 ((uint32_t)0x00000004)
5514/* RSTCTL_SOFTRESET_CLR[SRC3] Bits */
5515#define RSTCTL_SOFTRESET_CLR_SRC3_OFS ( 3)
5516#define RSTCTL_SOFTRESET_CLR_SRC3 ((uint32_t)0x00000008)
5517/* RSTCTL_SOFTRESET_CLR[SRC4] Bits */
5518#define RSTCTL_SOFTRESET_CLR_SRC4_OFS ( 4)
5519#define RSTCTL_SOFTRESET_CLR_SRC4 ((uint32_t)0x00000010)
5520/* RSTCTL_SOFTRESET_CLR[SRC5] Bits */
5521#define RSTCTL_SOFTRESET_CLR_SRC5_OFS ( 5)
5522#define RSTCTL_SOFTRESET_CLR_SRC5 ((uint32_t)0x00000020)
5523/* RSTCTL_SOFTRESET_CLR[SRC6] Bits */
5524#define RSTCTL_SOFTRESET_CLR_SRC6_OFS ( 6)
5525#define RSTCTL_SOFTRESET_CLR_SRC6 ((uint32_t)0x00000040)
5526/* RSTCTL_SOFTRESET_CLR[SRC7] Bits */
5527#define RSTCTL_SOFTRESET_CLR_SRC7_OFS ( 7)
5528#define RSTCTL_SOFTRESET_CLR_SRC7 ((uint32_t)0x00000080)
5529/* RSTCTL_SOFTRESET_CLR[SRC8] Bits */
5530#define RSTCTL_SOFTRESET_CLR_SRC8_OFS ( 8)
5531#define RSTCTL_SOFTRESET_CLR_SRC8 ((uint32_t)0x00000100)
5532/* RSTCTL_SOFTRESET_CLR[SRC9] Bits */
5533#define RSTCTL_SOFTRESET_CLR_SRC9_OFS ( 9)
5534#define RSTCTL_SOFTRESET_CLR_SRC9 ((uint32_t)0x00000200)
5535/* RSTCTL_SOFTRESET_CLR[SRC10] Bits */
5536#define RSTCTL_SOFTRESET_CLR_SRC10_OFS (10)
5537#define RSTCTL_SOFTRESET_CLR_SRC10 ((uint32_t)0x00000400)
5538/* RSTCTL_SOFTRESET_CLR[SRC11] Bits */
5539#define RSTCTL_SOFTRESET_CLR_SRC11_OFS (11)
5540#define RSTCTL_SOFTRESET_CLR_SRC11 ((uint32_t)0x00000800)
5541/* RSTCTL_SOFTRESET_CLR[SRC12] Bits */
5542#define RSTCTL_SOFTRESET_CLR_SRC12_OFS (12)
5543#define RSTCTL_SOFTRESET_CLR_SRC12 ((uint32_t)0x00001000)
5544/* RSTCTL_SOFTRESET_CLR[SRC13] Bits */
5545#define RSTCTL_SOFTRESET_CLR_SRC13_OFS (13)
5546#define RSTCTL_SOFTRESET_CLR_SRC13 ((uint32_t)0x00002000)
5547/* RSTCTL_SOFTRESET_CLR[SRC14] Bits */
5548#define RSTCTL_SOFTRESET_CLR_SRC14_OFS (14)
5549#define RSTCTL_SOFTRESET_CLR_SRC14 ((uint32_t)0x00004000)
5550/* RSTCTL_SOFTRESET_CLR[SRC15] Bits */
5551#define RSTCTL_SOFTRESET_CLR_SRC15_OFS (15)
5552#define RSTCTL_SOFTRESET_CLR_SRC15 ((uint32_t)0x00008000)
5553/* RSTCTL_SOFTRESET_SET[SRC0] Bits */
5554#define RSTCTL_SOFTRESET_SET_SRC0_OFS ( 0)
5555#define RSTCTL_SOFTRESET_SET_SRC0 ((uint32_t)0x00000001)
5556 /* initiates a Soft Reset) */
5557/* RSTCTL_SOFTRESET_SET[SRC1] Bits */
5558#define RSTCTL_SOFTRESET_SET_SRC1_OFS ( 1)
5559#define RSTCTL_SOFTRESET_SET_SRC1 ((uint32_t)0x00000002)
5560 /* initiates a Soft Reset) */
5561/* RSTCTL_SOFTRESET_SET[SRC2] Bits */
5562#define RSTCTL_SOFTRESET_SET_SRC2_OFS ( 2)
5563#define RSTCTL_SOFTRESET_SET_SRC2 ((uint32_t)0x00000004)
5564 /* initiates a Soft Reset) */
5565/* RSTCTL_SOFTRESET_SET[SRC3] Bits */
5566#define RSTCTL_SOFTRESET_SET_SRC3_OFS ( 3)
5567#define RSTCTL_SOFTRESET_SET_SRC3 ((uint32_t)0x00000008)
5568 /* initiates a Soft Reset) */
5569/* RSTCTL_SOFTRESET_SET[SRC4] Bits */
5570#define RSTCTL_SOFTRESET_SET_SRC4_OFS ( 4)
5571#define RSTCTL_SOFTRESET_SET_SRC4 ((uint32_t)0x00000010)
5572 /* initiates a Soft Reset) */
5573/* RSTCTL_SOFTRESET_SET[SRC5] Bits */
5574#define RSTCTL_SOFTRESET_SET_SRC5_OFS ( 5)
5575#define RSTCTL_SOFTRESET_SET_SRC5 ((uint32_t)0x00000020)
5576 /* initiates a Soft Reset) */
5577/* RSTCTL_SOFTRESET_SET[SRC6] Bits */
5578#define RSTCTL_SOFTRESET_SET_SRC6_OFS ( 6)
5579#define RSTCTL_SOFTRESET_SET_SRC6 ((uint32_t)0x00000040)
5580 /* initiates a Soft Reset) */
5581/* RSTCTL_SOFTRESET_SET[SRC7] Bits */
5582#define RSTCTL_SOFTRESET_SET_SRC7_OFS ( 7)
5583#define RSTCTL_SOFTRESET_SET_SRC7 ((uint32_t)0x00000080)
5584 /* initiates a Soft Reset) */
5585/* RSTCTL_SOFTRESET_SET[SRC8] Bits */
5586#define RSTCTL_SOFTRESET_SET_SRC8_OFS ( 8)
5587#define RSTCTL_SOFTRESET_SET_SRC8 ((uint32_t)0x00000100)
5588 /* initiates a Soft Reset) */
5589/* RSTCTL_SOFTRESET_SET[SRC9] Bits */
5590#define RSTCTL_SOFTRESET_SET_SRC9_OFS ( 9)
5591#define RSTCTL_SOFTRESET_SET_SRC9 ((uint32_t)0x00000200)
5592 /* initiates a Soft Reset) */
5593/* RSTCTL_SOFTRESET_SET[SRC10] Bits */
5594#define RSTCTL_SOFTRESET_SET_SRC10_OFS (10)
5595#define RSTCTL_SOFTRESET_SET_SRC10 ((uint32_t)0x00000400)
5596 /* initiates a Soft Reset) */
5597/* RSTCTL_SOFTRESET_SET[SRC11] Bits */
5598#define RSTCTL_SOFTRESET_SET_SRC11_OFS (11)
5599#define RSTCTL_SOFTRESET_SET_SRC11 ((uint32_t)0x00000800)
5600 /* initiates a Soft Reset) */
5601/* RSTCTL_SOFTRESET_SET[SRC12] Bits */
5602#define RSTCTL_SOFTRESET_SET_SRC12_OFS (12)
5603#define RSTCTL_SOFTRESET_SET_SRC12 ((uint32_t)0x00001000)
5604 /* initiates a Soft Reset) */
5605/* RSTCTL_SOFTRESET_SET[SRC13] Bits */
5606#define RSTCTL_SOFTRESET_SET_SRC13_OFS (13)
5607#define RSTCTL_SOFTRESET_SET_SRC13 ((uint32_t)0x00002000)
5608 /* initiates a Soft Reset) */
5609/* RSTCTL_SOFTRESET_SET[SRC14] Bits */
5610#define RSTCTL_SOFTRESET_SET_SRC14_OFS (14)
5611#define RSTCTL_SOFTRESET_SET_SRC14 ((uint32_t)0x00004000)
5612 /* initiates a Soft Reset) */
5613/* RSTCTL_SOFTRESET_SET[SRC15] Bits */
5614#define RSTCTL_SOFTRESET_SET_SRC15_OFS (15)
5615#define RSTCTL_SOFTRESET_SET_SRC15 ((uint32_t)0x00008000)
5616 /* initiates a Soft Reset) */
5617/* RSTCTL_PSSRESET_STAT[SVSMH] Bits */
5618#define RSTCTL_PSSRESET_STAT_SVSMH_OFS ( 1)
5619#define RSTCTL_PSSRESET_STAT_SVSMH ((uint32_t)0x00000002)
5620/* RSTCTL_PSSRESET_STAT[BGREF] Bits */
5621#define RSTCTL_PSSRESET_STAT_BGREF_OFS ( 2)
5622#define RSTCTL_PSSRESET_STAT_BGREF ((uint32_t)0x00000004)
5623/* RSTCTL_PSSRESET_STAT[VCCDET] Bits */
5624#define RSTCTL_PSSRESET_STAT_VCCDET_OFS ( 3)
5625#define RSTCTL_PSSRESET_STAT_VCCDET ((uint32_t)0x00000008)
5626/* RSTCTL_PSSRESET_CLR[CLR] Bits */
5627#define RSTCTL_PSSRESET_CLR_CLR_OFS ( 0)
5628#define RSTCTL_PSSRESET_CLR_CLR ((uint32_t)0x00000001)
5629/* RSTCTL_PCMRESET_STAT[LPM35] Bits */
5630#define RSTCTL_PCMRESET_STAT_LPM35_OFS ( 0)
5631#define RSTCTL_PCMRESET_STAT_LPM35 ((uint32_t)0x00000001)
5632/* RSTCTL_PCMRESET_STAT[LPM45] Bits */
5633#define RSTCTL_PCMRESET_STAT_LPM45_OFS ( 1)
5634#define RSTCTL_PCMRESET_STAT_LPM45 ((uint32_t)0x00000002)
5635/* RSTCTL_PCMRESET_CLR[CLR] Bits */
5636#define RSTCTL_PCMRESET_CLR_CLR_OFS ( 0)
5637#define RSTCTL_PCMRESET_CLR_CLR ((uint32_t)0x00000001)
5638/* RSTCTL_PINRESET_STAT[RSTNMI] Bits */
5639#define RSTCTL_PINRESET_STAT_RSTNMI_OFS ( 0)
5640#define RSTCTL_PINRESET_STAT_RSTNMI ((uint32_t)0x00000001)
5641/* RSTCTL_PINRESET_CLR[CLR] Bits */
5642#define RSTCTL_PINRESET_CLR_CLR_OFS ( 0)
5643#define RSTCTL_PINRESET_CLR_CLR ((uint32_t)0x00000001)
5644/* RSTCTL_REBOOTRESET_STAT[REBOOT] Bits */
5645#define RSTCTL_REBOOTRESET_STAT_REBOOT_OFS ( 0)
5646#define RSTCTL_REBOOTRESET_STAT_REBOOT ((uint32_t)0x00000001)
5647/* RSTCTL_REBOOTRESET_CLR[CLR] Bits */
5648#define RSTCTL_REBOOTRESET_CLR_CLR_OFS ( 0)
5649#define RSTCTL_REBOOTRESET_CLR_CLR ((uint32_t)0x00000001)
5650/* RSTCTL_CSRESET_STAT[DCOR_SHT] Bits */
5651#define RSTCTL_CSRESET_STAT_DCOR_SHT_OFS ( 0)
5652#define RSTCTL_CSRESET_STAT_DCOR_SHT ((uint32_t)0x00000001)
5653 /* resistor mode */
5654/* RSTCTL_CSRESET_CLR[CLR] Bits */
5655#define RSTCTL_CSRESET_CLR_CLR_OFS ( 0)
5656#define RSTCTL_CSRESET_CLR_CLR ((uint32_t)0x00000001)
5657 /* DCOR_SHTIFG flag in CSIFG register of clock system */
5658/* Pre-defined bitfield values */
5659#define RSTCTL_RESETREQ_RSTKEY_VAL ((uint32_t)0x00006900)
5662/******************************************************************************
5663* RTC_C Bits
5664******************************************************************************/
5665/* RTC_C_CTL0[RDYIFG] Bits */
5666#define RTC_C_CTL0_RDYIFG_OFS ( 0)
5667#define RTC_C_CTL0_RDYIFG ((uint16_t)0x0001)
5668/* RTC_C_CTL0[AIFG] Bits */
5669#define RTC_C_CTL0_AIFG_OFS ( 1)
5670#define RTC_C_CTL0_AIFG ((uint16_t)0x0002)
5671/* RTC_C_CTL0[TEVIFG] Bits */
5672#define RTC_C_CTL0_TEVIFG_OFS ( 2)
5673#define RTC_C_CTL0_TEVIFG ((uint16_t)0x0004)
5674/* RTC_C_CTL0[OFIFG] Bits */
5675#define RTC_C_CTL0_OFIFG_OFS ( 3)
5676#define RTC_C_CTL0_OFIFG ((uint16_t)0x0008)
5677/* RTC_C_CTL0[RDYIE] Bits */
5678#define RTC_C_CTL0_RDYIE_OFS ( 4)
5679#define RTC_C_CTL0_RDYIE ((uint16_t)0x0010)
5680/* RTC_C_CTL0[AIE] Bits */
5681#define RTC_C_CTL0_AIE_OFS ( 5)
5682#define RTC_C_CTL0_AIE ((uint16_t)0x0020)
5683/* RTC_C_CTL0[TEVIE] Bits */
5684#define RTC_C_CTL0_TEVIE_OFS ( 6)
5685#define RTC_C_CTL0_TEVIE ((uint16_t)0x0040)
5686/* RTC_C_CTL0[OFIE] Bits */
5687#define RTC_C_CTL0_OFIE_OFS ( 7)
5688#define RTC_C_CTL0_OFIE ((uint16_t)0x0080)
5689/* RTC_C_CTL0[KEY] Bits */
5690#define RTC_C_CTL0_KEY_OFS ( 8)
5691#define RTC_C_CTL0_KEY_MASK ((uint16_t)0xFF00)
5692/* RTC_C_CTL13[TEV] Bits */
5693#define RTC_C_CTL13_TEV_OFS ( 0)
5694#define RTC_C_CTL13_TEV_MASK ((uint16_t)0x0003)
5695#define RTC_C_CTL13_TEV0 ((uint16_t)0x0001)
5696#define RTC_C_CTL13_TEV1 ((uint16_t)0x0002)
5697#define RTC_C_CTL13_TEV_0 ((uint16_t)0x0000)
5698#define RTC_C_CTL13_TEV_1 ((uint16_t)0x0001)
5699#define RTC_C_CTL13_TEV_2 ((uint16_t)0x0002)
5700#define RTC_C_CTL13_TEV_3 ((uint16_t)0x0003)
5701/* RTC_C_CTL13[SSEL] Bits */
5702#define RTC_C_CTL13_SSEL_OFS ( 2)
5703#define RTC_C_CTL13_SSEL_MASK ((uint16_t)0x000C)
5704#define RTC_C_CTL13_SSEL0 ((uint16_t)0x0004)
5705#define RTC_C_CTL13_SSEL1 ((uint16_t)0x0008)
5706#define RTC_C_CTL13_SSEL_0 ((uint16_t)0x0000)
5707#define RTC_C_CTL13_SSEL__BCLK ((uint16_t)0x0000)
5708/* RTC_C_CTL13[RDY] Bits */
5709#define RTC_C_CTL13_RDY_OFS ( 4)
5710#define RTC_C_CTL13_RDY ((uint16_t)0x0010)
5711/* RTC_C_CTL13[MODE] Bits */
5712#define RTC_C_CTL13_MODE_OFS ( 5)
5713#define RTC_C_CTL13_MODE ((uint16_t)0x0020)
5714/* RTC_C_CTL13[HOLD] Bits */
5715#define RTC_C_CTL13_HOLD_OFS ( 6)
5716#define RTC_C_CTL13_HOLD ((uint16_t)0x0040)
5717/* RTC_C_CTL13[BCD] Bits */
5718#define RTC_C_CTL13_BCD_OFS ( 7)
5719#define RTC_C_CTL13_BCD ((uint16_t)0x0080)
5720/* RTC_C_CTL13[CALF] Bits */
5721#define RTC_C_CTL13_CALF_OFS ( 8)
5722#define RTC_C_CTL13_CALF_MASK ((uint16_t)0x0300)
5723#define RTC_C_CTL13_CALF0 ((uint16_t)0x0100)
5724#define RTC_C_CTL13_CALF1 ((uint16_t)0x0200)
5725#define RTC_C_CTL13_CALF_0 ((uint16_t)0x0000)
5726#define RTC_C_CTL13_CALF_1 ((uint16_t)0x0100)
5727#define RTC_C_CTL13_CALF_2 ((uint16_t)0x0200)
5728#define RTC_C_CTL13_CALF_3 ((uint16_t)0x0300)
5729#define RTC_C_CTL13_CALF__NONE ((uint16_t)0x0000)
5730#define RTC_C_CTL13_CALF__512 ((uint16_t)0x0100)
5731#define RTC_C_CTL13_CALF__256 ((uint16_t)0x0200)
5732#define RTC_C_CTL13_CALF__1 ((uint16_t)0x0300)
5733/* RTC_C_OCAL[OCAL] Bits */
5734#define RTC_C_OCAL_OCAL_OFS ( 0)
5735#define RTC_C_OCAL_OCAL_MASK ((uint16_t)0x00FF)
5736/* RTC_C_OCAL[OCALS] Bits */
5737#define RTC_C_OCAL_OCALS_OFS (15)
5738#define RTC_C_OCAL_OCALS ((uint16_t)0x8000)
5739/* RTC_C_TCMP[TCMPx] Bits */
5740#define RTC_C_TCMP_TCMPX_OFS ( 0)
5741#define RTC_C_TCMP_TCMPX_MASK ((uint16_t)0x00FF)
5742/* RTC_C_TCMP[TCOK] Bits */
5743#define RTC_C_TCMP_TCOK_OFS (13)
5744#define RTC_C_TCMP_TCOK ((uint16_t)0x2000)
5745/* RTC_C_TCMP[TCRDY] Bits */
5746#define RTC_C_TCMP_TCRDY_OFS (14)
5747#define RTC_C_TCMP_TCRDY ((uint16_t)0x4000)
5748/* RTC_C_TCMP[TCMPS] Bits */
5749#define RTC_C_TCMP_TCMPS_OFS (15)
5750#define RTC_C_TCMP_TCMPS ((uint16_t)0x8000)
5751/* RTC_C_PS0CTL[RT0PSIFG] Bits */
5752#define RTC_C_PS0CTL_RT0PSIFG_OFS ( 0)
5753#define RTC_C_PS0CTL_RT0PSIFG ((uint16_t)0x0001)
5754/* RTC_C_PS0CTL[RT0PSIE] Bits */
5755#define RTC_C_PS0CTL_RT0PSIE_OFS ( 1)
5756#define RTC_C_PS0CTL_RT0PSIE ((uint16_t)0x0002)
5757/* RTC_C_PS0CTL[RT0IP] Bits */
5758#define RTC_C_PS0CTL_RT0IP_OFS ( 2)
5759#define RTC_C_PS0CTL_RT0IP_MASK ((uint16_t)0x001C)
5760#define RTC_C_PS0CTL_RT0IP0 ((uint16_t)0x0004)
5761#define RTC_C_PS0CTL_RT0IP1 ((uint16_t)0x0008)
5762#define RTC_C_PS0CTL_RT0IP2 ((uint16_t)0x0010)
5763#define RTC_C_PS0CTL_RT0IP_0 ((uint16_t)0x0000)
5764#define RTC_C_PS0CTL_RT0IP_1 ((uint16_t)0x0004)
5765#define RTC_C_PS0CTL_RT0IP_2 ((uint16_t)0x0008)
5766#define RTC_C_PS0CTL_RT0IP_3 ((uint16_t)0x000C)
5767#define RTC_C_PS0CTL_RT0IP_4 ((uint16_t)0x0010)
5768#define RTC_C_PS0CTL_RT0IP_5 ((uint16_t)0x0014)
5769#define RTC_C_PS0CTL_RT0IP_6 ((uint16_t)0x0018)
5770#define RTC_C_PS0CTL_RT0IP_7 ((uint16_t)0x001C)
5771#define RTC_C_PS0CTL_RT0IP__2 ((uint16_t)0x0000)
5772#define RTC_C_PS0CTL_RT0IP__4 ((uint16_t)0x0004)
5773#define RTC_C_PS0CTL_RT0IP__8 ((uint16_t)0x0008)
5774#define RTC_C_PS0CTL_RT0IP__16 ((uint16_t)0x000C)
5775#define RTC_C_PS0CTL_RT0IP__32 ((uint16_t)0x0010)
5776#define RTC_C_PS0CTL_RT0IP__64 ((uint16_t)0x0014)
5777#define RTC_C_PS0CTL_RT0IP__128 ((uint16_t)0x0018)
5778#define RTC_C_PS0CTL_RT0IP__256 ((uint16_t)0x001C)
5779/* RTC_C_PS1CTL[RT1PSIFG] Bits */
5780#define RTC_C_PS1CTL_RT1PSIFG_OFS ( 0)
5781#define RTC_C_PS1CTL_RT1PSIFG ((uint16_t)0x0001)
5782/* RTC_C_PS1CTL[RT1PSIE] Bits */
5783#define RTC_C_PS1CTL_RT1PSIE_OFS ( 1)
5784#define RTC_C_PS1CTL_RT1PSIE ((uint16_t)0x0002)
5785/* RTC_C_PS1CTL[RT1IP] Bits */
5786#define RTC_C_PS1CTL_RT1IP_OFS ( 2)
5787#define RTC_C_PS1CTL_RT1IP_MASK ((uint16_t)0x001C)
5788#define RTC_C_PS1CTL_RT1IP0 ((uint16_t)0x0004)
5789#define RTC_C_PS1CTL_RT1IP1 ((uint16_t)0x0008)
5790#define RTC_C_PS1CTL_RT1IP2 ((uint16_t)0x0010)
5791#define RTC_C_PS1CTL_RT1IP_0 ((uint16_t)0x0000)
5792#define RTC_C_PS1CTL_RT1IP_1 ((uint16_t)0x0004)
5793#define RTC_C_PS1CTL_RT1IP_2 ((uint16_t)0x0008)
5794#define RTC_C_PS1CTL_RT1IP_3 ((uint16_t)0x000C)
5795#define RTC_C_PS1CTL_RT1IP_4 ((uint16_t)0x0010)
5796#define RTC_C_PS1CTL_RT1IP_5 ((uint16_t)0x0014)
5797#define RTC_C_PS1CTL_RT1IP_6 ((uint16_t)0x0018)
5798#define RTC_C_PS1CTL_RT1IP_7 ((uint16_t)0x001C)
5799#define RTC_C_PS1CTL_RT1IP__2 ((uint16_t)0x0000)
5800#define RTC_C_PS1CTL_RT1IP__4 ((uint16_t)0x0004)
5801#define RTC_C_PS1CTL_RT1IP__8 ((uint16_t)0x0008)
5802#define RTC_C_PS1CTL_RT1IP__16 ((uint16_t)0x000C)
5803#define RTC_C_PS1CTL_RT1IP__32 ((uint16_t)0x0010)
5804#define RTC_C_PS1CTL_RT1IP__64 ((uint16_t)0x0014)
5805#define RTC_C_PS1CTL_RT1IP__128 ((uint16_t)0x0018)
5806#define RTC_C_PS1CTL_RT1IP__256 ((uint16_t)0x001C)
5807/* RTC_C_PS[RT0PS] Bits */
5808#define RTC_C_PS_RT0PS_OFS ( 0)
5809#define RTC_C_PS_RT0PS_MASK ((uint16_t)0x00FF)
5810/* RTC_C_PS[RT1PS] Bits */
5811#define RTC_C_PS_RT1PS_OFS ( 8)
5812#define RTC_C_PS_RT1PS_MASK ((uint16_t)0xFF00)
5813/* RTC_C_TIM0[SEC] Bits */
5814#define RTC_C_TIM0_SEC_OFS ( 0)
5815#define RTC_C_TIM0_SEC_MASK ((uint16_t)0x003F)
5816/* RTC_C_TIM0[MIN] Bits */
5817#define RTC_C_TIM0_MIN_OFS ( 8)
5818#define RTC_C_TIM0_MIN_MASK ((uint16_t)0x3F00)
5819/* RTC_C_TIM0[SEC_LD] Bits */
5820#define RTC_C_TIM0_SEC_LD_OFS ( 0)
5821#define RTC_C_TIM0_SEC_LD_MASK ((uint16_t)0x000F)
5822/* RTC_C_TIM0[SEC_HD] Bits */
5823#define RTC_C_TIM0_SEC_HD_OFS ( 4)
5824#define RTC_C_TIM0_SEC_HD_MASK ((uint16_t)0x0070)
5825/* RTC_C_TIM0[MIN_LD] Bits */
5826#define RTC_C_TIM0_MIN_LD_OFS ( 8)
5827#define RTC_C_TIM0_MIN_LD_MASK ((uint16_t)0x0F00)
5828/* RTC_C_TIM0[MIN_HD] Bits */
5829#define RTC_C_TIM0_MIN_HD_OFS (12)
5830#define RTC_C_TIM0_MIN_HD_MASK ((uint16_t)0x7000)
5831/* RTC_C_TIM1[HOUR] Bits */
5832#define RTC_C_TIM1_HOUR_OFS ( 0)
5833#define RTC_C_TIM1_HOUR_MASK ((uint16_t)0x001F)
5834/* RTC_C_TIM1[DOW] Bits */
5835#define RTC_C_TIM1_DOW_OFS ( 8)
5836#define RTC_C_TIM1_DOW_MASK ((uint16_t)0x0700)
5837/* RTC_C_TIM1[HOUR_LD] Bits */
5838#define RTC_C_TIM1_HOUR_LD_OFS ( 0)
5839#define RTC_C_TIM1_HOUR_LD_MASK ((uint16_t)0x000F)
5840/* RTC_C_TIM1[HOUR_HD] Bits */
5841#define RTC_C_TIM1_HOUR_HD_OFS ( 4)
5842#define RTC_C_TIM1_HOUR_HD_MASK ((uint16_t)0x0030)
5843/* RTC_C_DATE[DAY] Bits */
5844#define RTC_C_DATE_DAY_OFS ( 0)
5845#define RTC_C_DATE_DAY_MASK ((uint16_t)0x001F)
5846/* RTC_C_DATE[MON] Bits */
5847#define RTC_C_DATE_MON_OFS ( 8)
5848#define RTC_C_DATE_MON_MASK ((uint16_t)0x0F00)
5849/* RTC_C_DATE[DAY_LD] Bits */
5850#define RTC_C_DATE_DAY_LD_OFS ( 0)
5851#define RTC_C_DATE_DAY_LD_MASK ((uint16_t)0x000F)
5852/* RTC_C_DATE[DAY_HD] Bits */
5853#define RTC_C_DATE_DAY_HD_OFS ( 4)
5854#define RTC_C_DATE_DAY_HD_MASK ((uint16_t)0x0030)
5855/* RTC_C_DATE[MON_LD] Bits */
5856#define RTC_C_DATE_MON_LD_OFS ( 8)
5857#define RTC_C_DATE_MON_LD_MASK ((uint16_t)0x0F00)
5858/* RTC_C_DATE[MON_HD] Bits */
5859#define RTC_C_DATE_MON_HD_OFS (12)
5860#define RTC_C_DATE_MON_HD ((uint16_t)0x1000)
5861/* RTC_C_YEAR[YEAR_LB] Bits */
5862#define RTC_C_YEAR_YEAR_LB_OFS ( 0)
5863#define RTC_C_YEAR_YEAR_LB_MASK ((uint16_t)0x00FF)
5864/* RTC_C_YEAR[YEAR_HB] Bits */
5865#define RTC_C_YEAR_YEAR_HB_OFS ( 8)
5866#define RTC_C_YEAR_YEAR_HB_MASK ((uint16_t)0x0F00)
5867/* RTC_C_YEAR[YEAR] Bits */
5868#define RTC_C_YEAR_YEAR_OFS ( 0)
5869#define RTC_C_YEAR_YEAR_MASK ((uint16_t)0x000F)
5870/* RTC_C_YEAR[DEC] Bits */
5871#define RTC_C_YEAR_DEC_OFS ( 4)
5872#define RTC_C_YEAR_DEC_MASK ((uint16_t)0x00F0)
5873/* RTC_C_YEAR[CENT_LD] Bits */
5874#define RTC_C_YEAR_CENT_LD_OFS ( 8)
5875#define RTC_C_YEAR_CENT_LD_MASK ((uint16_t)0x0F00)
5876/* RTC_C_YEAR[CENT_HD] Bits */
5877#define RTC_C_YEAR_CENT_HD_OFS (12)
5878#define RTC_C_YEAR_CENT_HD_MASK ((uint16_t)0x7000)
5879/* RTC_C_AMINHR[MIN] Bits */
5880#define RTC_C_AMINHR_MIN_OFS ( 0)
5881#define RTC_C_AMINHR_MIN_MASK ((uint16_t)0x003F)
5882/* RTC_C_AMINHR[MINAE] Bits */
5883#define RTC_C_AMINHR_MINAE_OFS ( 7)
5884#define RTC_C_AMINHR_MINAE ((uint16_t)0x0080)
5885/* RTC_C_AMINHR[HOUR] Bits */
5886#define RTC_C_AMINHR_HOUR_OFS ( 8)
5887#define RTC_C_AMINHR_HOUR_MASK ((uint16_t)0x1F00)
5888/* RTC_C_AMINHR[HOURAE] Bits */
5889#define RTC_C_AMINHR_HOURAE_OFS (15)
5890#define RTC_C_AMINHR_HOURAE ((uint16_t)0x8000)
5891/* RTC_C_AMINHR[MIN_LD] Bits */
5892#define RTC_C_AMINHR_MIN_LD_OFS ( 0)
5893#define RTC_C_AMINHR_MIN_LD_MASK ((uint16_t)0x000F)
5894/* RTC_C_AMINHR[MIN_HD] Bits */
5895#define RTC_C_AMINHR_MIN_HD_OFS ( 4)
5896#define RTC_C_AMINHR_MIN_HD_MASK ((uint16_t)0x0070)
5897/* RTC_C_AMINHR[HOUR_LD] Bits */
5898#define RTC_C_AMINHR_HOUR_LD_OFS ( 8)
5899#define RTC_C_AMINHR_HOUR_LD_MASK ((uint16_t)0x0F00)
5900/* RTC_C_AMINHR[HOUR_HD] Bits */
5901#define RTC_C_AMINHR_HOUR_HD_OFS (12)
5902#define RTC_C_AMINHR_HOUR_HD_MASK ((uint16_t)0x3000)
5903/* RTC_C_ADOWDAY[DOW] Bits */
5904#define RTC_C_ADOWDAY_DOW_OFS ( 0)
5905#define RTC_C_ADOWDAY_DOW_MASK ((uint16_t)0x0007)
5906/* RTC_C_ADOWDAY[DOWAE] Bits */
5907#define RTC_C_ADOWDAY_DOWAE_OFS ( 7)
5908#define RTC_C_ADOWDAY_DOWAE ((uint16_t)0x0080)
5909/* RTC_C_ADOWDAY[DAY] Bits */
5910#define RTC_C_ADOWDAY_DAY_OFS ( 8)
5911#define RTC_C_ADOWDAY_DAY_MASK ((uint16_t)0x1F00)
5912/* RTC_C_ADOWDAY[DAYAE] Bits */
5913#define RTC_C_ADOWDAY_DAYAE_OFS (15)
5914#define RTC_C_ADOWDAY_DAYAE ((uint16_t)0x8000)
5915/* RTC_C_ADOWDAY[DAY_LD] Bits */
5916#define RTC_C_ADOWDAY_DAY_LD_OFS ( 8)
5917#define RTC_C_ADOWDAY_DAY_LD_MASK ((uint16_t)0x0F00)
5918/* RTC_C_ADOWDAY[DAY_HD] Bits */
5919#define RTC_C_ADOWDAY_DAY_HD_OFS (12)
5920#define RTC_C_ADOWDAY_DAY_HD_MASK ((uint16_t)0x3000)
5921/* Pre-defined bitfield values */
5922#define RTC_C_KEY ((uint16_t)0xA500)
5923#define RTC_C_KEY_H ((uint16_t)0x00A5)
5924#define RTC_C_KEY_VAL ((uint16_t)0xA500)
5927/******************************************************************************
5928* SCB Bits
5929******************************************************************************/
5930/* SCB_PFR0[STATE0] Bits */
5931#define SCB_PFR0_STATE0_OFS ( 0)
5932#define SCB_PFR0_STATE0_MASK ((uint32_t)0x0000000F)
5933#define SCB_PFR0_STATE00 ((uint32_t)0x00000001)
5934#define SCB_PFR0_STATE01 ((uint32_t)0x00000002)
5935#define SCB_PFR0_STATE02 ((uint32_t)0x00000004)
5936#define SCB_PFR0_STATE03 ((uint32_t)0x00000008)
5937#define SCB_PFR0_STATE0_0 ((uint32_t)0x00000000)
5938#define SCB_PFR0_STATE0_1 ((uint32_t)0x00000001)
5939/* SCB_PFR0[STATE1] Bits */
5940#define SCB_PFR0_STATE1_OFS ( 4)
5941#define SCB_PFR0_STATE1_MASK ((uint32_t)0x000000F0)
5942#define SCB_PFR0_STATE10 ((uint32_t)0x00000010)
5943#define SCB_PFR0_STATE11 ((uint32_t)0x00000020)
5944#define SCB_PFR0_STATE12 ((uint32_t)0x00000040)
5945#define SCB_PFR0_STATE13 ((uint32_t)0x00000080)
5946#define SCB_PFR0_STATE1_0 ((uint32_t)0x00000000)
5947#define SCB_PFR0_STATE1_1 ((uint32_t)0x00000010)
5948#define SCB_PFR0_STATE1_2 ((uint32_t)0x00000020)
5949 /* but no other 32-bit basic instructions (Note non-basic 32-bit instructions */
5950 /* can be added using the appropriate instruction attribute, but other 32-bit */
5951 /* basic instructions cannot.) */
5952#define SCB_PFR0_STATE1_3 ((uint32_t)0x00000030)
5953/* SCB_PFR1[MICROCONTROLLER_PROGRAMMERS_MODEL] Bits */
5954#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_OFS ( 8)
5955#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_MASK ((uint32_t)0x00000F00)
5956#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL0 ((uint32_t)0x00000100)
5957#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL1 ((uint32_t)0x00000200)
5958#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL2 ((uint32_t)0x00000400)
5959#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL3 ((uint32_t)0x00000800)
5960#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_0 ((uint32_t)0x00000000)
5961#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_2 ((uint32_t)0x00000200)
5962/* SCB_DFR0[MICROCONTROLLER_DEBUG_MODEL] Bits */
5963#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_OFS (20)
5964#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_MASK ((uint32_t)0x00F00000)
5965#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL0 ((uint32_t)0x00100000)
5966#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL1 ((uint32_t)0x00200000)
5967#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL2 ((uint32_t)0x00400000)
5968#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL3 ((uint32_t)0x00800000)
5969#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_0 ((uint32_t)0x00000000)
5970#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_1 ((uint32_t)0x00100000)
5971/* SCB_MMFR0[PMSA_SUPPORT] Bits */
5972#define SCB_MMFR0_PMSA_SUPPORT_OFS ( 4)
5973#define SCB_MMFR0_PMSA_SUPPORT_MASK ((uint32_t)0x000000F0)
5974#define SCB_MMFR0_PMSA_SUPPORT0 ((uint32_t)0x00000010)
5975#define SCB_MMFR0_PMSA_SUPPORT1 ((uint32_t)0x00000020)
5976#define SCB_MMFR0_PMSA_SUPPORT2 ((uint32_t)0x00000040)
5977#define SCB_MMFR0_PMSA_SUPPORT3 ((uint32_t)0x00000080)
5978#define SCB_MMFR0_PMSA_SUPPORT_0 ((uint32_t)0x00000000)
5979#define SCB_MMFR0_PMSA_SUPPORT_1 ((uint32_t)0x00000010)
5980#define SCB_MMFR0_PMSA_SUPPORT_2 ((uint32_t)0x00000020)
5981#define SCB_MMFR0_PMSA_SUPPORT_3 ((uint32_t)0x00000030)
5982/* SCB_MMFR0[CACHE_COHERENCE_SUPPORT] Bits */
5983#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_OFS ( 8)
5984#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_MASK ((uint32_t)0x00000F00)
5985#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT0 ((uint32_t)0x00000100)
5986#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT1 ((uint32_t)0x00000200)
5987#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT2 ((uint32_t)0x00000400)
5988#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT3 ((uint32_t)0x00000800)
5989#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_0 ((uint32_t)0x00000000)
5990#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_1 ((uint32_t)0x00000100)
5991 /* the entities within an inner-coherent domain) */
5992#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_2 ((uint32_t)0x00000200)
5993 /* inner-coherent domain) */
5994#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_3 ((uint32_t)0x00000300)
5995/* SCB_MMFR0[OUTER_NON_SHARABLE_SUPPORT] Bits */
5996#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_OFS (12)
5997#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_MASK ((uint32_t)0x0000F000)
5998#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT0 ((uint32_t)0x00001000)
5999#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT1 ((uint32_t)0x00002000)
6000#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT2 ((uint32_t)0x00004000)
6001#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT3 ((uint32_t)0x00008000)
6002#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_0 ((uint32_t)0x00000000)
6003#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_1 ((uint32_t)0x00001000)
6004/* SCB_MMFR0[AUILIARY_REGISTER_SUPPORT] Bits */
6005#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_OFS (20)
6006#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_MASK ((uint32_t)0x00F00000)
6007#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT0 ((uint32_t)0x00100000)
6008#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT1 ((uint32_t)0x00200000)
6009#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT2 ((uint32_t)0x00400000)
6010#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT3 ((uint32_t)0x00800000)
6011#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_0 ((uint32_t)0x00000000)
6012#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_1 ((uint32_t)0x00100000)
6013/* SCB_MMFR2[WAIT_FOR_INTERRUPT_STALLING] Bits */
6014#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_OFS (24)
6015#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_MASK ((uint32_t)0x0F000000)
6016#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING0 ((uint32_t)0x01000000)
6017#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING1 ((uint32_t)0x02000000)
6018#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING2 ((uint32_t)0x04000000)
6019#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING3 ((uint32_t)0x08000000)
6020#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_0 ((uint32_t)0x00000000)
6021#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_1 ((uint32_t)0x01000000)
6022/* SCB_ISAR0[BITCOUNT_INSTRS] Bits */
6023#define SCB_ISAR0_BITCOUNT_INSTRS_OFS ( 4)
6024#define SCB_ISAR0_BITCOUNT_INSTRS_MASK ((uint32_t)0x000000F0)
6025#define SCB_ISAR0_BITCOUNT_INSTRS0 ((uint32_t)0x00000010)
6026#define SCB_ISAR0_BITCOUNT_INSTRS1 ((uint32_t)0x00000020)
6027#define SCB_ISAR0_BITCOUNT_INSTRS2 ((uint32_t)0x00000040)
6028#define SCB_ISAR0_BITCOUNT_INSTRS3 ((uint32_t)0x00000080)
6029#define SCB_ISAR0_BITCOUNT_INSTRS_0 ((uint32_t)0x00000000)
6030#define SCB_ISAR0_BITCOUNT_INSTRS_1 ((uint32_t)0x00000010)
6031/* SCB_ISAR0[BITFIELD_INSTRS] Bits */
6032#define SCB_ISAR0_BITFIELD_INSTRS_OFS ( 8)
6033#define SCB_ISAR0_BITFIELD_INSTRS_MASK ((uint32_t)0x00000F00)
6034#define SCB_ISAR0_BITFIELD_INSTRS0 ((uint32_t)0x00000100)
6035#define SCB_ISAR0_BITFIELD_INSTRS1 ((uint32_t)0x00000200)
6036#define SCB_ISAR0_BITFIELD_INSTRS2 ((uint32_t)0x00000400)
6037#define SCB_ISAR0_BITFIELD_INSTRS3 ((uint32_t)0x00000800)
6038#define SCB_ISAR0_BITFIELD_INSTRS_0 ((uint32_t)0x00000000)
6039#define SCB_ISAR0_BITFIELD_INSTRS_1 ((uint32_t)0x00000100)
6040/* SCB_ISAR0[CMPBRANCH_INSTRS] Bits */
6041#define SCB_ISAR0_CMPBRANCH_INSTRS_OFS (12)
6042#define SCB_ISAR0_CMPBRANCH_INSTRS_MASK ((uint32_t)0x0000F000)
6043#define SCB_ISAR0_CMPBRANCH_INSTRS0 ((uint32_t)0x00001000)
6044#define SCB_ISAR0_CMPBRANCH_INSTRS1 ((uint32_t)0x00002000)
6045#define SCB_ISAR0_CMPBRANCH_INSTRS2 ((uint32_t)0x00004000)
6046#define SCB_ISAR0_CMPBRANCH_INSTRS3 ((uint32_t)0x00008000)
6047#define SCB_ISAR0_CMPBRANCH_INSTRS_0 ((uint32_t)0x00000000)
6048#define SCB_ISAR0_CMPBRANCH_INSTRS_1 ((uint32_t)0x00001000)
6049/* SCB_ISAR0[COPROC_INSTRS] Bits */
6050#define SCB_ISAR0_COPROC_INSTRS_OFS (16)
6051#define SCB_ISAR0_COPROC_INSTRS_MASK ((uint32_t)0x000F0000)
6052#define SCB_ISAR0_COPROC_INSTRS0 ((uint32_t)0x00010000)
6053#define SCB_ISAR0_COPROC_INSTRS1 ((uint32_t)0x00020000)
6054#define SCB_ISAR0_COPROC_INSTRS2 ((uint32_t)0x00040000)
6055#define SCB_ISAR0_COPROC_INSTRS3 ((uint32_t)0x00080000)
6056#define SCB_ISAR0_COPROC_INSTRS_0 ((uint32_t)0x00000000)
6057 /* such as CP15 or VFP */
6058#define SCB_ISAR0_COPROC_INSTRS_1 ((uint32_t)0x00010000)
6059#define SCB_ISAR0_COPROC_INSTRS_2 ((uint32_t)0x00020000)
6060#define SCB_ISAR0_COPROC_INSTRS_3 ((uint32_t)0x00030000)
6061#define SCB_ISAR0_COPROC_INSTRS_4 ((uint32_t)0x00040000)
6062/* SCB_ISAR0[DEBUG_INSTRS] Bits */
6063#define SCB_ISAR0_DEBUG_INSTRS_OFS (20)
6064#define SCB_ISAR0_DEBUG_INSTRS_MASK ((uint32_t)0x00F00000)
6065#define SCB_ISAR0_DEBUG_INSTRS0 ((uint32_t)0x00100000)
6066#define SCB_ISAR0_DEBUG_INSTRS1 ((uint32_t)0x00200000)
6067#define SCB_ISAR0_DEBUG_INSTRS2 ((uint32_t)0x00400000)
6068#define SCB_ISAR0_DEBUG_INSTRS3 ((uint32_t)0x00800000)
6069#define SCB_ISAR0_DEBUG_INSTRS_0 ((uint32_t)0x00000000)
6070#define SCB_ISAR0_DEBUG_INSTRS_1 ((uint32_t)0x00100000)
6071/* SCB_ISAR0[DIVIDE_INSTRS] Bits */
6072#define SCB_ISAR0_DIVIDE_INSTRS_OFS (24)
6073#define SCB_ISAR0_DIVIDE_INSTRS_MASK ((uint32_t)0x0F000000)
6074#define SCB_ISAR0_DIVIDE_INSTRS0 ((uint32_t)0x01000000)
6075#define SCB_ISAR0_DIVIDE_INSTRS1 ((uint32_t)0x02000000)
6076#define SCB_ISAR0_DIVIDE_INSTRS2 ((uint32_t)0x04000000)
6077#define SCB_ISAR0_DIVIDE_INSTRS3 ((uint32_t)0x08000000)
6078#define SCB_ISAR0_DIVIDE_INSTRS_0 ((uint32_t)0x00000000)
6079#define SCB_ISAR0_DIVIDE_INSTRS_1 ((uint32_t)0x01000000)
6080/* SCB_ISAR1[ETEND_INSRS] Bits */
6081#define SCB_ISAR1_ETEND_INSRS_OFS (12)
6082#define SCB_ISAR1_ETEND_INSRS_MASK ((uint32_t)0x0000F000)
6083#define SCB_ISAR1_ETEND_INSRS0 ((uint32_t)0x00001000)
6084#define SCB_ISAR1_ETEND_INSRS1 ((uint32_t)0x00002000)
6085#define SCB_ISAR1_ETEND_INSRS2 ((uint32_t)0x00004000)
6086#define SCB_ISAR1_ETEND_INSRS3 ((uint32_t)0x00008000)
6087#define SCB_ISAR1_ETEND_INSRS_0 ((uint32_t)0x00000000)
6088#define SCB_ISAR1_ETEND_INSRS_1 ((uint32_t)0x00001000)
6089#define SCB_ISAR1_ETEND_INSRS_2 ((uint32_t)0x00002000)
6090/* SCB_ISAR1[IFTHEN_INSTRS] Bits */
6091#define SCB_ISAR1_IFTHEN_INSTRS_OFS (16)
6092#define SCB_ISAR1_IFTHEN_INSTRS_MASK ((uint32_t)0x000F0000)
6093#define SCB_ISAR1_IFTHEN_INSTRS0 ((uint32_t)0x00010000)
6094#define SCB_ISAR1_IFTHEN_INSTRS1 ((uint32_t)0x00020000)
6095#define SCB_ISAR1_IFTHEN_INSTRS2 ((uint32_t)0x00040000)
6096#define SCB_ISAR1_IFTHEN_INSTRS3 ((uint32_t)0x00080000)
6097#define SCB_ISAR1_IFTHEN_INSTRS_0 ((uint32_t)0x00000000)
6098#define SCB_ISAR1_IFTHEN_INSTRS_1 ((uint32_t)0x00010000)
6099/* SCB_ISAR1[IMMEDIATE_INSTRS] Bits */
6100#define SCB_ISAR1_IMMEDIATE_INSTRS_OFS (20)
6101#define SCB_ISAR1_IMMEDIATE_INSTRS_MASK ((uint32_t)0x00F00000)
6102#define SCB_ISAR1_IMMEDIATE_INSTRS0 ((uint32_t)0x00100000)
6103#define SCB_ISAR1_IMMEDIATE_INSTRS1 ((uint32_t)0x00200000)
6104#define SCB_ISAR1_IMMEDIATE_INSTRS2 ((uint32_t)0x00400000)
6105#define SCB_ISAR1_IMMEDIATE_INSTRS3 ((uint32_t)0x00800000)
6106#define SCB_ISAR1_IMMEDIATE_INSTRS_0 ((uint32_t)0x00000000)
6107#define SCB_ISAR1_IMMEDIATE_INSTRS_1 ((uint32_t)0x00100000)
6108/* SCB_ISAR1[INTERWORK_INSTRS] Bits */
6109#define SCB_ISAR1_INTERWORK_INSTRS_OFS (24)
6110#define SCB_ISAR1_INTERWORK_INSTRS_MASK ((uint32_t)0x0F000000)
6111#define SCB_ISAR1_INTERWORK_INSTRS0 ((uint32_t)0x01000000)
6112#define SCB_ISAR1_INTERWORK_INSTRS1 ((uint32_t)0x02000000)
6113#define SCB_ISAR1_INTERWORK_INSTRS2 ((uint32_t)0x04000000)
6114#define SCB_ISAR1_INTERWORK_INSTRS3 ((uint32_t)0x08000000)
6115#define SCB_ISAR1_INTERWORK_INSTRS_0 ((uint32_t)0x00000000)
6116#define SCB_ISAR1_INTERWORK_INSTRS_1 ((uint32_t)0x01000000)
6117#define SCB_ISAR1_INTERWORK_INSTRS_2 ((uint32_t)0x02000000)
6118#define SCB_ISAR1_INTERWORK_INSTRS_3 ((uint32_t)0x03000000)
6119/* SCB_ISAR2[LOADSTORE_INSTRS] Bits */
6120#define SCB_ISAR2_LOADSTORE_INSTRS_OFS ( 0)
6121#define SCB_ISAR2_LOADSTORE_INSTRS_MASK ((uint32_t)0x0000000F)
6122#define SCB_ISAR2_LOADSTORE_INSTRS0 ((uint32_t)0x00000001)
6123#define SCB_ISAR2_LOADSTORE_INSTRS1 ((uint32_t)0x00000002)
6124#define SCB_ISAR2_LOADSTORE_INSTRS2 ((uint32_t)0x00000004)
6125#define SCB_ISAR2_LOADSTORE_INSTRS3 ((uint32_t)0x00000008)
6126#define SCB_ISAR2_LOADSTORE_INSTRS_0 ((uint32_t)0x00000000)
6127#define SCB_ISAR2_LOADSTORE_INSTRS_1 ((uint32_t)0x00000001)
6128/* SCB_ISAR2[MEMHINT_INSTRS] Bits */
6129#define SCB_ISAR2_MEMHINT_INSTRS_OFS ( 4)
6130#define SCB_ISAR2_MEMHINT_INSTRS_MASK ((uint32_t)0x000000F0)
6131#define SCB_ISAR2_MEMHINT_INSTRS0 ((uint32_t)0x00000010)
6132#define SCB_ISAR2_MEMHINT_INSTRS1 ((uint32_t)0x00000020)
6133#define SCB_ISAR2_MEMHINT_INSTRS2 ((uint32_t)0x00000040)
6134#define SCB_ISAR2_MEMHINT_INSTRS3 ((uint32_t)0x00000080)
6135#define SCB_ISAR2_MEMHINT_INSTRS_0 ((uint32_t)0x00000000)
6136#define SCB_ISAR2_MEMHINT_INSTRS_1 ((uint32_t)0x00000010)
6137#define SCB_ISAR2_MEMHINT_INSTRS_2 ((uint32_t)0x00000020)
6138#define SCB_ISAR2_MEMHINT_INSTRS_3 ((uint32_t)0x00000030)
6139/* SCB_ISAR2[MULTIACCESSINT_INSTRS] Bits */
6140#define SCB_ISAR2_MULTIACCESSINT_INSTRS_OFS ( 8)
6141#define SCB_ISAR2_MULTIACCESSINT_INSTRS_MASK ((uint32_t)0x00000F00)
6142#define SCB_ISAR2_MULTIACCESSINT_INSTRS0 ((uint32_t)0x00000100)
6143#define SCB_ISAR2_MULTIACCESSINT_INSTRS1 ((uint32_t)0x00000200)
6144#define SCB_ISAR2_MULTIACCESSINT_INSTRS2 ((uint32_t)0x00000400)
6145#define SCB_ISAR2_MULTIACCESSINT_INSTRS3 ((uint32_t)0x00000800)
6146#define SCB_ISAR2_MULTIACCESSINT_INSTRS_0 ((uint32_t)0x00000000)
6147#define SCB_ISAR2_MULTIACCESSINT_INSTRS_1 ((uint32_t)0x00000100)
6148#define SCB_ISAR2_MULTIACCESSINT_INSTRS_2 ((uint32_t)0x00000200)
6149/* SCB_ISAR2[MULT_INSTRS] Bits */
6150#define SCB_ISAR2_MULT_INSTRS_OFS (12)
6151#define SCB_ISAR2_MULT_INSTRS_MASK ((uint32_t)0x0000F000)
6152#define SCB_ISAR2_MULT_INSTRS0 ((uint32_t)0x00001000)
6153#define SCB_ISAR2_MULT_INSTRS1 ((uint32_t)0x00002000)
6154#define SCB_ISAR2_MULT_INSTRS2 ((uint32_t)0x00004000)
6155#define SCB_ISAR2_MULT_INSTRS3 ((uint32_t)0x00008000)
6156#define SCB_ISAR2_MULT_INSTRS_0 ((uint32_t)0x00000000)
6157#define SCB_ISAR2_MULT_INSTRS_1 ((uint32_t)0x00001000)
6158#define SCB_ISAR2_MULT_INSTRS_2 ((uint32_t)0x00002000)
6159/* SCB_ISAR2[MULTS_INSTRS] Bits */
6160#define SCB_ISAR2_MULTS_INSTRS_OFS (16)
6161#define SCB_ISAR2_MULTS_INSTRS_MASK ((uint32_t)0x000F0000)
6162#define SCB_ISAR2_MULTS_INSTRS0 ((uint32_t)0x00010000)
6163#define SCB_ISAR2_MULTS_INSTRS1 ((uint32_t)0x00020000)
6164#define SCB_ISAR2_MULTS_INSTRS2 ((uint32_t)0x00040000)
6165#define SCB_ISAR2_MULTS_INSTRS3 ((uint32_t)0x00080000)
6166#define SCB_ISAR2_MULTS_INSTRS_0 ((uint32_t)0x00000000)
6167#define SCB_ISAR2_MULTS_INSTRS_1 ((uint32_t)0x00010000)
6168#define SCB_ISAR2_MULTS_INSTRS_2 ((uint32_t)0x00020000)
6169#define SCB_ISAR2_MULTS_INSTRS_3 ((uint32_t)0x00030000)
6170/* SCB_ISAR2[MULTU_INSTRS] Bits */
6171#define SCB_ISAR2_MULTU_INSTRS_OFS (20)
6172#define SCB_ISAR2_MULTU_INSTRS_MASK ((uint32_t)0x00F00000)
6173#define SCB_ISAR2_MULTU_INSTRS0 ((uint32_t)0x00100000)
6174#define SCB_ISAR2_MULTU_INSTRS1 ((uint32_t)0x00200000)
6175#define SCB_ISAR2_MULTU_INSTRS2 ((uint32_t)0x00400000)
6176#define SCB_ISAR2_MULTU_INSTRS3 ((uint32_t)0x00800000)
6177#define SCB_ISAR2_MULTU_INSTRS_0 ((uint32_t)0x00000000)
6178#define SCB_ISAR2_MULTU_INSTRS_1 ((uint32_t)0x00100000)
6179#define SCB_ISAR2_MULTU_INSTRS_2 ((uint32_t)0x00200000)
6180/* SCB_ISAR2[REVERSAL_INSTRS] Bits */
6181#define SCB_ISAR2_REVERSAL_INSTRS_OFS (28)
6182#define SCB_ISAR2_REVERSAL_INSTRS_MASK ((uint32_t)0xF0000000)
6183#define SCB_ISAR2_REVERSAL_INSTRS0 ((uint32_t)0x10000000)
6184#define SCB_ISAR2_REVERSAL_INSTRS1 ((uint32_t)0x20000000)
6185#define SCB_ISAR2_REVERSAL_INSTRS2 ((uint32_t)0x40000000)
6186#define SCB_ISAR2_REVERSAL_INSTRS3 ((uint32_t)0x80000000)
6187#define SCB_ISAR2_REVERSAL_INSTRS_0 ((uint32_t)0x00000000)
6188#define SCB_ISAR2_REVERSAL_INSTRS_1 ((uint32_t)0x10000000)
6189#define SCB_ISAR2_REVERSAL_INSTRS_2 ((uint32_t)0x20000000)
6190/* SCB_ISAR3[SATRUATE_INSTRS] Bits */
6191#define SCB_ISAR3_SATRUATE_INSTRS_OFS ( 0)
6192#define SCB_ISAR3_SATRUATE_INSTRS_MASK ((uint32_t)0x0000000F)
6193#define SCB_ISAR3_SATRUATE_INSTRS0 ((uint32_t)0x00000001)
6194#define SCB_ISAR3_SATRUATE_INSTRS1 ((uint32_t)0x00000002)
6195#define SCB_ISAR3_SATRUATE_INSTRS2 ((uint32_t)0x00000004)
6196#define SCB_ISAR3_SATRUATE_INSTRS3 ((uint32_t)0x00000008)
6197#define SCB_ISAR3_SATRUATE_INSTRS_0 ((uint32_t)0x00000000)
6198#define SCB_ISAR3_SATRUATE_INSTRS_1 ((uint32_t)0x00000001)
6199/* SCB_ISAR3[SIMD_INSTRS] Bits */
6200#define SCB_ISAR3_SIMD_INSTRS_OFS ( 4)
6201#define SCB_ISAR3_SIMD_INSTRS_MASK ((uint32_t)0x000000F0)
6202#define SCB_ISAR3_SIMD_INSTRS0 ((uint32_t)0x00000010)
6203#define SCB_ISAR3_SIMD_INSTRS1 ((uint32_t)0x00000020)
6204#define SCB_ISAR3_SIMD_INSTRS2 ((uint32_t)0x00000040)
6205#define SCB_ISAR3_SIMD_INSTRS3 ((uint32_t)0x00000080)
6206#define SCB_ISAR3_SIMD_INSTRS_0 ((uint32_t)0x00000000)
6207#define SCB_ISAR3_SIMD_INSTRS_1 ((uint32_t)0x00000010)
6208#define SCB_ISAR3_SIMD_INSTRS_3 ((uint32_t)0x00000030)
6209/* SCB_ISAR3[SVC_INSTRS] Bits */
6210#define SCB_ISAR3_SVC_INSTRS_OFS ( 8)
6211#define SCB_ISAR3_SVC_INSTRS_MASK ((uint32_t)0x00000F00)
6212#define SCB_ISAR3_SVC_INSTRS0 ((uint32_t)0x00000100)
6213#define SCB_ISAR3_SVC_INSTRS1 ((uint32_t)0x00000200)
6214#define SCB_ISAR3_SVC_INSTRS2 ((uint32_t)0x00000400)
6215#define SCB_ISAR3_SVC_INSTRS3 ((uint32_t)0x00000800)
6216#define SCB_ISAR3_SVC_INSTRS_0 ((uint32_t)0x00000000)
6217#define SCB_ISAR3_SVC_INSTRS_1 ((uint32_t)0x00000100)
6218/* SCB_ISAR3[SYNCPRIM_INSTRS] Bits */
6219#define SCB_ISAR3_SYNCPRIM_INSTRS_OFS (12)
6220#define SCB_ISAR3_SYNCPRIM_INSTRS_MASK ((uint32_t)0x0000F000)
6221#define SCB_ISAR3_SYNCPRIM_INSTRS0 ((uint32_t)0x00001000)
6222#define SCB_ISAR3_SYNCPRIM_INSTRS1 ((uint32_t)0x00002000)
6223#define SCB_ISAR3_SYNCPRIM_INSTRS2 ((uint32_t)0x00004000)
6224#define SCB_ISAR3_SYNCPRIM_INSTRS3 ((uint32_t)0x00008000)
6225#define SCB_ISAR3_SYNCPRIM_INSTRS_0 ((uint32_t)0x00000000)
6226#define SCB_ISAR3_SYNCPRIM_INSTRS_1 ((uint32_t)0x00001000)
6227#define SCB_ISAR3_SYNCPRIM_INSTRS_2 ((uint32_t)0x00002000)
6228/* SCB_ISAR3[TABBRANCH_INSTRS] Bits */
6229#define SCB_ISAR3_TABBRANCH_INSTRS_OFS (16)
6230#define SCB_ISAR3_TABBRANCH_INSTRS_MASK ((uint32_t)0x000F0000)
6231#define SCB_ISAR3_TABBRANCH_INSTRS0 ((uint32_t)0x00010000)
6232#define SCB_ISAR3_TABBRANCH_INSTRS1 ((uint32_t)0x00020000)
6233#define SCB_ISAR3_TABBRANCH_INSTRS2 ((uint32_t)0x00040000)
6234#define SCB_ISAR3_TABBRANCH_INSTRS3 ((uint32_t)0x00080000)
6235#define SCB_ISAR3_TABBRANCH_INSTRS_0 ((uint32_t)0x00000000)
6236#define SCB_ISAR3_TABBRANCH_INSTRS_1 ((uint32_t)0x00010000)
6237/* SCB_ISAR3[THUMBCOPY_INSTRS] Bits */
6238#define SCB_ISAR3_THUMBCOPY_INSTRS_OFS (20)
6239#define SCB_ISAR3_THUMBCOPY_INSTRS_MASK ((uint32_t)0x00F00000)
6240#define SCB_ISAR3_THUMBCOPY_INSTRS0 ((uint32_t)0x00100000)
6241#define SCB_ISAR3_THUMBCOPY_INSTRS1 ((uint32_t)0x00200000)
6242#define SCB_ISAR3_THUMBCOPY_INSTRS2 ((uint32_t)0x00400000)
6243#define SCB_ISAR3_THUMBCOPY_INSTRS3 ((uint32_t)0x00800000)
6244#define SCB_ISAR3_THUMBCOPY_INSTRS_0 ((uint32_t)0x00000000)
6245#define SCB_ISAR3_THUMBCOPY_INSTRS_1 ((uint32_t)0x00100000)
6246/* SCB_ISAR3[TRUENOP_INSTRS] Bits */
6247#define SCB_ISAR3_TRUENOP_INSTRS_OFS (24)
6248#define SCB_ISAR3_TRUENOP_INSTRS_MASK ((uint32_t)0x0F000000)
6249#define SCB_ISAR3_TRUENOP_INSTRS0 ((uint32_t)0x01000000)
6250#define SCB_ISAR3_TRUENOP_INSTRS1 ((uint32_t)0x02000000)
6251#define SCB_ISAR3_TRUENOP_INSTRS2 ((uint32_t)0x04000000)
6252#define SCB_ISAR3_TRUENOP_INSTRS3 ((uint32_t)0x08000000)
6253#define SCB_ISAR3_TRUENOP_INSTRS_0 ((uint32_t)0x00000000)
6254 /* register dependencies */
6255#define SCB_ISAR3_TRUENOP_INSTRS_1 ((uint32_t)0x01000000)
6256/* SCB_ISAR4[UNPRIV_INSTRS] Bits */
6257#define SCB_ISAR4_UNPRIV_INSTRS_OFS ( 0)
6258#define SCB_ISAR4_UNPRIV_INSTRS_MASK ((uint32_t)0x0000000F)
6259#define SCB_ISAR4_UNPRIV_INSTRS0 ((uint32_t)0x00000001)
6260#define SCB_ISAR4_UNPRIV_INSTRS1 ((uint32_t)0x00000002)
6261#define SCB_ISAR4_UNPRIV_INSTRS2 ((uint32_t)0x00000004)
6262#define SCB_ISAR4_UNPRIV_INSTRS3 ((uint32_t)0x00000008)
6263#define SCB_ISAR4_UNPRIV_INSTRS_0 ((uint32_t)0x00000000)
6264#define SCB_ISAR4_UNPRIV_INSTRS_1 ((uint32_t)0x00000001)
6265#define SCB_ISAR4_UNPRIV_INSTRS_2 ((uint32_t)0x00000002)
6266/* SCB_ISAR4[WITHSHIFTS_INSTRS] Bits */
6267#define SCB_ISAR4_WITHSHIFTS_INSTRS_OFS ( 4)
6268#define SCB_ISAR4_WITHSHIFTS_INSTRS_MASK ((uint32_t)0x000000F0)
6269#define SCB_ISAR4_WITHSHIFTS_INSTRS0 ((uint32_t)0x00000010)
6270#define SCB_ISAR4_WITHSHIFTS_INSTRS1 ((uint32_t)0x00000020)
6271#define SCB_ISAR4_WITHSHIFTS_INSTRS2 ((uint32_t)0x00000040)
6272#define SCB_ISAR4_WITHSHIFTS_INSTRS3 ((uint32_t)0x00000080)
6273#define SCB_ISAR4_WITHSHIFTS_INSTRS_0 ((uint32_t)0x00000000)
6274#define SCB_ISAR4_WITHSHIFTS_INSTRS_1 ((uint32_t)0x00000010)
6275#define SCB_ISAR4_WITHSHIFTS_INSTRS_3 ((uint32_t)0x00000030)
6276#define SCB_ISAR4_WITHSHIFTS_INSTRS_4 ((uint32_t)0x00000040)
6277/* SCB_ISAR4[WRITEBACK_INSTRS] Bits */
6278#define SCB_ISAR4_WRITEBACK_INSTRS_OFS ( 8)
6279#define SCB_ISAR4_WRITEBACK_INSTRS_MASK ((uint32_t)0x00000F00)
6280#define SCB_ISAR4_WRITEBACK_INSTRS0 ((uint32_t)0x00000100)
6281#define SCB_ISAR4_WRITEBACK_INSTRS1 ((uint32_t)0x00000200)
6282#define SCB_ISAR4_WRITEBACK_INSTRS2 ((uint32_t)0x00000400)
6283#define SCB_ISAR4_WRITEBACK_INSTRS3 ((uint32_t)0x00000800)
6284#define SCB_ISAR4_WRITEBACK_INSTRS_0 ((uint32_t)0x00000000)
6285 /* LDMIA/STMDB/PUSH/POP instructions support writeback addressing. */
6286#define SCB_ISAR4_WRITEBACK_INSTRS_1 ((uint32_t)0x00000100)
6287/* SCB_ISAR4[BARRIER_INSTRS] Bits */
6288#define SCB_ISAR4_BARRIER_INSTRS_OFS (16)
6289#define SCB_ISAR4_BARRIER_INSTRS_MASK ((uint32_t)0x000F0000)
6290#define SCB_ISAR4_BARRIER_INSTRS0 ((uint32_t)0x00010000)
6291#define SCB_ISAR4_BARRIER_INSTRS1 ((uint32_t)0x00020000)
6292#define SCB_ISAR4_BARRIER_INSTRS2 ((uint32_t)0x00040000)
6293#define SCB_ISAR4_BARRIER_INSTRS3 ((uint32_t)0x00080000)
6294#define SCB_ISAR4_BARRIER_INSTRS_0 ((uint32_t)0x00000000)
6295#define SCB_ISAR4_BARRIER_INSTRS_1 ((uint32_t)0x00010000)
6296/* SCB_ISAR4[SYNCPRIM_INSTRS_FRAC] Bits */
6297#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_OFS (20)
6298#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_MASK ((uint32_t)0x00F00000)
6299#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC0 ((uint32_t)0x00100000)
6300#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC1 ((uint32_t)0x00200000)
6301#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC2 ((uint32_t)0x00400000)
6302#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC3 ((uint32_t)0x00800000)
6303#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_0 ((uint32_t)0x00000000)
6304#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_3 ((uint32_t)0x00300000)
6305/* SCB_ISAR4[PSR_M_INSTRS] Bits */
6306#define SCB_ISAR4_PSR_M_INSTRS_OFS (24)
6307#define SCB_ISAR4_PSR_M_INSTRS_MASK ((uint32_t)0x0F000000)
6308#define SCB_ISAR4_PSR_M_INSTRS0 ((uint32_t)0x01000000)
6309#define SCB_ISAR4_PSR_M_INSTRS1 ((uint32_t)0x02000000)
6310#define SCB_ISAR4_PSR_M_INSTRS2 ((uint32_t)0x04000000)
6311#define SCB_ISAR4_PSR_M_INSTRS3 ((uint32_t)0x08000000)
6312#define SCB_ISAR4_PSR_M_INSTRS_0 ((uint32_t)0x00000000)
6313#define SCB_ISAR4_PSR_M_INSTRS_1 ((uint32_t)0x01000000)
6314/* SCB_CPACR[CP11] Bits */
6315#define SCB_CPACR_CP11_OFS (22)
6316#define SCB_CPACR_CP11_MASK ((uint32_t)0x00C00000)
6317/* SCB_CPACR[CP10] Bits */
6318#define SCB_CPACR_CP10_OFS (20)
6319#define SCB_CPACR_CP10_MASK ((uint32_t)0x00300000)
6320/* SCB_SHPR1[SCB_SHPR1_PRI_4] Bits */
6321#define SCB_SHPR1_PRI_4_OFS ( 0)
6322#define SCB_SHPR1_PRI_4_M ((uint32_t)0x000000ff) /* */
6323/* SCB_SHPR1[SCB_SHPR1_PRI_5] Bits */
6324#define SCB_SHPR1_PRI_5_OFS ( 8)
6325#define SCB_SHPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */
6326/* SCB_SHPR1[SCB_SHPR1_PRI_6] Bits */
6327#define SCB_SHPR1_PRI_6_OFS (16)
6328#define SCB_SHPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */
6329/* SCB_SHPR1[SCB_SHPR1_PRI_7] Bits */
6330#define SCB_SHPR1_PRI_7_OFS (24)
6331#define SCB_SHPR1_PRI_7_M ((uint32_t)0xff000000) /* */
6332/* SCB_SHPR2[SCB_SHPR2_PRI_8] Bits */
6333#define SCB_SHPR2_PRI_8_OFS ( 0)
6334#define SCB_SHPR2_PRI_8_M ((uint32_t)0x000000ff) /* */
6335/* SCB_SHPR2[SCB_SHPR2_PRI_9] Bits */
6336#define SCB_SHPR2_PRI_9_OFS ( 8)
6337#define SCB_SHPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */
6338/* SCB_SHPR2[SCB_SHPR2_PRI_10] Bits */
6339#define SCB_SHPR2_PRI_10_OFS (16)
6340#define SCB_SHPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */
6341/* SCB_SHPR2[SCB_SHPR2_PRI_11] Bits */
6342#define SCB_SHPR2_PRI_11_OFS (24)
6343#define SCB_SHPR2_PRI_11_M ((uint32_t)0xff000000) /* */
6344/* SCB_SHPR3[SCB_SHPR3_PRI_12] Bits */
6345#define SCB_SHPR3_PRI_12_OFS ( 0)
6346#define SCB_SHPR3_PRI_12_M ((uint32_t)0x000000ff) /* */
6347/* SCB_SHPR3[SCB_SHPR3_PRI_13] Bits */
6348#define SCB_SHPR3_PRI_13_OFS ( 8)
6349#define SCB_SHPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */
6350/* SCB_SHPR3[SCB_SHPR3_PRI_14] Bits */
6351#define SCB_SHPR3_PRI_14_OFS (16)
6352#define SCB_SHPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */
6353/* SCB_SHPR3[SCB_SHPR3_PRI_15] Bits */
6354#define SCB_SHPR3_PRI_15_OFS (24)
6355#define SCB_SHPR3_PRI_15_M ((uint32_t)0xff000000) /* */
6356
6357/* SCB_CFSR[SCB_CFSR_IACCVIOL] Bits */
6358#define SCB_CFSR_IACCVIOL_OFS ( 0)
6359#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /* */
6360/* SCB_CFSR[SCB_CFSR_DACCVIOL] Bits */
6361#define SCB_CFSR_DACCVIOL_OFS ( 1)
6362#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /* */
6363/* SCB_CFSR[SCB_CFSR_MUNSTKERR] Bits */
6364#define SCB_CFSR_MUNSTKERR_OFS ( 3)
6365#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /* */
6366/* SCB_CFSR[SCB_CFSR_MSTKERR] Bits */
6367#define SCB_CFSR_MSTKERR_OFS ( 4)
6368#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /* */
6369/* SCB_CFSR[SCB_CFSR_MMARVALID] Bits */
6370#define SCB_CFSR_MMARVALID_OFS ( 7)
6371#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /* */
6372/* SCB_CFSR[SCB_CFSR_IBUSERR] Bits */
6373#define SCB_CFSR_IBUSERR_OFS ( 8)
6374#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /* */
6375/* SCB_CFSR[SCB_CFSR_PRECISERR] Bits */
6376#define SCB_CFSR_PRECISERR_OFS ( 9)
6377#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /* */
6378/* SCB_CFSR[SCB_CFSR_IMPRECISERR] Bits */
6379#define SCB_CFSR_IMPRECISERR_OFS (10)
6380#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /* */
6381/* SCB_CFSR[SCB_CFSR_UNSTKERR] Bits */
6382#define SCB_CFSR_UNSTKERR_OFS (11)
6383#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /* */
6384/* SCB_CFSR[SCB_CFSR_STKERR] Bits */
6385#define SCB_CFSR_STKERR_OFS (12)
6386#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /* */
6387/* SCB_CFSR[SCB_CFSR_BFARVALID] Bits */
6388#define SCB_CFSR_BFARVALID_OFS (15)
6389#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /* */
6390/* SCB_CFSR[SCB_CFSR_UNDEFINSTR] Bits */
6391#define SCB_CFSR_UNDEFINSTR_OFS (16)
6392#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /* */
6393/* SCB_CFSR[SCB_CFSR_INVSTATE] Bits */
6394#define SCB_CFSR_INVSTATE_OFS (17)
6395#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /* */
6396/* SCB_CFSR[SCB_CFSR_INVPC] Bits */
6397#define SCB_CFSR_INVPC_OFS (18)
6398#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /* */
6399/* SCB_CFSR[SCB_CFSR_NOCP] Bits */
6400#define SCB_CFSR_NOCP_OFS (19)
6401#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /* */
6402/* SCB_CFSR[SCB_CFSR_UNALIGNED] Bits */
6403#define SCB_CFSR_UNALIGNED_OFS (24)
6404#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /* */
6405/* SCB_CFSR[SCB_CFSR_DIVBYZERO] Bits */
6406#define SCB_CFSR_DIVBYZERO_OFS (25)
6407#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /* */
6408/* SCB_CFSR[SCB_CFSR_MLSPERR] Bits */
6409#define SCB_CFSR_MLSPERR_OFS ( 5)
6410#define SCB_CFSR_MLSPERR ((uint32_t)0x00000020) /* */
6411/* SCB_CFSR[SCB_CFSR_LSPERR] Bits */
6412#define SCB_CFSR_LSPERR_OFS (13)
6413#define SCB_CFSR_LSPERR ((uint32_t)0x00002000) /* */
6414
6415
6416/******************************************************************************
6417* SCNSCB Bits
6418******************************************************************************/
6419
6420
6421/******************************************************************************
6422* SYSCTL Bits
6423******************************************************************************/
6424/* SYSCTL_REBOOT_CTL[REBOOT] Bits */
6425#define SYSCTL_REBOOT_CTL_REBOOT_OFS ( 0)
6426#define SYSCTL_REBOOT_CTL_REBOOT ((uint32_t)0x00000001)
6427/* SYSCTL_REBOOT_CTL[WKEY] Bits */
6428#define SYSCTL_REBOOT_CTL_WKEY_OFS ( 8)
6429#define SYSCTL_REBOOT_CTL_WKEY_MASK ((uint32_t)0x0000FF00)
6430/* SYSCTL_NMI_CTLSTAT[CS_SRC] Bits */
6431#define SYSCTL_NMI_CTLSTAT_CS_SRC_OFS ( 0)
6432#define SYSCTL_NMI_CTLSTAT_CS_SRC ((uint32_t)0x00000001)
6433/* SYSCTL_NMI_CTLSTAT[PSS_SRC] Bits */
6434#define SYSCTL_NMI_CTLSTAT_PSS_SRC_OFS ( 1)
6435#define SYSCTL_NMI_CTLSTAT_PSS_SRC ((uint32_t)0x00000002)
6436/* SYSCTL_NMI_CTLSTAT[PCM_SRC] Bits */
6437#define SYSCTL_NMI_CTLSTAT_PCM_SRC_OFS ( 2)
6438#define SYSCTL_NMI_CTLSTAT_PCM_SRC ((uint32_t)0x00000004)
6439/* SYSCTL_NMI_CTLSTAT[PIN_SRC] Bits */
6440#define SYSCTL_NMI_CTLSTAT_PIN_SRC_OFS ( 3)
6441#define SYSCTL_NMI_CTLSTAT_PIN_SRC ((uint32_t)0x00000008)
6442/* SYSCTL_NMI_CTLSTAT[CS_FLG] Bits */
6443#define SYSCTL_NMI_CTLSTAT_CS_FLG_OFS (16)
6444#define SYSCTL_NMI_CTLSTAT_CS_FLG ((uint32_t)0x00010000)
6445/* SYSCTL_NMI_CTLSTAT[PSS_FLG] Bits */
6446#define SYSCTL_NMI_CTLSTAT_PSS_FLG_OFS (17)
6447#define SYSCTL_NMI_CTLSTAT_PSS_FLG ((uint32_t)0x00020000)
6448/* SYSCTL_NMI_CTLSTAT[PCM_FLG] Bits */
6449#define SYSCTL_NMI_CTLSTAT_PCM_FLG_OFS (18)
6450#define SYSCTL_NMI_CTLSTAT_PCM_FLG ((uint32_t)0x00040000)
6451/* SYSCTL_NMI_CTLSTAT[PIN_FLG] Bits */
6452#define SYSCTL_NMI_CTLSTAT_PIN_FLG_OFS (19)
6453#define SYSCTL_NMI_CTLSTAT_PIN_FLG ((uint32_t)0x00080000)
6454/* SYSCTL_WDTRESET_CTL[TIMEOUT] Bits */
6455#define SYSCTL_WDTRESET_CTL_TIMEOUT_OFS ( 0)
6456#define SYSCTL_WDTRESET_CTL_TIMEOUT ((uint32_t)0x00000001)
6457/* SYSCTL_WDTRESET_CTL[VIOLATION] Bits */
6458#define SYSCTL_WDTRESET_CTL_VIOLATION_OFS ( 1)
6459#define SYSCTL_WDTRESET_CTL_VIOLATION ((uint32_t)0x00000002)
6460/* SYSCTL_PERIHALT_CTL[HALT_T16_0] Bits */
6461#define SYSCTL_PERIHALT_CTL_HALT_T16_0_OFS ( 0)
6462#define SYSCTL_PERIHALT_CTL_HALT_T16_0 ((uint32_t)0x00000001)
6463/* SYSCTL_PERIHALT_CTL[HALT_T16_1] Bits */
6464#define SYSCTL_PERIHALT_CTL_HALT_T16_1_OFS ( 1)
6465#define SYSCTL_PERIHALT_CTL_HALT_T16_1 ((uint32_t)0x00000002)
6466/* SYSCTL_PERIHALT_CTL[HALT_T16_2] Bits */
6467#define SYSCTL_PERIHALT_CTL_HALT_T16_2_OFS ( 2)
6468#define SYSCTL_PERIHALT_CTL_HALT_T16_2 ((uint32_t)0x00000004)
6469/* SYSCTL_PERIHALT_CTL[HALT_T16_3] Bits */
6470#define SYSCTL_PERIHALT_CTL_HALT_T16_3_OFS ( 3)
6471#define SYSCTL_PERIHALT_CTL_HALT_T16_3 ((uint32_t)0x00000008)
6472/* SYSCTL_PERIHALT_CTL[HALT_T32_0] Bits */
6473#define SYSCTL_PERIHALT_CTL_HALT_T32_0_OFS ( 4)
6474#define SYSCTL_PERIHALT_CTL_HALT_T32_0 ((uint32_t)0x00000010)
6475/* SYSCTL_PERIHALT_CTL[HALT_eUA0] Bits */
6476#define SYSCTL_PERIHALT_CTL_HALT_EUA0_OFS ( 5)
6477#define SYSCTL_PERIHALT_CTL_HALT_EUA0 ((uint32_t)0x00000020)
6478/* SYSCTL_PERIHALT_CTL[HALT_eUA1] Bits */
6479#define SYSCTL_PERIHALT_CTL_HALT_EUA1_OFS ( 6)
6480#define SYSCTL_PERIHALT_CTL_HALT_EUA1 ((uint32_t)0x00000040)
6481/* SYSCTL_PERIHALT_CTL[HALT_eUA2] Bits */
6482#define SYSCTL_PERIHALT_CTL_HALT_EUA2_OFS ( 7)
6483#define SYSCTL_PERIHALT_CTL_HALT_EUA2 ((uint32_t)0x00000080)
6484/* SYSCTL_PERIHALT_CTL[HALT_eUA3] Bits */
6485#define SYSCTL_PERIHALT_CTL_HALT_EUA3_OFS ( 8)
6486#define SYSCTL_PERIHALT_CTL_HALT_EUA3 ((uint32_t)0x00000100)
6487/* SYSCTL_PERIHALT_CTL[HALT_eUB0] Bits */
6488#define SYSCTL_PERIHALT_CTL_HALT_EUB0_OFS ( 9)
6489#define SYSCTL_PERIHALT_CTL_HALT_EUB0 ((uint32_t)0x00000200)
6490/* SYSCTL_PERIHALT_CTL[HALT_eUB1] Bits */
6491#define SYSCTL_PERIHALT_CTL_HALT_EUB1_OFS (10)
6492#define SYSCTL_PERIHALT_CTL_HALT_EUB1 ((uint32_t)0x00000400)
6493/* SYSCTL_PERIHALT_CTL[HALT_eUB2] Bits */
6494#define SYSCTL_PERIHALT_CTL_HALT_EUB2_OFS (11)
6495#define SYSCTL_PERIHALT_CTL_HALT_EUB2 ((uint32_t)0x00000800)
6496/* SYSCTL_PERIHALT_CTL[HALT_eUB3] Bits */
6497#define SYSCTL_PERIHALT_CTL_HALT_EUB3_OFS (12)
6498#define SYSCTL_PERIHALT_CTL_HALT_EUB3 ((uint32_t)0x00001000)
6499/* SYSCTL_PERIHALT_CTL[HALT_ADC] Bits */
6500#define SYSCTL_PERIHALT_CTL_HALT_ADC_OFS (13)
6501#define SYSCTL_PERIHALT_CTL_HALT_ADC ((uint32_t)0x00002000)
6502/* SYSCTL_PERIHALT_CTL[HALT_WDT] Bits */
6503#define SYSCTL_PERIHALT_CTL_HALT_WDT_OFS (14)
6504#define SYSCTL_PERIHALT_CTL_HALT_WDT ((uint32_t)0x00004000)
6505/* SYSCTL_PERIHALT_CTL[HALT_DMA] Bits */
6506#define SYSCTL_PERIHALT_CTL_HALT_DMA_OFS (15)
6507#define SYSCTL_PERIHALT_CTL_HALT_DMA ((uint32_t)0x00008000)
6508/* SYSCTL_SRAM_BANKEN[BNK0_EN] Bits */
6509#define SYSCTL_SRAM_BANKEN_BNK0_EN_OFS ( 0)
6510#define SYSCTL_SRAM_BANKEN_BNK0_EN ((uint32_t)0x00000001)
6511/* SYSCTL_SRAM_BANKEN[BNK1_EN] Bits */
6512#define SYSCTL_SRAM_BANKEN_BNK1_EN_OFS ( 1)
6513#define SYSCTL_SRAM_BANKEN_BNK1_EN ((uint32_t)0x00000002)
6514/* SYSCTL_SRAM_BANKEN[BNK2_EN] Bits */
6515#define SYSCTL_SRAM_BANKEN_BNK2_EN_OFS ( 2)
6516#define SYSCTL_SRAM_BANKEN_BNK2_EN ((uint32_t)0x00000004)
6517/* SYSCTL_SRAM_BANKEN[BNK3_EN] Bits */
6518#define SYSCTL_SRAM_BANKEN_BNK3_EN_OFS ( 3)
6519#define SYSCTL_SRAM_BANKEN_BNK3_EN ((uint32_t)0x00000008)
6520/* SYSCTL_SRAM_BANKEN[BNK4_EN] Bits */
6521#define SYSCTL_SRAM_BANKEN_BNK4_EN_OFS ( 4)
6522#define SYSCTL_SRAM_BANKEN_BNK4_EN ((uint32_t)0x00000010)
6523/* SYSCTL_SRAM_BANKEN[BNK5_EN] Bits */
6524#define SYSCTL_SRAM_BANKEN_BNK5_EN_OFS ( 5)
6525#define SYSCTL_SRAM_BANKEN_BNK5_EN ((uint32_t)0x00000020)
6526/* SYSCTL_SRAM_BANKEN[BNK6_EN] Bits */
6527#define SYSCTL_SRAM_BANKEN_BNK6_EN_OFS ( 6)
6528#define SYSCTL_SRAM_BANKEN_BNK6_EN ((uint32_t)0x00000040)
6529/* SYSCTL_SRAM_BANKEN[BNK7_EN] Bits */
6530#define SYSCTL_SRAM_BANKEN_BNK7_EN_OFS ( 7)
6531#define SYSCTL_SRAM_BANKEN_BNK7_EN ((uint32_t)0x00000080)
6532/* SYSCTL_SRAM_BANKEN[SRAM_RDY] Bits */
6533#define SYSCTL_SRAM_BANKEN_SRAM_RDY_OFS (16)
6534#define SYSCTL_SRAM_BANKEN_SRAM_RDY ((uint32_t)0x00010000)
6535/* SYSCTL_SRAM_BANKRET[BNK0_RET] Bits */
6536#define SYSCTL_SRAM_BANKRET_BNK0_RET_OFS ( 0)
6537#define SYSCTL_SRAM_BANKRET_BNK0_RET ((uint32_t)0x00000001)
6538/* SYSCTL_SRAM_BANKRET[BNK1_RET] Bits */
6539#define SYSCTL_SRAM_BANKRET_BNK1_RET_OFS ( 1)
6540#define SYSCTL_SRAM_BANKRET_BNK1_RET ((uint32_t)0x00000002)
6541/* SYSCTL_SRAM_BANKRET[BNK2_RET] Bits */
6542#define SYSCTL_SRAM_BANKRET_BNK2_RET_OFS ( 2)
6543#define SYSCTL_SRAM_BANKRET_BNK2_RET ((uint32_t)0x00000004)
6544/* SYSCTL_SRAM_BANKRET[BNK3_RET] Bits */
6545#define SYSCTL_SRAM_BANKRET_BNK3_RET_OFS ( 3)
6546#define SYSCTL_SRAM_BANKRET_BNK3_RET ((uint32_t)0x00000008)
6547/* SYSCTL_SRAM_BANKRET[BNK4_RET] Bits */
6548#define SYSCTL_SRAM_BANKRET_BNK4_RET_OFS ( 4)
6549#define SYSCTL_SRAM_BANKRET_BNK4_RET ((uint32_t)0x00000010)
6550/* SYSCTL_SRAM_BANKRET[BNK5_RET] Bits */
6551#define SYSCTL_SRAM_BANKRET_BNK5_RET_OFS ( 5)
6552#define SYSCTL_SRAM_BANKRET_BNK5_RET ((uint32_t)0x00000020)
6553/* SYSCTL_SRAM_BANKRET[BNK6_RET] Bits */
6554#define SYSCTL_SRAM_BANKRET_BNK6_RET_OFS ( 6)
6555#define SYSCTL_SRAM_BANKRET_BNK6_RET ((uint32_t)0x00000040)
6556/* SYSCTL_SRAM_BANKRET[BNK7_RET] Bits */
6557#define SYSCTL_SRAM_BANKRET_BNK7_RET_OFS ( 7)
6558#define SYSCTL_SRAM_BANKRET_BNK7_RET ((uint32_t)0x00000080)
6559/* SYSCTL_SRAM_BANKRET[SRAM_RDY] Bits */
6560#define SYSCTL_SRAM_BANKRET_SRAM_RDY_OFS (16)
6561#define SYSCTL_SRAM_BANKRET_SRAM_RDY ((uint32_t)0x00010000)
6562/* SYSCTL_DIO_GLTFLT_CTL[GLTCH_EN] Bits */
6563#define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN_OFS ( 0)
6564#define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN ((uint32_t)0x00000001)
6565/* SYSCTL_SECDATA_UNLOCK[UNLKEY] Bits */
6566#define SYSCTL_SECDATA_UNLOCK_UNLKEY_OFS ( 0)
6567#define SYSCTL_SECDATA_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF)
6568/* SYSCTL_MASTER_UNLOCK[UNLKEY] Bits */
6569#define SYSCTL_MASTER_UNLOCK_UNLKEY_OFS ( 0)
6570#define SYSCTL_MASTER_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF)
6571/* SYSCTL_RESET_REQ[POR] Bits */
6572#define SYSCTL_RESET_REQ_POR_OFS ( 0)
6573#define SYSCTL_RESET_REQ_POR ((uint32_t)0x00000001)
6574/* SYSCTL_RESET_REQ[REBOOT] Bits */
6575#define SYSCTL_RESET_REQ_REBOOT_OFS ( 1)
6576#define SYSCTL_RESET_REQ_REBOOT ((uint32_t)0x00000002)
6577/* SYSCTL_RESET_REQ[WKEY] Bits */
6578#define SYSCTL_RESET_REQ_WKEY_OFS ( 8)
6579#define SYSCTL_RESET_REQ_WKEY_MASK ((uint32_t)0x0000FF00)
6580/* SYSCTL_RESET_STATOVER[SOFT] Bits */
6581#define SYSCTL_RESET_STATOVER_SOFT_OFS ( 0)
6582#define SYSCTL_RESET_STATOVER_SOFT ((uint32_t)0x00000001)
6583/* SYSCTL_RESET_STATOVER[HARD] Bits */
6584#define SYSCTL_RESET_STATOVER_HARD_OFS ( 1)
6585#define SYSCTL_RESET_STATOVER_HARD ((uint32_t)0x00000002)
6586/* SYSCTL_RESET_STATOVER[REBOOT] Bits */
6587#define SYSCTL_RESET_STATOVER_REBOOT_OFS ( 2)
6588#define SYSCTL_RESET_STATOVER_REBOOT ((uint32_t)0x00000004)
6589/* SYSCTL_RESET_STATOVER[SOFT_OVER] Bits */
6590#define SYSCTL_RESET_STATOVER_SOFT_OVER_OFS ( 8)
6591#define SYSCTL_RESET_STATOVER_SOFT_OVER ((uint32_t)0x00000100)
6592/* SYSCTL_RESET_STATOVER[HARD_OVER] Bits */
6593#define SYSCTL_RESET_STATOVER_HARD_OVER_OFS ( 9)
6594#define SYSCTL_RESET_STATOVER_HARD_OVER ((uint32_t)0x00000200)
6595/* SYSCTL_RESET_STATOVER[RBT_OVER] Bits */
6596#define SYSCTL_RESET_STATOVER_RBT_OVER_OFS (10)
6597#define SYSCTL_RESET_STATOVER_RBT_OVER ((uint32_t)0x00000400)
6598/* Pre-defined bitfield values */
6599#define SYSCTL_REBOOT_CTL_WKEY_VAL ((uint32_t)0x00006900)
6600 /* cleared */
6601
6602
6603/******************************************************************************
6604* SYSTICK Bits
6605******************************************************************************/
6606
6607/******************************************************************************
6608* Timer32 Bits
6609******************************************************************************/
6610/* TIMER32_CONTROL[ONESHOT] Bits */
6611#define TIMER32_CONTROL_ONESHOT_OFS ( 0)
6612#define TIMER32_CONTROL_ONESHOT ((uint32_t)0x00000001)
6613/* TIMER32_CONTROL[SIZE] Bits */
6614#define TIMER32_CONTROL_SIZE_OFS ( 1)
6615#define TIMER32_CONTROL_SIZE ((uint32_t)0x00000002)
6616/* TIMER32_CONTROL[PRESCALE] Bits */
6617#define TIMER32_CONTROL_PRESCALE_OFS ( 2)
6618#define TIMER32_CONTROL_PRESCALE_MASK ((uint32_t)0x0000000C)
6619#define TIMER32_CONTROL_PRESCALE0 ((uint32_t)0x00000004)
6620#define TIMER32_CONTROL_PRESCALE1 ((uint32_t)0x00000008)
6621#define TIMER32_CONTROL_PRESCALE_0 ((uint32_t)0x00000000)
6622#define TIMER32_CONTROL_PRESCALE_1 ((uint32_t)0x00000004)
6623#define TIMER32_CONTROL_PRESCALE_2 ((uint32_t)0x00000008)
6624/* TIMER32_CONTROL[IE] Bits */
6625#define TIMER32_CONTROL_IE_OFS ( 5)
6626#define TIMER32_CONTROL_IE ((uint32_t)0x00000020)
6627/* TIMER32_CONTROL[MODE] Bits */
6628#define TIMER32_CONTROL_MODE_OFS ( 6)
6629#define TIMER32_CONTROL_MODE ((uint32_t)0x00000040)
6630/* TIMER32_CONTROL[ENABLE] Bits */
6631#define TIMER32_CONTROL_ENABLE_OFS ( 7)
6632#define TIMER32_CONTROL_ENABLE ((uint32_t)0x00000080)
6633/* TIMER32_RIS[RAW_IFG] Bits */
6634#define TIMER32_RIS_RAW_IFG_OFS ( 0)
6635#define TIMER32_RIS_RAW_IFG ((uint32_t)0x00000001)
6636/* TIMER32_MIS[IFG] Bits */
6637#define TIMER32_MIS_IFG_OFS ( 0)
6638#define TIMER32_MIS_IFG ((uint32_t)0x00000001)
6642/******************************************************************************
6643* TIMER_A Bits
6644******************************************************************************/
6645/* TIMER_A_CTL[IFG] Bits */
6646#define TIMER_A_CTL_IFG_OFS ( 0)
6647#define TIMER_A_CTL_IFG ((uint16_t)0x0001)
6648/* TIMER_A_CTL[IE] Bits */
6649#define TIMER_A_CTL_IE_OFS ( 1)
6650#define TIMER_A_CTL_IE ((uint16_t)0x0002)
6651/* TIMER_A_CTL[CLR] Bits */
6652#define TIMER_A_CTL_CLR_OFS ( 2)
6653#define TIMER_A_CTL_CLR ((uint16_t)0x0004)
6654/* TIMER_A_CTL[MC] Bits */
6655#define TIMER_A_CTL_MC_OFS ( 4)
6656#define TIMER_A_CTL_MC_MASK ((uint16_t)0x0030)
6657#define TIMER_A_CTL_MC0 ((uint16_t)0x0010)
6658#define TIMER_A_CTL_MC1 ((uint16_t)0x0020)
6659#define TIMER_A_CTL_MC_0 ((uint16_t)0x0000)
6660#define TIMER_A_CTL_MC_1 ((uint16_t)0x0010)
6661#define TIMER_A_CTL_MC_2 ((uint16_t)0x0020)
6662#define TIMER_A_CTL_MC_3 ((uint16_t)0x0030)
6663#define TIMER_A_CTL_MC__STOP ((uint16_t)0x0000)
6664#define TIMER_A_CTL_MC__UP ((uint16_t)0x0010)
6665#define TIMER_A_CTL_MC__CONTINUOUS ((uint16_t)0x0020)
6666#define TIMER_A_CTL_MC__UPDOWN ((uint16_t)0x0030)
6667/* TIMER_A_CTL[ID] Bits */
6668#define TIMER_A_CTL_ID_OFS ( 6)
6669#define TIMER_A_CTL_ID_MASK ((uint16_t)0x00C0)
6670#define TIMER_A_CTL_ID0 ((uint16_t)0x0040)
6671#define TIMER_A_CTL_ID1 ((uint16_t)0x0080)
6672#define TIMER_A_CTL_ID_0 ((uint16_t)0x0000)
6673#define TIMER_A_CTL_ID_1 ((uint16_t)0x0040)
6674#define TIMER_A_CTL_ID_2 ((uint16_t)0x0080)
6675#define TIMER_A_CTL_ID_3 ((uint16_t)0x00C0)
6676#define TIMER_A_CTL_ID__1 ((uint16_t)0x0000)
6677#define TIMER_A_CTL_ID__2 ((uint16_t)0x0040)
6678#define TIMER_A_CTL_ID__4 ((uint16_t)0x0080)
6679#define TIMER_A_CTL_ID__8 ((uint16_t)0x00C0)
6680/* TIMER_A_CTL[SSEL] Bits */
6681#define TIMER_A_CTL_SSEL_OFS ( 8)
6682#define TIMER_A_CTL_SSEL_MASK ((uint16_t)0x0300)
6683#define TIMER_A_CTL_SSEL0 ((uint16_t)0x0100)
6684#define TIMER_A_CTL_SSEL1 ((uint16_t)0x0200)
6685#define TIMER_A_CTL_TASSEL_0 ((uint16_t)0x0000)
6686#define TIMER_A_CTL_TASSEL_1 ((uint16_t)0x0100)
6687#define TIMER_A_CTL_TASSEL_2 ((uint16_t)0x0200)
6688#define TIMER_A_CTL_TASSEL_3 ((uint16_t)0x0300)
6689#define TIMER_A_CTL_SSEL__TACLK ((uint16_t)0x0000)
6690#define TIMER_A_CTL_SSEL__ACLK ((uint16_t)0x0100)
6691#define TIMER_A_CTL_SSEL__SMCLK ((uint16_t)0x0200)
6692#define TIMER_A_CTL_SSEL__INCLK ((uint16_t)0x0300)
6693/* TIMER_A_CCTLN[CCIFG] Bits */
6694#define TIMER_A_CCTLN_CCIFG_OFS ( 0)
6695#define TIMER_A_CCTLN_CCIFG ((uint16_t)0x0001)
6696/* TIMER_A_CCTLN[COV] Bits */
6697#define TIMER_A_CCTLN_COV_OFS ( 1)
6698#define TIMER_A_CCTLN_COV ((uint16_t)0x0002)
6699/* TIMER_A_CCTLN[OUT] Bits */
6700#define TIMER_A_CCTLN_OUT_OFS ( 2)
6701#define TIMER_A_CCTLN_OUT ((uint16_t)0x0004)
6702/* TIMER_A_CCTLN[CCI] Bits */
6703#define TIMER_A_CCTLN_CCI_OFS ( 3)
6704#define TIMER_A_CCTLN_CCI ((uint16_t)0x0008)
6705/* TIMER_A_CCTLN[CCIE] Bits */
6706#define TIMER_A_CCTLN_CCIE_OFS ( 4)
6707#define TIMER_A_CCTLN_CCIE ((uint16_t)0x0010)
6708/* TIMER_A_CCTLN[OUTMOD] Bits */
6709#define TIMER_A_CCTLN_OUTMOD_OFS ( 5)
6710#define TIMER_A_CCTLN_OUTMOD_MASK ((uint16_t)0x00E0)
6711#define TIMER_A_CCTLN_OUTMOD0 ((uint16_t)0x0020)
6712#define TIMER_A_CCTLN_OUTMOD1 ((uint16_t)0x0040)
6713#define TIMER_A_CCTLN_OUTMOD2 ((uint16_t)0x0080)
6714#define TIMER_A_CCTLN_OUTMOD_0 ((uint16_t)0x0000)
6715#define TIMER_A_CCTLN_OUTMOD_1 ((uint16_t)0x0020)
6716#define TIMER_A_CCTLN_OUTMOD_2 ((uint16_t)0x0040)
6717#define TIMER_A_CCTLN_OUTMOD_3 ((uint16_t)0x0060)
6718#define TIMER_A_CCTLN_OUTMOD_4 ((uint16_t)0x0080)
6719#define TIMER_A_CCTLN_OUTMOD_5 ((uint16_t)0x00A0)
6720#define TIMER_A_CCTLN_OUTMOD_6 ((uint16_t)0x00C0)
6721#define TIMER_A_CCTLN_OUTMOD_7 ((uint16_t)0x00E0)
6722/* TIMER_A_CCTLN[CAP] Bits */
6723#define TIMER_A_CCTLN_CAP_OFS ( 8)
6724#define TIMER_A_CCTLN_CAP ((uint16_t)0x0100)
6725/* TIMER_A_CCTLN[SCCI] Bits */
6726#define TIMER_A_CCTLN_SCCI_OFS (10)
6727#define TIMER_A_CCTLN_SCCI ((uint16_t)0x0400)
6728/* TIMER_A_CCTLN[SCS] Bits */
6729#define TIMER_A_CCTLN_SCS_OFS (11)
6730#define TIMER_A_CCTLN_SCS ((uint16_t)0x0800)
6731/* TIMER_A_CCTLN[CCIS] Bits */
6732#define TIMER_A_CCTLN_CCIS_OFS (12)
6733#define TIMER_A_CCTLN_CCIS_MASK ((uint16_t)0x3000)
6734#define TIMER_A_CCTLN_CCIS0 ((uint16_t)0x1000)
6735#define TIMER_A_CCTLN_CCIS1 ((uint16_t)0x2000)
6736#define TIMER_A_CCTLN_CCIS_0 ((uint16_t)0x0000)
6737#define TIMER_A_CCTLN_CCIS_1 ((uint16_t)0x1000)
6738#define TIMER_A_CCTLN_CCIS_2 ((uint16_t)0x2000)
6739#define TIMER_A_CCTLN_CCIS_3 ((uint16_t)0x3000)
6740#define TIMER_A_CCTLN_CCIS__CCIA ((uint16_t)0x0000)
6741#define TIMER_A_CCTLN_CCIS__CCIB ((uint16_t)0x1000)
6742#define TIMER_A_CCTLN_CCIS__GND ((uint16_t)0x2000)
6743#define TIMER_A_CCTLN_CCIS__VCC ((uint16_t)0x3000)
6744/* TIMER_A_CCTLN[CM] Bits */
6745#define TIMER_A_CCTLN_CM_OFS (14)
6746#define TIMER_A_CCTLN_CM_MASK ((uint16_t)0xC000)
6747#define TIMER_A_CCTLN_CM0 ((uint16_t)0x4000)
6748#define TIMER_A_CCTLN_CM1 ((uint16_t)0x8000)
6749#define TIMER_A_CCTLN_CM_0 ((uint16_t)0x0000)
6750#define TIMER_A_CCTLN_CM_1 ((uint16_t)0x4000)
6751#define TIMER_A_CCTLN_CM_2 ((uint16_t)0x8000)
6752#define TIMER_A_CCTLN_CM_3 ((uint16_t)0xC000)
6753#define TIMER_A_CCTLN_CM__NONE ((uint16_t)0x0000)
6754#define TIMER_A_CCTLN_CM__RISING ((uint16_t)0x4000)
6755#define TIMER_A_CCTLN_CM__FALLING ((uint16_t)0x8000)
6756#define TIMER_A_CCTLN_CM__BOTH ((uint16_t)0xC000)
6757/* TIMER_A_EX0[IDEX] Bits */
6758#define TIMER_A_EX0_IDEX_OFS ( 0)
6759#define TIMER_A_EX0_IDEX_MASK ((uint16_t)0x0007)
6760#define TIMER_A_EX0_IDEX0 ((uint16_t)0x0001)
6761#define TIMER_A_EX0_IDEX1 ((uint16_t)0x0002)
6762#define TIMER_A_EX0_IDEX2 ((uint16_t)0x0004)
6763#define TIMER_A_EX0_TAIDEX_0 ((uint16_t)0x0000)
6764#define TIMER_A_EX0_TAIDEX_1 ((uint16_t)0x0001)
6765#define TIMER_A_EX0_TAIDEX_2 ((uint16_t)0x0002)
6766#define TIMER_A_EX0_TAIDEX_3 ((uint16_t)0x0003)
6767#define TIMER_A_EX0_TAIDEX_4 ((uint16_t)0x0004)
6768#define TIMER_A_EX0_TAIDEX_5 ((uint16_t)0x0005)
6769#define TIMER_A_EX0_TAIDEX_6 ((uint16_t)0x0006)
6770#define TIMER_A_EX0_TAIDEX_7 ((uint16_t)0x0007)
6771#define TIMER_A_EX0_IDEX__1 ((uint16_t)0x0000)
6772#define TIMER_A_EX0_IDEX__2 ((uint16_t)0x0001)
6773#define TIMER_A_EX0_IDEX__3 ((uint16_t)0x0002)
6774#define TIMER_A_EX0_IDEX__4 ((uint16_t)0x0003)
6775#define TIMER_A_EX0_IDEX__5 ((uint16_t)0x0004)
6776#define TIMER_A_EX0_IDEX__6 ((uint16_t)0x0005)
6777#define TIMER_A_EX0_IDEX__7 ((uint16_t)0x0006)
6778#define TIMER_A_EX0_IDEX__8 ((uint16_t)0x0007)
6780/******************************************************************************
6781* TLV Bits
6782******************************************************************************/
6783/******************************************************************************
6784* TLV table start and TLV tags *
6785******************************************************************************/
6786#define TLV_START_ADDR (TLV_BASE + 0x0004)
6788#define TLV_TAG_RESERVED1 1
6789#define TLV_TAG_RESERVED2 2
6790#define TLV_TAG_CS 3
6791#define TLV_TAG_FLASHCTL 4
6792#define TLV_TAG_ADC14 5
6793#define TLV_TAG_RESERVED6 6
6794#define TLV_TAG_RESERVED7 7
6795#define TLV_TAG_REF 8
6796#define TLV_TAG_RESERVED9 9
6797#define TLV_TAG_RESERVED10 10
6798#define TLV_TAG_DEVINFO 11
6799#define TLV_TAG_DIEREC 12
6800#define TLV_TAG_RANDNUM 13
6801#define TLV_TAG_RESERVED14 14
6802#define TLV_TAG_BSL 15
6803#define TLV_TAG_END (0x0BD0E11D)
6804
6805
6806/******************************************************************************
6807* TPIU Bits
6808******************************************************************************/
6809
6810
6811/******************************************************************************
6812* WDT_A Bits
6813******************************************************************************/
6814/* WDT_A_CTL[IS] Bits */
6815#define WDT_A_CTL_IS_OFS ( 0)
6816#define WDT_A_CTL_IS_MASK ((uint16_t)0x0007)
6817#define WDT_A_CTL_IS0 ((uint16_t)0x0001)
6818#define WDT_A_CTL_IS1 ((uint16_t)0x0002)
6819#define WDT_A_CTL_IS2 ((uint16_t)0x0004)
6820#define WDT_A_CTL_IS_0 ((uint16_t)0x0000)
6821#define WDT_A_CTL_IS_1 ((uint16_t)0x0001)
6822#define WDT_A_CTL_IS_2 ((uint16_t)0x0002)
6823#define WDT_A_CTL_IS_3 ((uint16_t)0x0003)
6824#define WDT_A_CTL_IS_4 ((uint16_t)0x0004)
6825#define WDT_A_CTL_IS_5 ((uint16_t)0x0005)
6826#define WDT_A_CTL_IS_6 ((uint16_t)0x0006)
6827#define WDT_A_CTL_IS_7 ((uint16_t)0x0007)
6828/* WDT_A_CTL[CNTCL] Bits */
6829#define WDT_A_CTL_CNTCL_OFS ( 3)
6830#define WDT_A_CTL_CNTCL ((uint16_t)0x0008)
6831/* WDT_A_CTL[TMSEL] Bits */
6832#define WDT_A_CTL_TMSEL_OFS ( 4)
6833#define WDT_A_CTL_TMSEL ((uint16_t)0x0010)
6834/* WDT_A_CTL[SSEL] Bits */
6835#define WDT_A_CTL_SSEL_OFS ( 5)
6836#define WDT_A_CTL_SSEL_MASK ((uint16_t)0x0060)
6837#define WDT_A_CTL_SSEL0 ((uint16_t)0x0020)
6838#define WDT_A_CTL_SSEL1 ((uint16_t)0x0040)
6839#define WDT_A_CTL_SSEL_0 ((uint16_t)0x0000)
6840#define WDT_A_CTL_SSEL_1 ((uint16_t)0x0020)
6841#define WDT_A_CTL_SSEL_2 ((uint16_t)0x0040)
6842#define WDT_A_CTL_SSEL_3 ((uint16_t)0x0060)
6843#define WDT_A_CTL_SSEL__SMCLK ((uint16_t)0x0000)
6844#define WDT_A_CTL_SSEL__ACLK ((uint16_t)0x0020)
6845#define WDT_A_CTL_SSEL__VLOCLK ((uint16_t)0x0040)
6846#define WDT_A_CTL_SSEL__BCLK ((uint16_t)0x0060)
6847/* WDT_A_CTL[HOLD] Bits */
6848#define WDT_A_CTL_HOLD_OFS ( 7)
6849#define WDT_A_CTL_HOLD ((uint16_t)0x0080)
6850/* WDT_A_CTL[PW] Bits */
6851#define WDT_A_CTL_PW_OFS ( 8)
6852#define WDT_A_CTL_PW_MASK ((uint16_t)0xFF00)
6853/* Pre-defined bitfield values */
6854#define WDT_A_CTL_PW ((uint16_t)0x5A00)
6857/******************************************************************************
6858* BSL *
6859******************************************************************************/
6860#define BSL_DEFAULT_PARAM ((uint32_t)0xFC48FFFF)
6861#define BSL_API_TABLE_ADDR ((uint32_t)0x00202000)
6862#define BSL_ENTRY_FUNCTION (*((uint32_t *)BSL_API_TABLE_ADDR))
6863
6864#define BSL_AUTO_INTERFACE ((uint32_t)0x0000E0000)
6865#define BSL_UART_INTERFACE ((uint32_t)0x0000C0000)
6866#define BSL_SPI_INTERFACE ((uint32_t)0x0000A0000)
6867#define BSL_I2C_INTERFACE ((uint32_t)0x000080000)
6869#define BSL_INVOKE(x) ((void (*)())BSL_ENTRY_FUNCTION)((uint32_t) x)
6872/******************************************************************************
6873* Mailbox struct legacy definition *
6874******************************************************************************/
6875#define FLASH_MAILBOX_Type FL_BOOTOVER_MAILBOX_Type
6876
6877/******************************************************************************
6878* Device Unlock Support *
6879******************************************************************************/
6880/* unlock the device by:
6881 * Load SYSCTL_SECDATA_UNLOCK register address into R0
6882 * Load SYSCTL_SECDATA_UNLOCK unlock key into R1
6883 * Write the unlock key to the SYSCTL_SECDATA_UNLOCK register
6884 */
6885#define UNLOCK_DEVICE\
6886 __asm(" MOVW.W R0, #0x3040");\
6887 __asm(" MOVT.W R0, #0xE004");\
6888 __asm(" MOVW.W R1, #0x695A");\
6889 __asm(" MOVT.W R1, #0x0000");\
6890 __asm(" STR R1, [R0]");
6891
6892/******************************************************************************
6893*
6894* The following are values that can be used to choose the command that will be
6895* run by the boot code. Perform a logical OR of these settings to create your
6896* general parameter command.
6897*
6898******************************************************************************/
6899#define COMMAND_FACTORY_RESET ((uint32_t)0x00010000)
6900#define COMMAND_BSL_CONFIG ((uint32_t)0x00020000)
6901#define COMMAND_JTAG_SWD_LOCK_SECEN ((uint32_t)0x00080000)
6902#define COMMAND_SEC_ZONE0_EN ((uint32_t)0x00100000)
6903#define COMMAND_SEC_ZONE1_EN ((uint32_t)0x00200000)
6904#define COMMAND_SEC_ZONE2_EN ((uint32_t)0x00400000)
6905#define COMMAND_SEC_ZONE3_EN ((uint32_t)0x00800000)
6906#define COMMAND_SEC_ZONE0_UPDATE ((uint32_t)0x01000000)
6907#define COMMAND_SEC_ZONE1_UPDATE ((uint32_t)0x02000000)
6908#define COMMAND_SEC_ZONE2_UPDATE ((uint32_t)0x04000000)
6909#define COMMAND_SEC_ZONE3_UPDATE ((uint32_t)0x08000000)
6910#define COMMAND_JTAG_SWD_LOCK_ENC_UPDATE ((uint32_t)0x10000000)
6911#define COMMAND_NONE ((uint32_t)0xFFFFFFFF)
6912
6913/******************************************************************************
6914*
6915* The following are values that can be used to configure the BSL. Perform a
6916* logical OR of these settings to create your BSL parameter.
6917*
6918******************************************************************************/
6919#define BSL_CONFIG_HW_INVOKE ((uint32_t)0x70000000)
6920
6921#define BSL_CONFIG_HW_INVOKE_PORT1 ((uint32_t)0x00000000)
6922#define BSL_CONFIG_HW_INVOKE_PORT2 ((uint32_t)0x00000001)
6923#define BSL_CONFIG_HW_INVOKE_PORT3 ((uint32_t)0x00000002)
6924
6925#define BSL_CONFIG_HW_INVOKE_PIN0 ((uint32_t)0x00000000)
6926#define BSL_CONFIG_HW_INVOKE_PIN1 ((uint32_t)0x00000010)
6927#define BSL_CONFIG_HW_INVOKE_PIN2 ((uint32_t)0x00000020)
6928#define BSL_CONFIG_HW_INVOKE_PIN3 ((uint32_t)0x00000030)
6929#define BSL_CONFIG_HW_INVOKE_PIN4 ((uint32_t)0x00000040)
6930#define BSL_CONFIG_HW_INVOKE_PIN5 ((uint32_t)0x00000050)
6931#define BSL_CONFIG_HW_INVOKE_PIN6 ((uint32_t)0x00000060)
6932#define BSL_CONFIG_HW_INVOKE_PIN7 ((uint32_t)0x00000070)
6933
6934#define BSL_CONFIG_HW_INVOKE_PIN_LOW ((uint32_t)0x00000000)
6935#define BSL_CONFIG_HW_INVOKE_PIN_HIGH ((uint32_t)0x00001000)
6936
6937#define BSL_CONFIG_INTERFACE_I2C ((uint32_t)0x00008000)
6938#define BSL_CONFIG_INTERFACE_SPI ((uint32_t)0x0000A000)
6939#define BSL_CONFIG_INTERFACE_UART ((uint32_t)0x0000C000)
6940#define BSL_CONFIG_INTERFACE_AUTO ((uint32_t)0x0000E000)
6941
6942#define BSL_CONFIG_I2C_ADD_OFFSET (16)
6943
6944
6945/******************************************************************************
6946* ULP Advisor *
6947******************************************************************************/
6948#ifdef __TI_ARM__
6949#pragma ULP_PORT_CONFIG(1,DIR={0x40004C04,8},OUT={0x40004C02,8},SEL1={0x40004C0A,8},SEL2={0x40004C0C,8})
6950#pragma ULP_PORT_CONFIG(2,DIR={0x40004C05,8},OUT={0x40004C03,8},SEL1={0x40004C0B,8},SEL2={0x40004C0D,8})
6951#pragma ULP_PORT_CONFIG(3,DIR={0x40004C24,8},OUT={0x40004C22,8},SEL1={0x40004C2A,8},SEL2={0x40004C2C,8})
6952#pragma ULP_PORT_CONFIG(4,DIR={0x40004C25,8},OUT={0x40004C23,8},SEL1={0x40004C2B,8},SEL2={0x40004C2D,8})
6953#pragma ULP_PORT_CONFIG(5,DIR={0x40004C44,8},OUT={0x40004C42,8},SEL1={0x40004C4A,8},SEL2={0x40004C4C,8})
6954#pragma ULP_PORT_CONFIG(6,DIR={0x40004C45,8},OUT={0x40004C43,8},SEL1={0x40004C4B,8},SEL2={0x40004C4D,8})
6955#pragma ULP_PORT_CONFIG(7,DIR={0x40004C64,8},OUT={0x40004C62,8},SEL1={0x40004C6A,8},SEL2={0x40004C6C,8})
6956#pragma ULP_PORT_CONFIG(8,DIR={0x40004C65,8},OUT={0x40004C63,8},SEL1={0x40004C6B,8},SEL2={0x40004C6D,8})
6957#pragma ULP_PORT_CONFIG(9,DIR={0x40004C84,8},OUT={0x40004C82,8},SEL1={0x40004C8A,8},SEL2={0x40004C8C,8})
6958#pragma ULP_PORT_CONFIG(10,DIR={0x40004C85,8},OUT={0x40004C83,8},SEL1={0x40004C8B,8},SEL2={0x40004C8D,8})
6959#endif
6960
6961
6962#ifdef __cplusplus
6963}
6964#endif
6965
6966#endif /* __MSP432P401R_H__ */
6967
__O
#define __O
Definition core_armv81mml.h:312
__IO
#define __IO
Definition core_armv81mml.h:313
__I
#define __I
Definition core_armv81mml.h:310
EUSCI_A_Type::IFG
__IO uint16_t IFG
Definition msp432p401r.h:766
TLV_Type::ADC14_CAL_LEN
__I uint32_t ADC14_CAL_LEN
Definition msp432p401r.h:1256
DIO_PORT_Odd_Interruptable_Type::DS
__IO uint8_t DS
Definition msp432p401r.h:656
EUSCI_A_SPI_Type::TXBUF
__IO uint16_t TXBUF
Definition msp432p401r.h:782
TLV_Type::RANDOM_NUM_2
__I uint32_t RANDOM_NUM_2
Definition msp432p401r.h:1293
ADC14_Type::CLRIFGR1
__IO uint32_t CLRIFGR1
Definition msp432p401r.h:379
DIO_PORT_Even_Interruptable_Type::DIR
__IO uint8_t DIR
Definition msp432p401r.h:680
DIO_PORT_Not_Interruptable_Type::DS_H
__IO uint8_t DS_H
Definition msp432p401r.h:619
TLV_Type::DIE_REC_LEN
__I uint32_t DIE_REC_LEN
Definition msp432p401r.h:1228
PSS_Type::CLRIFG
__IO uint32_t CLRIFG
Definition msp432p401r.h:1046
COMP_E_Type::IV
__I uint16_t IV
Definition msp432p401r.h:433
DIO_PORT_Not_Interruptable_Type::DIR_L
__IO uint8_t DIR_L
Definition msp432p401r.h:604
RTC_C_Type::TIM0
__IO uint16_t TIM0
Definition msp432p401r.h:1110
CS_Type::KEY
__IO uint32_t KEY
Definition msp432p401r.h:473
EUSCI_B_SPI_Type::TXBUF
__IO uint16_t TXBUF
Definition msp432p401r.h:833
DIO_PORT_Interruptable_Type::IN
__I uint16_t IN
Definition msp432p401r.h:505
TLV_Type::RESERVED19
__I uint32_t RESERVED19
Definition msp432p401r.h:1267
EUSCI_A_Type::IV
__I uint16_t IV
Definition msp432p401r.h:767
RTC_C_Type::PS
__IO uint16_t PS
Definition msp432p401r.h:1108
FLCTL_Type::PRGBRST_DATA0_1
__IO uint32_t PRGBRST_DATA0_1
Definition msp432p401r.h:867
Timer_A_Type::IV
__I uint16_t IV
Definition msp432p401r.h:1207
EUSCI_A_SPI_Type::BRW
__IO uint16_t BRW
Definition msp432p401r.h:778
FLCTL_Type::PRGBRST_DATA2_2
__IO uint32_t PRGBRST_DATA2_2
Definition msp432p401r.h:876
DIO_PORT_Interruptable_Type::OUT_L
__IO uint8_t OUT_L
Definition msp432p401r.h:514
DMA_Control_Type::ENASET
__IO uint32_t ENASET
Definition msp432p401r.h:734
CS_Type::CTL1
__IO uint32_t CTL1
Definition msp432p401r.h:475
EUSCI_A_Type::STATW
__IO uint16_t STATW
Definition msp432p401r.h:759
EUSCI_B_Type::CTLW0
__IO uint16_t CTLW0
Definition msp432p401r.h:799
ADC14_Type::CTL0
__IO uint32_t CTL0
Definition msp432p401r.h:365
SEC_ZONE_PARAMS_Type::SEC_ZONE_LENGTH
__IO uint32_t SEC_ZONE_LENGTH
Definition msp432p401r.h:923
FLCTL_Type::POWER_STAT
__I uint32_t POWER_STAT
Definition msp432p401r.h:850
DIO_PORT_Interruptable_Type::IE_H
__IO uint8_t IE_H
Definition msp432p401r.h:573
FLCTL_Type::BANK0_RDCTL
__IO uint32_t BANK0_RDCTL
Definition msp432p401r.h:852
EUSCI_B_Type::I2CSA
__IO uint16_t I2CSA
Definition msp432p401r.h:814
RSTCTL_Type::PSSRESET_CLR
__IO uint32_t PSSRESET_CLR
Definition msp432p401r.h:1081
FLCTL_Type::PRGBRST_DATA3_0
__IO uint32_t PRGBRST_DATA3_0
Definition msp432p401r.h:878
DMA_Control_Type::WAITSTAT
__I uint32_t WAITSTAT
Definition msp432p401r.h:728
EUSCI_B_Type::I2COA1
__IO uint16_t I2COA1
Definition msp432p401r.h:809
Timer32_Type::CONTROL
__IO uint32_t CONTROL
Definition msp432p401r.h:1182
TLV_Type::ROM_DRVLIB_REV
__I uint32_t ROM_DRVLIB_REV
Definition msp432p401r.h:1226
DIO_PORT_Not_Interruptable_Type::SEL1
__IO uint16_t SEL1
Definition msp432p401r.h:630
TLV_Type::CS_CAL_LEN
__I uint32_t CS_CAL_LEN
Definition msp432p401r.h:1238
TLV_Type::REF_CAL_TAG
__I uint32_t REF_CAL_TAG
Definition msp432p401r.h:1281
DMA_Channel_Type::INT0_SRCFLG
__I uint32_t INT0_SRCFLG
Definition msp432p401r.h:719
CS_Type::IE
__IO uint32_t IE
Definition msp432p401r.h:482
TLV_Type::ADC14_REF1P45V_TS85C
__I uint32_t ADC14_REF1P45V_TS85C
Definition msp432p401r.h:1278
FLCTL_Type::BMRK_CTLSTAT
__IO uint32_t BMRK_CTLSTAT
Definition msp432p401r.h:891
TLV_Type::FLASH_MAX_PROG_PULSES
__I uint32_t FLASH_MAX_PROG_PULSES
Definition msp432p401r.h:1288
RTC_C_Type::BIN2BCD
__IO uint16_t BIN2BCD
Definition msp432p401r.h:1116
DMA_Channel_Type::INT2_SRCCFG
__IO uint32_t INT2_SRCCFG
Definition msp432p401r.h:716
TLV_Type::HWREV
__I uint32_t HWREV
Definition msp432p401r.h:1224
AES256_Type::STAT
__IO uint16_t STAT
Definition msp432p401r.h:395
ADC14_Type::IER1
__IO uint32_t IER1
Definition msp432p401r.h:375
TLV_Type::ADC14_CAL_TAG
__I uint32_t ADC14_CAL_TAG
Definition msp432p401r.h:1255
CS_Type::CLKEN
__IO uint32_t CLKEN
Definition msp432p401r.h:479
DIO_PORT_Not_Interruptable_Type::DS_L
__IO uint8_t DS_L
Definition msp432p401r.h:618
AES256_Type::CTL0
__IO uint16_t CTL0
Definition msp432p401r.h:393
TLV_Type::DEVICE_ID
__I uint32_t DEVICE_ID
Definition msp432p401r.h:1223
PCM_Type::CTL0
__IO uint32_t CTL0
Definition msp432p401r.h:994
TLV_Type::LOT_ID
__I uint32_t LOT_ID
Definition msp432p401r.h:1232
TLV_Type::DCOER_FCAL_RSEL04
__I uint32_t DCOER_FCAL_RSEL04
Definition msp432p401r.h:1247
CS_Type::DCOERCAL1
__IO uint32_t DCOERCAL1
Definition msp432p401r.h:491
TLV_Type::RESERVED8
__I uint32_t RESERVED8
Definition msp432p401r.h:1250
TLV_Type::DCOIR_CONSTK_RSEL04
__I uint32_t DCOIR_CONSTK_RSEL04
Definition msp432p401r.h:1245
TLV_Type::RESERVED17
__I uint32_t RESERVED17
Definition msp432p401r.h:1265
RTC_C_Type::TCMP
__IO uint16_t TCMP
Definition msp432p401r.h:1105
CS_Type::CTL0
__IO uint32_t CTL0
Definition msp432p401r.h:474
DIO_PORT_Even_Interruptable_Type::OUT
__IO uint8_t OUT
Definition msp432p401r.h:678
RTC_C_Type::ADOWDAY
__IO uint16_t ADOWDAY
Definition msp432p401r.h:1115
RTC_C_Type::TIM1
__IO uint16_t TIM1
Definition msp432p401r.h:1111
EUSCI_B_Type::IV
__I uint16_t IV
Definition msp432p401r.h:818
FLCTL_Type::PRGBRST_DATA1_3
__IO uint32_t PRGBRST_DATA1_3
Definition msp432p401r.h:873
DIO_PORT_Odd_Interruptable_Type::IV
__I uint16_t IV
Definition msp432p401r.h:662
RSTCTL_Type::SOFTRESET_STAT
__I uint32_t SOFTRESET_STAT
Definition msp432p401r.h:1076
TLV_Type::ADC14_REF1P2V_TS85C
__I uint32_t ADC14_REF1P2V_TS85C
Definition msp432p401r.h:1276
EUSCI_A_Type::CTLW0
__IO uint16_t CTLW0
Definition msp432p401r.h:754
FL_BOOTOVER_MAILBOX_Type::BSL_ENABLE
__IO uint32_t BSL_ENABLE
Definition msp432p401r.h:961
FLCTL_Type::ERASE_SECTADDR
__IO uint32_t ERASE_SECTADDR
Definition msp432p401r.h:883
EUSCI_A_SPI_Type::IE
__IO uint16_t IE
Definition msp432p401r.h:784
SEC_ZONE_UPDATE_Type::SEC_ZONE_PAYLOADADDR
__IO uint32_t SEC_ZONE_PAYLOADADDR
Definition msp432p401r.h:939
RTC_C_BCD_Type::TIM1
__IO uint16_t TIM1
Definition msp432p401r.h:1128
DIO_PORT_Interruptable_Type::IFG
__IO uint16_t IFG
Definition msp432p401r.h:577
TLV_Type::RESERVED23
__I uint32_t RESERVED23
Definition msp432p401r.h:1271
DIO_PORT_Interruptable_Type::IE
__IO uint16_t IE
Definition msp432p401r.h:570
DMA_Control_Type::USEBURSTCLR
__O uint32_t USEBURSTCLR
Definition msp432p401r.h:731
EUSCI_B_SPI_Type::IE
__IO uint16_t IE
Definition msp432p401r.h:835
DIO_PORT_Even_Interruptable_Type::SELC
__IO uint8_t SELC
Definition msp432p401r.h:690
PSS_Type::CTL0
__IO uint32_t CTL0
Definition msp432p401r.h:1042
FLCTL_Type::PRG_CTLSTAT
__IO uint32_t PRG_CTLSTAT
Definition msp432p401r.h:862
CRC32_Type::DIRB16
__IO uint16_t DIRB16
Definition msp432p401r.h:456
DIO_PORT_Interruptable_Type::REN_L
__IO uint8_t REN_L
Definition msp432p401r.h:528
ADC14_Type::IFGR0
__I uint32_t IFGR0
Definition msp432p401r.h:376
EUSCI_B_Type::I2COA3
__IO uint16_t I2COA3
Definition msp432p401r.h:811
DIO_PORT_Odd_Interruptable_Type::IE
__IO uint8_t IE
Definition msp432p401r.h:668
DIO_PORT_Interruptable_Type::DIR_L
__IO uint8_t DIR_L
Definition msp432p401r.h:521
DIO_PORT_Interruptable_Type::DS_H
__IO uint8_t DS_H
Definition msp432p401r.h:536
TLV_Type::RANDOM_NUM_1
__I uint32_t RANDOM_NUM_1
Definition msp432p401r.h:1292
FL_BOOTOVER_MAILBOX_Type::BSL_PARAMETERS
__IO uint32_t BSL_PARAMETERS
Definition msp432p401r.h:963
TLV_Type::RESERVED13
__I uint32_t RESERVED13
Definition msp432p401r.h:1261
TLV_Type::ADC_GAIN_FACTOR
__I uint32_t ADC_GAIN_FACTOR
Definition msp432p401r.h:1257
Timer32_Type::INTCLR
__O uint32_t INTCLR
Definition msp432p401r.h:1183
DMA_Control_Type::REQMASKSET
__IO uint32_t REQMASKSET
Definition msp432p401r.h:732
FLCTL_Type::RDBRST_FAILADDR
__IO uint32_t RDBRST_FAILADDR
Definition msp432p401r.h:859
RSTCTL_Type::SOFTRESET_CLR
__IO uint32_t SOFTRESET_CLR
Definition msp432p401r.h:1077
Timer32_Type::MIS
__I uint32_t MIS
Definition msp432p401r.h:1185
DIO_PORT_Interruptable_Type::REN_H
__IO uint8_t REN_H
Definition msp432p401r.h:529
FLCTL_Type::ERSVER_TIMCTL
__I uint32_t ERSVER_TIMCTL
Definition msp432p401r.h:903
TLV_Type::DEVICE_INFO_TAG
__I uint32_t DEVICE_INFO_TAG
Definition msp432p401r.h:1221
SYSCTL_Type::DIO_GLTFLT_CTL
__IO uint32_t DIO_GLTFLT_CTL
Definition msp432p401r.h:1155
REF_A_Type::CTL0
__IO uint16_t CTL0
Definition msp432p401r.h:1059
TLV_Type::RESERVED9
__I uint32_t RESERVED9
Definition msp432p401r.h:1251
RTC_C_Type::CTL0
__IO uint16_t CTL0
Definition msp432p401r.h:1102
RSTCTL_Type::CSRESET_STAT
__I uint32_t CSRESET_STAT
Definition msp432p401r.h:1088
FLCTL_Type::LKGVER_TIMCTL
__I uint32_t LKGVER_TIMCTL
Definition msp432p401r.h:904
TLV_Type::DIE_YPOS
__I uint32_t DIE_YPOS
Definition msp432p401r.h:1230
DIO_PORT_Interruptable_Type::OUT_H
__IO uint8_t OUT_H
Definition msp432p401r.h:515
TLV_Type::RESERVED20
__I uint32_t RESERVED20
Definition msp432p401r.h:1268
TLV_Type::REF_2P5V
__I uint32_t REF_2P5V
Definition msp432p401r.h:1285
FLCTL_Type::READ_TIMCTL
__I uint32_t READ_TIMCTL
Definition msp432p401r.h:900
SYSCTL_Type::NMI_CTLSTAT
__IO uint32_t NMI_CTLSTAT
Definition msp432p401r.h:1146
TLV_Type::RESERVED0
__I uint32_t RESERVED0
Definition msp432p401r.h:1233
COMP_E_Type::INT
__IO uint16_t INT
Definition msp432p401r.h:432
DIO_PORT_Not_Interruptable_Type::IN_H
__I uint8_t IN_H
Definition msp432p401r.h:591
SEC_ZONE_PARAMS_Type::SEC_ZONE_DATA_EN
__IO uint32_t SEC_ZONE_DATA_EN
Definition msp432p401r.h:928
TLV_Type::RESERVED22
__I uint32_t RESERVED22
Definition msp432p401r.h:1270
Timer32_Type::VALUE
__I uint32_t VALUE
Definition msp432p401r.h:1181
FLCTL_Type::PRGBRST_DATA1_2
__IO uint32_t PRGBRST_DATA1_2
Definition msp432p401r.h:872
DIO_PORT_Interruptable_Type::DS_L
__IO uint8_t DS_L
Definition msp432p401r.h:535
FLCTL_Type::PRGBRST_DATA1_1
__IO uint32_t PRGBRST_DATA1_1
Definition msp432p401r.h:871
COMP_E_Type::CTL2
__IO uint16_t CTL2
Definition msp432p401r.h:429
CRC32_Type::INIRES16
__IO uint16_t INIRES16
Definition msp432p401r.h:458
FLCTL_Type::RDBRST_CTLSTAT
__IO uint32_t RDBRST_CTLSTAT
Definition msp432p401r.h:855
EUSCI_B_SPI_Type::CTLW0
__IO uint16_t CTLW0
Definition msp432p401r.h:827
DIO_PORT_Not_Interruptable_Type::REN_H
__IO uint8_t REN_H
Definition msp432p401r.h:612
TLV_Type::RESERVED2
__I uint32_t RESERVED2
Definition msp432p401r.h:1235
FLCTL_Type::IFG
__IO uint32_t IFG
Definition msp432p401r.h:896
SYSCTL_Type::WDTRESET_CTL
__IO uint32_t WDTRESET_CTL
Definition msp432p401r.h:1147
FL_BOOTOVER_MAILBOX_Type::JTAG_SWD_LOCK_ACK
__IO uint32_t JTAG_SWD_LOCK_ACK
Definition msp432p401r.h:958
EUSCI_B_SPI_Type::IV
__I uint16_t IV
Definition msp432p401r.h:837
DIO_PORT_Interruptable_Type::IES_L
__IO uint8_t IES_L
Definition msp432p401r.h:565
RTC_C_BCD_Type::DATE
__IO uint16_t DATE
Definition msp432p401r.h:1129
DMA_Control_Type::CTLBASE
__IO uint32_t CTLBASE
Definition msp432p401r.h:726
DIO_PORT_Not_Interruptable_Type::SELC
__IO uint16_t SELC
Definition msp432p401r.h:638
SYSCTL_Type::SRAM_BANKRET
__IO uint32_t SRAM_BANKRET
Definition msp432p401r.h:1151
FLCTL_Type::PRGBRST_STARTADDR
__IO uint32_t PRGBRST_STARTADDR
Definition msp432p401r.h:864
TLV_Type::ADC14_REF1P2V_TS30C
__I uint32_t ADC14_REF1P2V_TS30C
Definition msp432p401r.h:1275
DIO_PORT_Interruptable_Type::IE_L
__IO uint8_t IE_L
Definition msp432p401r.h:572
DIO_PORT_Not_Interruptable_Type::OUT
__IO uint16_t OUT
Definition msp432p401r.h:595
EUSCI_A_SPI_Type::RXBUF
__I uint16_t RXBUF
Definition msp432p401r.h:781
TLV_Type::DCOIR_FCAL_RSEL04
__I uint32_t DCOIR_FCAL_RSEL04
Definition msp432p401r.h:1239
TLV_Type::DIE_REC_TAG
__I uint32_t DIE_REC_TAG
Definition msp432p401r.h:1227
DIO_PORT_Not_Interruptable_Type::SEL0_H
__IO uint8_t SEL0_H
Definition msp432p401r.h:626
CS_Type::SETIFG
__O uint32_t SETIFG
Definition msp432p401r.h:488
FLCTL_Type::BMRK_DREAD
__IO uint32_t BMRK_DREAD
Definition msp432p401r.h:893
RTC_C_Type::YEAR
__IO uint16_t YEAR
Definition msp432p401r.h:1113
TLV_Type::DIE_XPOS
__I uint32_t DIE_XPOS
Definition msp432p401r.h:1229
EUSCI_B_Type::TBCNT
__IO uint16_t TBCNT
Definition msp432p401r.h:804
CS_Type::DCOERCAL0
__IO uint32_t DCOERCAL0
Definition msp432p401r.h:490
RSTCTL_Type::REBOOTRESET_CLR
__IO uint32_t REBOOTRESET_CLR
Definition msp432p401r.h:1087
TLV_Type::REF_1P2V
__I uint32_t REF_1P2V
Definition msp432p401r.h:1283
TLV_Type::FLASH_MAX_ERASE_PULSES
__I uint32_t FLASH_MAX_ERASE_PULSES
Definition msp432p401r.h:1289
TLV_Type::ADC14_REF2P5V_TS30C
__I uint32_t ADC14_REF2P5V_TS30C
Definition msp432p401r.h:1279
CRC32_Type::RESR32_LO
__IO uint16_t RESR32_LO
Definition msp432p401r.h:452
FLCTL_Type::CLRIFG
__IO uint32_t CLRIFG
Definition msp432p401r.h:898
TLV_Type::RESERVED25
__I uint32_t RESERVED25
Definition msp432p401r.h:1273
SYSCTL_Type::SRAM_SIZE
__I uint32_t SRAM_SIZE
Definition msp432p401r.h:1149
ADC14_Type::IV
__IO uint32_t IV
Definition msp432p401r.h:380
TLV_Type::ADC14_REF2P5V_TS85C
__I uint32_t ADC14_REF2P5V_TS85C
Definition msp432p401r.h:1280
EUSCI_B_SPI_Type::BRW
__IO uint16_t BRW
Definition msp432p401r.h:829
TLV_Type::RANDOM_NUM_TAG
__I uint32_t RANDOM_NUM_TAG
Definition msp432p401r.h:1290
SYSCTL_Boot_Type::BOOTOVER_ACK
__IO uint32_t BOOTOVER_ACK
Definition msp432p401r.h:1163
FLCTL_Type::BANK1_INFO_WEPROT
__IO uint32_t BANK1_INFO_WEPROT
Definition msp432p401r.h:888
DIO_PORT_Not_Interruptable_Type::SEL0
__IO uint16_t SEL0
Definition msp432p401r.h:623
ADC14_Type::HI1
__IO uint32_t HI1
Definition msp432p401r.h:370
FL_BOOTOVER_MAILBOX_Type::ENC_UPDATE_ACK
__IO uint32_t ENC_UPDATE_ACK
Definition msp432p401r.h:969
EUSCI_B_Type::I2COA2
__IO uint16_t I2COA2
Definition msp432p401r.h:810
COMP_E_Type::CTL3
__IO uint16_t CTL3
Definition msp432p401r.h:430
FL_BOOTOVER_MAILBOX_Type::BSL_START_ADDRESS
__IO uint32_t BSL_START_ADDRESS
Definition msp432p401r.h:962
SYSCTL_Type::PERIHALT_CTL
__IO uint32_t PERIHALT_CTL
Definition msp432p401r.h:1148
TLV_Type::RANDOM_NUM_4
__I uint32_t RANDOM_NUM_4
Definition msp432p401r.h:1295
FLCTL_Type::ERASE_TIMCTL
__I uint32_t ERASE_TIMCTL
Definition msp432p401r.h:906
DIO_PORT_Odd_Interruptable_Type::OUT
__IO uint8_t OUT
Definition msp432p401r.h:650
FLCTL_Type::PRGBRST_DATA0_0
__IO uint32_t PRGBRST_DATA0_0
Definition msp432p401r.h:866
DMA_Control_Type::CFG
__O uint32_t CFG
Definition msp432p401r.h:725
DMA_Control_Type::ALTBASE
__I uint32_t ALTBASE
Definition msp432p401r.h:727
TLV_Type::DCOER_CONSTK_RSEL04
__I uint32_t DCOER_CONSTK_RSEL04
Definition msp432p401r.h:1253
AES256_Type::XDIN
__O uint16_t XDIN
Definition msp432p401r.h:399
CRC32_Type::DI16
__IO uint16_t DI16
Definition msp432p401r.h:454
DMA_Channel_Type::DEVICE_CFG
__I uint32_t DEVICE_CFG
Definition msp432p401r.h:710
TLV_Type::RESERVED24
__I uint32_t RESERVED24
Definition msp432p401r.h:1272
DIO_PORT_Interruptable_Type::SEL1_H
__IO uint8_t SEL1_H
Definition msp432p401r.h:550
DIO_PORT_Odd_Interruptable_Type::DIR
__IO uint8_t DIR
Definition msp432p401r.h:652
TLV_Type::BSL_PERIPHIF_SEL
__I uint32_t BSL_PERIPHIF_SEL
Definition msp432p401r.h:1298
EUSCI_B_Type::RXBUF
__I uint16_t RXBUF
Definition msp432p401r.h:805
TLV_Type::RESERVED5
__I uint32_t RESERVED5
Definition msp432p401r.h:1243
TLV_Type::RESERVED4
__I uint32_t RESERVED4
Definition msp432p401r.h:1242
Timer32_Type::BGLOAD
__IO uint32_t BGLOAD
Definition msp432p401r.h:1186
DMA_Control_Type::SWREQ
__O uint32_t SWREQ
Definition msp432p401r.h:729
DIO_PORT_Interruptable_Type::IFG_H
__IO uint8_t IFG_H
Definition msp432p401r.h:580
CS_Type::CTL2
__IO uint32_t CTL2
Definition msp432p401r.h:476
TLV_Type::BSL_CFG_LEN
__I uint32_t BSL_CFG_LEN
Definition msp432p401r.h:1297
EUSCI_A_Type::TXBUF
__IO uint16_t TXBUF
Definition msp432p401r.h:761
FLCTL_Type::IE
__IO uint32_t IE
Definition msp432p401r.h:897
TLV_Type::BSL_CFG_TAG
__I uint32_t BSL_CFG_TAG
Definition msp432p401r.h:1296
FLCTL_Type::RDBRST_FAILCNT
__IO uint32_t RDBRST_FAILCNT
Definition msp432p401r.h:860
FLCTL_Type::BANK0_INFO_WEPROT
__IO uint32_t BANK0_INFO_WEPROT
Definition msp432p401r.h:885
TLV_Type::RESERVED16
__I uint32_t RESERVED16
Definition msp432p401r.h:1264
RTC_C_Type::OCAL
__IO uint16_t OCAL
Definition msp432p401r.h:1104
FLCTL_Type::READMARGIN_TIMCTL
__I uint32_t READMARGIN_TIMCTL
Definition msp432p401r.h:901
DIO_PORT_Interruptable_Type::IV_H
__I uint16_t IV_H
Definition msp432p401r.h:583
FL_BOOTOVER_MAILBOX_Type::JTAG_SWD_LOCK_ENCPAYLOADLEN
__IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADLEN
Definition msp432p401r.h:967
SYSCTL_Type::REBOOT_CTL
__IO uint32_t REBOOT_CTL
Definition msp432p401r.h:1145
DMA_Control_Type::PRIOSET
__IO uint32_t PRIOSET
Definition msp432p401r.h:738
SEC_ZONE_PARAMS_Type::SEC_ZONE_ENCUPDATE_EN
__IO uint32_t SEC_ZONE_ENCUPDATE_EN
Definition msp432p401r.h:927
DIO_PORT_Interruptable_Type::REN
__IO uint16_t REN
Definition msp432p401r.h:526
CS_Type::CTL3
__IO uint32_t CTL3
Definition msp432p401r.h:477
DMA_Control_Type::ERRCLR
__IO uint32_t ERRCLR
Definition msp432p401r.h:741
DIO_PORT_Interruptable_Type::SEL0_H
__IO uint8_t SEL0_H
Definition msp432p401r.h:543
DMA_Control_Type::REQMASKCLR
__O uint32_t REQMASKCLR
Definition msp432p401r.h:733
FL_BOOTOVER_MAILBOX_Type::JTAG_SWD_LOCK_DST_ADDR
__IO uint32_t JTAG_SWD_LOCK_DST_ADDR
Definition msp432p401r.h:968
DIO_PORT_Interruptable_Type::SELC_H
__IO uint8_t SELC_H
Definition msp432p401r.h:559
TLV_Type::ADC14_REF1P45V_TS30C
__I uint32_t ADC14_REF1P45V_TS30C
Definition msp432p401r.h:1277
EUSCI_B_Type::IFG
__IO uint16_t IFG
Definition msp432p401r.h:817
RTC_C_Type::CTL13
__IO uint16_t CTL13
Definition msp432p401r.h:1103
TLV_Type::DEVICE_INFO_LEN
__I uint32_t DEVICE_INFO_LEN
Definition msp432p401r.h:1222
RTC_C_BCD_Type::AMINHR
__IO uint16_t AMINHR
Definition msp432p401r.h:1131
RSTCTL_Type::PINRESET_STAT
__I uint32_t PINRESET_STAT
Definition msp432p401r.h:1084
FL_BOOTOVER_MAILBOX_Type::JTAG_SWD_LOCK_SECEN
__IO uint32_t JTAG_SWD_LOCK_SECEN
Definition msp432p401r.h:954
SEC_ZONE_PARAMS_Type::SEC_ZONE_SECEN
__IO uint32_t SEC_ZONE_SECEN
Definition msp432p401r.h:921
TLV_Type::TLV_CHECKSUM
__I uint32_t TLV_CHECKSUM
Definition msp432p401r.h:1220
TLV_Type::RESERVED26
__I uint32_t RESERVED26
Definition msp432p401r.h:1274
EUSCI_A_SPI_Type::IV
__I uint16_t IV
Definition msp432p401r.h:786
Timer32_Type::RIS
__I uint32_t RIS
Definition msp432p401r.h:1184
DIO_PORT_Not_Interruptable_Type::REN_L
__IO uint8_t REN_L
Definition msp432p401r.h:611
RSTCTL_Type::SOFTRESET_SET
__IO uint32_t SOFTRESET_SET
Definition msp432p401r.h:1078
FLCTL_Type::RDBRST_LEN
__IO uint32_t RDBRST_LEN
Definition msp432p401r.h:857
DIO_PORT_Not_Interruptable_Type::SELC_L
__IO uint8_t SELC_L
Definition msp432p401r.h:640
DIO_PORT_Odd_Interruptable_Type::IN
__I uint8_t IN
Definition msp432p401r.h:648
EUSCI_B_SPI_Type::IFG
__IO uint16_t IFG
Definition msp432p401r.h:836
RTC_C_Type::PS0CTL
__IO uint16_t PS0CTL
Definition msp432p401r.h:1106
DMA_Control_Type::PRIOCLR
__O uint32_t PRIOCLR
Definition msp432p401r.h:739
SEC_ZONE_PARAMS_Type::SEC_ZONE_START_ADDR
__IO uint32_t SEC_ZONE_START_ADDR
Definition msp432p401r.h:922
Timer_A_Type::R
__IO uint16_t R
Definition msp432p401r.h:1202
EUSCI_B_Type::IE
__IO uint16_t IE
Definition msp432p401r.h:816
FLCTL_Type::PRGVER_TIMCTL
__I uint32_t PRGVER_TIMCTL
Definition msp432p401r.h:902
RTC_C_BCD_Type::YEAR
__IO uint16_t YEAR
Definition msp432p401r.h:1130
FLCTL_Type::BANK1_RDCTL
__IO uint32_t BANK1_RDCTL
Definition msp432p401r.h:853
RTC_C_Type::DATE
__IO uint16_t DATE
Definition msp432p401r.h:1112
CRC32_Type::INIRES32_HI
__IO uint16_t INIRES32_HI
Definition msp432p401r.h:451
RSTCTL_Type::REBOOTRESET_STAT
__I uint32_t REBOOTRESET_STAT
Definition msp432p401r.h:1086
FLCTL_Type::PRGBRST_DATA3_1
__IO uint32_t PRGBRST_DATA3_1
Definition msp432p401r.h:879
DIO_PORT_Interruptable_Type::IES_H
__IO uint8_t IES_H
Definition msp432p401r.h:566
RSTCTL_Type::PINRESET_CLR
__IO uint32_t PINRESET_CLR
Definition msp432p401r.h:1085
AES256_Type::KEY
__O uint16_t KEY
Definition msp432p401r.h:396
PSS_Type::IFG
__I uint32_t IFG
Definition msp432p401r.h:1045
TLV_Type::DCOIR_CONSTK_RSEL5
__I uint32_t DCOIR_CONSTK_RSEL5
Definition msp432p401r.h:1246
AES256_Type::XIN
__O uint16_t XIN
Definition msp432p401r.h:400
TLV_Type::BSL_PORTIF_CFG_I2C
__I uint32_t BSL_PORTIF_CFG_I2C
Definition msp432p401r.h:1301
DIO_PORT_Interruptable_Type::SEL0
__IO uint16_t SEL0
Definition msp432p401r.h:540
RTC_C_Type::IV
__I uint16_t IV
Definition msp432p401r.h:1109
PSS_Type::IE
__IO uint32_t IE
Definition msp432p401r.h:1044
DIO_PORT_Odd_Interruptable_Type::REN
__IO uint8_t REN
Definition msp432p401r.h:654
Timer32_Type::LOAD
__IO uint32_t LOAD
Definition msp432p401r.h:1180
Timer_A_Type::EX0
__IO uint16_t EX0
Definition msp432p401r.h:1205
Timer_A_Type::CTL
__IO uint16_t CTL
Definition msp432p401r.h:1199
DIO_PORT_Not_Interruptable_Type::DIR
__IO uint16_t DIR
Definition msp432p401r.h:602
PCM_Type::CTL1
__IO uint32_t CTL1
Definition msp432p401r.h:995
SEC_ZONE_UPDATE_Type::SEC_ZONE_UPDATE_ACK
__IO uint32_t SEC_ZONE_UPDATE_ACK
Definition msp432p401r.h:941
TLV_Type::RESERVED7
__I uint32_t RESERVED7
Definition msp432p401r.h:1249
TLV_Type::TLV_END
__I uint32_t TLV_END
Definition msp432p401r.h:1302
FLCTL_Type::PRGBRST_DATA3_2
__IO uint32_t PRGBRST_DATA3_2
Definition msp432p401r.h:880
EUSCI_B_Type::STATW
__IO uint16_t STATW
Definition msp432p401r.h:803
DIO_PORT_Not_Interruptable_Type::DIR_H
__IO uint8_t DIR_H
Definition msp432p401r.h:605
DIO_PORT_Even_Interruptable_Type::SEL0
__IO uint8_t SEL0
Definition msp432p401r.h:686
FLCTL_Type::BMRK_CMP
__IO uint32_t BMRK_CMP
Definition msp432p401r.h:894
SYSCTL_Boot_Type::SYSTEM_STAT
__I uint32_t SYSTEM_STAT
Definition msp432p401r.h:1167
SYSCTL_Boot_Type::MASTER_UNLOCK
__IO uint32_t MASTER_UNLOCK
Definition msp432p401r.h:1161
FLCTL_Type::ERASE_CTLSTAT
__IO uint32_t ERASE_CTLSTAT
Definition msp432p401r.h:882
DMA_Control_Type::ALTSET
__IO uint32_t ALTSET
Definition msp432p401r.h:736
CRC32_Type::RESR16
__IO uint16_t RESR16
Definition msp432p401r.h:460
DIO_PORT_Interruptable_Type::DS
__IO uint16_t DS
Definition msp432p401r.h:533
RSTCTL_Type::CSRESET_CLR
__IO uint32_t CSRESET_CLR
Definition msp432p401r.h:1089
SYSCTL_Type::SECDATA_UNLOCK
__IO uint32_t SECDATA_UNLOCK
Definition msp432p401r.h:1157
EUSCI_A_Type::MCTLW
__IO uint16_t MCTLW
Definition msp432p401r.h:758
FLCTL_Type::BMRK_IFETCH
__IO uint32_t BMRK_IFETCH
Definition msp432p401r.h:892
ADC14_Type::IFGR1
__I uint32_t IFGR1
Definition msp432p401r.h:377
RSTCTL_Type::HARDRESET_CLR
__IO uint32_t HARDRESET_CLR
Definition msp432p401r.h:1074
DIO_PORT_Interruptable_Type::IN_H
__I uint8_t IN_H
Definition msp432p401r.h:508
DMA_Control_Type::USEBURSTSET
__IO uint32_t USEBURSTSET
Definition msp432p401r.h:730
EUSCI_B_SPI_Type::RXBUF
__I uint16_t RXBUF
Definition msp432p401r.h:832
TLV_Type::BCREV
__I uint32_t BCREV
Definition msp432p401r.h:1225
DIO_PORT_Even_Interruptable_Type::IV
__I uint16_t IV
Definition msp432p401r.h:697
FLCTL_Type::BANK0_MAIN_WEPROT
__IO uint32_t BANK0_MAIN_WEPROT
Definition msp432p401r.h:886
TLV_Type::ADC_OFFSET
__I uint32_t ADC_OFFSET
Definition msp432p401r.h:1258
TLV_Type::DCOIR_FCAL_RSEL5
__I uint32_t DCOIR_FCAL_RSEL5
Definition msp432p401r.h:1240
SYSCTL_Type::FLASH_SIZE
__I uint32_t FLASH_SIZE
Definition msp432p401r.h:1153
RTC_C_BCD_Type::TIM0
__IO uint16_t TIM0
Definition msp432p401r.h:1127
PCM_Type::IFG
__I uint32_t IFG
Definition msp432p401r.h:997
DIO_PORT_Not_Interruptable_Type::SEL0_L
__IO uint8_t SEL0_L
Definition msp432p401r.h:625
DIO_PORT_Even_Interruptable_Type::SEL1
__IO uint8_t SEL1
Definition msp432p401r.h:688
TLV_Type::WAFER_ID
__I uint32_t WAFER_ID
Definition msp432p401r.h:1231
CS_Type::IFG
__I uint32_t IFG
Definition msp432p401r.h:484
TLV_Type::REF_1P45V
__I uint32_t REF_1P45V
Definition msp432p401r.h:1284
SYSCTL_Boot_Type::RESET_STATOVER
__IO uint32_t RESET_STATOVER
Definition msp432p401r.h:1165
FLCTL_Type::PRGBRST_CTLSTAT
__IO uint32_t PRGBRST_CTLSTAT
Definition msp432p401r.h:863
FLCTL_Type::PRGBRST_DATA2_0
__IO uint32_t PRGBRST_DATA2_0
Definition msp432p401r.h:874
DIO_PORT_Odd_Interruptable_Type::SEL1
__IO uint8_t SEL1
Definition msp432p401r.h:660
RTC_C_Type::PS1CTL
__IO uint16_t PS1CTL
Definition msp432p401r.h:1107
DIO_PORT_Interruptable_Type::OUT
__IO uint16_t OUT
Definition msp432p401r.h:512
DIO_PORT_Interruptable_Type::SEL1
__IO uint16_t SEL1
Definition msp432p401r.h:547
TLV_Type::RESERVED10
__I uint32_t RESERVED10
Definition msp432p401r.h:1252
TLV_Type::BSL_PORTIF_CFG_UART
__I uint32_t BSL_PORTIF_CFG_UART
Definition msp432p401r.h:1299
DIO_PORT_Odd_Interruptable_Type::IFG
__IO uint8_t IFG
Definition msp432p401r.h:670
CRC32_Type::DIRB32
__IO uint16_t DIRB32
Definition msp432p401r.h:448
CRC32_Type::DI32
__IO uint16_t DI32
Definition msp432p401r.h:446
ADC14_Type::IER0
__IO uint32_t IER0
Definition msp432p401r.h:374
FLCTL_Type::BURSTPRG_TIMCTL
__I uint32_t BURSTPRG_TIMCTL
Definition msp432p401r.h:908
FLCTL_Type::RDBRST_STARTADDR
__IO uint32_t RDBRST_STARTADDR
Definition msp432p401r.h:856
AES256_Type::DOUT
__O uint16_t DOUT
Definition msp432p401r.h:398
TLV_Type::RANDOM_NUM_LEN
__I uint32_t RANDOM_NUM_LEN
Definition msp432p401r.h:1291
EUSCI_B_Type::TXBUF
__IO uint16_t TXBUF
Definition msp432p401r.h:806
RSTCTL_Type::RESET_REQ
__IO uint32_t RESET_REQ
Definition msp432p401r.h:1072
EUSCI_B_Type::ADDRX
__I uint16_t ADDRX
Definition msp432p401r.h:812
DIO_PORT_Not_Interruptable_Type::DS
__IO uint16_t DS
Definition msp432p401r.h:616
DIO_PORT_Interruptable_Type::IES
__IO uint16_t IES
Definition msp432p401r.h:563
DIO_PORT_Even_Interruptable_Type::IFG
__IO uint8_t IFG
Definition msp432p401r.h:696
DIO_PORT_Interruptable_Type::SEL0_L
__IO uint8_t SEL0_L
Definition msp432p401r.h:542
FLCTL_Type::SETIFG
__IO uint32_t SETIFG
Definition msp432p401r.h:899
FLCTL_Type::PRGBRST_DATA1_0
__IO uint32_t PRGBRST_DATA1_0
Definition msp432p401r.h:870
TLV_Type::RESERVED3
__I uint32_t RESERVED3
Definition msp432p401r.h:1241
ADC14_Type::LO0
__IO uint32_t LO0
Definition msp432p401r.h:367
AES256_Type::DIN
__O uint16_t DIN
Definition msp432p401r.h:397
FL_BOOTOVER_MAILBOX_Type::CMD
__IO uint32_t CMD
Definition msp432p401r.h:952
FL_BOOTOVER_MAILBOX_Type::MB_END
__IO uint32_t MB_END
Definition msp432p401r.h:981
FLCTL_Type::PRGBRST_DATA3_3
__IO uint32_t PRGBRST_DATA3_3
Definition msp432p401r.h:881
DIO_PORT_Not_Interruptable_Type::SELC_H
__IO uint8_t SELC_H
Definition msp432p401r.h:641
DIO_PORT_Interruptable_Type::DIR_H
__IO uint8_t DIR_H
Definition msp432p401r.h:522
DIO_PORT_Interruptable_Type::SELC
__IO uint16_t SELC
Definition msp432p401r.h:556
PCM_Type::IE
__IO uint32_t IE
Definition msp432p401r.h:996
DIO_PORT_Even_Interruptable_Type::DS
__IO uint8_t DS
Definition msp432p401r.h:684
DIO_PORT_Even_Interruptable_Type::IN
__I uint8_t IN
Definition msp432p401r.h:676
DIO_PORT_Interruptable_Type::SELC_L
__IO uint8_t SELC_L
Definition msp432p401r.h:558
ADC14_Type::CLRIFGR0
__O uint32_t CLRIFGR0
Definition msp432p401r.h:378
DIO_PORT_Odd_Interruptable_Type::SELC
__IO uint8_t SELC
Definition msp432p401r.h:664
RSTCTL_Type::HARDRESET_SET
__IO uint32_t HARDRESET_SET
Definition msp432p401r.h:1075
DMA_Channel_Type::INT1_SRCCFG
__IO uint32_t INT1_SRCCFG
Definition msp432p401r.h:715
RSTCTL_Type::HARDRESET_STAT
__I uint32_t HARDRESET_STAT
Definition msp432p401r.h:1073
TLV_Type::RESERVED12
__I uint32_t RESERVED12
Definition msp432p401r.h:1260
DIO_PORT_Not_Interruptable_Type::IN_L
__I uint8_t IN_L
Definition msp432p401r.h:590
CS_Type::STAT
__I uint32_t STAT
Definition msp432p401r.h:480
EUSCI_A_Type::IRCTL
__IO uint16_t IRCTL
Definition msp432p401r.h:763
DIO_PORT_Even_Interruptable_Type::IES
__IO uint8_t IES
Definition msp432p401r.h:692
TLV_Type::RESERVED6
__I uint32_t RESERVED6
Definition msp432p401r.h:1244
PSS_Type::KEY
__IO uint32_t KEY
Definition msp432p401r.h:1041
COMP_E_Type::CTL1
__IO uint16_t CTL1
Definition msp432p401r.h:428
EUSCI_B_Type::ADDMASK
__IO uint16_t ADDMASK
Definition msp432p401r.h:813
COMP_E_Type::CTL0
__IO uint16_t CTL0
Definition msp432p401r.h:427
TLV_Type::FLASH_INFO_TAG
__I uint32_t FLASH_INFO_TAG
Definition msp432p401r.h:1286
CRC32_Type::INIRES32_LO
__IO uint16_t INIRES32_LO
Definition msp432p401r.h:450
DIO_PORT_Not_Interruptable_Type::SEL1_H
__IO uint8_t SEL1_H
Definition msp432p401r.h:633
SYSCTL_Boot_Type::RESET_REQ
__IO uint32_t RESET_REQ
Definition msp432p401r.h:1164
TLV_Type::RESERVED11
__I uint32_t RESERVED11
Definition msp432p401r.h:1259
RSTCTL_Type::PSSRESET_STAT
__I uint32_t PSSRESET_STAT
Definition msp432p401r.h:1080
TLV_Type::DCOER_CONSTK_RSEL5
__I uint32_t DCOER_CONSTK_RSEL5
Definition msp432p401r.h:1254
FL_BOOTOVER_MAILBOX_Type::FACTORY_RESET_ENABLE
__IO uint32_t FACTORY_RESET_ENABLE
Definition msp432p401r.h:973
AES256_Type::CTL1
__IO uint16_t CTL1
Definition msp432p401r.h:394
EUSCI_A_Type::IE
__IO uint16_t IE
Definition msp432p401r.h:765
TLV_Type::TEST_RESULTS
__I uint32_t TEST_RESULTS
Definition msp432p401r.h:1236
FL_BOOTOVER_MAILBOX_Type::FACTORY_RESET_PARAMS_ACK
__IO uint32_t FACTORY_RESET_PARAMS_ACK
Definition msp432p401r.h:976
TLV_Type::RANDOM_NUM_3
__I uint32_t RANDOM_NUM_3
Definition msp432p401r.h:1294
DMA_Channel_Type::INT0_CLRFLG
__O uint32_t INT0_CLRFLG
Definition msp432p401r.h:720
EUSCI_A_SPI_Type::IFG
__IO uint16_t IFG
Definition msp432p401r.h:785
SEC_ZONE_UPDATE_Type::SEC_ZONE_PAYLOADLEN
__IO uint32_t SEC_ZONE_PAYLOADLEN
Definition msp432p401r.h:940
DIO_PORT_Interruptable_Type::IN_L
__I uint8_t IN_L
Definition msp432p401r.h:507
FLCTL_Type::PRGBRST_DATA0_2
__IO uint32_t PRGBRST_DATA0_2
Definition msp432p401r.h:868
DMA_Control_Type::ENACLR
__O uint32_t ENACLR
Definition msp432p401r.h:735
DIO_PORT_Not_Interruptable_Type::REN
__IO uint16_t REN
Definition msp432p401r.h:609
CRC32_Type::RESR32_HI
__IO uint16_t RESR32_HI
Definition msp432p401r.h:453
FL_BOOTOVER_MAILBOX_Type::BSL_ACK
__IO uint32_t BSL_ACK
Definition msp432p401r.h:965
ADC14_Type::CTL1
__IO uint32_t CTL1
Definition msp432p401r.h:366
DIO_PORT_Interruptable_Type::SEL1_L
__IO uint8_t SEL1_L
Definition msp432p401r.h:549
DIO_PORT_Interruptable_Type::IV_L
__I uint16_t IV_L
Definition msp432p401r.h:553
RSTCTL_Type::PCMRESET_STAT
__I uint32_t PCMRESET_STAT
Definition msp432p401r.h:1082
FLCTL_Type::PRGBRST_DATA2_3
__IO uint32_t PRGBRST_DATA2_3
Definition msp432p401r.h:877
DIO_PORT_Not_Interruptable_Type::IN
__I uint16_t IN
Definition msp432p401r.h:588
RTC_C_Type::AMINHR
__IO uint16_t AMINHR
Definition msp432p401r.h:1114
PCM_Type::CLRIFG
__O uint32_t CLRIFG
Definition msp432p401r.h:998
EUSCI_B_Type::BRW
__IO uint16_t BRW
Definition msp432p401r.h:802
DMA_Channel_Type::INT3_SRCCFG
__IO uint32_t INT3_SRCCFG
Definition msp432p401r.h:717
EUSCI_A_Type::CTLW1
__IO uint16_t CTLW1
Definition msp432p401r.h:755
FLCTL_Type::MASSERASE_TIMCTL
__I uint32_t MASSERASE_TIMCTL
Definition msp432p401r.h:907
EUSCI_B_Type::I2COA0
__IO uint16_t I2COA0
Definition msp432p401r.h:808
DIO_PORT_Interruptable_Type::DIR
__IO uint16_t DIR
Definition msp432p401r.h:519
TLV_Type::RESERVED14
__I uint32_t RESERVED14
Definition msp432p401r.h:1262
TLV_Type::RESERVED18
__I uint32_t RESERVED18
Definition msp432p401r.h:1266
TLV_Type::CS_CAL_TAG
__I uint32_t CS_CAL_TAG
Definition msp432p401r.h:1237
DIO_PORT_Odd_Interruptable_Type::SEL0
__IO uint8_t SEL0
Definition msp432p401r.h:658
TLV_Type::BSL_PORTIF_CFG_SPI
__I uint32_t BSL_PORTIF_CFG_SPI
Definition msp432p401r.h:1300
FL_BOOTOVER_MAILBOX_Type::FACTORY_RESET_PWDEN
__IO uint32_t FACTORY_RESET_PWDEN
Definition msp432p401r.h:974
EUSCI_A_SPI_Type::CTLW0
__IO uint16_t CTLW0
Definition msp432p401r.h:776
TLV_Type::RESERVED21
__I uint32_t RESERVED21
Definition msp432p401r.h:1269
TLV_Type::DCOER_FCAL_RSEL5
__I uint32_t DCOER_FCAL_RSEL5
Definition msp432p401r.h:1248
FLCTL_Type::PRGBRST_DATA2_1
__IO uint32_t PRGBRST_DATA2_1
Definition msp432p401r.h:875
TLV_Type::FLASH_INFO_LEN
__I uint32_t FLASH_INFO_LEN
Definition msp432p401r.h:1287
DMA_Channel_Type::SW_CHTRIG
__IO uint32_t SW_CHTRIG
Definition msp432p401r.h:711
EUSCI_A_Type::BRW
__IO uint16_t BRW
Definition msp432p401r.h:757
FL_BOOTOVER_MAILBOX_Type::MB_START
__IO uint32_t MB_START
Definition msp432p401r.h:951
CS_Type::CLRIFG
__O uint32_t CLRIFG
Definition msp432p401r.h:486
DIO_PORT_Even_Interruptable_Type::REN
__IO uint8_t REN
Definition msp432p401r.h:682
FLCTL_Type::PROGRAM_TIMCTL
__I uint32_t PROGRAM_TIMCTL
Definition msp432p401r.h:905
WDT_A_Type::CTL
__IO uint16_t CTL
Definition msp432p401r.h:1316
FL_BOOTOVER_MAILBOX_Type::JTAG_SWD_LOCK_ENCPAYLOADADD
__IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADADD
Definition msp432p401r.h:966
SEC_ZONE_PARAMS_Type::SEC_ZONE_ACK
__IO uint32_t SEC_ZONE_ACK
Definition msp432p401r.h:929
DIO_PORT_Not_Interruptable_Type::SEL1_L
__IO uint8_t SEL1_L
Definition msp432p401r.h:632
RTC_C_Type::BCD2BIN
__IO uint16_t BCD2BIN
Definition msp432p401r.h:1117
ADC14_Type::HI0
__IO uint32_t HI0
Definition msp432p401r.h:368
ADC14_Type::LO1
__IO uint32_t LO1
Definition msp432p401r.h:369
EUSCI_A_Type::ABCTL
__IO uint16_t ABCTL
Definition msp432p401r.h:762
SYSCTL_Type::SRAM_BANKEN
__IO uint32_t SRAM_BANKEN
Definition msp432p401r.h:1150
DIO_PORT_Not_Interruptable_Type::OUT_L
__IO uint8_t OUT_L
Definition msp432p401r.h:597
DMA_Control_Type::ALTCLR
__O uint32_t ALTCLR
Definition msp432p401r.h:737
FLCTL_Type::PRGBRST_DATA0_3
__IO uint32_t PRGBRST_DATA0_3
Definition msp432p401r.h:869
RTC_C_BCD_Type::ADOWDAY
__IO uint16_t ADOWDAY
Definition msp432p401r.h:1132
FL_BOOTOVER_MAILBOX_Type::FACTORY_RESET_ACK
__IO uint32_t FACTORY_RESET_ACK
Definition msp432p401r.h:979
FLCTL_Type::BANK1_MAIN_WEPROT
__IO uint32_t BANK1_MAIN_WEPROT
Definition msp432p401r.h:889
EUSCI_A_Type::RXBUF
__I uint16_t RXBUF
Definition msp432p401r.h:760
DIO_PORT_Odd_Interruptable_Type::IES
__IO uint8_t IES
Definition msp432p401r.h:666
DIO_PORT_Even_Interruptable_Type::IE
__IO uint8_t IE
Definition msp432p401r.h:694
TLV_Type::REF_CAL_LEN
__I uint32_t REF_CAL_LEN
Definition msp432p401r.h:1282
TLV_Type::RESERVED1
__I uint32_t RESERVED1
Definition msp432p401r.h:1234
EUSCI_B_Type::CTLW1
__IO uint16_t CTLW1
Definition msp432p401r.h:800
DMA_Control_Type::STAT
__I uint32_t STAT
Definition msp432p401r.h:724
TLV_Type::RESERVED15
__I uint32_t RESERVED15
Definition msp432p401r.h:1263
CAPTIO_Type::CTL
__IO uint16_t CTL
Definition msp432p401r.h:414
DIO_PORT_Interruptable_Type::IFG_L
__IO uint8_t IFG_L
Definition msp432p401r.h:579
RSTCTL_Type::PCMRESET_CLR
__IO uint32_t PCMRESET_CLR
Definition msp432p401r.h:1083
DIO_PORT_Not_Interruptable_Type::OUT_H
__IO uint8_t OUT_H
Definition msp432p401r.h:598
ADC14_Type
Definition msp432p401r.h:364
AES256_Type
Definition msp432p401r.h:392
CAPTIO_Type
Definition msp432p401r.h:412
COMP_E_Type
Definition msp432p401r.h:426
CRC32_Type
Definition msp432p401r.h:445
CS_Type
Definition msp432p401r.h:472
DIO_PORT_Even_Interruptable_Type
Definition msp432p401r.h:674
DIO_PORT_Interruptable_Type
Definition msp432p401r.h:503
DIO_PORT_Not_Interruptable_Type
Definition msp432p401r.h:586
DIO_PORT_Odd_Interruptable_Type
Definition msp432p401r.h:647
DMA_Channel_Type
Definition msp432p401r.h:709
DMA_Control_Type
Definition msp432p401r.h:723
EUSCI_A_SPI_Type
Definition msp432p401r.h:775
EUSCI_A_Type
Definition msp432p401r.h:753
EUSCI_B_SPI_Type
Definition msp432p401r.h:826
EUSCI_B_Type
Definition msp432p401r.h:798
FLCTL_Type
Definition msp432p401r.h:849
FL_BOOTOVER_MAILBOX_Type
Definition msp432p401r.h:950
PCM_Type
Definition msp432p401r.h:993
PMAP_COMMON_Type
Definition msp432p401r.h:1010
PMAP_REGISTER_Type
Definition msp432p401r.h:1015
PSS_Type
Definition msp432p401r.h:1040
REF_A_Type
Definition msp432p401r.h:1058
RSTCTL_Type
Definition msp432p401r.h:1071
RTC_C_BCD_Type
Definition msp432p401r.h:1125
RTC_C_Type
Definition msp432p401r.h:1101
SEC_ZONE_PARAMS_Type
Definition msp432p401r.h:920
SEC_ZONE_UPDATE_Type
Definition msp432p401r.h:938
SYSCTL_Boot_Type
Definition msp432p401r.h:1160
SYSCTL_Type
Definition msp432p401r.h:1144
TLV_Type
Definition msp432p401r.h:1219
Timer32_Type
Definition msp432p401r.h:1179
Timer_A_Type
Definition msp432p401r.h:1198
WDT_A_Type
Definition msp432p401r.h:1314
system_msp432p401r.h
CMSIS Cortex-M4F Device Peripheral Access Layer Header File for MSP432P401R.
Generated by doxygen 1.12.0