YAHAL
Yet Another Hardware Abstraction Library
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cmsis_armcc.h
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1/**************************************************************************/
7/*
8 * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25#ifndef __CMSIS_ARMCC_H
26#define __CMSIS_ARMCC_H
27
28
29#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
30 #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
31#endif
32
33/* CMSIS compiler control architecture macros */
34#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
35 (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
36 #define __ARM_ARCH_6M__ 1
37#endif
38
39#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
40 #define __ARM_ARCH_7M__ 1
41#endif
42
43#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
44 #define __ARM_ARCH_7EM__ 1
45#endif
46
47 /* __ARM_ARCH_8M_BASE__ not applicable */
48 /* __ARM_ARCH_8M_MAIN__ not applicable */
49 /* __ARM_ARCH_8_1M_MAIN__ not applicable */
50
51/* CMSIS compiler control DSP macros */
52#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
53 #define __ARM_FEATURE_DSP 1
54#endif
55
56/* CMSIS compiler specific defines */
57#ifndef __ASM
58 #define __ASM __asm
59#endif
60#ifndef __INLINE
61 #define __INLINE __inline
62#endif
63#ifndef __STATIC_INLINE
64 #define __STATIC_INLINE static __inline
65#endif
66#ifndef __STATIC_FORCEINLINE
67 #define __STATIC_FORCEINLINE static __forceinline
68#endif
69#ifndef __NO_RETURN
70 #define __NO_RETURN __declspec(noreturn)
71#endif
72#ifndef __USED
73 #define __USED __attribute__((used))
74#endif
75#ifndef __WEAK
76 #define __WEAK __attribute__((weak))
77#endif
78#ifndef __PACKED
79 #define __PACKED __attribute__((packed))
80#endif
81#ifndef __PACKED_STRUCT
82 #define __PACKED_STRUCT __packed struct
83#endif
84#ifndef __PACKED_UNION
85 #define __PACKED_UNION __packed union
86#endif
87#ifndef __UNALIGNED_UINT32 /* deprecated */
88 #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
89#endif
90#ifndef __UNALIGNED_UINT16_WRITE
91 #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
92#endif
93#ifndef __UNALIGNED_UINT16_READ
94 #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
95#endif
96#ifndef __UNALIGNED_UINT32_WRITE
97 #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
98#endif
99#ifndef __UNALIGNED_UINT32_READ
100 #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
101#endif
102#ifndef __ALIGNED
103 #define __ALIGNED(x) __attribute__((aligned(x)))
104#endif
105#ifndef __RESTRICT
106 #define __RESTRICT __restrict
107#endif
108#ifndef __COMPILER_BARRIER
109 #define __COMPILER_BARRIER() __memory_changed()
110#endif
111#ifndef __NO_INIT
112 #define __NO_INIT __attribute__ ((section (".bss.noinit"), zero_init))
113#endif
114#ifndef __ALIAS
115 #define __ALIAS(x) __attribute__ ((alias(x)))
116#endif
117
118/* ######################### Startup and Lowlevel Init ######################## */
119
120#ifndef __PROGRAM_START
121#define __PROGRAM_START __main
122#endif
123
124#ifndef __INITIAL_SP
125#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
126#endif
127
128#ifndef __STACK_LIMIT
129#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
130#endif
131
132#ifndef __VECTOR_TABLE
133#define __VECTOR_TABLE __Vectors
134#endif
135
136#ifndef __VECTOR_TABLE_ATTRIBUTE
137#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
138#endif
139
140/* ########################## Core Instruction Access ######################### */
150#define __NOP __nop
151
152
157#define __WFI __wfi
158
159
165#define __WFE __wfe
166
167
172#define __SEV __sev
173
174
181#define __ISB() __isb(0xF)
182
188#define __DSB() __dsb(0xF)
189
195#define __DMB() __dmb(0xF)
196
197
204#define __REV __rev
205
206
213#ifndef __NO_EMBEDDED_ASM
214__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
215{
216 rev16 r0, r0
217 bx lr
218}
219#endif
220
221
228#ifndef __NO_EMBEDDED_ASM
229__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
230{
231 revsh r0, r0
232 bx lr
233}
234#endif
235
236
244#define __ROR __ror
245
246
254#define __BKPT(value) __breakpoint(value)
255
256
263#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
264 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
265 #define __RBIT __rbit
266#else
267__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
268{
269 uint32_t result;
270 uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
271
272 result = value; /* r will be reversed bits of v; first get LSB of v */
273 for (value >>= 1U; value != 0U; value >>= 1U)
274 {
275 result <<= 1U;
276 result |= value & 1U;
277 s--;
278 }
279 result <<= s; /* shift when v's highest bits are zero */
280 return result;
281}
282#endif
283
284
291#define __CLZ __clz
292
293
294#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
295 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
296
303#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
304 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
305#else
306 #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
307#endif
308
309
316#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
317 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
318#else
319 #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
320#endif
321
322
329#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
330 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
331#else
332 #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
333#endif
334
335
344#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
345 #define __STREXB(value, ptr) __strex(value, ptr)
346#else
347 #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
348#endif
349
350
359#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
360 #define __STREXH(value, ptr) __strex(value, ptr)
361#else
362 #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
363#endif
364
365
374#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
375 #define __STREXW(value, ptr) __strex(value, ptr)
376#else
377 #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
378#endif
379
380
385#define __CLREX __clrex
386
387
395#define __SSAT __ssat
396
397
405#define __USAT __usat
406
407
415#ifndef __NO_EMBEDDED_ASM
416__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
417{
418 rrx r0, r0
419 bx lr
420}
421#endif
422
423
430#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
431
432
439#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
440
441
448#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
449
450
457#define __STRBT(value, ptr) __strt(value, ptr)
458
459
466#define __STRHT(value, ptr) __strt(value, ptr)
467
468
475#define __STRT(value, ptr) __strt(value, ptr)
476
477#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
478 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
479
487__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
488{
489 if ((sat >= 1U) && (sat <= 32U))
490 {
491 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
492 const int32_t min = -1 - max ;
493 if (val > max)
494 {
495 return max;
496 }
497 else if (val < min)
498 {
499 return min;
500 }
501 }
502 return val;
503}
504
512__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
513{
514 if (sat <= 31U)
515 {
516 const uint32_t max = ((1U << sat) - 1U);
517 if (val > (int32_t)max)
518 {
519 return max;
520 }
521 else if (val < 0)
522 {
523 return 0U;
524 }
525 }
526 return (uint32_t)val;
527}
528
529#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
530 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
531 /* end of group CMSIS_Core_InstructionInterface */
533
534
535/* ########################### Core Function Access ########################### */
546/* intrinsic void __enable_irq(); */
547
548
554/* intrinsic void __disable_irq(); */
555
561__STATIC_INLINE uint32_t __get_CONTROL(void)
562{
563 register uint32_t __regControl __ASM("control");
564 return(__regControl);
565}
566
567
573__STATIC_INLINE void __set_CONTROL(uint32_t control)
574{
575 register uint32_t __regControl __ASM("control");
576 __regControl = control;
577 __ISB();
578}
579
580
586__STATIC_INLINE uint32_t __get_IPSR(void)
587{
588 register uint32_t __regIPSR __ASM("ipsr");
589 return(__regIPSR);
590}
591
592
598__STATIC_INLINE uint32_t __get_APSR(void)
599{
600 register uint32_t __regAPSR __ASM("apsr");
601 return(__regAPSR);
602}
603
604
610__STATIC_INLINE uint32_t __get_xPSR(void)
611{
612 register uint32_t __regXPSR __ASM("xpsr");
613 return(__regXPSR);
614}
615
616
622__STATIC_INLINE uint32_t __get_PSP(void)
623{
624 register uint32_t __regProcessStackPointer __ASM("psp");
625 return(__regProcessStackPointer);
626}
627
628
634__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
635{
636 register uint32_t __regProcessStackPointer __ASM("psp");
637 __regProcessStackPointer = topOfProcStack;
638}
639
640
646__STATIC_INLINE uint32_t __get_MSP(void)
647{
648 register uint32_t __regMainStackPointer __ASM("msp");
649 return(__regMainStackPointer);
650}
651
652
658__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
659{
660 register uint32_t __regMainStackPointer __ASM("msp");
661 __regMainStackPointer = topOfMainStack;
662}
663
664
670__STATIC_INLINE uint32_t __get_PRIMASK(void)
671{
672 register uint32_t __regPriMask __ASM("primask");
673 return(__regPriMask);
674}
675
676
682__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
683{
684 register uint32_t __regPriMask __ASM("primask");
685 __regPriMask = (priMask);
686}
687
688
689#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
690 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
691
697#define __enable_fault_irq __enable_fiq
698
699
705#define __disable_fault_irq __disable_fiq
706
707
713__STATIC_INLINE uint32_t __get_BASEPRI(void)
714{
715 register uint32_t __regBasePri __ASM("basepri");
716 return(__regBasePri);
717}
718
719
725__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
726{
727 register uint32_t __regBasePri __ASM("basepri");
728 __regBasePri = (basePri & 0xFFU);
729}
730
731
738__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
739{
740 register uint32_t __regBasePriMax __ASM("basepri_max");
741 __regBasePriMax = (basePri & 0xFFU);
742}
743
744
750__STATIC_INLINE uint32_t __get_FAULTMASK(void)
751{
752 register uint32_t __regFaultMask __ASM("faultmask");
753 return(__regFaultMask);
754}
755
756
762__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
763{
764 register uint32_t __regFaultMask __ASM("faultmask");
765 __regFaultMask = (faultMask & (uint32_t)1U);
766}
767
768#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
769 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
770
771
777__STATIC_INLINE uint32_t __get_FPSCR(void)
778{
779#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
780 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
781 register uint32_t __regfpscr __ASM("fpscr");
782 return(__regfpscr);
783#else
784 return(0U);
785#endif
786}
787
788
794__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
795{
796#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
797 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
798 register uint32_t __regfpscr __ASM("fpscr");
799 __regfpscr = (fpscr);
800#else
801 (void)fpscr;
802#endif
803}
804
805
809/* ################### Compiler specific Intrinsics ########################### */
815#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
816
817#define __SADD8 __sadd8
818#define __QADD8 __qadd8
819#define __SHADD8 __shadd8
820#define __UADD8 __uadd8
821#define __UQADD8 __uqadd8
822#define __UHADD8 __uhadd8
823#define __SSUB8 __ssub8
824#define __QSUB8 __qsub8
825#define __SHSUB8 __shsub8
826#define __USUB8 __usub8
827#define __UQSUB8 __uqsub8
828#define __UHSUB8 __uhsub8
829#define __SADD16 __sadd16
830#define __QADD16 __qadd16
831#define __SHADD16 __shadd16
832#define __UADD16 __uadd16
833#define __UQADD16 __uqadd16
834#define __UHADD16 __uhadd16
835#define __SSUB16 __ssub16
836#define __QSUB16 __qsub16
837#define __SHSUB16 __shsub16
838#define __USUB16 __usub16
839#define __UQSUB16 __uqsub16
840#define __UHSUB16 __uhsub16
841#define __SASX __sasx
842#define __QASX __qasx
843#define __SHASX __shasx
844#define __UASX __uasx
845#define __UQASX __uqasx
846#define __UHASX __uhasx
847#define __SSAX __ssax
848#define __QSAX __qsax
849#define __SHSAX __shsax
850#define __USAX __usax
851#define __UQSAX __uqsax
852#define __UHSAX __uhsax
853#define __USAD8 __usad8
854#define __USADA8 __usada8
855#define __SSAT16 __ssat16
856#define __USAT16 __usat16
857#define __UXTB16 __uxtb16
858#define __UXTAB16 __uxtab16
859#define __SXTB16 __sxtb16
860#define __SXTAB16 __sxtab16
861#define __SMUAD __smuad
862#define __SMUADX __smuadx
863#define __SMLAD __smlad
864#define __SMLADX __smladx
865#define __SMLALD __smlald
866#define __SMLALDX __smlaldx
867#define __SMUSD __smusd
868#define __SMUSDX __smusdx
869#define __SMLSD __smlsd
870#define __SMLSDX __smlsdx
871#define __SMLSLD __smlsld
872#define __SMLSLDX __smlsldx
873#define __SEL __sel
874#define __QADD __qadd
875#define __QSUB __qsub
876
877#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
878 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
879
880#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
881 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
882
883#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
884 ((int64_t)(ARG3) << 32U) ) >> 32U))
885
886#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
887
888#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
889
890#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
894#endif /* __CMSIS_ARMCC_H */
__ISB
#define __ISB()
Instruction Synchronization Barrier.
Definition cmsis_armcc.h:181
__SSAT
__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
Signed Saturate.
Definition cmsis_armclang.h:533
__USAT
__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
Unsigned Saturate.
Definition cmsis_armclang.h:558
__RBIT
#define __RBIT
Reverse bit order of value.
Definition cmsis_armclang.h:294
__REV16
#define __REV16(value)
Reverse byte order (16 bit)
Definition cmsis_armclang.h:248
__REVSH
#define __REVSH(value)
Reverse byte order (16 bit)
Definition cmsis_armclang.h:257
__set_CONTROL
__STATIC_INLINE void __set_CONTROL(uint32_t control)
Set Control Register.
Definition cmsis_armcc.h:573
__set_MSP
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
Set Main Stack Pointer.
Definition cmsis_armcc.h:658
__set_PSP
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Set Process Stack Pointer.
Definition cmsis_armcc.h:634
__get_PRIMASK
__STATIC_INLINE uint32_t __get_PRIMASK(void)
Get Priority Mask.
Definition cmsis_armcc.h:670
__get_MSP
__STATIC_INLINE uint32_t __get_MSP(void)
Get Main Stack Pointer.
Definition cmsis_armcc.h:646
__get_FPSCR
__STATIC_INLINE uint32_t __get_FPSCR(void)
Get FPSCR.
Definition cmsis_armcc.h:777
__get_CONTROL
__STATIC_INLINE uint32_t __get_CONTROL(void)
Enable IRQ Interrupts.
Definition cmsis_armcc.h:561
__get_PSP
__STATIC_INLINE uint32_t __get_PSP(void)
Get Process Stack Pointer.
Definition cmsis_armcc.h:622
__get_xPSR
__STATIC_INLINE uint32_t __get_xPSR(void)
Get xPSR Register.
Definition cmsis_armcc.h:610
__set_FPSCR
#define __set_FPSCR(fpscr)
Set FPSCR.
Definition cmsis_armclang.h:1413
__get_APSR
__STATIC_INLINE uint32_t __get_APSR(void)
Get APSR Register.
Definition cmsis_armcc.h:598
__get_IPSR
__STATIC_INLINE uint32_t __get_IPSR(void)
Get IPSR Register.
Definition cmsis_armcc.h:586
__set_PRIMASK
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
Set Priority Mask.
Definition cmsis_armcc.h:682
__attribute__
void __attribute__((noreturn))(*rom_reset_usb_boot_fn)(uint32_t
Reboot the device into BOOTSEL mode.
Definition bootrom.h:66
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