YAHAL
Yet Another Hardware Abstraction Library
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cmsis_iccarm.h
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1/**************************************************************************/
8//------------------------------------------------------------------------------
9//
10// Copyright (c) 2017-2021 IAR Systems
11// Copyright (c) 2017-2023 Arm Limited. All rights reserved.
12//
13// SPDX-License-Identifier: Apache-2.0
14//
15// Licensed under the Apache License, Version 2.0 (the "License")
16// you may not use this file except in compliance with the License.
17// You may obtain a copy of the License at
18// http://www.apache.org/licenses/LICENSE-2.0
19//
20// Unless required by applicable law or agreed to in writing, software
21// distributed under the License is distributed on an "AS IS" BASIS,
22// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23// See the License for the specific language governing permissions and
24// limitations under the License.
25//
26//------------------------------------------------------------------------------
27
28
29#ifndef __CMSIS_ICCARM_H__
30#define __CMSIS_ICCARM_H__
31
32#ifndef __ICCARM__
33 #error This file should only be compiled by ICCARM
34#endif
35
36#pragma system_include
37
38#define __IAR_FT _Pragma("inline=forced") __intrinsic
39
40#if (__VER__ >= 8000000)
41 #define __ICCARM_V8 1
42#else
43 #define __ICCARM_V8 0
44#endif
45
46#ifndef __ALIGNED
47 #if __ICCARM_V8
48 #define __ALIGNED(x) __attribute__((aligned(x)))
49 #elif (__VER__ >= 7080000)
50 /* Needs IAR language extensions */
51 #define __ALIGNED(x) __attribute__((aligned(x)))
52 #else
53 #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
54 #define __ALIGNED(x)
55 #endif
56#endif
57
58
59/* Define compiler macros for CPU architecture, used in CMSIS 5.
60 */
61#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
62/* Macros already defined */
63#else
64 #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
65 #define __ARM_ARCH_8M_MAIN__ 1
66 #elif defined(__ARM8M_BASELINE__)
67 #define __ARM_ARCH_8M_BASE__ 1
68 #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
69 #if __ARM_ARCH == 6
70 #define __ARM_ARCH_6M__ 1
71 #elif __ARM_ARCH == 7
72 #if __ARM_FEATURE_DSP
73 #define __ARM_ARCH_7EM__ 1
74 #else
75 #define __ARM_ARCH_7M__ 1
76 #endif
77 #endif /* __ARM_ARCH */
78 #endif /* __ARM_ARCH_PROFILE == 'M' */
79#endif
80
81/* Alternativ core deduction for older ICCARM's */
82#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
83 !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
84 #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
85 #define __ARM_ARCH_6M__ 1
86 #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
87 #define __ARM_ARCH_7M__ 1
88 #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
89 #define __ARM_ARCH_7EM__ 1
90 #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
91 #define __ARM_ARCH_8M_BASE__ 1
92 #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
93 #define __ARM_ARCH_8M_MAIN__ 1
94 #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
95 #define __ARM_ARCH_8M_MAIN__ 1
96 #else
97 #error "Unknown target."
98 #endif
99#endif
100
101
102
103#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
104 #define __IAR_M0_FAMILY 1
105#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
106 #define __IAR_M0_FAMILY 1
107#else
108 #define __IAR_M0_FAMILY 0
109#endif
110
111#ifndef __NO_INIT
112 #define __NO_INIT __attribute__ ((section (".noinit")))
113#endif
114#ifndef __ALIAS
115 #define __ALIAS(x) __attribute__ ((alias(x)))
116#endif
117
118#ifndef __ASM
119 #define __ASM __asm
120#endif
121
122#ifndef __COMPILER_BARRIER
123 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
124#endif
125
126#ifndef __INLINE
127 #define __INLINE inline
128#endif
129
130#ifndef __NO_RETURN
131 #if __ICCARM_V8
132 #define __NO_RETURN __attribute__((__noreturn__))
133 #else
134 #define __NO_RETURN _Pragma("object_attribute=__noreturn")
135 #endif
136#endif
137
138#ifndef __PACKED
139 #if __ICCARM_V8
140 #define __PACKED __attribute__((packed, aligned(1)))
141 #else
142 /* Needs IAR language extensions */
143 #define __PACKED __packed
144 #endif
145#endif
146
147#ifndef __PACKED_STRUCT
148 #if __ICCARM_V8
149 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
150 #else
151 /* Needs IAR language extensions */
152 #define __PACKED_STRUCT __packed struct
153 #endif
154#endif
155
156#ifndef __PACKED_UNION
157 #if __ICCARM_V8
158 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
159 #else
160 /* Needs IAR language extensions */
161 #define __PACKED_UNION __packed union
162 #endif
163#endif
164
165#ifndef __RESTRICT
166 #if __ICCARM_V8
167 #define __RESTRICT __restrict
168 #else
169 /* Needs IAR language extensions */
170 #define __RESTRICT restrict
171 #endif
172#endif
173
174#ifndef __STATIC_INLINE
175 #define __STATIC_INLINE static inline
176#endif
177
178#ifndef __FORCEINLINE
179 #define __FORCEINLINE _Pragma("inline=forced")
180#endif
181
182#ifndef __STATIC_FORCEINLINE
183 #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
184#endif
185
186#ifndef __UNALIGNED_UINT16_READ
187#pragma language=save
188#pragma language=extended
189__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
190{
191 return *(__packed uint16_t*)(ptr);
192}
193#pragma language=restore
194#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
195#endif
196
197
198#ifndef __UNALIGNED_UINT16_WRITE
199#pragma language=save
200#pragma language=extended
201__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
202{
203 *(__packed uint16_t*)(ptr) = val;;
204}
205#pragma language=restore
206#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
207#endif
208
209#ifndef __UNALIGNED_UINT32_READ
210#pragma language=save
211#pragma language=extended
212__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
213{
214 return *(__packed uint32_t*)(ptr);
215}
216#pragma language=restore
217#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
218#endif
219
220#ifndef __UNALIGNED_UINT32_WRITE
221#pragma language=save
222#pragma language=extended
223__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
224{
225 *(__packed uint32_t*)(ptr) = val;;
226}
227#pragma language=restore
228#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
229#endif
230
231#ifndef __UNALIGNED_UINT32 /* deprecated */
232#pragma language=save
233#pragma language=extended
234__packed struct __iar_u32 { uint32_t v; };
235#pragma language=restore
236#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
237#endif
238
239#ifndef __USED
240 #if __ICCARM_V8
241 #define __USED __attribute__((used))
242 #else
243 #define __USED _Pragma("__root")
244 #endif
245#endif
246
247#undef __WEAK /* undo the definition from DLib_Defaults.h */
248#ifndef __WEAK
249 #if __ICCARM_V8
250 #define __WEAK __attribute__((weak))
251 #else
252 #define __WEAK _Pragma("__weak")
253 #endif
254#endif
255
256#ifndef __PROGRAM_START
257#define __PROGRAM_START __iar_program_start
258#endif
259
260#ifndef __INITIAL_SP
261#define __INITIAL_SP CSTACK$$Limit
262#endif
263
264#ifndef __STACK_LIMIT
265#define __STACK_LIMIT CSTACK$$Base
266#endif
267
268#ifndef __VECTOR_TABLE
269#define __VECTOR_TABLE __vector_table
270#endif
271
272#ifndef __VECTOR_TABLE_ATTRIBUTE
273#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
274#endif
275
276#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
277#ifndef __STACK_SEAL
278#define __STACK_SEAL STACKSEAL$$Base
279#endif
280
281#ifndef __TZ_STACK_SEAL_SIZE
282#define __TZ_STACK_SEAL_SIZE 8U
283#endif
284
285#ifndef __TZ_STACK_SEAL_VALUE
286#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
287#endif
288
289__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
290 *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
291}
292#endif
293
294#ifndef __ICCARM_INTRINSICS_VERSION__
295 #define __ICCARM_INTRINSICS_VERSION__ 0
296#endif
297
298#if __ICCARM_INTRINSICS_VERSION__ == 2
299
300 #if defined(__CLZ)
301 #undef __CLZ
302 #endif
303 #if defined(__REVSH)
304 #undef __REVSH
305 #endif
306 #if defined(__RBIT)
307 #undef __RBIT
308 #endif
309 #if defined(__SSAT)
310 #undef __SSAT
311 #endif
312 #if defined(__USAT)
313 #undef __USAT
314 #endif
315
316 #include "iccarm_builtin.h"
317
318 #define __disable_fault_irq __iar_builtin_disable_fiq
319 #define __disable_irq __iar_builtin_disable_interrupt
320 #define __enable_fault_irq __iar_builtin_enable_fiq
321 #define __enable_irq __iar_builtin_enable_interrupt
322 #define __arm_rsr __iar_builtin_rsr
323 #define __arm_wsr __iar_builtin_wsr
324
325
326 #define __get_APSR() (__arm_rsr("APSR"))
327 #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
328 #define __get_CONTROL() (__arm_rsr("CONTROL"))
329 #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
330
331 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
332 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
333 #define __get_FPSCR() (__arm_rsr("FPSCR"))
334 #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
335 #else
336 #define __get_FPSCR() ( 0 )
337 #define __set_FPSCR(VALUE) ((void)VALUE)
338 #endif
339
340 #define __get_IPSR() (__arm_rsr("IPSR"))
341 #define __get_MSP() (__arm_rsr("MSP"))
342 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
343 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
344 // without main extensions, the non-secure MSPLIM is RAZ/WI
345 #define __get_MSPLIM() (0U)
346 #else
347 #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
348 #endif
349 #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
350 #define __get_PSP() (__arm_rsr("PSP"))
351
352 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
353 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
354 // without main extensions, the non-secure PSPLIM is RAZ/WI
355 #define __get_PSPLIM() (0U)
356 #else
357 #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
358 #endif
359
360 #define __get_xPSR() (__arm_rsr("xPSR"))
361
362 #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
363 #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
364
365__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
366{
367 __arm_wsr("CONTROL", control);
368 __iar_builtin_ISB();
369}
370
371 #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
372 #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
373
374 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
375 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
376 // without main extensions, the non-secure MSPLIM is RAZ/WI
377 #define __set_MSPLIM(VALUE) ((void)(VALUE))
378 #else
379 #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
380 #endif
381 #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
382 #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
383 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
384 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
385 // without main extensions, the non-secure PSPLIM is RAZ/WI
386 #define __set_PSPLIM(VALUE) ((void)(VALUE))
387 #else
388 #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
389 #endif
390
391 #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
392
393__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
394{
395 __arm_wsr("CONTROL_NS", control);
396 __iar_builtin_ISB();
397}
398
399 #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
400 #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
401 #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
402 #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
403 #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
404 #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
405 #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
406 #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
407 #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
408 #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
409 #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
410 #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
411
412 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
413 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
414 // without main extensions, the non-secure PSPLIM is RAZ/WI
415 #define __TZ_get_PSPLIM_NS() (0U)
416 #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
417 #else
418 #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
419 #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
420 #endif
421
422 #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
423 #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
424
425 #define __NOP __iar_builtin_no_operation
426
427 #define __CLZ __iar_builtin_CLZ
428 #define __CLREX __iar_builtin_CLREX
429
430 #define __DMB __iar_builtin_DMB
431 #define __DSB __iar_builtin_DSB
432 #define __ISB __iar_builtin_ISB
433
434 #define __LDREXB __iar_builtin_LDREXB
435 #define __LDREXH __iar_builtin_LDREXH
436 #define __LDREXW __iar_builtin_LDREX
437
438 #define __RBIT __iar_builtin_RBIT
439 #define __REV __iar_builtin_REV
440 #define __REV16 __iar_builtin_REV16
441
442 __IAR_FT int16_t __REVSH(int16_t val)
443 {
444 return (int16_t) __iar_builtin_REVSH(val);
445 }
446
447 #define __ROR __iar_builtin_ROR
448 #define __RRX __iar_builtin_RRX
449
450 #define __SEV __iar_builtin_SEV
451
452 #if !__IAR_M0_FAMILY
453 #define __SSAT __iar_builtin_SSAT
454 #endif
455
456 #define __STREXB __iar_builtin_STREXB
457 #define __STREXH __iar_builtin_STREXH
458 #define __STREXW __iar_builtin_STREX
459
460 #if !__IAR_M0_FAMILY
461 #define __USAT __iar_builtin_USAT
462 #endif
463
464 #define __WFE __iar_builtin_WFE
465 #define __WFI __iar_builtin_WFI
466
467 #if __ARM_MEDIA__
468 #define __SADD8 __iar_builtin_SADD8
469 #define __QADD8 __iar_builtin_QADD8
470 #define __SHADD8 __iar_builtin_SHADD8
471 #define __UADD8 __iar_builtin_UADD8
472 #define __UQADD8 __iar_builtin_UQADD8
473 #define __UHADD8 __iar_builtin_UHADD8
474 #define __SSUB8 __iar_builtin_SSUB8
475 #define __QSUB8 __iar_builtin_QSUB8
476 #define __SHSUB8 __iar_builtin_SHSUB8
477 #define __USUB8 __iar_builtin_USUB8
478 #define __UQSUB8 __iar_builtin_UQSUB8
479 #define __UHSUB8 __iar_builtin_UHSUB8
480 #define __SADD16 __iar_builtin_SADD16
481 #define __QADD16 __iar_builtin_QADD16
482 #define __SHADD16 __iar_builtin_SHADD16
483 #define __UADD16 __iar_builtin_UADD16
484 #define __UQADD16 __iar_builtin_UQADD16
485 #define __UHADD16 __iar_builtin_UHADD16
486 #define __SSUB16 __iar_builtin_SSUB16
487 #define __QSUB16 __iar_builtin_QSUB16
488 #define __SHSUB16 __iar_builtin_SHSUB16
489 #define __USUB16 __iar_builtin_USUB16
490 #define __UQSUB16 __iar_builtin_UQSUB16
491 #define __UHSUB16 __iar_builtin_UHSUB16
492 #define __SASX __iar_builtin_SASX
493 #define __QASX __iar_builtin_QASX
494 #define __SHASX __iar_builtin_SHASX
495 #define __UASX __iar_builtin_UASX
496 #define __UQASX __iar_builtin_UQASX
497 #define __UHASX __iar_builtin_UHASX
498 #define __SSAX __iar_builtin_SSAX
499 #define __QSAX __iar_builtin_QSAX
500 #define __SHSAX __iar_builtin_SHSAX
501 #define __USAX __iar_builtin_USAX
502 #define __UQSAX __iar_builtin_UQSAX
503 #define __UHSAX __iar_builtin_UHSAX
504 #define __USAD8 __iar_builtin_USAD8
505 #define __USADA8 __iar_builtin_USADA8
506 #define __SSAT16 __iar_builtin_SSAT16
507 #define __USAT16 __iar_builtin_USAT16
508 #define __UXTB16 __iar_builtin_UXTB16
509 #define __UXTAB16 __iar_builtin_UXTAB16
510 #define __SXTB16 __iar_builtin_SXTB16
511 #define __SXTAB16 __iar_builtin_SXTAB16
512 #define __SMUAD __iar_builtin_SMUAD
513 #define __SMUADX __iar_builtin_SMUADX
514 #define __SMMLA __iar_builtin_SMMLA
515 #define __SMLAD __iar_builtin_SMLAD
516 #define __SMLADX __iar_builtin_SMLADX
517 #define __SMLALD __iar_builtin_SMLALD
518 #define __SMLALDX __iar_builtin_SMLALDX
519 #define __SMUSD __iar_builtin_SMUSD
520 #define __SMUSDX __iar_builtin_SMUSDX
521 #define __SMLSD __iar_builtin_SMLSD
522 #define __SMLSDX __iar_builtin_SMLSDX
523 #define __SMLSLD __iar_builtin_SMLSLD
524 #define __SMLSLDX __iar_builtin_SMLSLDX
525 #define __SEL __iar_builtin_SEL
526 #define __QADD __iar_builtin_QADD
527 #define __QSUB __iar_builtin_QSUB
528 #define __PKHBT __iar_builtin_PKHBT
529 #define __PKHTB __iar_builtin_PKHTB
530 #endif
531
532#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
533
534 #if __IAR_M0_FAMILY
535 /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
536 #define __CLZ __cmsis_iar_clz_not_active
537 #define __SSAT __cmsis_iar_ssat_not_active
538 #define __USAT __cmsis_iar_usat_not_active
539 #define __RBIT __cmsis_iar_rbit_not_active
540 #define __get_APSR __cmsis_iar_get_APSR_not_active
541 #endif
542
543
544 #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
545 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
546 #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
547 #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
548 #endif
549
550 #ifdef __INTRINSICS_INCLUDED
551 #error intrinsics.h is already included previously!
552 #endif
553
554 #include <intrinsics.h>
555
556 #if __IAR_M0_FAMILY
557 /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
558 #undef __CLZ
559 #undef __SSAT
560 #undef __USAT
561 #undef __RBIT
562 #undef __get_APSR
563
564 __STATIC_INLINE uint8_t __CLZ(uint32_t data)
565 {
566 if (data == 0U) { return 32U; }
567
568 uint32_t count = 0U;
569 uint32_t mask = 0x80000000U;
570
571 while ((data & mask) == 0U)
572 {
573 count += 1U;
574 mask = mask >> 1U;
575 }
576 return count;
577 }
578
579 __STATIC_INLINE uint32_t __RBIT(uint32_t v)
580 {
581 uint8_t sc = 31U;
582 uint32_t r = v;
583 for (v >>= 1U; v; v >>= 1U)
584 {
585 r <<= 1U;
586 r |= v & 1U;
587 sc--;
588 }
589 return (r << sc);
590 }
591
592 __STATIC_INLINE uint32_t __get_APSR(void)
593 {
594 uint32_t res;
595 __asm("MRS %0,APSR" : "=r" (res));
596 return res;
597 }
598
599 #endif
600
601 #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
602 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
603 #undef __get_FPSCR
604 #undef __set_FPSCR
605 #define __get_FPSCR() (0)
606 #define __set_FPSCR(VALUE) ((void)VALUE)
607 #endif
608
609 #pragma diag_suppress=Pe940
610 #pragma diag_suppress=Pe177
611
612 #define __enable_irq __enable_interrupt
613 #define __disable_irq __disable_interrupt
614 #define __NOP __no_operation
615
616 #define __get_xPSR __get_PSR
617
618 #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
619
620 __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
621 {
622 return __LDREX((unsigned long *)ptr);
623 }
624
625 __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
626 {
627 return __STREX(value, (unsigned long *)ptr);
628 }
629 #endif
630
631
632 /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
633 #if (__CORTEX_M >= 0x03)
634
635 __IAR_FT uint32_t __RRX(uint32_t value)
636 {
637 uint32_t result;
638 __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value));
639 return(result);
640 }
641
642 __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
643 {
644 __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
645 }
646
647
648 #define __enable_fault_irq __enable_fiq
649 #define __disable_fault_irq __disable_fiq
650
651
652 #endif /* (__CORTEX_M >= 0x03) */
653
654 __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
655 {
656 return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
657 }
658
659 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
660 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
661
662 __IAR_FT uint32_t __get_MSPLIM(void)
663 {
664 uint32_t res;
665 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
666 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
667 // without main extensions, the non-secure MSPLIM is RAZ/WI
668 res = 0U;
669 #else
670 __asm volatile("MRS %0,MSPLIM" : "=r" (res));
671 #endif
672 return res;
673 }
674
675 __IAR_FT void __set_MSPLIM(uint32_t value)
676 {
677 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
678 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
679 // without main extensions, the non-secure MSPLIM is RAZ/WI
680 (void)value;
681 #else
682 __asm volatile("MSR MSPLIM,%0" :: "r" (value));
683 #endif
684 }
685
686 __IAR_FT uint32_t __get_PSPLIM(void)
687 {
688 uint32_t res;
689 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
690 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
691 // without main extensions, the non-secure PSPLIM is RAZ/WI
692 res = 0U;
693 #else
694 __asm volatile("MRS %0,PSPLIM" : "=r" (res));
695 #endif
696 return res;
697 }
698
699 __IAR_FT void __set_PSPLIM(uint32_t value)
700 {
701 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
702 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
703 // without main extensions, the non-secure PSPLIM is RAZ/WI
704 (void)value;
705 #else
706 __asm volatile("MSR PSPLIM,%0" :: "r" (value));
707 #endif
708 }
709
710 __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
711 {
712 uint32_t res;
713 __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
714 return res;
715 }
716
717 __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
718 {
719 __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
720 __iar_builtin_ISB();
721 }
722
723 __IAR_FT uint32_t __TZ_get_PSP_NS(void)
724 {
725 uint32_t res;
726 __asm volatile("MRS %0,PSP_NS" : "=r" (res));
727 return res;
728 }
729
730 __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
731 {
732 __asm volatile("MSR PSP_NS,%0" :: "r" (value));
733 }
734
735 __IAR_FT uint32_t __TZ_get_MSP_NS(void)
736 {
737 uint32_t res;
738 __asm volatile("MRS %0,MSP_NS" : "=r" (res));
739 return res;
740 }
741
742 __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
743 {
744 __asm volatile("MSR MSP_NS,%0" :: "r" (value));
745 }
746
747 __IAR_FT uint32_t __TZ_get_SP_NS(void)
748 {
749 uint32_t res;
750 __asm volatile("MRS %0,SP_NS" : "=r" (res));
751 return res;
752 }
753 __IAR_FT void __TZ_set_SP_NS(uint32_t value)
754 {
755 __asm volatile("MSR SP_NS,%0" :: "r" (value));
756 }
757
758 __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
759 {
760 uint32_t res;
761 __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
762 return res;
763 }
764
765 __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
766 {
767 __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
768 }
769
770 __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
771 {
772 uint32_t res;
773 __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
774 return res;
775 }
776
777 __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
778 {
779 __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
780 }
781
782 __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
783 {
784 uint32_t res;
785 __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
786 return res;
787 }
788
789 __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
790 {
791 __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
792 }
793
794 __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
795 {
796 uint32_t res;
797 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
798 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
799 // without main extensions, the non-secure PSPLIM is RAZ/WI
800 res = 0U;
801 #else
802 __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
803 #endif
804 return res;
805 }
806
807 __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
808 {
809 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
810 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
811 // without main extensions, the non-secure PSPLIM is RAZ/WI
812 (void)value;
813 #else
814 __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
815 #endif
816 }
817
818 __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
819 {
820 uint32_t res;
821 __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
822 return res;
823 }
824
825 __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
826 {
827 __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
828 }
829
830 #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
831
832#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
833
834#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
835
836#if __IAR_M0_FAMILY
837 __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
838 {
839 if ((sat >= 1U) && (sat <= 32U))
840 {
841 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
842 const int32_t min = -1 - max ;
843 if (val > max)
844 {
845 return max;
846 }
847 else if (val < min)
848 {
849 return min;
850 }
851 }
852 return val;
853 }
854
855 __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
856 {
857 if (sat <= 31U)
858 {
859 const uint32_t max = ((1U << sat) - 1U);
860 if (val > (int32_t)max)
861 {
862 return max;
863 }
864 else if (val < 0)
865 {
866 return 0U;
867 }
868 }
869 return (uint32_t)val;
870 }
871#endif
872
873#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
874
875 __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
876 {
877 uint32_t res;
878 __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
879 return ((uint8_t)res);
880 }
881
882 __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
883 {
884 uint32_t res;
885 __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
886 return ((uint16_t)res);
887 }
888
889 __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
890 {
891 uint32_t res;
892 __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
893 return res;
894 }
895
896 __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
897 {
898 __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
899 }
900
901 __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
902 {
903 __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
904 }
905
906 __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
907 {
908 __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
909 }
910
911#endif /* (__CORTEX_M >= 0x03) */
912
913#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
914 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
915
916
917 __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
918 {
919 uint32_t res;
920 __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
921 return ((uint8_t)res);
922 }
923
924 __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
925 {
926 uint32_t res;
927 __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
928 return ((uint16_t)res);
929 }
930
931 __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
932 {
933 uint32_t res;
934 __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
935 return res;
936 }
937
938 __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
939 {
940 __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
941 }
942
943 __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
944 {
945 __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
946 }
947
948 __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
949 {
950 __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
951 }
952
953 __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
954 {
955 uint32_t res;
956 __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
957 return ((uint8_t)res);
958 }
959
960 __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
961 {
962 uint32_t res;
963 __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
964 return ((uint16_t)res);
965 }
966
967 __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
968 {
969 uint32_t res;
970 __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
971 return res;
972 }
973
974 __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
975 {
976 uint32_t res;
977 __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
978 return res;
979 }
980
981 __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
982 {
983 uint32_t res;
984 __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
985 return res;
986 }
987
988 __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
989 {
990 uint32_t res;
991 __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
992 return res;
993 }
994
995#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
996
997#undef __IAR_FT
998#undef __IAR_M0_FAMILY
999#undef __ICCARM_V8
1000
1001#pragma diag_default=Pe940
1002#pragma diag_default=Pe177
1003
1004#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
1005
1006#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
1007
1008#endif /* __CMSIS_ICCARM_H__ */
__SSAT
__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
Signed Saturate.
Definition cmsis_armclang.h:533
__CLZ
#define __CLZ
Count leading zeros.
Definition cmsis_armcc.h:291
__USAT
__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
Unsigned Saturate.
Definition cmsis_armclang.h:558
__ROR
#define __ROR
Rotate Right in unsigned value (32 bit)
Definition cmsis_armcc.h:244
__RBIT
#define __RBIT
Reverse bit order of value.
Definition cmsis_armclang.h:294
__REVSH
#define __REVSH(value)
Reverse byte order (16 bit)
Definition cmsis_armclang.h:257
__set_CONTROL
__STATIC_INLINE void __set_CONTROL(uint32_t control)
Set Control Register.
Definition cmsis_armcc.h:573
__get_APSR
__STATIC_INLINE uint32_t __get_APSR(void)
Get APSR Register.
Definition cmsis_armcc.h:598
__iar_u32
Definition cmsis_iccarm.h:234
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