YAHAL
Yet Another Hardware Abstraction Library
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msp_compatibility.h
1//*****************************************************************************
2//
3// Copyright (C) 2013 - 2015 Texas Instruments Incorporated - http://www.ti.com/
4//
5// Redistribution and use in source and binary forms, with or without
6// modification, are permitted provided that the following conditions
7// are met:
8//
9// Redistributions of source code must retain the above copyright
10// notice, this list of conditions and the following disclaimer.
11//
12// Redistributions in binary form must reproduce the above copyright
13// notice, this list of conditions and the following disclaimer in the
14// documentation and/or other materials provided with the
15// distribution.
16//
17// Neither the name of Texas Instruments Incorporated nor the names of
18// its contributors may be used to endorse or promote products derived
19// from this software without specific prior written permission.
20//
21// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32//
33// MSP430 intrinsic redefinitions for use with MSP432 Family Devices
34//
35//****************************************************************************
36
37/******************************************************************************
38* Definitions for 8/16/32-bit wide memory access *
39******************************************************************************/
40#define HWREG8(x) (*((volatile uint8_t *)(x)))
41#define HWREG16(x) (*((volatile uint16_t *)(x)))
42#define HWREG32(x) (*((volatile uint32_t *)(x)))
43#define HWREG(x) (HWREG16(x))
44#define HWREG8_L(x) (*((volatile uint8_t *)((uint8_t *)&x)))
45#define HWREG8_H(x) (*((volatile uint8_t *)(((uint8_t *)&x)+1)))
46#define HWREG16_L(x) (*((volatile uint16_t *)((uint16_t *)&x)))
47#define HWREG16_H(x) (*((volatile uint16_t *)(((uint16_t *)&x)+1)))
48
49/******************************************************************************
50* Definitions for 8/16/32-bit wide bit band access *
51******************************************************************************/
52#define HWREGBIT8(x, b) (HWREG8(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
53#define HWREGBIT16(x, b) (HWREG16(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
54#define HWREGBIT32(x, b) (HWREG32(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
55
56// Intrinsics with ARM equivalents
57#if defined ( __TI_ARM__ ) /* TI CGT Compiler */
58
59#define __sleep() __wfi()
60#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; }
61#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; }
62#define __get_SP_register() __get_MSP()
63#define __set_SP_register(x) __set_MSP(x)
64#define __get_interrupt_state() __get_PRIMASK()
65#define __set_interrupt_state(x) __set_PRIMASK(x)
66#define __enable_interrupt() _enable_IRQ()
67#define __enable_interrupts() _enable_IRQ()
68#define __disable_interrupt() _disable_IRQ()
69#define __disable_interrupts() _disable_IRQ()
70#define __no_operation() __asm(" nop")
71
72#elif defined ( __ICCARM__ ) /* IAR Compiler */
73
74#include <stdint.h>
75
76#define __INLINE inline
77#define __sleep() __WFI()
78#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __WFI(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; }
79#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; }
80
81#if (__VER__ < 8020002)
82#define __get_SP_register() __get_MSP()
83#define __set_SP_register() __set_MSP()
84#define __get_interrupt_state() __get_PRIMASK()
85#define __set_interrupt_state(x) __set_PRIMASK(x)
86#define __enable_interrupt() __asm(" cpsie i")
87#define __enable_interrupts() __asm(" cpsie i")
88#define __disable_interrupt() __asm(" cpsid i")
89#define __disable_interrupts() __asm(" cpsid i")
90#define __no_operation() __asm(" nop")
91#endif
92
93// Intrinsics without ARM equivalents
94#define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
95#define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
96#define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
97#define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
98#define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
99#define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
100#define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
101#define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
102#define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
103#define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
104#define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
105#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
106#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
107#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
108#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ }
109
110#elif defined ( __CC_ARM ) /* ARM Compiler */
111
112#define __sleep() __wfi()
113#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; }
114#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; }
115#define __get_SP_register() __get_MSP()
116#define __set_SP_register(x) __set_MSP(x)
117#define __get_interrupt_state() __get_PRIMASK()
118#define __set_interrupt_state(x) __set_PRIMASK(x)
119#define __enable_interrupt() __asm(" cpsie i")
120#define __enable_interrupts() __asm(" cpsie i")
121#define __disable_interrupt() __asm(" cpsid i")
122#define __disable_interrupts() __asm(" cpsid i")
123#define __no_operation() __asm(" nop")
124
125// Intrinsics without ARM equivalents
126#define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
127#define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
128#define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
129#define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
130#define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
131#define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
132#define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
133#define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
134#define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
135#define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
136#define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
137#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
138#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
139#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
140#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ }
141
142#elif defined ( __GNUC__ ) /* GCC Compiler */
143#undef __wfi
144#define __wfi() __asm(" wfi")
145#define __sleep() __wfi()
146#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; }
147#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; }
148#define __get_SP_register() __get_MSP()
149#define __set_SP_register(x) __set_MSP(x)
150#define __get_interrupt_state() __get_PRIMASK()
151#define __set_interrupt_state(x) __set_PRIMASK(x)
152#define __enable_interrupt() __asm(" cpsie i")
153#define __enable_interrupts() __asm(" cpsie i")
154#define __disable_interrupt() __asm(" cpsid i")
155#define __disable_interrupts() __asm(" cpsid i")
156#define __no_operation() __asm(" nop")
157
158// Intrinsics without ARM equivalents
159#define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
160#define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
161#define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
162#define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
163#define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
164#define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
165#define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
166#define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
167#define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
168#define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
169#define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
170#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
171#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
172#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
173#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ }
174
175#endif
176
177// Intrinsics without ARM equivalents
178#define __low_power_mode_0() { __sleep(); }
179#define __low_power_mode_1() { __sleep(); }
180#define __low_power_mode_2() { __sleep(); }
181#define __low_power_mode_3() { __deep_sleep(); }
182#define __low_power_mode_4() { __deep_sleep(); }
183#define __data16_read_addr(x) (*((volatile uint32_t *)(x)))
184#define __data20_read_char(x) (*((volatile uint8_t *)(x)))
185#define __data20_read_short(x) (*((volatile uint16_t *)(x)))
186#define __data20_read_long(x) (*((volatile uint32_t *)(x)))
187#define __data16_write_addr(x,y) { (*((volatile uint32_t *)(x))) }
188#define __get_SR_register() 0
189#define __get_SR_register_on_exit() 0
190
191// the following defines are deprecated and will be removed in future releases
192#define ATLBASE ALTBASE
193#define CS_CTL1_SELM_7 ((uint32_t)0x00000007)
194 /* compatibilities. */
195#define CS_CTL1_SELS_7 ((uint32_t)0x00000070)
196 /* compatibilities. */
197#define CS_CTL1_SELA_3 ((uint32_t)0x00000300)
198 /* compatibilities. */
199#define CS_CTL1_SELA_4 ((uint32_t)0x00000400)
200 /* compatibilities. */
201#define CS_CTL1_SELA_5 ((uint32_t)0x00000500)
202 /* compatibilities. */
203#define CS_CTL1_SELA_6 ((uint32_t)0x00000600)
204 /* compatibilities. */
205#define CS_CTL1_SELA_7 ((uint32_t)0x00000700)
206 /* compatibilities. */
207 /* CS_CTL2[LFXTAGCOFF] Bits */
208#define CS_CTL2_LFXTAGCOFF_OFS ( 7)
209#define CS_CTL2_LFXTAGCOFF ((uint32_t)0x00000080)
211/* CS_CTL3[FCNTHF2] Bits */
212#define CS_CTL3_FCNTHF2_OFS ( 8)
213#define CS_CTL3_FCNTHF2_MASK ((uint32_t)0x00000300)
214#define CS_CTL3_FCNTHF20 ((uint32_t)0x00000100)
215#define CS_CTL3_FCNTHF21 ((uint32_t)0x00000200)
216#define CS_CTL3_FCNTHF2_0 ((uint32_t)0x00000000)
217#define CS_CTL3_FCNTHF2_1 ((uint32_t)0x00000100)
218#define CS_CTL3_FCNTHF2_2 ((uint32_t)0x00000200)
219#define CS_CTL3_FCNTHF2_3 ((uint32_t)0x00000300)
220#define CS_CTL3_FCNTHF2__2048 ((uint32_t)0x00000000)
221#define CS_CTL3_FCNTHF2__4096 ((uint32_t)0x00000100)
222#define CS_CTL3_FCNTHF2__8192 ((uint32_t)0x00000200)
223#define CS_CTL3_FCNTHF2__16384 ((uint32_t)0x00000300)
224/* CS_CTL3[RFCNTHF2] Bits */
225#define CS_CTL3_RFCNTHF2_OFS (10)
226#define CS_CTL3_RFCNTHF2 ((uint32_t)0x00000400)
227/* CS_CTL3[FCNTHF2_EN] Bits */
228#define CS_CTL3_FCNTHF2_EN_OFS (11)
229#define CS_CTL3_FCNTHF2_EN ((uint32_t)0x00000800)
230/* CS_STAT[HFXT2_ON] Bits */
231#define CS_STAT_HFXT2_ON_OFS ( 3)
232#define CS_STAT_HFXT2_ON ((uint32_t)0x00000008)
233/* CS_IE[HFXT2IE] Bits */
234#define CS_IE_HFXT2IE_OFS ( 2)
235#define CS_IE_HFXT2IE ((uint32_t)0x00000004)
236/* CS_IE[FCNTHF2IE] Bits */
237#define CS_IE_FCNTHF2IE_OFS (10)
238#define CS_IE_FCNTHF2IE ((uint32_t)0x00000400)
239/* CS_IE[PLLOOLIE] Bits */
240#define CS_IE_PLLOOLIE_OFS (12)
241#define CS_IE_PLLOOLIE ((uint32_t)0x00001000)
242/* CS_IE[PLLLOSIE] Bits */
243#define CS_IE_PLLLOSIE_OFS (13)
244#define CS_IE_PLLLOSIE ((uint32_t)0x00002000)
245/* CS_IE[PLLOORIE] Bits */
246#define CS_IE_PLLOORIE_OFS (14)
247#define CS_IE_PLLOORIE ((uint32_t)0x00004000)
248/* CS_IE[CALIE] Bits */
249#define CS_IE_CALIE_OFS (15)
250#define CS_IE_CALIE ((uint32_t)0x00008000)
251/* CS_IFG[HFXT2IFG] Bits */
252#define CS_IFG_HFXT2IFG_OFS ( 2)
253#define CS_IFG_HFXT2IFG ((uint32_t)0x00000004)
254/* CS_IFG[FCNTHF2IFG] Bits */
255#define CS_IFG_FCNTHF2IFG_OFS (11)
256#define CS_IFG_FCNTHF2IFG ((uint32_t)0x00000800)
257/* CS_IFG[PLLOOLIFG] Bits */
258#define CS_IFG_PLLOOLIFG_OFS (12)
259#define CS_IFG_PLLOOLIFG ((uint32_t)0x00001000)
260/* CS_IFG[PLLLOSIFG] Bits */
261#define CS_IFG_PLLLOSIFG_OFS (13)
262#define CS_IFG_PLLLOSIFG ((uint32_t)0x00002000)
263/* CS_IFG[PLLOORIFG] Bits */
264#define CS_IFG_PLLOORIFG_OFS (14)
265#define CS_IFG_PLLOORIFG ((uint32_t)0x00004000)
266/* CS_IFG[CALIFG] Bits */
267#define CS_IFG_CALIFG_OFS (15)
268#define CS_IFG_CALIFG ((uint32_t)0x00008000)
269/* CS_CLRIFG[CLR_HFXT2IFG] Bits */
270#define CS_CLRIFG_CLR_HFXT2IFG_OFS ( 2)
271#define CS_CLRIFG_CLR_HFXT2IFG ((uint32_t)0x00000004)
272/* CS_CLRIFG[CLR_CALIFG] Bits */
273#define CS_CLRIFG_CLR_CALIFG_OFS (15)
274#define CS_CLRIFG_CLR_CALIFG ((uint32_t)0x00008000)
275/* CS_CLRIFG[CLR_FCNTHF2IFG] Bits */
276#define CS_CLRIFG_CLR_FCNTHF2IFG_OFS (10)
277#define CS_CLRIFG_CLR_FCNTHF2IFG ((uint32_t)0x00000400)
278/* CS_CLRIFG[CLR_PLLOOLIFG] Bits */
279#define CS_CLRIFG_CLR_PLLOOLIFG_OFS (12)
280#define CS_CLRIFG_CLR_PLLOOLIFG ((uint32_t)0x00001000)
281/* CS_CLRIFG[CLR_PLLLOSIFG] Bits */
282#define CS_CLRIFG_CLR_PLLLOSIFG_OFS (13)
283#define CS_CLRIFG_CLR_PLLLOSIFG ((uint32_t)0x00002000)
284/* CS_CLRIFG[CLR_PLLOORIFG] Bits */
285#define CS_CLRIFG_CLR_PLLOORIFG_OFS (14)
286#define CS_CLRIFG_CLR_PLLOORIFG ((uint32_t)0x00004000)
287/* CS_SETIFG[SET_HFXT2IFG] Bits */
288#define CS_SETIFG_SET_HFXT2IFG_OFS ( 2)
289#define CS_SETIFG_SET_HFXT2IFG ((uint32_t)0x00000004)
290/* CS_SETIFG[SET_CALIFG] Bits */
291#define CS_SETIFG_SET_CALIFG_OFS (15)
292#define CS_SETIFG_SET_CALIFG ((uint32_t)0x00008000)
293/* CS_SETIFG[SET_FCNTHF2IFG] Bits */
294#define CS_SETIFG_SET_FCNTHF2IFG_OFS (10)
295#define CS_SETIFG_SET_FCNTHF2IFG ((uint32_t)0x00000400)
296/* CS_SETIFG[SET_PLLOOLIFG] Bits */
297#define CS_SETIFG_SET_PLLOOLIFG_OFS (12)
298#define CS_SETIFG_SET_PLLOOLIFG ((uint32_t)0x00001000)
299/* CS_SETIFG[SET_PLLLOSIFG] Bits */
300#define CS_SETIFG_SET_PLLLOSIFG_OFS (13)
301#define CS_SETIFG_SET_PLLLOSIFG ((uint32_t)0x00002000)
302/* CS_SETIFG[SET_PLLOORIFG] Bits */
303#define CS_SETIFG_SET_PLLOORIFG_OFS (14)
304#define CS_SETIFG_SET_PLLOORIFG ((uint32_t)0x00004000)
306/* EUSCI_x_CTLW0[SSEL] Bits */
307#define EUSCI_A_CTLW0_SSEL_0 ((uint16_t)0x0000)
308#define EUSCI_B_CTLW0_SSEL_0 ((uint16_t)0x0000)
309#define EUSCI_B_CTLW0_SSEL_3 ((uint16_t)0x00C0)
311/* RSTCTL_PSSRESET_STAT[SVSL] Bits */
312#define RSTCTL_PSSRESET_STAT_SVSL_OFS ( 0)
313#define RSTCTL_PSSRESET_STAT_SVSL ((uint32_t)0x00000001)
315/* SYSCTL_SYSTEM_STAT[DBG_SEC_ACT] Bits */
316#define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT_OFS ( 3)
317#define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT ((uint32_t)0x00000008)
318/* SYSCTL_SYSTEM_STAT[JTAG_SWD_LOCK_ACT] Bits */
319#define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT_OFS ( 4)
320#define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT ((uint32_t)0x00000010)
321/* SYSCTL_SYSTEM_STAT[IP_PROT_ACT] Bits */
322#define SYSCTL_SYSTEM_STAT_IP_PROT_ACT_OFS ( 5)
323#define SYSCTL_SYSTEM_STAT_IP_PROT_ACT ((uint32_t)0x00000020)
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