msp432p401r__classic_8h_source.html

/******************************************************************************

*

* Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/

*

* Redistribution and use in source and binary forms, with or without

* modification, are permitted provided that the following conditions

* are met:

*

*  Redistributions of source code must retain the above copyright

*  notice, this list of conditions and the following disclaimer.

*

*  Redistributions in binary form must reproduce the above copyright

*  notice, this list of conditions and the following disclaimer in the

*  documentation and/or other materials provided with the

*  distribution.

*

*  Neither the name of Texas Instruments Incorporated nor the names of

*  its contributors may be used to endorse or promote products derived

*  from this software without specific prior written permission.

*

* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR

* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT

* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,

* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,

* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY

* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

*

* MSP432P401R Register Definitions

*

* This file includes MSP430 style component and register definitions

* for legacy components re-used in MSP432

*

* File creation date: 2017-12-06

*

******************************************************************************/


#ifndef __MSP432P401R_CLASSIC_H__

#define __MSP432P401R_CLASSIC_H__


/* Use standard integer types with explicit width */

#include <stdint.h>


#ifdef __cplusplus

 extern "C" {

#endif


/******************************************************************************

* Device memory map                                                           *

******************************************************************************/

#define __MAIN_MEMORY_START__                              (0x00000000)

#define __MAIN_MEMORY_END__                                (0x0003FFFF)

#define __BSL_MEMORY_START__                               (0x00202000)

#define __BSL_MEMORY_END__                                 (0x00203FFF)

#define __SRAM_START__                                     (0x20000000)

#define __SRAM_END__                                       (0x2000FFFF)

/******************************************************************************

* MSP-format peripheral registers                                             *

******************************************************************************/


/******************************************************************************

* AES256 Registers

******************************************************************************/

#define AESACTL0                                 (HWREG16(0x40003C00))

#define AESACTL1                                 (HWREG16(0x40003C02))

#define AESASTAT                                 (HWREG16(0x40003C04))

#define AESAKEY                                  (HWREG16(0x40003C06))

#define AESADIN                                  (HWREG16(0x40003C08))

#define AESADOUT                                 (HWREG16(0x40003C0A))

#define AESAXDIN                                 (HWREG16(0x40003C0C))

#define AESAXIN                                  (HWREG16(0x40003C0E))

/* Register offsets from AES256_BASE address */

#define OFS_AESACTL0                                       (0x0000)

#define OFS_AESACTL1                                       (0x0002)

#define OFS_AESASTAT                                       (0x0004)

#define OFS_AESAKEY                                        (0x0006)

#define OFS_AESADIN                                        (0x0008)

#define OFS_AESADOUT                                       (0x000A)

#define OFS_AESAXDIN                                       (0x000C)

#define OFS_AESAXIN                                        (0x000E)

/******************************************************************************

* CAPTIO0 Registers

******************************************************************************/

#define CAPTIO0CTL                               (HWREG16(0x4000540E))

/* Register offsets from CAPTIO0_BASE address */

#define OFS_CAPTIO0CTL                                     (0x000E)

#define CAPTIO0CTL_L                                       (HWREG8_L(CAPTIO0CTL))/* Capacitive Touch IO x Control Register */

#define CAPTIO0CTL_H                                       (HWREG8_H(CAPTIO0CTL))/* Capacitive Touch IO x Control Register */


/******************************************************************************

* CAPTIO1 Registers

******************************************************************************/

#define CAPTIO1CTL                               (HWREG16(0x4000580E))

/* Register offsets from CAPTIO1_BASE address */

#define OFS_CAPTIO1CTL                                     (0x000E)

#define CAPTIO1CTL_L                                       (HWREG8_L(CAPTIO1CTL))/* Capacitive Touch IO x Control Register */

#define CAPTIO1CTL_H                                       (HWREG8_H(CAPTIO1CTL))/* Capacitive Touch IO x Control Register */


/******************************************************************************

* COMP_E0 Registers

******************************************************************************/

#define CE0CTL0                                  (HWREG16(0x40003400))

#define CE0CTL1                                  (HWREG16(0x40003402))

#define CE0CTL2                                  (HWREG16(0x40003404))

#define CE0CTL3                                  (HWREG16(0x40003406))

#define CE0INT                                   (HWREG16(0x4000340C))

#define CE0IV                                    (HWREG16(0x4000340E))

/* Register offsets from COMP_E0_BASE address */

#define OFS_CE0CTL0                                        (0x0000)

#define OFS_CE0CTL1                                        (0x0002)

#define OFS_CE0CTL2                                        (0x0004)

#define OFS_CE0CTL3                                        (0x0006)

#define OFS_CE0INT                                         (0x000C)

#define OFS_CE0IV                                          (0x000E)

/******************************************************************************

* COMP_E1 Registers

******************************************************************************/

#define CE1CTL0                                  (HWREG16(0x40003800))

#define CE1CTL1                                  (HWREG16(0x40003802))

#define CE1CTL2                                  (HWREG16(0x40003804))

#define CE1CTL3                                  (HWREG16(0x40003806))

#define CE1INT                                   (HWREG16(0x4000380C))

#define CE1IV                                    (HWREG16(0x4000380E))

/* Register offsets from COMP_E1_BASE address */

#define OFS_CE1CTL0                                        (0x0000)

#define OFS_CE1CTL1                                        (0x0002)

#define OFS_CE1CTL2                                        (0x0004)

#define OFS_CE1CTL3                                        (0x0006)

#define OFS_CE1INT                                         (0x000C)

#define OFS_CE1IV                                          (0x000E)

/******************************************************************************

* CRC32 Registers

******************************************************************************/

#define CRC32DI                                  (HWREG16(0x40004000))

#define CRC32DIRB                                (HWREG16(0x40004004))

#define CRC32INIRES_LO                           (HWREG16(0x40004008))

#define CRC32INIRES_HI                           (HWREG16(0x4000400A))

#define CRC32RESR_LO                             (HWREG16(0x4000400C))

#define CRC32RESR_HI                             (HWREG16(0x4000400E))

#define CRC16DI                                  (HWREG16(0x40004010))

#define CRC16DIRB                                (HWREG16(0x40004014))

#define CRC16INIRES                              (HWREG16(0x40004018))

#define CRC16RESR                                (HWREG16(0x4000401E))

/* Register offsets from CRC32_BASE address */

#define OFS_CRC32DI                                        (0x0000)

#define OFS_CRC32DIRB                                      (0x0004)

#define OFS_CRC32INIRES_LO                                 (0x0008)

#define OFS_CRC32INIRES_HI                                 (0x000A)

#define OFS_CRC32RESR_LO                                   (0x000C)

#define OFS_CRC32RESR_HI                                   (0x000E)

#define OFS_CRC16DI                                        (0x0010)

#define OFS_CRC16DIRB                                      (0x0014)

#define OFS_CRC16INIRES                                    (0x0018)

#define OFS_CRC16RESR                                      (0x001E)

/******************************************************************************

* DIO Registers

******************************************************************************/

#define PAIN                                     (HWREG16(0x40004C00))

#define PAOUT                                    (HWREG16(0x40004C02))

#define PADIR                                    (HWREG16(0x40004C04))

#define PAREN                                    (HWREG16(0x40004C06))

#define PADS                                     (HWREG16(0x40004C08))

#define PASEL0                                   (HWREG16(0x40004C0A))

#define PASEL1                                   (HWREG16(0x40004C0C))

#define P1IV                                     (HWREG16(0x40004C0E))

#define PASELC                                   (HWREG16(0x40004C16))

#define PAIES                                    (HWREG16(0x40004C18))

#define PAIE                                     (HWREG16(0x40004C1A))

#define PAIFG                                    (HWREG16(0x40004C1C))

#define P2IV                                     (HWREG16(0x40004C1E))

#define PBIN                                     (HWREG16(0x40004C20))

#define PBOUT                                    (HWREG16(0x40004C22))

#define PBDIR                                    (HWREG16(0x40004C24))

#define PBREN                                    (HWREG16(0x40004C26))

#define PBDS                                     (HWREG16(0x40004C28))

#define PBSEL0                                   (HWREG16(0x40004C2A))

#define PBSEL1                                   (HWREG16(0x40004C2C))

#define P3IV                                     (HWREG16(0x40004C2E))

#define PBSELC                                   (HWREG16(0x40004C36))

#define PBIES                                    (HWREG16(0x40004C38))

#define PBIE                                     (HWREG16(0x40004C3A))

#define PBIFG                                    (HWREG16(0x40004C3C))

#define P4IV                                     (HWREG16(0x40004C3E))

#define PCIN                                     (HWREG16(0x40004C40))

#define PCOUT                                    (HWREG16(0x40004C42))

#define PCDIR                                    (HWREG16(0x40004C44))

#define PCREN                                    (HWREG16(0x40004C46))

#define PCDS                                     (HWREG16(0x40004C48))

#define PCSEL0                                   (HWREG16(0x40004C4A))

#define PCSEL1                                   (HWREG16(0x40004C4C))

#define P5IV                                     (HWREG16(0x40004C4E))

#define PCSELC                                   (HWREG16(0x40004C56))

#define PCIES                                    (HWREG16(0x40004C58))

#define PCIE                                     (HWREG16(0x40004C5A))

#define PCIFG                                    (HWREG16(0x40004C5C))

#define P6IV                                     (HWREG16(0x40004C5E))

#define PDIN                                     (HWREG16(0x40004C60))

#define PDOUT                                    (HWREG16(0x40004C62))

#define PDDIR                                    (HWREG16(0x40004C64))

#define PDREN                                    (HWREG16(0x40004C66))

#define PDDS                                     (HWREG16(0x40004C68))

#define PDSEL0                                   (HWREG16(0x40004C6A))

#define PDSEL1                                   (HWREG16(0x40004C6C))

#define P7IV                                     (HWREG16(0x40004C6E))

#define PDSELC                                   (HWREG16(0x40004C76))

#define PDIES                                    (HWREG16(0x40004C78))

#define PDIE                                     (HWREG16(0x40004C7A))

#define PDIFG                                    (HWREG16(0x40004C7C))

#define P8IV                                     (HWREG16(0x40004C7E))

#define PEIN                                     (HWREG16(0x40004C80))

#define PEOUT                                    (HWREG16(0x40004C82))

#define PEDIR                                    (HWREG16(0x40004C84))

#define PEREN                                    (HWREG16(0x40004C86))

#define PEDS                                     (HWREG16(0x40004C88))

#define PESEL0                                   (HWREG16(0x40004C8A))

#define PESEL1                                   (HWREG16(0x40004C8C))

#define P9IV                                     (HWREG16(0x40004C8E))

#define PESELC                                   (HWREG16(0x40004C96))

#define PEIES                                    (HWREG16(0x40004C98))

#define PEIE                                     (HWREG16(0x40004C9A))

#define PEIFG                                    (HWREG16(0x40004C9C))

#define P10IV                                    (HWREG16(0x40004C9E))

#define PJIN                                     (HWREG16(0x40004D20))

#define PJOUT                                    (HWREG16(0x40004D22))

#define PJDIR                                    (HWREG16(0x40004D24))

#define PJREN                                    (HWREG16(0x40004D26))

#define PJDS                                     (HWREG16(0x40004D28))

#define PJSEL0                                   (HWREG16(0x40004D2A))

#define PJSEL1                                   (HWREG16(0x40004D2C))

#define PJSELC                                   (HWREG16(0x40004D36))

#define P1IN                                     (HWREG8(0x40004C00))

#define P2IN                                     (HWREG8(0x40004C01))

#define P2OUT                                    (HWREG8(0x40004C03))

#define P1OUT                                    (HWREG8(0x40004C02))

#define P1DIR                                    (HWREG8(0x40004C04))

#define P2DIR                                    (HWREG8(0x40004C05))

#define P1REN                                    (HWREG8(0x40004C06))

#define P2REN                                    (HWREG8(0x40004C07))

#define P1DS                                     (HWREG8(0x40004C08))

#define P2DS                                     (HWREG8(0x40004C09))

#define P1SEL0                                   (HWREG8(0x40004C0A))

#define P2SEL0                                   (HWREG8(0x40004C0B))

#define P1SEL1                                   (HWREG8(0x40004C0C))

#define P2SEL1                                   (HWREG8(0x40004C0D))

#define P1SELC                                   (HWREG8(0x40004C16))

#define P2SELC                                   (HWREG8(0x40004C17))

#define P1IES                                    (HWREG8(0x40004C18))

#define P2IES                                    (HWREG8(0x40004C19))

#define P1IE                                     (HWREG8(0x40004C1A))

#define P2IE                                     (HWREG8(0x40004C1B))

#define P1IFG                                    (HWREG8(0x40004C1C))

#define P2IFG                                    (HWREG8(0x40004C1D))

#define P3IN                                     (HWREG8(0x40004C20))

#define P4IN                                     (HWREG8(0x40004C21))

#define P3OUT                                    (HWREG8(0x40004C22))

#define P4OUT                                    (HWREG8(0x40004C23))

#define P3DIR                                    (HWREG8(0x40004C24))

#define P4DIR                                    (HWREG8(0x40004C25))

#define P3REN                                    (HWREG8(0x40004C26))

#define P4REN                                    (HWREG8(0x40004C27))

#define P3DS                                     (HWREG8(0x40004C28))

#define P4DS                                     (HWREG8(0x40004C29))

#define P4SEL0                                   (HWREG8(0x40004C2B))

#define P3SEL0                                   (HWREG8(0x40004C2A))

#define P3SEL1                                   (HWREG8(0x40004C2C))

#define P4SEL1                                   (HWREG8(0x40004C2D))

#define P3SELC                                   (HWREG8(0x40004C36))

#define P4SELC                                   (HWREG8(0x40004C37))

#define P3IES                                    (HWREG8(0x40004C38))

#define P4IES                                    (HWREG8(0x40004C39))

#define P3IE                                     (HWREG8(0x40004C3A))

#define P4IE                                     (HWREG8(0x40004C3B))

#define P3IFG                                    (HWREG8(0x40004C3C))

#define P4IFG                                    (HWREG8(0x40004C3D))

#define P5IN                                     (HWREG8(0x40004C40))

#define P6IN                                     (HWREG8(0x40004C41))

#define P5OUT                                    (HWREG8(0x40004C42))

#define P6OUT                                    (HWREG8(0x40004C43))

#define P5DIR                                    (HWREG8(0x40004C44))

#define P6DIR                                    (HWREG8(0x40004C45))

#define P5REN                                    (HWREG8(0x40004C46))

#define P6REN                                    (HWREG8(0x40004C47))

#define P5DS                                     (HWREG8(0x40004C48))

#define P6DS                                     (HWREG8(0x40004C49))

#define P5SEL0                                   (HWREG8(0x40004C4A))

#define P6SEL0                                   (HWREG8(0x40004C4B))

#define P5SEL1                                   (HWREG8(0x40004C4C))

#define P6SEL1                                   (HWREG8(0x40004C4D))

#define P5SELC                                   (HWREG8(0x40004C56))

#define P6SELC                                   (HWREG8(0x40004C57))

#define P5IES                                    (HWREG8(0x40004C58))

#define P6IES                                    (HWREG8(0x40004C59))

#define P5IE                                     (HWREG8(0x40004C5A))

#define P6IE                                     (HWREG8(0x40004C5B))

#define P5IFG                                    (HWREG8(0x40004C5C))

#define P6IFG                                    (HWREG8(0x40004C5D))

#define P7IN                                     (HWREG8(0x40004C60))

#define P8IN                                     (HWREG8(0x40004C61))

#define P7OUT                                    (HWREG8(0x40004C62))

#define P8OUT                                    (HWREG8(0x40004C63))

#define P7DIR                                    (HWREG8(0x40004C64))

#define P8DIR                                    (HWREG8(0x40004C65))

#define P7REN                                    (HWREG8(0x40004C66))

#define P8REN                                    (HWREG8(0x40004C67))

#define P7DS                                     (HWREG8(0x40004C68))

#define P8DS                                     (HWREG8(0x40004C69))

#define P7SEL0                                   (HWREG8(0x40004C6A))

#define P8SEL0                                   (HWREG8(0x40004C6B))

#define P7SEL1                                   (HWREG8(0x40004C6C))

#define P8SEL1                                   (HWREG8(0x40004C6D))

#define P7SELC                                   (HWREG8(0x40004C76))

#define P8SELC                                   (HWREG8(0x40004C77))

#define P7IES                                    (HWREG8(0x40004C78))

#define P8IES                                    (HWREG8(0x40004C79))

#define P7IE                                     (HWREG8(0x40004C7A))

#define P8IE                                     (HWREG8(0x40004C7B))

#define P7IFG                                    (HWREG8(0x40004C7C))

#define P8IFG                                    (HWREG8(0x40004C7D))

#define P9IN                                     (HWREG8(0x40004C80))

#define P10IN                                    (HWREG8(0x40004C81))

#define P9OUT                                    (HWREG8(0x40004C82))

#define P10OUT                                   (HWREG8(0x40004C83))

#define P9DIR                                    (HWREG8(0x40004C84))

#define P10DIR                                   (HWREG8(0x40004C85))

#define P9REN                                    (HWREG8(0x40004C86))

#define P10REN                                   (HWREG8(0x40004C87))

#define P9DS                                     (HWREG8(0x40004C88))

#define P10DS                                    (HWREG8(0x40004C89))

#define P9SEL0                                   (HWREG8(0x40004C8A))

#define P10SEL0                                  (HWREG8(0x40004C8B))

#define P9SEL1                                   (HWREG8(0x40004C8C))

#define P10SEL1                                  (HWREG8(0x40004C8D))

#define P9SELC                                   (HWREG8(0x40004C96))

#define P10SELC                                  (HWREG8(0x40004C97))

#define P9IES                                    (HWREG8(0x40004C98))

#define P10IES                                   (HWREG8(0x40004C99))

#define P9IE                                     (HWREG8(0x40004C9A))

#define P10IE                                    (HWREG8(0x40004C9B))

#define P9IFG                                    (HWREG8(0x40004C9C))

#define P10IFG                                   (HWREG8(0x40004C9D))

/* Register offsets from DIO_BASE address */

#define OFS_PAIN                                           (0x0000)

#define OFS_PAOUT                                          (0x0002)

#define OFS_PADIR                                          (0x0004)

#define OFS_PAREN                                          (0x0006)

#define OFS_PADS                                           (0x0008)

#define OFS_PASEL0                                         (0x000A)

#define OFS_PASEL1                                         (0x000C)

#define OFS_P1IV                                           (0x000E)

#define OFS_PASELC                                         (0x0016)

#define OFS_PAIES                                          (0x0018)

#define OFS_PAIE                                           (0x001A)

#define OFS_PAIFG                                          (0x001C)

#define OFS_P2IV                                           (0x001E)

#define OFS_PBIN                                           (0x0020)

#define OFS_PBOUT                                          (0x0022)

#define OFS_PBDIR                                          (0x0024)

#define OFS_PBREN                                          (0x0026)

#define OFS_PBDS                                           (0x0028)

#define OFS_PBSEL0                                         (0x002A)

#define OFS_PBSEL1                                         (0x002C)

#define OFS_P3IV                                           (0x002E)

#define OFS_PBSELC                                         (0x0036)

#define OFS_PBIES                                          (0x0038)

#define OFS_PBIE                                           (0x003A)

#define OFS_PBIFG                                          (0x003C)

#define OFS_P4IV                                           (0x003E)

#define OFS_PCIN                                           (0x0040)

#define OFS_PCOUT                                          (0x0042)

#define OFS_PCDIR                                          (0x0044)

#define OFS_PCREN                                          (0x0046)

#define OFS_PCDS                                           (0x0048)

#define OFS_PCSEL0                                         (0x004A)

#define OFS_PCSEL1                                         (0x004C)

#define OFS_P5IV                                           (0x004E)

#define OFS_PCSELC                                         (0x0056)

#define OFS_PCIES                                          (0x0058)

#define OFS_PCIE                                           (0x005A)

#define OFS_PCIFG                                          (0x005C)

#define OFS_P6IV                                           (0x005E)

#define OFS_PDIN                                           (0x0060)

#define OFS_PDOUT                                          (0x0062)

#define OFS_PDDIR                                          (0x0064)

#define OFS_PDREN                                          (0x0066)

#define OFS_PDDS                                           (0x0068)

#define OFS_PDSEL0                                         (0x006A)

#define OFS_PDSEL1                                         (0x006C)

#define OFS_P7IV                                           (0x006E)

#define OFS_PDSELC                                         (0x0076)

#define OFS_PDIES                                          (0x0078)

#define OFS_PDIE                                           (0x007A)

#define OFS_PDIFG                                          (0x007C)

#define OFS_P8IV                                           (0x007E)

#define OFS_PEIN                                           (0x0080)

#define OFS_PEOUT                                          (0x0082)

#define OFS_PEDIR                                          (0x0084)

#define OFS_PEREN                                          (0x0086)

#define OFS_PEDS                                           (0x0088)

#define OFS_PESEL0                                         (0x008A)

#define OFS_PESEL1                                         (0x008C)

#define OFS_P9IV                                           (0x008E)

#define OFS_PESELC                                         (0x0096)

#define OFS_PEIES                                          (0x0098)

#define OFS_PEIE                                           (0x009A)

#define OFS_PEIFG                                          (0x009C)

#define OFS_P10IV                                          (0x009E)

#define OFS_PJIN                                           (0x0120)

#define OFS_PJOUT                                          (0x0122)

#define OFS_PJDIR                                          (0x0124)

#define OFS_PJREN                                          (0x0126)

#define OFS_PJDS                                           (0x0128)

#define OFS_PJSEL0                                         (0x012A)

#define OFS_PJSEL1                                         (0x012C)

#define OFS_PJSELC                                         (0x0136)

#define OFS_P1IN                                           (0x0000)

#define OFS_P2IN                                           (0x0001)

#define OFS_P2OUT                                          (0x0003)

#define OFS_P1OUT                                          (0x0002)

#define OFS_P1DIR                                          (0x0004)

#define OFS_P2DIR                                          (0x0005)

#define OFS_P1REN                                          (0x0006)

#define OFS_P2REN                                          (0x0007)

#define OFS_P1DS                                           (0x0008)

#define OFS_P2DS                                           (0x0009)

#define OFS_P1SEL0                                         (0x000A)

#define OFS_P2SEL0                                         (0x000B)

#define OFS_P1SEL1                                         (0x000C)

#define OFS_P2SEL1                                         (0x000D)

#define OFS_P1SELC                                         (0x0016)

#define OFS_P2SELC                                         (0x0017)

#define OFS_P1IES                                          (0x0018)

#define OFS_P2IES                                          (0x0019)

#define OFS_P1IE                                           (0x001A)

#define OFS_P2IE                                           (0x001B)

#define OFS_P1IFG                                          (0x001C)

#define OFS_P2IFG                                          (0x001D)

#define OFS_P3IN                                           (0x0020)

#define OFS_P4IN                                           (0x0021)

#define OFS_P3OUT                                          (0x0022)

#define OFS_P4OUT                                          (0x0023)

#define OFS_P3DIR                                          (0x0024)

#define OFS_P4DIR                                          (0x0025)

#define OFS_P3REN                                          (0x0026)

#define OFS_P4REN                                          (0x0027)

#define OFS_P3DS                                           (0x0028)

#define OFS_P4DS                                           (0x0029)

#define OFS_P4SEL0                                         (0x002B)

#define OFS_P3SEL0                                         (0x002A)

#define OFS_P3SEL1                                         (0x002C)

#define OFS_P4SEL1                                         (0x002D)

#define OFS_P3SELC                                         (0x0036)

#define OFS_P4SELC                                         (0x0037)

#define OFS_P3IES                                          (0x0038)

#define OFS_P4IES                                          (0x0039)

#define OFS_P3IE                                           (0x003A)

#define OFS_P4IE                                           (0x003B)

#define OFS_P3IFG                                          (0x003C)

#define OFS_P4IFG                                          (0x003D)

#define OFS_P5IN                                           (0x0040)

#define OFS_P6IN                                           (0x0041)

#define OFS_P5OUT                                          (0x0042)

#define OFS_P6OUT                                          (0x0043)

#define OFS_P5DIR                                          (0x0044)

#define OFS_P6DIR                                          (0x0045)

#define OFS_P5REN                                          (0x0046)

#define OFS_P6REN                                          (0x0047)

#define OFS_P5DS                                           (0x0048)

#define OFS_P6DS                                           (0x0049)

#define OFS_P5SEL0                                         (0x004A)

#define OFS_P6SEL0                                         (0x004B)

#define OFS_P5SEL1                                         (0x004C)

#define OFS_P6SEL1                                         (0x004D)

#define OFS_P5SELC                                         (0x0056)

#define OFS_P6SELC                                         (0x0057)

#define OFS_P5IES                                          (0x0058)

#define OFS_P6IES                                          (0x0059)

#define OFS_P5IE                                           (0x005A)

#define OFS_P6IE                                           (0x005B)

#define OFS_P5IFG                                          (0x005C)

#define OFS_P6IFG                                          (0x005D)

#define OFS_P7IN                                           (0x0060)

#define OFS_P8IN                                           (0x0061)

#define OFS_P7OUT                                          (0x0062)

#define OFS_P8OUT                                          (0x0063)

#define OFS_P7DIR                                          (0x0064)

#define OFS_P8DIR                                          (0x0065)

#define OFS_P7REN                                          (0x0066)

#define OFS_P8REN                                          (0x0067)

#define OFS_P7DS                                           (0x0068)

#define OFS_P8DS                                           (0x0069)

#define OFS_P7SEL0                                         (0x006A)

#define OFS_P8SEL0                                         (0x006B)

#define OFS_P7SEL1                                         (0x006C)

#define OFS_P8SEL1                                         (0x006D)

#define OFS_P7SELC                                         (0x0076)

#define OFS_P8SELC                                         (0x0077)

#define OFS_P7IES                                          (0x0078)

#define OFS_P8IES                                          (0x0079)

#define OFS_P7IE                                           (0x007A)

#define OFS_P8IE                                           (0x007B)

#define OFS_P7IFG                                          (0x007C)

#define OFS_P8IFG                                          (0x007D)

#define OFS_P9IN                                           (0x0080)

#define OFS_P10IN                                          (0x0081)

#define OFS_P9OUT                                          (0x0082)

#define OFS_P10OUT                                         (0x0083)

#define OFS_P9DIR                                          (0x0084)

#define OFS_P10DIR                                         (0x0085)

#define OFS_P9REN                                          (0x0086)

#define OFS_P10REN                                         (0x0087)

#define OFS_P9DS                                           (0x0088)

#define OFS_P10DS                                          (0x0089)

#define OFS_P9SEL0                                         (0x008A)

#define OFS_P10SEL0                                        (0x008B)

#define OFS_P9SEL1                                         (0x008C)

#define OFS_P10SEL1                                        (0x008D)

#define OFS_P9SELC                                         (0x0096)

#define OFS_P10SELC                                        (0x0097)

#define OFS_P9IES                                          (0x0098)

#define OFS_P10IES                                         (0x0099)

#define OFS_P9IE                                           (0x009A)

#define OFS_P10IE                                          (0x009B)

#define OFS_P9IFG                                          (0x009C)

#define OFS_P10IFG                                         (0x009D)

/******************************************************************************

* EUSCI_A0 Registers

******************************************************************************/

#define UCA0CTLW0                                (HWREG16(0x40001000))

#define UCA0CTLW0_SPI                            (HWREG16(0x40001000))

#define UCA0CTLW1                                (HWREG16(0x40001002))

#define UCA0BRW                                  (HWREG16(0x40001006))

#define UCA0BRW_SPI                              (HWREG16(0x40001006))

#define UCA0MCTLW                                (HWREG16(0x40001008))

#define UCA0STATW                                (HWREG16(0x4000100A))

#define UCA0STATW_SPI                            (HWREG16(0x4000100A))

#define UCA0RXBUF                                (HWREG16(0x4000100C))

#define UCA0RXBUF_SPI                            (HWREG16(0x4000100C))

#define UCA0TXBUF                                (HWREG16(0x4000100E))

#define UCA0TXBUF_SPI                            (HWREG16(0x4000100E))

#define UCA0ABCTL                                (HWREG16(0x40001010))

#define UCA0IRCTL                                (HWREG16(0x40001012))

#define UCA0IE                                   (HWREG16(0x4000101A))

#define UCA0IE_SPI                               (HWREG16(0x4000101A))

#define UCA0IFG                                  (HWREG16(0x4000101C))

#define UCA0IFG_SPI                              (HWREG16(0x4000101C))

#define UCA0IV                                   (HWREG16(0x4000101E))

#define UCA0IV_SPI                               (HWREG16(0x4000101E))


/* Register offsets from EUSCI_A0_BASE address */

#define OFS_UCA0CTLW0                                      (0x0000)

#define OFS_UCA0CTLW0_SPI                                  (0x0000)

#define OFS_UCA0CTLW1                                      (0x0002)

#define OFS_UCA0BRW                                        (0x0006)

#define OFS_UCA0BRW_SPI                                    (0x0006)

#define OFS_UCA0MCTLW                                      (0x0008)

#define OFS_UCA0STATW                                      (0x000A)

#define OFS_UCA0STATW_SPI                                  (0x000A)

#define OFS_UCA0RXBUF                                      (0x000C)

#define OFS_UCA0RXBUF_SPI                                  (0x000C)

#define OFS_UCA0TXBUF                                      (0x000E)

#define OFS_UCA0TXBUF_SPI                                  (0x000E)

#define OFS_UCA0ABCTL                                      (0x0010)

#define OFS_UCA0IRCTL                                      (0x0012)

#define OFS_UCA0IE                                         (0x001A)

#define OFS_UCA0IE_SPI                                     (0x001A)

#define OFS_UCA0IFG                                        (0x001C)

#define OFS_UCA0IFG_SPI                                    (0x001C)

#define OFS_UCA0IV                                         (0x001E)

#define OFS_UCA0IV_SPI                                     (0x001E)


#define UCA0CTL0                                           (HWREG8_L(UCA0CTLW0)) /* eUSCI_Ax Control 0 */

#define UCA0CTL1                                           (HWREG8_H(UCA0CTLW0)) /* eUSCI_Ax Control 1 */

#define UCA0BR0                                            (HWREG8_L(UCA0BRW))   /* eUSCI_Ax Baud Rate Control 0 */

#define UCA0BR1                                            (HWREG8_H(UCA0BRW))   /* eUSCI_Ax Baud Rate Control 1 */

#define UCA0IRTCTL                                         (HWREG8_L(UCA0IRCTL)) /* eUSCI_Ax IrDA Transmit Control */

#define UCA0IRRCTL                                         (HWREG8_H(UCA0IRCTL)) /* eUSCI_Ax IrDA Receive Control */


/******************************************************************************

* EUSCI_A1 Registers

******************************************************************************/

#define UCA1CTLW0                                (HWREG16(0x40001400))

#define UCA1CTLW0_SPI                            (HWREG16(0x40001400))

#define UCA1CTLW1                                (HWREG16(0x40001402))

#define UCA1BRW                                  (HWREG16(0x40001406))

#define UCA1BRW_SPI                              (HWREG16(0x40001406))

#define UCA1MCTLW                                (HWREG16(0x40001408))

#define UCA1STATW                                (HWREG16(0x4000140A))

#define UCA1STATW_SPI                            (HWREG16(0x4000140A))

#define UCA1RXBUF                                (HWREG16(0x4000140C))

#define UCA1RXBUF_SPI                            (HWREG16(0x4000140C))

#define UCA1TXBUF                                (HWREG16(0x4000140E))

#define UCA1TXBUF_SPI                            (HWREG16(0x4000140E))

#define UCA1ABCTL                                (HWREG16(0x40001410))

#define UCA1IRCTL                                (HWREG16(0x40001412))

#define UCA1IE                                   (HWREG16(0x4000141A))

#define UCA1IE_SPI                               (HWREG16(0x4000141A))

#define UCA1IFG                                  (HWREG16(0x4000141C))

#define UCA1IFG_SPI                              (HWREG16(0x4000141C))

#define UCA1IV                                   (HWREG16(0x4000141E))

#define UCA1IV_SPI                               (HWREG16(0x4000141E))


/* Register offsets from EUSCI_A1_BASE address */

#define OFS_UCA1CTLW0                                      (0x0000)

#define OFS_UCA1CTLW0_SPI                                  (0x0000)

#define OFS_UCA1CTLW1                                      (0x0002)

#define OFS_UCA1BRW                                        (0x0006)

#define OFS_UCA1BRW_SPI                                    (0x0006)

#define OFS_UCA1MCTLW                                      (0x0008)

#define OFS_UCA1STATW                                      (0x000A)

#define OFS_UCA1STATW_SPI                                  (0x000A)

#define OFS_UCA1RXBUF                                      (0x000C)

#define OFS_UCA1RXBUF_SPI                                  (0x000C)

#define OFS_UCA1TXBUF                                      (0x000E)

#define OFS_UCA1TXBUF_SPI                                  (0x000E)

#define OFS_UCA1ABCTL                                      (0x0010)

#define OFS_UCA1IRCTL                                      (0x0012)

#define OFS_UCA1IE                                         (0x001A)

#define OFS_UCA1IE_SPI                                     (0x001A)

#define OFS_UCA1IFG                                        (0x001C)

#define OFS_UCA1IFG_SPI                                    (0x001C)

#define OFS_UCA1IV                                         (0x001E)

#define OFS_UCA1IV_SPI                                     (0x001E)


#define UCA1CTL0                                           (HWREG8_L(UCA1CTLW0)) /* eUSCI_Ax Control 0 */

#define UCA1CTL1                                           (HWREG8_H(UCA1CTLW0)) /* eUSCI_Ax Control 1 */

#define UCA1BR0                                            (HWREG8_L(UCA1BRW))   /* eUSCI_Ax Baud Rate Control 0 */

#define UCA1BR1                                            (HWREG8_H(UCA1BRW))   /* eUSCI_Ax Baud Rate Control 1 */

#define UCA1IRTCTL                                         (HWREG8_L(UCA1IRCTL)) /* eUSCI_Ax IrDA Transmit Control */

#define UCA1IRRCTL                                         (HWREG8_H(UCA1IRCTL)) /* eUSCI_Ax IrDA Receive Control */


/******************************************************************************

* EUSCI_A2 Registers

******************************************************************************/

#define UCA2CTLW0                                (HWREG16(0x40001800))

#define UCA2CTLW0_SPI                            (HWREG16(0x40001800))

#define UCA2CTLW1                                (HWREG16(0x40001802))

#define UCA2BRW                                  (HWREG16(0x40001806))

#define UCA2BRW_SPI                              (HWREG16(0x40001806))

#define UCA2MCTLW                                (HWREG16(0x40001808))

#define UCA2STATW                                (HWREG16(0x4000180A))

#define UCA2STATW_SPI                            (HWREG16(0x4000180A))

#define UCA2RXBUF                                (HWREG16(0x4000180C))

#define UCA2RXBUF_SPI                            (HWREG16(0x4000180C))

#define UCA2TXBUF                                (HWREG16(0x4000180E))

#define UCA2TXBUF_SPI                            (HWREG16(0x4000180E))

#define UCA2ABCTL                                (HWREG16(0x40001810))

#define UCA2IRCTL                                (HWREG16(0x40001812))

#define UCA2IE                                   (HWREG16(0x4000181A))

#define UCA2IE_SPI                               (HWREG16(0x4000181A))

#define UCA2IFG                                  (HWREG16(0x4000181C))

#define UCA2IFG_SPI                              (HWREG16(0x4000181C))

#define UCA2IV                                   (HWREG16(0x4000181E))

#define UCA2IV_SPI                               (HWREG16(0x4000181E))


/* Register offsets from EUSCI_A2_BASE address */

#define OFS_UCA2CTLW0                                      (0x0000)

#define OFS_UCA2CTLW0_SPI                                  (0x0000)

#define OFS_UCA2CTLW1                                      (0x0002)

#define OFS_UCA2BRW                                        (0x0006)

#define OFS_UCA2BRW_SPI                                    (0x0006)

#define OFS_UCA2MCTLW                                      (0x0008)

#define OFS_UCA2STATW                                      (0x000A)

#define OFS_UCA2STATW_SPI                                  (0x000A)

#define OFS_UCA2RXBUF                                      (0x000C)

#define OFS_UCA2RXBUF_SPI                                  (0x000C)

#define OFS_UCA2TXBUF                                      (0x000E)

#define OFS_UCA2TXBUF_SPI                                  (0x000E)

#define OFS_UCA2ABCTL                                      (0x0010)

#define OFS_UCA2IRCTL                                      (0x0012)

#define OFS_UCA2IE                                         (0x001A)

#define OFS_UCA2IE_SPI                                     (0x001A)

#define OFS_UCA2IFG                                        (0x001C)

#define OFS_UCA2IFG_SPI                                    (0x001C)

#define OFS_UCA2IV                                         (0x001E)

#define OFS_UCA2IV_SPI                                     (0x001E)


#define UCA2CTL0                                           (HWREG8_L(UCA2CTLW0)) /* eUSCI_Ax Control 0 */

#define UCA2CTL1                                           (HWREG8_H(UCA2CTLW0)) /* eUSCI_Ax Control 1 */

#define UCA2BR0                                            (HWREG8_L(UCA2BRW))   /* eUSCI_Ax Baud Rate Control 0 */

#define UCA2BR1                                            (HWREG8_H(UCA2BRW))   /* eUSCI_Ax Baud Rate Control 1 */

#define UCA2IRTCTL                                         (HWREG8_L(UCA2IRCTL)) /* eUSCI_Ax IrDA Transmit Control */

#define UCA2IRRCTL                                         (HWREG8_H(UCA2IRCTL)) /* eUSCI_Ax IrDA Receive Control */


/******************************************************************************

* EUSCI_A3 Registers

******************************************************************************/

#define UCA3CTLW0                                (HWREG16(0x40001C00))

#define UCA3CTLW0_SPI                            (HWREG16(0x40001C00))

#define UCA3CTLW1                                (HWREG16(0x40001C02))

#define UCA3BRW                                  (HWREG16(0x40001C06))

#define UCA3BRW_SPI                              (HWREG16(0x40001C06))

#define UCA3MCTLW                                (HWREG16(0x40001C08))

#define UCA3STATW                                (HWREG16(0x40001C0A))

#define UCA3STATW_SPI                            (HWREG16(0x40001C0A))

#define UCA3RXBUF                                (HWREG16(0x40001C0C))

#define UCA3RXBUF_SPI                            (HWREG16(0x40001C0C))

#define UCA3TXBUF                                (HWREG16(0x40001C0E))

#define UCA3TXBUF_SPI                            (HWREG16(0x40001C0E))

#define UCA3ABCTL                                (HWREG16(0x40001C10))

#define UCA3IRCTL                                (HWREG16(0x40001C12))

#define UCA3IE                                   (HWREG16(0x40001C1A))

#define UCA3IE_SPI                               (HWREG16(0x40001C1A))

#define UCA3IFG                                  (HWREG16(0x40001C1C))

#define UCA3IFG_SPI                              (HWREG16(0x40001C1C))

#define UCA3IV                                   (HWREG16(0x40001C1E))

#define UCA3IV_SPI                               (HWREG16(0x40001C1E))


/* Register offsets from EUSCI_A3_BASE address */

#define OFS_UCA3CTLW0                                      (0x0000)

#define OFS_UCA3CTLW0_SPI                                  (0x0000)

#define OFS_UCA3CTLW1                                      (0x0002)

#define OFS_UCA3BRW                                        (0x0006)

#define OFS_UCA3BRW_SPI                                    (0x0006)

#define OFS_UCA3MCTLW                                      (0x0008)

#define OFS_UCA3STATW                                      (0x000A)

#define OFS_UCA3STATW_SPI                                  (0x000A)

#define OFS_UCA3RXBUF                                      (0x000C)

#define OFS_UCA3RXBUF_SPI                                  (0x000C)

#define OFS_UCA3TXBUF                                      (0x000E)

#define OFS_UCA3TXBUF_SPI                                  (0x000E)

#define OFS_UCA3ABCTL                                      (0x0010)

#define OFS_UCA3IRCTL                                      (0x0012)

#define OFS_UCA3IE                                         (0x001A)

#define OFS_UCA3IE_SPI                                     (0x001A)

#define OFS_UCA3IFG                                        (0x001C)

#define OFS_UCA3IFG_SPI                                    (0x001C)

#define OFS_UCA3IV                                         (0x001E)

#define OFS_UCA3IV_SPI                                     (0x001E)


#define UCA3CTL0                                           (HWREG8_L(UCA3CTLW0)) /* eUSCI_Ax Control 0 */

#define UCA3CTL1                                           (HWREG8_H(UCA3CTLW0)) /* eUSCI_Ax Control 1 */

#define UCA3BR0                                            (HWREG8_L(UCA3BRW))   /* eUSCI_Ax Baud Rate Control 0 */

#define UCA3BR1                                            (HWREG8_H(UCA3BRW))   /* eUSCI_Ax Baud Rate Control 1 */

#define UCA3IRTCTL                                         (HWREG8_L(UCA3IRCTL)) /* eUSCI_Ax IrDA Transmit Control */

#define UCA3IRRCTL                                         (HWREG8_H(UCA3IRCTL)) /* eUSCI_Ax IrDA Receive Control */


/******************************************************************************

* EUSCI_B0 Registers

******************************************************************************/

#define UCB0CTLW0                                (HWREG16(0x40002000))

#define UCB0CTLW0_SPI                            (HWREG16(0x40002000))

#define UCB0CTLW1                                (HWREG16(0x40002002))

#define UCB0BRW                                  (HWREG16(0x40002006))

#define UCB0BRW_SPI                              (HWREG16(0x40002006))

#define UCB0STATW                                (HWREG16(0x40002008))

#define UCB0STATW_SPI                            (HWREG16(0x40002008))

#define UCB0TBCNT                                (HWREG16(0x4000200A))

#define UCB0RXBUF                                (HWREG16(0x4000200C))

#define UCB0RXBUF_SPI                            (HWREG16(0x4000200C))

#define UCB0TXBUF                                (HWREG16(0x4000200E))

#define UCB0TXBUF_SPI                            (HWREG16(0x4000200E))

#define UCB0I2COA0                               (HWREG16(0x40002014))

#define UCB0I2COA1                               (HWREG16(0x40002016))

#define UCB0I2COA2                               (HWREG16(0x40002018))

#define UCB0I2COA3                               (HWREG16(0x4000201A))

#define UCB0ADDRX                                (HWREG16(0x4000201C))

#define UCB0ADDMASK                              (HWREG16(0x4000201E))

#define UCB0I2CSA                                (HWREG16(0x40002020))

#define UCB0IE                                   (HWREG16(0x4000202A))

#define UCB0IE_SPI                               (HWREG16(0x4000202A))

#define UCB0IFG                                  (HWREG16(0x4000202C))

#define UCB0IFG_SPI                              (HWREG16(0x4000202C))

#define UCB0IV                                   (HWREG16(0x4000202E))

#define UCB0IV_SPI                               (HWREG16(0x4000202E))


/* Register offsets from EUSCI_B0_BASE address */

#define OFS_UCB0CTLW0                                      (0x0000)

#define OFS_UCB0CTLW0_SPI                                  (0x0000)

#define OFS_UCB0CTLW1                                      (0x0002)

#define OFS_UCB0BRW                                        (0x0006)

#define OFS_UCB0BRW_SPI                                    (0x0006)

#define OFS_UCB0STATW                                      (0x0008)

#define OFS_UCB0STATW_SPI                                  (0x0008)

#define OFS_UCB0TBCNT                                      (0x000A)

#define OFS_UCB0RXBUF                                      (0x000C)

#define OFS_UCB0RXBUF_SPI                                  (0x000C)

#define OFS_UCB0TXBUF                                      (0x000E)

#define OFS_UCB0TXBUF_SPI                                  (0x000E)

#define OFS_UCB0I2COA0                                     (0x0014)

#define OFS_UCB0I2COA1                                     (0x0016)

#define OFS_UCB0I2COA2                                     (0x0018)

#define OFS_UCB0I2COA3                                     (0x001A)

#define OFS_UCB0ADDRX                                      (0x001C)

#define OFS_UCB0ADDMASK                                    (0x001E)

#define OFS_UCB0I2CSA                                      (0x0020)

#define OFS_UCB0IE                                         (0x002A)

#define OFS_UCB0IE_SPI                                     (0x002A)

#define OFS_UCB0IFG                                        (0x002C)

#define OFS_UCB0IFG_SPI                                    (0x002C)

#define OFS_UCB0IV                                         (0x002E)

#define OFS_UCB0IV_SPI                                     (0x002E)


#define UCB0CTL0                                           (HWREG8_L(UCB0CTLW0)) /* eUSCI_Bx Control 1 */

#define UCB0CTL1                                           (HWREG8_H(UCB0CTLW0)) /* eUSCI_Bx Control 0 */

#define UCB0BR0                                            (HWREG8_L(UCB0BRW))   /* eUSCI_Bx Bit Rate Control 0 */

#define UCB0BR1                                            (HWREG8_H(UCB0BRW))   /* eUSCI_Bx Bit Rate Control 1 */

#define UCB0STAT                                           (HWREG8_L(UCB0STATW)) /* eUSCI_Bx Status */

#define UCB0BCNT                                           (HWREG8_H(UCB0STATW)) /* eUSCI_Bx Byte Counter Register */


/******************************************************************************

* EUSCI_B1 Registers

******************************************************************************/

#define UCB1CTLW0                                (HWREG16(0x40002400))

#define UCB1CTLW0_SPI                            (HWREG16(0x40002400))

#define UCB1CTLW1                                (HWREG16(0x40002402))

#define UCB1BRW                                  (HWREG16(0x40002406))

#define UCB1BRW_SPI                              (HWREG16(0x40002406))

#define UCB1STATW                                (HWREG16(0x40002408))

#define UCB1STATW_SPI                            (HWREG16(0x40002408))

#define UCB1TBCNT                                (HWREG16(0x4000240A))

#define UCB1RXBUF                                (HWREG16(0x4000240C))

#define UCB1RXBUF_SPI                            (HWREG16(0x4000240C))

#define UCB1TXBUF                                (HWREG16(0x4000240E))

#define UCB1TXBUF_SPI                            (HWREG16(0x4000240E))

#define UCB1I2COA0                               (HWREG16(0x40002414))

#define UCB1I2COA1                               (HWREG16(0x40002416))

#define UCB1I2COA2                               (HWREG16(0x40002418))

#define UCB1I2COA3                               (HWREG16(0x4000241A))

#define UCB1ADDRX                                (HWREG16(0x4000241C))

#define UCB1ADDMASK                              (HWREG16(0x4000241E))

#define UCB1I2CSA                                (HWREG16(0x40002420))

#define UCB1IE                                   (HWREG16(0x4000242A))

#define UCB1IE_SPI                               (HWREG16(0x4000242A))

#define UCB1IFG                                  (HWREG16(0x4000242C))

#define UCB1IFG_SPI                              (HWREG16(0x4000242C))

#define UCB1IV                                   (HWREG16(0x4000242E))

#define UCB1IV_SPI                               (HWREG16(0x4000242E))


/* Register offsets from EUSCI_B1_BASE address */

#define OFS_UCB1CTLW0                                      (0x0000)

#define OFS_UCB1CTLW0_SPI                                  (0x0000)

#define OFS_UCB1CTLW1                                      (0x0002)

#define OFS_UCB1BRW                                        (0x0006)

#define OFS_UCB1BRW_SPI                                    (0x0006)

#define OFS_UCB1STATW                                      (0x0008)

#define OFS_UCB1STATW_SPI                                  (0x0008)

#define OFS_UCB1TBCNT                                      (0x000A)

#define OFS_UCB1RXBUF                                      (0x000C)

#define OFS_UCB1RXBUF_SPI                                  (0x000C)

#define OFS_UCB1TXBUF                                      (0x000E)

#define OFS_UCB1TXBUF_SPI                                  (0x000E)

#define OFS_UCB1I2COA0                                     (0x0014)

#define OFS_UCB1I2COA1                                     (0x0016)

#define OFS_UCB1I2COA2                                     (0x0018)

#define OFS_UCB1I2COA3                                     (0x001A)

#define OFS_UCB1ADDRX                                      (0x001C)

#define OFS_UCB1ADDMASK                                    (0x001E)

#define OFS_UCB1I2CSA                                      (0x0020)

#define OFS_UCB1IE                                         (0x002A)

#define OFS_UCB1IE_SPI                                     (0x002A)

#define OFS_UCB1IFG                                        (0x002C)

#define OFS_UCB1IFG_SPI                                    (0x002C)

#define OFS_UCB1IV                                         (0x002E)

#define OFS_UCB1IV_SPI                                     (0x002E)


#define UCB1CTL0                                           (HWREG8_L(UCB1CTLW0)) /* eUSCI_Bx Control 1 */

#define UCB1CTL1                                           (HWREG8_H(UCB1CTLW0)) /* eUSCI_Bx Control 0 */

#define UCB1BR0                                            (HWREG8_L(UCB1BRW))   /* eUSCI_Bx Bit Rate Control 0 */

#define UCB1BR1                                            (HWREG8_H(UCB1BRW))   /* eUSCI_Bx Bit Rate Control 1 */

#define UCB1STAT                                           (HWREG8_L(UCB1STATW)) /* eUSCI_Bx Status */

#define UCB1BCNT                                           (HWREG8_H(UCB1STATW)) /* eUSCI_Bx Byte Counter Register */


/******************************************************************************

* EUSCI_B2 Registers

******************************************************************************/

#define UCB2CTLW0                                (HWREG16(0x40002800))

#define UCB2CTLW0_SPI                            (HWREG16(0x40002800))

#define UCB2CTLW1                                (HWREG16(0x40002802))

#define UCB2BRW                                  (HWREG16(0x40002806))

#define UCB2BRW_SPI                              (HWREG16(0x40002806))

#define UCB2STATW                                (HWREG16(0x40002808))

#define UCB2STATW_SPI                            (HWREG16(0x40002808))

#define UCB2TBCNT                                (HWREG16(0x4000280A))

#define UCB2RXBUF                                (HWREG16(0x4000280C))

#define UCB2RXBUF_SPI                            (HWREG16(0x4000280C))

#define UCB2TXBUF                                (HWREG16(0x4000280E))

#define UCB2TXBUF_SPI                            (HWREG16(0x4000280E))

#define UCB2I2COA0                               (HWREG16(0x40002814))

#define UCB2I2COA1                               (HWREG16(0x40002816))

#define UCB2I2COA2                               (HWREG16(0x40002818))

#define UCB2I2COA3                               (HWREG16(0x4000281A))

#define UCB2ADDRX                                (HWREG16(0x4000281C))

#define UCB2ADDMASK                              (HWREG16(0x4000281E))

#define UCB2I2CSA                                (HWREG16(0x40002820))

#define UCB2IE                                   (HWREG16(0x4000282A))

#define UCB2IE_SPI                               (HWREG16(0x4000282A))

#define UCB2IFG                                  (HWREG16(0x4000282C))

#define UCB2IFG_SPI                              (HWREG16(0x4000282C))

#define UCB2IV                                   (HWREG16(0x4000282E))

#define UCB2IV_SPI                               (HWREG16(0x4000282E))


/* Register offsets from EUSCI_B2_BASE address */

#define OFS_UCB2CTLW0                                      (0x0000)

#define OFS_UCB2CTLW0_SPI                                  (0x0000)

#define OFS_UCB2CTLW1                                      (0x0002)

#define OFS_UCB2BRW                                        (0x0006)

#define OFS_UCB2BRW_SPI                                    (0x0006)

#define OFS_UCB2STATW                                      (0x0008)

#define OFS_UCB2STATW_SPI                                  (0x0008)

#define OFS_UCB2TBCNT                                      (0x000A)

#define OFS_UCB2RXBUF                                      (0x000C)

#define OFS_UCB2RXBUF_SPI                                  (0x000C)

#define OFS_UCB2TXBUF                                      (0x000E)

#define OFS_UCB2TXBUF_SPI                                  (0x000E)

#define OFS_UCB2I2COA0                                     (0x0014)

#define OFS_UCB2I2COA1                                     (0x0016)

#define OFS_UCB2I2COA2                                     (0x0018)

#define OFS_UCB2I2COA3                                     (0x001A)

#define OFS_UCB2ADDRX                                      (0x001C)

#define OFS_UCB2ADDMASK                                    (0x001E)

#define OFS_UCB2I2CSA                                      (0x0020)

#define OFS_UCB2IE                                         (0x002A)

#define OFS_UCB2IE_SPI                                     (0x002A)

#define OFS_UCB2IFG                                        (0x002C)

#define OFS_UCB2IFG_SPI                                    (0x002C)

#define OFS_UCB2IV                                         (0x002E)

#define OFS_UCB2IV_SPI                                     (0x002E)


#define UCB2CTL0                                           (HWREG8_L(UCB2CTLW0)) /* eUSCI_Bx Control 1 */

#define UCB2CTL1                                           (HWREG8_H(UCB2CTLW0)) /* eUSCI_Bx Control 0 */

#define UCB2BR0                                            (HWREG8_L(UCB2BRW))   /* eUSCI_Bx Bit Rate Control 0 */

#define UCB2BR1                                            (HWREG8_H(UCB2BRW))   /* eUSCI_Bx Bit Rate Control 1 */

#define UCB2STAT                                           (HWREG8_L(UCB2STATW)) /* eUSCI_Bx Status */

#define UCB2BCNT                                           (HWREG8_H(UCB2STATW)) /* eUSCI_Bx Byte Counter Register */


/******************************************************************************

* EUSCI_B3 Registers

******************************************************************************/

#define UCB3CTLW0                                (HWREG16(0x40002C00))

#define UCB3CTLW0_SPI                            (HWREG16(0x40002C00))

#define UCB3CTLW1                                (HWREG16(0x40002C02))

#define UCB3BRW                                  (HWREG16(0x40002C06))

#define UCB3BRW_SPI                              (HWREG16(0x40002C06))

#define UCB3STATW                                (HWREG16(0x40002C08))

#define UCB3STATW_SPI                            (HWREG16(0x40002C08))

#define UCB3TBCNT                                (HWREG16(0x40002C0A))

#define UCB3RXBUF                                (HWREG16(0x40002C0C))

#define UCB3RXBUF_SPI                            (HWREG16(0x40002C0C))

#define UCB3TXBUF                                (HWREG16(0x40002C0E))

#define UCB3TXBUF_SPI                            (HWREG16(0x40002C0E))

#define UCB3I2COA0                               (HWREG16(0x40002C14))

#define UCB3I2COA1                               (HWREG16(0x40002C16))

#define UCB3I2COA2                               (HWREG16(0x40002C18))

#define UCB3I2COA3                               (HWREG16(0x40002C1A))

#define UCB3ADDRX                                (HWREG16(0x40002C1C))

#define UCB3ADDMASK                              (HWREG16(0x40002C1E))

#define UCB3I2CSA                                (HWREG16(0x40002C20))

#define UCB3IE                                   (HWREG16(0x40002C2A))

#define UCB3IE_SPI                               (HWREG16(0x40002C2A))

#define UCB3IFG                                  (HWREG16(0x40002C2C))

#define UCB3IFG_SPI                              (HWREG16(0x40002C2C))

#define UCB3IV                                   (HWREG16(0x40002C2E))

#define UCB3IV_SPI                               (HWREG16(0x40002C2E))


/* Register offsets from EUSCI_B3_BASE address */

#define OFS_UCB3CTLW0                                      (0x0000)

#define OFS_UCB3CTLW0_SPI                                  (0x0000)

#define OFS_UCB3CTLW1                                      (0x0002)

#define OFS_UCB3BRW                                        (0x0006)

#define OFS_UCB3BRW_SPI                                    (0x0006)

#define OFS_UCB3STATW                                      (0x0008)

#define OFS_UCB3STATW_SPI                                  (0x0008)

#define OFS_UCB3TBCNT                                      (0x000A)

#define OFS_UCB3RXBUF                                      (0x000C)

#define OFS_UCB3RXBUF_SPI                                  (0x000C)

#define OFS_UCB3TXBUF                                      (0x000E)

#define OFS_UCB3TXBUF_SPI                                  (0x000E)

#define OFS_UCB3I2COA0                                     (0x0014)

#define OFS_UCB3I2COA1                                     (0x0016)

#define OFS_UCB3I2COA2                                     (0x0018)

#define OFS_UCB3I2COA3                                     (0x001A)

#define OFS_UCB3ADDRX                                      (0x001C)

#define OFS_UCB3ADDMASK                                    (0x001E)

#define OFS_UCB3I2CSA                                      (0x0020)

#define OFS_UCB3IE                                         (0x002A)

#define OFS_UCB3IE_SPI                                     (0x002A)

#define OFS_UCB3IFG                                        (0x002C)

#define OFS_UCB3IFG_SPI                                    (0x002C)

#define OFS_UCB3IV                                         (0x002E)

#define OFS_UCB3IV_SPI                                     (0x002E)


#define UCB3CTL0                                           (HWREG8_L(UCB3CTLW0)) /* eUSCI_Bx Control 1 */

#define UCB3CTL1                                           (HWREG8_H(UCB3CTLW0)) /* eUSCI_Bx Control 0 */

#define UCB3BR0                                            (HWREG8_L(UCB3BRW))   /* eUSCI_Bx Bit Rate Control 0 */

#define UCB3BR1                                            (HWREG8_H(UCB3BRW))   /* eUSCI_Bx Bit Rate Control 1 */

#define UCB3STAT                                           (HWREG8_L(UCB3STATW)) /* eUSCI_Bx Status */

#define UCB3BCNT                                           (HWREG8_H(UCB3STATW)) /* eUSCI_Bx Byte Counter Register */


/******************************************************************************

* PMAP Registers

******************************************************************************/

#define PMAPKEYID                                (HWREG16(0x40005000))

#define PMAPCTL                                  (HWREG16(0x40005002))

#define P1MAP01                                  (HWREG16(0x40005008))

#define P1MAP23                                  (HWREG16(0x4000500A))

#define P1MAP45                                  (HWREG16(0x4000500C))

#define P1MAP67                                  (HWREG16(0x4000500E))

#define P2MAP01                                  (HWREG16(0x40005010))

#define P2MAP23                                  (HWREG16(0x40005012))

#define P2MAP45                                  (HWREG16(0x40005014))

#define P2MAP67                                  (HWREG16(0x40005016))

#define P3MAP01                                  (HWREG16(0x40005018))

#define P3MAP23                                  (HWREG16(0x4000501A))

#define P3MAP45                                  (HWREG16(0x4000501C))

#define P3MAP67                                  (HWREG16(0x4000501E))

#define P4MAP01                                  (HWREG16(0x40005020))

#define P4MAP23                                  (HWREG16(0x40005022))

#define P4MAP45                                  (HWREG16(0x40005024))

#define P4MAP67                                  (HWREG16(0x40005026))

#define P5MAP01                                  (HWREG16(0x40005028))

#define P5MAP23                                  (HWREG16(0x4000502A))

#define P5MAP45                                  (HWREG16(0x4000502C))

#define P5MAP67                                  (HWREG16(0x4000502E))

#define P6MAP01                                  (HWREG16(0x40005030))

#define P6MAP23                                  (HWREG16(0x40005032))

#define P6MAP45                                  (HWREG16(0x40005034))

#define P6MAP67                                  (HWREG16(0x40005036))

#define P7MAP01                                  (HWREG16(0x40005038))

#define P7MAP23                                  (HWREG16(0x4000503A))

#define P7MAP45                                  (HWREG16(0x4000503C))

#define P7MAP67                                  (HWREG16(0x4000503E))

/* Register offsets from PMAP_BASE address */

#define OFS_PMAPKEYID                                      (0x0000)

#define OFS_PMAPCTL                                        (0x0002)

#define OFS_P1MAP01                                        (0x0008)

#define OFS_P1MAP23                                        (0x000A)

#define OFS_P1MAP45                                        (0x000C)

#define OFS_P1MAP67                                        (0x000E)

#define OFS_P2MAP01                                        (0x0010)

#define OFS_P2MAP23                                        (0x0012)

#define OFS_P2MAP45                                        (0x0014)

#define OFS_P2MAP67                                        (0x0016)

#define OFS_P3MAP01                                        (0x0018)

#define OFS_P3MAP23                                        (0x001A)

#define OFS_P3MAP45                                        (0x001C)

#define OFS_P3MAP67                                        (0x001E)

#define OFS_P4MAP01                                        (0x0020)

#define OFS_P4MAP23                                        (0x0022)

#define OFS_P4MAP45                                        (0x0024)

#define OFS_P4MAP67                                        (0x0026)

#define OFS_P5MAP01                                        (0x0028)

#define OFS_P5MAP23                                        (0x002A)

#define OFS_P5MAP45                                        (0x002C)

#define OFS_P5MAP67                                        (0x002E)

#define OFS_P6MAP01                                        (0x0030)

#define OFS_P6MAP23                                        (0x0032)

#define OFS_P6MAP45                                        (0x0034)

#define OFS_P6MAP67                                        (0x0036)

#define OFS_P7MAP01                                        (0x0038)

#define OFS_P7MAP23                                        (0x003A)

#define OFS_P7MAP45                                        (0x003C)

#define OFS_P7MAP67                                        (0x003E)

/******************************************************************************

* REF_A Registers

******************************************************************************/

#define REFCTL0                                  (HWREG16(0x40003000))

/* Register offsets from REF_A_BASE address */

#define OFS_REFCTL0                                        (0x0000)

#define REFCTL0_L                                          (HWREG8_L(REFCTL0))   /* REF Control Register 0 */

#define REFCTL0_H                                          (HWREG8_H(REFCTL0))   /* REF Control Register 0 */


/******************************************************************************

* RTC_C Registers

******************************************************************************/

#define RTCCTL0                                  (HWREG16(0x40004400))

#define RTCCTL13                                 (HWREG16(0x40004402))

#define RTCOCAL                                  (HWREG16(0x40004404))

#define RTCTCMP                                  (HWREG16(0x40004406))

#define RTCPS0CTL                                (HWREG16(0x40004408))

#define RTCPS1CTL                                (HWREG16(0x4000440A))

#define RTCPS                                    (HWREG16(0x4000440C))

#define RTCIV                                    (HWREG16(0x4000440E))

#define RTCTIM0                                  (HWREG16(0x40004410))

#define RTCTIM0_BCD                              (HWREG16(0x40004410))

#define RTCTIM1                                  (HWREG16(0x40004412))

#define RTCTIM1_BCD                              (HWREG16(0x40004412))

#define RTCDATE                                  (HWREG16(0x40004414))

#define RTCDATE_BCD                              (HWREG16(0x40004414))

#define RTCYEAR                                  (HWREG16(0x40004416))

#define RTCYEAR_BCD                              (HWREG16(0x40004416))

#define RTCAMINHR                                (HWREG16(0x40004418))

#define RTCAMINHR_BCD                            (HWREG16(0x40004418))

#define RTCADOWDAY                               (HWREG16(0x4000441A))

#define RTCADOWDAY_BCD                           (HWREG16(0x4000441A))

#define RTCBIN2BCD                               (HWREG16(0x4000441C))

#define RTCBCD2BIN                               (HWREG16(0x4000441E))

/* Register offsets from RTC_C_BASE address */

#define OFS_RTCCTL0                                        (0x0000)

#define OFS_RTCCTL13                                       (0x0002)

#define OFS_RTCOCAL                                        (0x0004)

#define OFS_RTCTCMP                                        (0x0006)

#define OFS_RTCPS0CTL                                      (0x0008)

#define OFS_RTCPS1CTL                                      (0x000A)

#define OFS_RTCPS                                          (0x000C)

#define OFS_RTCIV                                          (0x000E)

#define OFS_RTCTIM0                                        (0x0010)

#define OFS_RTCTIM0_BCD                                    (0x0010)

#define OFS_RTCTIM1                                        (0x0012)

#define OFS_RTCTIM1_BCD                                    (0x0012)

#define OFS_RTCDATE                                        (0x0014)

#define OFS_RTCDATE_BCD                                    (0x0014)

#define OFS_RTCYEAR                                        (0x0016)

#define OFS_RTCYEAR_BCD                                    (0x0016)

#define OFS_RTCAMINHR                                      (0x0018)

#define OFS_RTCAMINHR_BCD                                  (0x0018)

#define OFS_RTCADOWDAY                                     (0x001A)

#define OFS_RTCADOWDAY_BCD                                 (0x001A)

#define OFS_RTCBIN2BCD                                     (0x001C)

#define OFS_RTCBCD2BIN                                     (0x001E)

#define RTCCTL0_L                                          (HWREG8_L(RTCCTL0))   /* RTCCTL0 Register */

#define RTCCTL0_H                                          (HWREG8_H(RTCCTL0))   /* RTCCTL0 Register */

#define RTCCTL1                                            (HWREG8_L(RTCCTL13))  /* RTCCTL13 Register */

#define RTCCTL13_L                                         (HWREG8_L(RTCCTL13))  /* RTCCTL13 Register */

#define RTCCTL3                                            (HWREG8_H(RTCCTL13))  /* RTCCTL13 Register */

#define RTCCTL13_H                                         (HWREG8_H(RTCCTL13))  /* RTCCTL13 Register */

#define RTCOCAL_L                                          (HWREG8_L(RTCOCAL))   /* RTCOCAL Register */

#define RTCOCAL_H                                          (HWREG8_H(RTCOCAL))   /* RTCOCAL Register */

#define RTCTCMP_L                                          (HWREG8_L(RTCTCMP))   /* RTCTCMP Register */

#define RTCTCMP_H                                          (HWREG8_H(RTCTCMP))   /* RTCTCMP Register */

#define RTCPS0CTL_L                                        (HWREG8_L(RTCPS0CTL)) /* Real-Time Clock Prescale Timer 0 Control Register */

#define RTCPS0CTL_H                                        (HWREG8_H(RTCPS0CTL)) /* Real-Time Clock Prescale Timer 0 Control Register */

#define RTCPS1CTL_L                                        (HWREG8_L(RTCPS1CTL)) /* Real-Time Clock Prescale Timer 1 Control Register */

#define RTCPS1CTL_H                                        (HWREG8_H(RTCPS1CTL)) /* Real-Time Clock Prescale Timer 1 Control Register */

#define RTCPS0                                             (HWREG8_L(RTCPS))     /* Real-Time Clock Prescale Timer Counter Register */

#define RTCPS_L                                            (HWREG8_L(RTCPS))     /* Real-Time Clock Prescale Timer Counter Register */

#define RTCPS1                                             (HWREG8_H(RTCPS))     /* Real-Time Clock Prescale Timer Counter Register */

#define RTCPS_H                                            (HWREG8_H(RTCPS))     /* Real-Time Clock Prescale Timer Counter Register */

#define RTCSEC                                             (HWREG8_L(RTCTIM0))   /* Real-Time Clock Seconds */

#define RTCTIM0_L                                          (HWREG8_L(RTCTIM0))   /* Real-Time Clock Seconds */

#define RTCMIN                                             (HWREG8_H(RTCTIM0))   /* Real-Time Clock Minutes */

#define RTCTIM0_H                                          (HWREG8_H(RTCTIM0))   /* Real-Time Clock Minutes */

#define RTCHOUR                                            (HWREG8_L(RTCTIM1))   /* Real-Time Clock Hour */

#define RTCTIM1_L                                          (HWREG8_L(RTCTIM1))   /* Real-Time Clock Hour */

#define RTCDOW                                             (HWREG8_H(RTCTIM1))   /* Real-Time Clock Day of Week */

#define RTCTIM1_H                                          (HWREG8_H(RTCTIM1))   /* Real-Time Clock Day of Week */

#define RTCDAY                                             (HWREG8_L(RTCDATE))   /* Real-Time Clock Day of Month */

#define RTCDATE_L                                          (HWREG8_L(RTCDATE))   /* Real-Time Clock Day of Month */

#define RTCMON                                             (HWREG8_H(RTCDATE))   /* Real-Time Clock Month */

#define RTCDATE_H                                          (HWREG8_H(RTCDATE))   /* Real-Time Clock Month */

#define RTCAMIN                                            (HWREG8_L(RTCAMINHR)) /* Real-Time Clock Minutes Alarm */

#define RTCAMINHR_L                                        (HWREG8_L(RTCAMINHR)) /* Real-Time Clock Minutes Alarm */

#define RTCAHOUR                                           (HWREG8_H(RTCAMINHR)) /* Real-Time Clock Hours Alarm */

#define RTCAMINHR_H                                        (HWREG8_H(RTCAMINHR)) /* Real-Time Clock Hours Alarm */

#define RTCADOW                                            (HWREG8_L(RTCADOWDAY))/* Real-Time Clock Day of Week Alarm */

#define RTCADOWDAY_L                                       (HWREG8_L(RTCADOWDAY))/* Real-Time Clock Day of Week Alarm */

#define RTCADAY                                            (HWREG8_H(RTCADOWDAY))/* Real-Time Clock Day of Month Alarm */

#define RTCADOWDAY_H                                       (HWREG8_H(RTCADOWDAY))/* Real-Time Clock Day of Month Alarm */


/******************************************************************************

* TIMER_A0 Registers

******************************************************************************/

#define TA0CTL                                   (HWREG16(0x40000000))

#define TA0CCTL0                                 (HWREG16(0x40000002))

#define TA0CCTL1                                 (HWREG16(0x40000004))

#define TA0CCTL2                                 (HWREG16(0x40000006))

#define TA0CCTL3                                 (HWREG16(0x40000008))

#define TA0CCTL4                                 (HWREG16(0x4000000A))

#define TA0R                                     (HWREG16(0x40000010))

#define TA0CCR0                                  (HWREG16(0x40000012))

#define TA0CCR1                                  (HWREG16(0x40000014))

#define TA0CCR2                                  (HWREG16(0x40000016))

#define TA0CCR3                                  (HWREG16(0x40000018))

#define TA0CCR4                                  (HWREG16(0x4000001A))

#define TA0EX0                                   (HWREG16(0x40000020))

#define TA0IV                                    (HWREG16(0x4000002E))

/* Register offsets from TIMER_A0_BASE address */

#define OFS_TA0CTL                                         (0x0000)

#define OFS_TA0CCTL0                                       (0x0002)

#define OFS_TA0CCTL1                                       (0x0004)

#define OFS_TA0CCTL2                                       (0x0006)

#define OFS_TA0CCTL3                                       (0x0008)

#define OFS_TA0CCTL4                                       (0x000A)

#define OFS_TA0R                                           (0x0010)

#define OFS_TA0CCR0                                        (0x0012)

#define OFS_TA0CCR1                                        (0x0014)

#define OFS_TA0CCR2                                        (0x0016)

#define OFS_TA0CCR3                                        (0x0018)

#define OFS_TA0CCR4                                        (0x001A)

#define OFS_TA0EX0                                         (0x0020)

#define OFS_TA0IV                                          (0x002E)

/******************************************************************************

* TIMER_A1 Registers

******************************************************************************/

#define TA1CTL                                   (HWREG16(0x40000400))

#define TA1CCTL0                                 (HWREG16(0x40000402))

#define TA1CCTL1                                 (HWREG16(0x40000404))

#define TA1CCTL2                                 (HWREG16(0x40000406))

#define TA1CCTL3                                 (HWREG16(0x40000408))

#define TA1CCTL4                                 (HWREG16(0x4000040A))

#define TA1R                                     (HWREG16(0x40000410))

#define TA1CCR0                                  (HWREG16(0x40000412))

#define TA1CCR1                                  (HWREG16(0x40000414))

#define TA1CCR2                                  (HWREG16(0x40000416))

#define TA1CCR3                                  (HWREG16(0x40000418))

#define TA1CCR4                                  (HWREG16(0x4000041A))

#define TA1EX0                                   (HWREG16(0x40000420))

#define TA1IV                                    (HWREG16(0x4000042E))

/* Register offsets from TIMER_A1_BASE address */

#define OFS_TA1CTL                                         (0x0000)

#define OFS_TA1CCTL0                                       (0x0002)

#define OFS_TA1CCTL1                                       (0x0004)

#define OFS_TA1CCTL2                                       (0x0006)

#define OFS_TA1CCTL3                                       (0x0008)

#define OFS_TA1CCTL4                                       (0x000A)

#define OFS_TA1R                                           (0x0010)

#define OFS_TA1CCR0                                        (0x0012)

#define OFS_TA1CCR1                                        (0x0014)

#define OFS_TA1CCR2                                        (0x0016)

#define OFS_TA1CCR3                                        (0x0018)

#define OFS_TA1CCR4                                        (0x001A)

#define OFS_TA1EX0                                         (0x0020)

#define OFS_TA1IV                                          (0x002E)

/******************************************************************************

* TIMER_A2 Registers

******************************************************************************/

#define TA2CTL                                   (HWREG16(0x40000800))

#define TA2CCTL0                                 (HWREG16(0x40000802))

#define TA2CCTL1                                 (HWREG16(0x40000804))

#define TA2CCTL2                                 (HWREG16(0x40000806))

#define TA2CCTL3                                 (HWREG16(0x40000808))

#define TA2CCTL4                                 (HWREG16(0x4000080A))

#define TA2R                                     (HWREG16(0x40000810))

#define TA2CCR0                                  (HWREG16(0x40000812))

#define TA2CCR1                                  (HWREG16(0x40000814))

#define TA2CCR2                                  (HWREG16(0x40000816))

#define TA2CCR3                                  (HWREG16(0x40000818))

#define TA2CCR4                                  (HWREG16(0x4000081A))

#define TA2EX0                                   (HWREG16(0x40000820))

#define TA2IV                                    (HWREG16(0x4000082E))

/* Register offsets from TIMER_A2_BASE address */

#define OFS_TA2CTL                                         (0x0000)

#define OFS_TA2CCTL0                                       (0x0002)

#define OFS_TA2CCTL1                                       (0x0004)

#define OFS_TA2CCTL2                                       (0x0006)

#define OFS_TA2CCTL3                                       (0x0008)

#define OFS_TA2CCTL4                                       (0x000A)

#define OFS_TA2R                                           (0x0010)

#define OFS_TA2CCR0                                        (0x0012)

#define OFS_TA2CCR1                                        (0x0014)

#define OFS_TA2CCR2                                        (0x0016)

#define OFS_TA2CCR3                                        (0x0018)

#define OFS_TA2CCR4                                        (0x001A)

#define OFS_TA2EX0                                         (0x0020)

#define OFS_TA2IV                                          (0x002E)

/******************************************************************************

* TIMER_A3 Registers

******************************************************************************/

#define TA3CTL                                   (HWREG16(0x40000C00))

#define TA3CCTL0                                 (HWREG16(0x40000C02))

#define TA3CCTL1                                 (HWREG16(0x40000C04))

#define TA3CCTL2                                 (HWREG16(0x40000C06))

#define TA3CCTL3                                 (HWREG16(0x40000C08))

#define TA3CCTL4                                 (HWREG16(0x40000C0A))

#define TA3R                                     (HWREG16(0x40000C10))

#define TA3CCR0                                  (HWREG16(0x40000C12))

#define TA3CCR1                                  (HWREG16(0x40000C14))

#define TA3CCR2                                  (HWREG16(0x40000C16))

#define TA3CCR3                                  (HWREG16(0x40000C18))

#define TA3CCR4                                  (HWREG16(0x40000C1A))

#define TA3EX0                                   (HWREG16(0x40000C20))

#define TA3IV                                    (HWREG16(0x40000C2E))

/* Register offsets from TIMER_A3_BASE address */

#define OFS_TA3CTL                                         (0x0000)

#define OFS_TA3CCTL0                                       (0x0002)

#define OFS_TA3CCTL1                                       (0x0004)

#define OFS_TA3CCTL2                                       (0x0006)

#define OFS_TA3CCTL3                                       (0x0008)

#define OFS_TA3CCTL4                                       (0x000A)

#define OFS_TA3R                                           (0x0010)

#define OFS_TA3CCR0                                        (0x0012)

#define OFS_TA3CCR1                                        (0x0014)

#define OFS_TA3CCR2                                        (0x0016)

#define OFS_TA3CCR3                                        (0x0018)

#define OFS_TA3CCR4                                        (0x001A)

#define OFS_TA3EX0                                         (0x0020)

#define OFS_TA3IV                                          (0x002E)

/******************************************************************************

* WDT_A Registers

******************************************************************************/

#define WDTCTL                                   (HWREG16(0x4000480C))

/* Register offsets from WDT_A_BASE address */

#define OFS_WDTCTL                                         (0x000C)

/******************************************************************************

* Peripheral register control bits (legacy section)                           *

******************************************************************************/


/******************************************************************************

* AES256 Bits (legacy section)

******************************************************************************/

/* AESACTL0[AESOP] Bits */

#define AESOP_OFS                                AES256_CTL0_OP_OFS

#define AESOP_M                                  AES256_CTL0_OP_MASK

#define AESOP0                                   AES256_CTL0_OP0

#define AESOP1                                   AES256_CTL0_OP1

#define AESOP_0                                  AES256_CTL0_OP_0

#define AESOP_1                                  AES256_CTL0_OP_1

#define AESOP_2                                  AES256_CTL0_OP_2

#define AESOP_3                                  AES256_CTL0_OP_3

/* AESACTL0[AESKL] Bits */

#define AESKL_OFS                                AES256_CTL0_KL_OFS

#define AESKL_M                                  AES256_CTL0_KL_MASK

#define AESKL0                                   AES256_CTL0_KL0

#define AESKL1                                   AES256_CTL0_KL1

#define AESKL_0                                  AES256_CTL0_KL_0

#define AESKL_1                                  AES256_CTL0_KL_1

#define AESKL_2                                  AES256_CTL0_KL_2

#define AESKL__128BIT                            AES256_CTL0_KL__128BIT

#define AESKL__192BIT                            AES256_CTL0_KL__192BIT

#define AESKL__256BIT                            AES256_CTL0_KL__256BIT

/* AESACTL0[AESCM] Bits */

#define AESCM_OFS                                AES256_CTL0_CM_OFS

#define AESCM_M                                  AES256_CTL0_CM_MASK

#define AESCM0                                   AES256_CTL0_CM0

#define AESCM1                                   AES256_CTL0_CM1

#define AESCM_0                                  AES256_CTL0_CM_0

#define AESCM_1                                  AES256_CTL0_CM_1

#define AESCM_2                                  AES256_CTL0_CM_2

#define AESCM_3                                  AES256_CTL0_CM_3

#define AESCM__ECB                               AES256_CTL0_CM__ECB

#define AESCM__CBC                               AES256_CTL0_CM__CBC

#define AESCM__OFB                               AES256_CTL0_CM__OFB

#define AESCM__CFB                               AES256_CTL0_CM__CFB

/* AESACTL0[AESSWRST] Bits */

#define AESSWRST_OFS                             AES256_CTL0_SWRST_OFS

#define AESSWRST                                 AES256_CTL0_SWRST

/* AESACTL0[AESRDYIFG] Bits */

#define AESRDYIFG_OFS                            AES256_CTL0_RDYIFG_OFS

#define AESRDYIFG                                AES256_CTL0_RDYIFG

/* AESACTL0[AESERRFG] Bits */

#define AESERRFG_OFS                             AES256_CTL0_ERRFG_OFS

#define AESERRFG                                 AES256_CTL0_ERRFG

/* AESACTL0[AESRDYIE] Bits */

#define AESRDYIE_OFS                             AES256_CTL0_RDYIE_OFS

#define AESRDYIE                                 AES256_CTL0_RDYIE

/* AESACTL0[AESCMEN] Bits */

#define AESCMEN_OFS                              AES256_CTL0_CMEN_OFS

#define AESCMEN                                  AES256_CTL0_CMEN

/* AESACTL1[AESBLKCNT] Bits */

#define AESBLKCNT_OFS                            AES256_CTL1_BLKCNT_OFS

#define AESBLKCNT_M                              AES256_CTL1_BLKCNT_MASK

#define AESBLKCNT0                               AES256_CTL1_BLKCNT0

#define AESBLKCNT1                               AES256_CTL1_BLKCNT1

#define AESBLKCNT2                               AES256_CTL1_BLKCNT2

#define AESBLKCNT3                               AES256_CTL1_BLKCNT3

#define AESBLKCNT4                               AES256_CTL1_BLKCNT4

#define AESBLKCNT5                               AES256_CTL1_BLKCNT5

#define AESBLKCNT6                               AES256_CTL1_BLKCNT6

#define AESBLKCNT7                               AES256_CTL1_BLKCNT7

/* AESASTAT[AESBUSY] Bits */

#define AESBUSY_OFS                              AES256_STAT_BUSY_OFS

#define AESBUSY                                  AES256_STAT_BUSY

/* AESASTAT[AESKEYWR] Bits */

#define AESKEYWR_OFS                             AES256_STAT_KEYWR_OFS

#define AESKEYWR                                 AES256_STAT_KEYWR

/* AESASTAT[AESDINWR] Bits */

#define AESDINWR_OFS                             AES256_STAT_DINWR_OFS

#define AESDINWR                                 AES256_STAT_DINWR

/* AESASTAT[AESDOUTRD] Bits */

#define AESDOUTRD_OFS                            AES256_STAT_DOUTRD_OFS

#define AESDOUTRD                                AES256_STAT_DOUTRD

/* AESASTAT[AESKEYCNT] Bits */

#define AESKEYCNT_OFS                            AES256_STAT_KEYCNT_OFS

#define AESKEYCNT_M                              AES256_STAT_KEYCNT_MASK

#define AESKEYCNT0                               AES256_STAT_KEYCNT0

#define AESKEYCNT1                               AES256_STAT_KEYCNT1

#define AESKEYCNT2                               AES256_STAT_KEYCNT2

#define AESKEYCNT3                               AES256_STAT_KEYCNT3

/* AESASTAT[AESDINCNT] Bits */

#define AESDINCNT_OFS                            AES256_STAT_DINCNT_OFS

#define AESDINCNT_M                              AES256_STAT_DINCNT_MASK

#define AESDINCNT0                               AES256_STAT_DINCNT0

#define AESDINCNT1                               AES256_STAT_DINCNT1

#define AESDINCNT2                               AES256_STAT_DINCNT2

#define AESDINCNT3                               AES256_STAT_DINCNT3

/* AESASTAT[AESDOUTCNT] Bits */

#define AESDOUTCNT_OFS                           AES256_STAT_DOUTCNT_OFS

#define AESDOUTCNT_M                             AES256_STAT_DOUTCNT_MASK

#define AESDOUTCNT0                              AES256_STAT_DOUTCNT0

#define AESDOUTCNT1                              AES256_STAT_DOUTCNT1

#define AESDOUTCNT2                              AES256_STAT_DOUTCNT2

#define AESDOUTCNT3                              AES256_STAT_DOUTCNT3

/* AESAKEY[AESKEY0] Bits */

#define AESKEY0_OFS                              AES256_KEY_KEY0_OFS

#define AESKEY0_M                                AES256_KEY_KEY0_MASK

#define AESKEY00                                 AES256_KEY_KEY00

#define AESKEY01                                 AES256_KEY_KEY01

#define AESKEY02                                 AES256_KEY_KEY02

#define AESKEY03                                 AES256_KEY_KEY03

#define AESKEY04                                 AES256_KEY_KEY04

#define AESKEY05                                 AES256_KEY_KEY05

#define AESKEY06                                 AES256_KEY_KEY06

#define AESKEY07                                 AES256_KEY_KEY07

/* AESAKEY[AESKEY1] Bits */

#define AESKEY1_OFS                              AES256_KEY_KEY1_OFS

#define AESKEY1_M                                AES256_KEY_KEY1_MASK

#define AESKEY10                                 AES256_KEY_KEY10

#define AESKEY11                                 AES256_KEY_KEY11

#define AESKEY12                                 AES256_KEY_KEY12

#define AESKEY13                                 AES256_KEY_KEY13

#define AESKEY14                                 AES256_KEY_KEY14

#define AESKEY15                                 AES256_KEY_KEY15

#define AESKEY16                                 AES256_KEY_KEY16

#define AESKEY17                                 AES256_KEY_KEY17

/* AESADIN[AESDIN0] Bits */

#define AESDIN0_OFS                              AES256_DIN_DIN0_OFS

#define AESDIN0_M                                AES256_DIN_DIN0_MASK

#define AESDIN00                                 AES256_DIN_DIN00

#define AESDIN01                                 AES256_DIN_DIN01

#define AESDIN02                                 AES256_DIN_DIN02

#define AESDIN03                                 AES256_DIN_DIN03

#define AESDIN04                                 AES256_DIN_DIN04

#define AESDIN05                                 AES256_DIN_DIN05

#define AESDIN06                                 AES256_DIN_DIN06

#define AESDIN07                                 AES256_DIN_DIN07

/* AESADIN[AESDIN1] Bits */

#define AESDIN1_OFS                              AES256_DIN_DIN1_OFS

#define AESDIN1_M                                AES256_DIN_DIN1_MASK

#define AESDIN10                                 AES256_DIN_DIN10

#define AESDIN11                                 AES256_DIN_DIN11

#define AESDIN12                                 AES256_DIN_DIN12

#define AESDIN13                                 AES256_DIN_DIN13

#define AESDIN14                                 AES256_DIN_DIN14

#define AESDIN15                                 AES256_DIN_DIN15

#define AESDIN16                                 AES256_DIN_DIN16

#define AESDIN17                                 AES256_DIN_DIN17

/* AESADOUT[AESDOUT0] Bits */

#define AESDOUT0_OFS                             AES256_DOUT_DOUT0_OFS

#define AESDOUT0_M                               AES256_DOUT_DOUT0_MASK

#define AESDOUT00                                AES256_DOUT_DOUT00

#define AESDOUT01                                AES256_DOUT_DOUT01

#define AESDOUT02                                AES256_DOUT_DOUT02

#define AESDOUT03                                AES256_DOUT_DOUT03

#define AESDOUT04                                AES256_DOUT_DOUT04

#define AESDOUT05                                AES256_DOUT_DOUT05

#define AESDOUT06                                AES256_DOUT_DOUT06

#define AESDOUT07                                AES256_DOUT_DOUT07

/* AESADOUT[AESDOUT1] Bits */

#define AESDOUT1_OFS                             AES256_DOUT_DOUT1_OFS

#define AESDOUT1_M                               AES256_DOUT_DOUT1_MASK

#define AESDOUT10                                AES256_DOUT_DOUT10

#define AESDOUT11                                AES256_DOUT_DOUT11

#define AESDOUT12                                AES256_DOUT_DOUT12

#define AESDOUT13                                AES256_DOUT_DOUT13

#define AESDOUT14                                AES256_DOUT_DOUT14

#define AESDOUT15                                AES256_DOUT_DOUT15

#define AESDOUT16                                AES256_DOUT_DOUT16

#define AESDOUT17                                AES256_DOUT_DOUT17

/* AESAXDIN[AESXDIN0] Bits */

#define AESXDIN0_OFS                             AES256_XDIN_XDIN0_OFS

#define AESXDIN0_M                               AES256_XDIN_XDIN0_MASK

#define AESXDIN00                                AES256_XDIN_XDIN00

#define AESXDIN01                                AES256_XDIN_XDIN01

#define AESXDIN02                                AES256_XDIN_XDIN02

#define AESXDIN03                                AES256_XDIN_XDIN03

#define AESXDIN04                                AES256_XDIN_XDIN04

#define AESXDIN05                                AES256_XDIN_XDIN05

#define AESXDIN06                                AES256_XDIN_XDIN06

#define AESXDIN07                                AES256_XDIN_XDIN07

/* AESAXDIN[AESXDIN1] Bits */

#define AESXDIN1_OFS                             AES256_XDIN_XDIN1_OFS

#define AESXDIN1_M                               AES256_XDIN_XDIN1_MASK

#define AESXDIN10                                AES256_XDIN_XDIN10

#define AESXDIN11                                AES256_XDIN_XDIN11

#define AESXDIN12                                AES256_XDIN_XDIN12

#define AESXDIN13                                AES256_XDIN_XDIN13

#define AESXDIN14                                AES256_XDIN_XDIN14

#define AESXDIN15                                AES256_XDIN_XDIN15

#define AESXDIN16                                AES256_XDIN_XDIN16

#define AESXDIN17                                AES256_XDIN_XDIN17

/* AESAXIN[AESXIN0] Bits */

#define AESXIN0_OFS                              AES256_XIN_XIN0_OFS

#define AESXIN0_M                                AES256_XIN_XIN0_MASK

#define AESXIN00                                 AES256_XIN_XIN00

#define AESXIN01                                 AES256_XIN_XIN01

#define AESXIN02                                 AES256_XIN_XIN02

#define AESXIN03                                 AES256_XIN_XIN03

#define AESXIN04                                 AES256_XIN_XIN04

#define AESXIN05                                 AES256_XIN_XIN05

#define AESXIN06                                 AES256_XIN_XIN06

#define AESXIN07                                 AES256_XIN_XIN07

/* AESAXIN[AESXIN1] Bits */

#define AESXIN1_OFS                              AES256_XIN_XIN1_OFS

#define AESXIN1_M                                AES256_XIN_XIN1_MASK

#define AESXIN10                                 AES256_XIN_XIN10

#define AESXIN11                                 AES256_XIN_XIN11

#define AESXIN12                                 AES256_XIN_XIN12

#define AESXIN13                                 AES256_XIN_XIN13

#define AESXIN14                                 AES256_XIN_XIN14

#define AESXIN15                                 AES256_XIN_XIN15

#define AESXIN16                                 AES256_XIN_XIN16

#define AESXIN17                                 AES256_XIN_XIN17

/******************************************************************************

* CAPTIO Bits (legacy section)

******************************************************************************/

/* CAPTIO0CTL[CAPTIOPISEL] Bits */

#define CAPTIOPISEL_OFS                          CAPTIO_CTL_PISEL_OFS

#define CAPTIOPISEL_M                            CAPTIO_CTL_PISEL_MASK

#define CAPTIOPISEL0                             CAPTIO_CTL_PISEL0

#define CAPTIOPISEL1                             CAPTIO_CTL_PISEL1

#define CAPTIOPISEL2                             CAPTIO_CTL_PISEL2

#define CAPTIOPISEL_0                            CAPTIO_CTL_PISEL_0

#define CAPTIOPISEL_1                            CAPTIO_CTL_PISEL_1

#define CAPTIOPISEL_2                            CAPTIO_CTL_PISEL_2

#define CAPTIOPISEL_3                            CAPTIO_CTL_PISEL_3

#define CAPTIOPISEL_4                            CAPTIO_CTL_PISEL_4

#define CAPTIOPISEL_5                            CAPTIO_CTL_PISEL_5

#define CAPTIOPISEL_6                            CAPTIO_CTL_PISEL_6

#define CAPTIOPISEL_7                            CAPTIO_CTL_PISEL_7

/* CAPTIO0CTL[CAPTIOPOSEL] Bits */

#define CAPTIOPOSEL_OFS                          CAPTIO_CTL_POSEL_OFS

#define CAPTIOPOSEL_M                            CAPTIO_CTL_POSEL_MASK

#define CAPTIOPOSEL0                             CAPTIO_CTL_POSEL0

#define CAPTIOPOSEL1                             CAPTIO_CTL_POSEL1

#define CAPTIOPOSEL2                             CAPTIO_CTL_POSEL2

#define CAPTIOPOSEL3                             CAPTIO_CTL_POSEL3

#define CAPTIOPOSEL_0                            CAPTIO_CTL_POSEL_0

#define CAPTIOPOSEL_1                            CAPTIO_CTL_POSEL_1

#define CAPTIOPOSEL_2                            CAPTIO_CTL_POSEL_2

#define CAPTIOPOSEL_3                            CAPTIO_CTL_POSEL_3

#define CAPTIOPOSEL_4                            CAPTIO_CTL_POSEL_4

#define CAPTIOPOSEL_5                            CAPTIO_CTL_POSEL_5

#define CAPTIOPOSEL_6                            CAPTIO_CTL_POSEL_6

#define CAPTIOPOSEL_7                            CAPTIO_CTL_POSEL_7

#define CAPTIOPOSEL_8                            CAPTIO_CTL_POSEL_8

#define CAPTIOPOSEL_9                            CAPTIO_CTL_POSEL_9

#define CAPTIOPOSEL_10                           CAPTIO_CTL_POSEL_10

#define CAPTIOPOSEL_11                           CAPTIO_CTL_POSEL_11

#define CAPTIOPOSEL_12                           CAPTIO_CTL_POSEL_12

#define CAPTIOPOSEL_13                           CAPTIO_CTL_POSEL_13

#define CAPTIOPOSEL_14                           CAPTIO_CTL_POSEL_14

#define CAPTIOPOSEL_15                           CAPTIO_CTL_POSEL_15

#define CAPTIOPOSEL__PJ                          CAPTIO_CTL_POSEL__PJ

#define CAPTIOPOSEL__P1                          CAPTIO_CTL_POSEL__P1

#define CAPTIOPOSEL__P2                          CAPTIO_CTL_POSEL__P2

#define CAPTIOPOSEL__P3                          CAPTIO_CTL_POSEL__P3

#define CAPTIOPOSEL__P4                          CAPTIO_CTL_POSEL__P4

#define CAPTIOPOSEL__P5                          CAPTIO_CTL_POSEL__P5

#define CAPTIOPOSEL__P6                          CAPTIO_CTL_POSEL__P6

#define CAPTIOPOSEL__P7                          CAPTIO_CTL_POSEL__P7

#define CAPTIOPOSEL__P8                          CAPTIO_CTL_POSEL__P8

#define CAPTIOPOSEL__P9                          CAPTIO_CTL_POSEL__P9

#define CAPTIOPOSEL__P10                         CAPTIO_CTL_POSEL__P10

#define CAPTIOPOSEL__P11                         CAPTIO_CTL_POSEL__P11

#define CAPTIOPOSEL__P12                         CAPTIO_CTL_POSEL__P12

#define CAPTIOPOSEL__P13                         CAPTIO_CTL_POSEL__P13

#define CAPTIOPOSEL__P14                         CAPTIO_CTL_POSEL__P14

#define CAPTIOPOSEL__P15                         CAPTIO_CTL_POSEL__P15

/* CAPTIO0CTL[CAPTIOEN] Bits */

#define CAPTIOEN_OFS                             CAPTIO_CTL_EN_OFS

#define CAPTIOEN                                 CAPTIO_CTL_EN

/* CAPTIO0CTL[CAPTIOSTATE] Bits */

#define CAPTIOSTATE_OFS                          CAPTIO_CTL_STATE_OFS

#define CAPTIOSTATE                              CAPTIO_CTL_STATE

/******************************************************************************

* COMP_E Bits (legacy section)

******************************************************************************/

/* CE0CTL0[CEIPSEL] Bits */

#define CEIPSEL_OFS                              COMP_E_CTL0_IPSEL_OFS

#define CEIPSEL_M                                COMP_E_CTL0_IPSEL_MASK

#define CEIPSEL0                                 COMP_E_CTL0_IPSEL0

#define CEIPSEL1                                 COMP_E_CTL0_IPSEL1

#define CEIPSEL2                                 COMP_E_CTL0_IPSEL2

#define CEIPSEL3                                 COMP_E_CTL0_IPSEL3

#define CEIPSEL_0                                COMP_E_CTL0_IPSEL_0

#define CEIPSEL_1                                COMP_E_CTL0_IPSEL_1

#define CEIPSEL_2                                COMP_E_CTL0_IPSEL_2

#define CEIPSEL_3                                COMP_E_CTL0_IPSEL_3

#define CEIPSEL_4                                COMP_E_CTL0_IPSEL_4

#define CEIPSEL_5                                COMP_E_CTL0_IPSEL_5

#define CEIPSEL_6                                COMP_E_CTL0_IPSEL_6

#define CEIPSEL_7                                COMP_E_CTL0_IPSEL_7

#define CEIPSEL_8                                COMP_E_CTL0_IPSEL_8

#define CEIPSEL_9                                COMP_E_CTL0_IPSEL_9

#define CEIPSEL_10                               COMP_E_CTL0_IPSEL_10

#define CEIPSEL_11                               COMP_E_CTL0_IPSEL_11

#define CEIPSEL_12                               COMP_E_CTL0_IPSEL_12

#define CEIPSEL_13                               COMP_E_CTL0_IPSEL_13

#define CEIPSEL_14                               COMP_E_CTL0_IPSEL_14

#define CEIPSEL_15                               COMP_E_CTL0_IPSEL_15

/* CE0CTL0[CEIPEN] Bits */

#define CEIPEN_OFS                               COMP_E_CTL0_IPEN_OFS

#define CEIPEN                                   COMP_E_CTL0_IPEN

/* CE0CTL0[CEIMSEL] Bits */

#define CEIMSEL_OFS                              COMP_E_CTL0_IMSEL_OFS

#define CEIMSEL_M                                COMP_E_CTL0_IMSEL_MASK

#define CEIMSEL0                                 COMP_E_CTL0_IMSEL0

#define CEIMSEL1                                 COMP_E_CTL0_IMSEL1

#define CEIMSEL2                                 COMP_E_CTL0_IMSEL2

#define CEIMSEL3                                 COMP_E_CTL0_IMSEL3

#define CEIMSEL_0                                COMP_E_CTL0_IMSEL_0

#define CEIMSEL_1                                COMP_E_CTL0_IMSEL_1

#define CEIMSEL_2                                COMP_E_CTL0_IMSEL_2

#define CEIMSEL_3                                COMP_E_CTL0_IMSEL_3

#define CEIMSEL_4                                COMP_E_CTL0_IMSEL_4

#define CEIMSEL_5                                COMP_E_CTL0_IMSEL_5

#define CEIMSEL_6                                COMP_E_CTL0_IMSEL_6

#define CEIMSEL_7                                COMP_E_CTL0_IMSEL_7

#define CEIMSEL_8                                COMP_E_CTL0_IMSEL_8

#define CEIMSEL_9                                COMP_E_CTL0_IMSEL_9

#define CEIMSEL_10                               COMP_E_CTL0_IMSEL_10

#define CEIMSEL_11                               COMP_E_CTL0_IMSEL_11

#define CEIMSEL_12                               COMP_E_CTL0_IMSEL_12

#define CEIMSEL_13                               COMP_E_CTL0_IMSEL_13

#define CEIMSEL_14                               COMP_E_CTL0_IMSEL_14

#define CEIMSEL_15                               COMP_E_CTL0_IMSEL_15

/* CE0CTL0[CEIMEN] Bits */

#define CEIMEN_OFS                               COMP_E_CTL0_IMEN_OFS

#define CEIMEN                                   COMP_E_CTL0_IMEN

/* CE0CTL1[CEOUT] Bits */

#define CEOUT_OFS                                COMP_E_CTL1_OUT_OFS

#define CEOUT                                    COMP_E_CTL1_OUT

/* CE0CTL1[CEOUTPOL] Bits */

#define CEOUTPOL_OFS                             COMP_E_CTL1_OUTPOL_OFS

#define CEOUTPOL                                 COMP_E_CTL1_OUTPOL

/* CE0CTL1[CEF] Bits */

#define CEF_OFS                                  COMP_E_CTL1_F_OFS

#define CEF                                      COMP_E_CTL1_F

/* CE0CTL1[CEIES] Bits */

#define CEIES_OFS                                COMP_E_CTL1_IES_OFS

#define CEIES                                    COMP_E_CTL1_IES

/* CE0CTL1[CESHORT] Bits */

#define CESHORT_OFS                              COMP_E_CTL1_SHORT_OFS

#define CESHORT                                  COMP_E_CTL1_SHORT

/* CE0CTL1[CEEX] Bits */

#define CEEX_OFS                                 COMP_E_CTL1_EX_OFS

#define CEEX                                     COMP_E_CTL1_EX

/* CE0CTL1[CEFDLY] Bits */

#define CEFDLY_OFS                               COMP_E_CTL1_FDLY_OFS

#define CEFDLY_M                                 COMP_E_CTL1_FDLY_MASK

#define CEFDLY0                                  COMP_E_CTL1_FDLY0

#define CEFDLY1                                  COMP_E_CTL1_FDLY1

#define CEFDLY_0                                 COMP_E_CTL1_FDLY_0

#define CEFDLY_1                                 COMP_E_CTL1_FDLY_1

#define CEFDLY_2                                 COMP_E_CTL1_FDLY_2

#define CEFDLY_3                                 COMP_E_CTL1_FDLY_3

/* CE0CTL1[CEPWRMD] Bits */

#define CEPWRMD_OFS                              COMP_E_CTL1_PWRMD_OFS

#define CEPWRMD_M                                COMP_E_CTL1_PWRMD_MASK

#define CEPWRMD0                                 COMP_E_CTL1_PWRMD0

#define CEPWRMD1                                 COMP_E_CTL1_PWRMD1

#define CEPWRMD_0                                COMP_E_CTL1_PWRMD_0

#define CEPWRMD_1                                COMP_E_CTL1_PWRMD_1

#define CEPWRMD_2                                COMP_E_CTL1_PWRMD_2

/* CE0CTL1[CEON] Bits */

#define CEON_OFS                                 COMP_E_CTL1_ON_OFS

#define CEON                                     COMP_E_CTL1_ON

/* CE0CTL1[CEMRVL] Bits */

#define CEMRVL_OFS                               COMP_E_CTL1_MRVL_OFS

#define CEMRVL                                   COMP_E_CTL1_MRVL

/* CE0CTL1[CEMRVS] Bits */

#define CEMRVS_OFS                               COMP_E_CTL1_MRVS_OFS

#define CEMRVS                                   COMP_E_CTL1_MRVS

/* CE0CTL2[CEREF0] Bits */

#define CEREF0_OFS                               COMP_E_CTL2_REF0_OFS

#define CEREF0_M                                 COMP_E_CTL2_REF0_MASK

#define CEREF00                                  COMP_E_CTL2_REF00

#define CEREF01                                  COMP_E_CTL2_REF01

#define CEREF02                                  COMP_E_CTL2_REF02

#define CEREF03                                  COMP_E_CTL2_REF03

#define CEREF04                                  COMP_E_CTL2_REF04

#define CEREF0_0                                 COMP_E_CTL2_REF0_0

#define CEREF0_1                                 COMP_E_CTL2_REF0_1

#define CEREF0_2                                 COMP_E_CTL2_REF0_2

#define CEREF0_3                                 COMP_E_CTL2_REF0_3

#define CEREF0_4                                 COMP_E_CTL2_REF0_4

#define CEREF0_5                                 COMP_E_CTL2_REF0_5

#define CEREF0_6                                 COMP_E_CTL2_REF0_6

#define CEREF0_7                                 COMP_E_CTL2_REF0_7

#define CEREF0_8                                 COMP_E_CTL2_REF0_8

#define CEREF0_9                                 COMP_E_CTL2_REF0_9

#define CEREF0_10                                COMP_E_CTL2_REF0_10

#define CEREF0_11                                COMP_E_CTL2_REF0_11

#define CEREF0_12                                COMP_E_CTL2_REF0_12

#define CEREF0_13                                COMP_E_CTL2_REF0_13

#define CEREF0_14                                COMP_E_CTL2_REF0_14

#define CEREF0_15                                COMP_E_CTL2_REF0_15

#define CEREF0_16                                COMP_E_CTL2_REF0_16

#define CEREF0_17                                COMP_E_CTL2_REF0_17

#define CEREF0_18                                COMP_E_CTL2_REF0_18

#define CEREF0_19                                COMP_E_CTL2_REF0_19

#define CEREF0_20                                COMP_E_CTL2_REF0_20

#define CEREF0_21                                COMP_E_CTL2_REF0_21

#define CEREF0_22                                COMP_E_CTL2_REF0_22

#define CEREF0_23                                COMP_E_CTL2_REF0_23

#define CEREF0_24                                COMP_E_CTL2_REF0_24

#define CEREF0_25                                COMP_E_CTL2_REF0_25

#define CEREF0_26                                COMP_E_CTL2_REF0_26

#define CEREF0_27                                COMP_E_CTL2_REF0_27

#define CEREF0_28                                COMP_E_CTL2_REF0_28

#define CEREF0_29                                COMP_E_CTL2_REF0_29

#define CEREF0_30                                COMP_E_CTL2_REF0_30

#define CEREF0_31                                COMP_E_CTL2_REF0_31

/* CE0CTL2[CERSEL] Bits */

#define CERSEL_OFS                               COMP_E_CTL2_RSEL_OFS

#define CERSEL                                   COMP_E_CTL2_RSEL

/* CE0CTL2[CERS] Bits */

#define CERS_OFS                                 COMP_E_CTL2_RS_OFS

#define CERS_M                                   COMP_E_CTL2_RS_MASK

#define CERS0                                    COMP_E_CTL2_RS0

#define CERS1                                    COMP_E_CTL2_RS1

#define CERS_0                                   COMP_E_CTL2_RS_0

#define CERS_1                                   COMP_E_CTL2_RS_1

#define CERS_2                                   COMP_E_CTL2_RS_2

#define CERS_3                                   COMP_E_CTL2_RS_3

/* CE0CTL2[CEREF1] Bits */

#define CEREF1_OFS                               COMP_E_CTL2_REF1_OFS

#define CEREF1_M                                 COMP_E_CTL2_REF1_MASK

#define CEREF10                                  COMP_E_CTL2_REF10

#define CEREF11                                  COMP_E_CTL2_REF11

#define CEREF12                                  COMP_E_CTL2_REF12

#define CEREF13                                  COMP_E_CTL2_REF13

#define CEREF14                                  COMP_E_CTL2_REF14

#define CEREF1_0                                 COMP_E_CTL2_REF1_0

#define CEREF1_1                                 COMP_E_CTL2_REF1_1

#define CEREF1_2                                 COMP_E_CTL2_REF1_2

#define CEREF1_3                                 COMP_E_CTL2_REF1_3

#define CEREF1_4                                 COMP_E_CTL2_REF1_4

#define CEREF1_5                                 COMP_E_CTL2_REF1_5

#define CEREF1_6                                 COMP_E_CTL2_REF1_6

#define CEREF1_7                                 COMP_E_CTL2_REF1_7

#define CEREF1_8                                 COMP_E_CTL2_REF1_8

#define CEREF1_9                                 COMP_E_CTL2_REF1_9

#define CEREF1_10                                COMP_E_CTL2_REF1_10

#define CEREF1_11                                COMP_E_CTL2_REF1_11

#define CEREF1_12                                COMP_E_CTL2_REF1_12

#define CEREF1_13                                COMP_E_CTL2_REF1_13

#define CEREF1_14                                COMP_E_CTL2_REF1_14

#define CEREF1_15                                COMP_E_CTL2_REF1_15

#define CEREF1_16                                COMP_E_CTL2_REF1_16

#define CEREF1_17                                COMP_E_CTL2_REF1_17

#define CEREF1_18                                COMP_E_CTL2_REF1_18

#define CEREF1_19                                COMP_E_CTL2_REF1_19

#define CEREF1_20                                COMP_E_CTL2_REF1_20

#define CEREF1_21                                COMP_E_CTL2_REF1_21

#define CEREF1_22                                COMP_E_CTL2_REF1_22

#define CEREF1_23                                COMP_E_CTL2_REF1_23

#define CEREF1_24                                COMP_E_CTL2_REF1_24

#define CEREF1_25                                COMP_E_CTL2_REF1_25

#define CEREF1_26                                COMP_E_CTL2_REF1_26

#define CEREF1_27                                COMP_E_CTL2_REF1_27

#define CEREF1_28                                COMP_E_CTL2_REF1_28

#define CEREF1_29                                COMP_E_CTL2_REF1_29

#define CEREF1_30                                COMP_E_CTL2_REF1_30

#define CEREF1_31                                COMP_E_CTL2_REF1_31

/* CE0CTL2[CEREFL] Bits */

#define CEREFL_OFS                               COMP_E_CTL2_REFL_OFS

#define CEREFL_M                                 COMP_E_CTL2_REFL_MASK

#define CEREFL0                                  COMP_E_CTL2_REFL0

#define CEREFL1                                  COMP_E_CTL2_REFL1

#define CEREFL_0                                 COMP_E_CTL2_CEREFL_0

#define CEREFL_1                                 COMP_E_CTL2_CEREFL_1

#define CEREFL_2                                 COMP_E_CTL2_CEREFL_2

#define CEREFL_3                                 COMP_E_CTL2_CEREFL_3

#define CEREFL__OFF                              COMP_E_CTL2_REFL__OFF

#define CEREFL__1P2V                             COMP_E_CTL2_REFL__1P2V

#define CEREFL__2P0V                             COMP_E_CTL2_REFL__2P0V

#define CEREFL__2P5V                             COMP_E_CTL2_REFL__2P5V

/* CE0CTL2[CEREFACC] Bits */

#define CEREFACC_OFS                             COMP_E_CTL2_REFACC_OFS

#define CEREFACC                                 COMP_E_CTL2_REFACC

/* CE0CTL3[CEPD0] Bits */

#define CEPD0_OFS                                COMP_E_CTL3_PD0_OFS

#define CEPD0                                    COMP_E_CTL3_PD0

/* CE0CTL3[CEPD1] Bits */

#define CEPD1_OFS                                COMP_E_CTL3_PD1_OFS

#define CEPD1                                    COMP_E_CTL3_PD1

/* CE0CTL3[CEPD2] Bits */

#define CEPD2_OFS                                COMP_E_CTL3_PD2_OFS

#define CEPD2                                    COMP_E_CTL3_PD2

/* CE0CTL3[CEPD3] Bits */

#define CEPD3_OFS                                COMP_E_CTL3_PD3_OFS

#define CEPD3                                    COMP_E_CTL3_PD3

/* CE0CTL3[CEPD4] Bits */

#define CEPD4_OFS                                COMP_E_CTL3_PD4_OFS

#define CEPD4                                    COMP_E_CTL3_PD4

/* CE0CTL3[CEPD5] Bits */

#define CEPD5_OFS                                COMP_E_CTL3_PD5_OFS

#define CEPD5                                    COMP_E_CTL3_PD5

/* CE0CTL3[CEPD6] Bits */

#define CEPD6_OFS                                COMP_E_CTL3_PD6_OFS

#define CEPD6                                    COMP_E_CTL3_PD6

/* CE0CTL3[CEPD7] Bits */

#define CEPD7_OFS                                COMP_E_CTL3_PD7_OFS

#define CEPD7                                    COMP_E_CTL3_PD7

/* CE0CTL3[CEPD8] Bits */

#define CEPD8_OFS                                COMP_E_CTL3_PD8_OFS

#define CEPD8                                    COMP_E_CTL3_PD8

/* CE0CTL3[CEPD9] Bits */

#define CEPD9_OFS                                COMP_E_CTL3_PD9_OFS

#define CEPD9                                    COMP_E_CTL3_PD9

/* CE0CTL3[CEPD10] Bits */

#define CEPD10_OFS                               COMP_E_CTL3_PD10_OFS

#define CEPD10                                   COMP_E_CTL3_PD10

/* CE0CTL3[CEPD11] Bits */

#define CEPD11_OFS                               COMP_E_CTL3_PD11_OFS

#define CEPD11                                   COMP_E_CTL3_PD11

/* CE0CTL3[CEPD12] Bits */

#define CEPD12_OFS                               COMP_E_CTL3_PD12_OFS

#define CEPD12                                   COMP_E_CTL3_PD12

/* CE0CTL3[CEPD13] Bits */

#define CEPD13_OFS                               COMP_E_CTL3_PD13_OFS

#define CEPD13                                   COMP_E_CTL3_PD13

/* CE0CTL3[CEPD14] Bits */

#define CEPD14_OFS                               COMP_E_CTL3_PD14_OFS

#define CEPD14                                   COMP_E_CTL3_PD14

/* CE0CTL3[CEPD15] Bits */

#define CEPD15_OFS                               COMP_E_CTL3_PD15_OFS

#define CEPD15                                   COMP_E_CTL3_PD15

/* CE0INT[CEIFG] Bits */

#define CEIFG_OFS                                COMP_E_INT_IFG_OFS

#define CEIFG                                    COMP_E_INT_IFG

/* CE0INT[CEIIFG] Bits */

#define CEIIFG_OFS                               COMP_E_INT_IIFG_OFS

#define CEIIFG                                   COMP_E_INT_IIFG

/* CE0INT[CERDYIFG] Bits */

#define CERDYIFG_OFS                             COMP_E_INT_RDYIFG_OFS

#define CERDYIFG                                 COMP_E_INT_RDYIFG

/* CE0INT[CEIE] Bits */

#define CEIE_OFS                                 COMP_E_INT_IE_OFS

#define CEIE                                     COMP_E_INT_IE

/* CE0INT[CEIIE] Bits */

#define CEIIE_OFS                                COMP_E_INT_IIE_OFS

#define CEIIE                                    COMP_E_INT_IIE

/* CE0INT[CERDYIE] Bits */

#define CERDYIE_OFS                              COMP_E_INT_RDYIE_OFS

#define CERDYIE                                  COMP_E_INT_RDYIE

/******************************************************************************

* CRC32 Bits (legacy section)

******************************************************************************/

/* DIO_PAIN[P1IN] Bits */

#define P1IN_OFS                                           ( 0)

#define P1IN_M                                             (0x00ff)

/* DIO_PAIN[P2IN] Bits */

#define P2IN_OFS                                           ( 8)

#define P2IN_M                                             (0xff00)

/* DIO_PAOUT[P2OUT] Bits */

#define P2OUT_OFS                                          ( 8)

#define P2OUT_M                                            (0xff00)

/* DIO_PAOUT[P1OUT] Bits */

#define P1OUT_OFS                                          ( 0)

#define P1OUT_M                                            (0x00ff)

/* DIO_PADIR[P1DIR] Bits */

#define P1DIR_OFS                                          ( 0)

#define P1DIR_M                                            (0x00ff)

/* DIO_PADIR[P2DIR] Bits */

#define P2DIR_OFS                                          ( 8)

#define P2DIR_M                                            (0xff00)

/* DIO_PAREN[P1REN] Bits */

#define P1REN_OFS                                          ( 0)

#define P1REN_M                                            (0x00ff)

/* DIO_PAREN[P2REN] Bits */

#define P2REN_OFS                                          ( 8)

#define P2REN_M                                            (0xff00)

/* DIO_PADS[P1DS] Bits */

#define P1DS_OFS                                           ( 0)

#define P1DS_M                                             (0x00ff)

/* DIO_PADS[P2DS] Bits */

#define P2DS_OFS                                           ( 8)

#define P2DS_M                                             (0xff00)

/* DIO_PASEL0[P1SEL0] Bits */

#define P1SEL0_OFS                                         ( 0)

#define P1SEL0_M                                           (0x00ff)

/* DIO_PASEL0[P2SEL0] Bits */

#define P2SEL0_OFS                                         ( 8)

#define P2SEL0_M                                           (0xff00)

/* DIO_PASEL1[P1SEL1] Bits */

#define P1SEL1_OFS                                         ( 0)

#define P1SEL1_M                                           (0x00ff)

/* DIO_PASEL1[P2SEL1] Bits */

#define P2SEL1_OFS                                         ( 8)

#define P2SEL1_M                                           (0xff00)

/* DIO_P1IV[P1IV] Bits */

#define P1IV_OFS                                           ( 0)

#define P1IV_M                                             (0x001f)

#define P1IV0                                              (0x0001)

#define P1IV1                                              (0x0002)

#define P1IV2                                              (0x0004)

#define P1IV3                                              (0x0008)

#define P1IV4                                              (0x0010)

#define P1IV_0                                             (0x0000)

#define P1IV_2                                             (0x0002)

#define P1IV_4                                             (0x0004)

#define P1IV_6                                             (0x0006)

#define P1IV_8                                             (0x0008)

#define P1IV_10                                            (0x000a)

#define P1IV_12                                            (0x000c)

#define P1IV_14                                            (0x000e)

#define P1IV_16                                            (0x0010)

#define P1IV__NONE                                         (0x0000)

#define P1IV__P1IFG0                                       (0x0002)

#define P1IV__P1IFG1                                       (0x0004)

#define P1IV__P1IFG2                                       (0x0006)

#define P1IV__P1IFG3                                       (0x0008)

#define P1IV__P1IFG4                                       (0x000a)

#define P1IV__P1IFG5                                       (0x000c)

#define P1IV__P1IFG6                                       (0x000e)

#define P1IV__P1IFG7                                       (0x0010)

/* DIO_PASELC[P1SELC] Bits */

#define P1SELC_OFS                                         ( 0)

#define P1SELC_M                                           (0x00ff)

/* DIO_PASELC[P2SELC] Bits */

#define P2SELC_OFS                                         ( 8)

#define P2SELC_M                                           (0xff00)

/* DIO_PAIES[P1IES] Bits */

#define P1IES_OFS                                          ( 0)

#define P1IES_M                                            (0x00ff)

/* DIO_PAIES[P2IES] Bits */

#define P2IES_OFS                                          ( 8)

#define P2IES_M                                            (0xff00)

/* DIO_PAIE[P1IE] Bits */

#define P1IE_OFS                                           ( 0)

#define P1IE_M                                             (0x00ff)

/* DIO_PAIE[P2IE] Bits */

#define P2IE_OFS                                           ( 8)

#define P2IE_M                                             (0xff00)

/* DIO_PAIFG[P1IFG] Bits */

#define P1IFG_OFS                                          ( 0)

#define P1IFG_M                                            (0x00ff)

/* DIO_PAIFG[P2IFG] Bits */

#define P2IFG_OFS                                          ( 8)

#define P2IFG_M                                            (0xff00)

/* DIO_P2IV[P2IV] Bits */

#define P2IV_OFS                                           ( 0)

#define P2IV_M                                             (0x001f)

#define P2IV0                                              (0x0001)

#define P2IV1                                              (0x0002)

#define P2IV2                                              (0x0004)

#define P2IV3                                              (0x0008)

#define P2IV4                                              (0x0010)

#define P2IV_0                                             (0x0000)

#define P2IV_2                                             (0x0002)

#define P2IV_4                                             (0x0004)

#define P2IV_6                                             (0x0006)

#define P2IV_8                                             (0x0008)

#define P2IV_10                                            (0x000a)

#define P2IV_12                                            (0x000c)

#define P2IV_14                                            (0x000e)

#define P2IV_16                                            (0x0010)

#define P2IV__NONE                                         (0x0000)

#define P2IV__P2IFG0                                       (0x0002)

#define P2IV__P2IFG1                                       (0x0004)

#define P2IV__P2IFG2                                       (0x0006)

#define P2IV__P2IFG3                                       (0x0008)

#define P2IV__P2IFG4                                       (0x000a)

#define P2IV__P2IFG5                                       (0x000c)

#define P2IV__P2IFG6                                       (0x000e)

#define P2IV__P2IFG7                                       (0x0010)

/* DIO_PBIN[P3IN] Bits */

#define P3IN_OFS                                           ( 0)

#define P3IN_M                                             (0x00ff)

/* DIO_PBIN[P4IN] Bits */

#define P4IN_OFS                                           ( 8)

#define P4IN_M                                             (0xff00)

/* DIO_PBOUT[P3OUT] Bits */

#define P3OUT_OFS                                          ( 0)

#define P3OUT_M                                            (0x00ff)

/* DIO_PBOUT[P4OUT] Bits */

#define P4OUT_OFS                                          ( 8)

#define P4OUT_M                                            (0xff00)

/* DIO_PBDIR[P3DIR] Bits */

#define P3DIR_OFS                                          ( 0)

#define P3DIR_M                                            (0x00ff)

/* DIO_PBDIR[P4DIR] Bits */

#define P4DIR_OFS                                          ( 8)

#define P4DIR_M                                            (0xff00)

/* DIO_PBREN[P3REN] Bits */

#define P3REN_OFS                                          ( 0)

#define P3REN_M                                            (0x00ff)

/* DIO_PBREN[P4REN] Bits */

#define P4REN_OFS                                          ( 8)

#define P4REN_M                                            (0xff00)

/* DIO_PBDS[P3DS] Bits */

#define P3DS_OFS                                           ( 0)

#define P3DS_M                                             (0x00ff)

/* DIO_PBDS[P4DS] Bits */

#define P4DS_OFS                                           ( 8)

#define P4DS_M                                             (0xff00)

/* DIO_PBSEL0[P4SEL0] Bits */

#define P4SEL0_OFS                                         ( 8)

#define P4SEL0_M                                           (0xff00)

/* DIO_PBSEL0[P3SEL0] Bits */

#define P3SEL0_OFS                                         ( 0)

#define P3SEL0_M                                           (0x00ff)

/* DIO_PBSEL1[P3SEL1] Bits */

#define P3SEL1_OFS                                         ( 0)

#define P3SEL1_M                                           (0x00ff)

/* DIO_PBSEL1[P4SEL1] Bits */

#define P4SEL1_OFS                                         ( 8)

#define P4SEL1_M                                           (0xff00)

/* DIO_P3IV[P3IV] Bits */

#define P3IV_OFS                                           ( 0)

#define P3IV_M                                             (0x001f)

#define P3IV0                                              (0x0001)

#define P3IV1                                              (0x0002)

#define P3IV2                                              (0x0004)

#define P3IV3                                              (0x0008)

#define P3IV4                                              (0x0010)

#define P3IV_0                                             (0x0000)

#define P3IV_2                                             (0x0002)

#define P3IV_4                                             (0x0004)

#define P3IV_6                                             (0x0006)

#define P3IV_8                                             (0x0008)

#define P3IV_10                                            (0x000a)

#define P3IV_12                                            (0x000c)

#define P3IV_14                                            (0x000e)

#define P3IV_16                                            (0x0010)

#define P3IV__NONE                                         (0x0000)

#define P3IV__P3IFG0                                       (0x0002)

#define P3IV__P3IFG1                                       (0x0004)

#define P3IV__P3IFG2                                       (0x0006)

#define P3IV__P3IFG3                                       (0x0008)

#define P3IV__P3IFG4                                       (0x000a)

#define P3IV__P3IFG5                                       (0x000c)

#define P3IV__P3IFG6                                       (0x000e)

#define P3IV__P3IFG7                                       (0x0010)

/* DIO_PBSELC[P3SELC] Bits */

#define P3SELC_OFS                                         ( 0)

#define P3SELC_M                                           (0x00ff)

/* DIO_PBSELC[P4SELC] Bits */

#define P4SELC_OFS                                         ( 8)

#define P4SELC_M                                           (0xff00)

/* DIO_PBIES[P3IES] Bits */

#define P3IES_OFS                                          ( 0)

#define P3IES_M                                            (0x00ff)

/* DIO_PBIES[P4IES] Bits */

#define P4IES_OFS                                          ( 8)

#define P4IES_M                                            (0xff00)

/* DIO_PBIE[P3IE] Bits */

#define P3IE_OFS                                           ( 0)

#define P3IE_M                                             (0x00ff)

/* DIO_PBIE[P4IE] Bits */

#define P4IE_OFS                                           ( 8)

#define P4IE_M                                             (0xff00)

/* DIO_PBIFG[P3IFG] Bits */

#define P3IFG_OFS                                          ( 0)

#define P3IFG_M                                            (0x00ff)

/* DIO_PBIFG[P4IFG] Bits */

#define P4IFG_OFS                                          ( 8)

#define P4IFG_M                                            (0xff00)

/* DIO_P4IV[P4IV] Bits */

#define P4IV_OFS                                           ( 0)

#define P4IV_M                                             (0x001f)

#define P4IV0                                              (0x0001)

#define P4IV1                                              (0x0002)

#define P4IV2                                              (0x0004)

#define P4IV3                                              (0x0008)

#define P4IV4                                              (0x0010)

#define P4IV_0                                             (0x0000)

#define P4IV_2                                             (0x0002)

#define P4IV_4                                             (0x0004)

#define P4IV_6                                             (0x0006)

#define P4IV_8                                             (0x0008)

#define P4IV_10                                            (0x000a)

#define P4IV_12                                            (0x000c)

#define P4IV_14                                            (0x000e)

#define P4IV_16                                            (0x0010)

#define P4IV__NONE                                         (0x0000)

#define P4IV__P4IFG0                                       (0x0002)

#define P4IV__P4IFG1                                       (0x0004)

#define P4IV__P4IFG2                                       (0x0006)

#define P4IV__P4IFG3                                       (0x0008)

#define P4IV__P4IFG4                                       (0x000a)

#define P4IV__P4IFG5                                       (0x000c)

#define P4IV__P4IFG6                                       (0x000e)

#define P4IV__P4IFG7                                       (0x0010)

/* DIO_PCIN[P5IN] Bits */

#define P5IN_OFS                                           ( 0)

#define P5IN_M                                             (0x00ff)

/* DIO_PCIN[P6IN] Bits */

#define P6IN_OFS                                           ( 8)

#define P6IN_M                                             (0xff00)

/* DIO_PCOUT[P5OUT] Bits */

#define P5OUT_OFS                                          ( 0)

#define P5OUT_M                                            (0x00ff)

/* DIO_PCOUT[P6OUT] Bits */

#define P6OUT_OFS                                          ( 8)

#define P6OUT_M                                            (0xff00)

/* DIO_PCDIR[P5DIR] Bits */

#define P5DIR_OFS                                          ( 0)

#define P5DIR_M                                            (0x00ff)

/* DIO_PCDIR[P6DIR] Bits */

#define P6DIR_OFS                                          ( 8)

#define P6DIR_M                                            (0xff00)

/* DIO_PCREN[P5REN] Bits */

#define P5REN_OFS                                          ( 0)

#define P5REN_M                                            (0x00ff)

/* DIO_PCREN[P6REN] Bits */

#define P6REN_OFS                                          ( 8)

#define P6REN_M                                            (0xff00)

/* DIO_PCDS[P5DS] Bits */

#define P5DS_OFS                                           ( 0)

#define P5DS_M                                             (0x00ff)

/* DIO_PCDS[P6DS] Bits */

#define P6DS_OFS                                           ( 8)

#define P6DS_M                                             (0xff00)

/* DIO_PCSEL0[P5SEL0] Bits */

#define P5SEL0_OFS                                         ( 0)

#define P5SEL0_M                                           (0x00ff)

/* DIO_PCSEL0[P6SEL0] Bits */

#define P6SEL0_OFS                                         ( 8)

#define P6SEL0_M                                           (0xff00)

/* DIO_PCSEL1[P5SEL1] Bits */

#define P5SEL1_OFS                                         ( 0)

#define P5SEL1_M                                           (0x00ff)

/* DIO_PCSEL1[P6SEL1] Bits */

#define P6SEL1_OFS                                         ( 8)

#define P6SEL1_M                                           (0xff00)

/* DIO_P5IV[P5IV] Bits */

#define P5IV_OFS                                           ( 0)

#define P5IV_M                                             (0x001f)

#define P5IV0                                              (0x0001)

#define P5IV1                                              (0x0002)

#define P5IV2                                              (0x0004)

#define P5IV3                                              (0x0008)

#define P5IV4                                              (0x0010)

#define P5IV_0                                             (0x0000)

#define P5IV_2                                             (0x0002)

#define P5IV_4                                             (0x0004)

#define P5IV_6                                             (0x0006)

#define P5IV_8                                             (0x0008)

#define P5IV_10                                            (0x000a)

#define P5IV_12                                            (0x000c)

#define P5IV_14                                            (0x000e)

#define P5IV_16                                            (0x0010)

#define P5IV__NONE                                         (0x0000)

#define P5IV__P5IFG0                                       (0x0002)

#define P5IV__P5IFG1                                       (0x0004)

#define P5IV__P5IFG2                                       (0x0006)

#define P5IV__P5IFG3                                       (0x0008)

#define P5IV__P5IFG4                                       (0x000a)

#define P5IV__P5IFG5                                       (0x000c)

#define P5IV__P5IFG6                                       (0x000e)

#define P5IV__P5IFG7                                       (0x0010)

/* DIO_PCSELC[P5SELC] Bits */

#define P5SELC_OFS                                         ( 0)

#define P5SELC_M                                           (0x00ff)

/* DIO_PCSELC[P6SELC] Bits */

#define P6SELC_OFS                                         ( 8)

#define P6SELC_M                                           (0xff00)

/* DIO_PCIES[P5IES] Bits */

#define P5IES_OFS                                          ( 0)

#define P5IES_M                                            (0x00ff)

/* DIO_PCIES[P6IES] Bits */

#define P6IES_OFS                                          ( 8)

#define P6IES_M                                            (0xff00)

/* DIO_PCIE[P5IE] Bits */

#define P5IE_OFS                                           ( 0)

#define P5IE_M                                             (0x00ff)

/* DIO_PCIE[P6IE] Bits */

#define P6IE_OFS                                           ( 8)

#define P6IE_M                                             (0xff00)

/* DIO_PCIFG[P5IFG] Bits */

#define P5IFG_OFS                                          ( 0)

#define P5IFG_M                                            (0x00ff)

/* DIO_PCIFG[P6IFG] Bits */

#define P6IFG_OFS                                          ( 8)

#define P6IFG_M                                            (0xff00)

/* DIO_P6IV[P6IV] Bits */

#define P6IV_OFS                                           ( 0)

#define P6IV_M                                             (0x001f)

#define P6IV0                                              (0x0001)

#define P6IV1                                              (0x0002)

#define P6IV2                                              (0x0004)

#define P6IV3                                              (0x0008)

#define P6IV4                                              (0x0010)

#define P6IV_0                                             (0x0000)

#define P6IV_2                                             (0x0002)

#define P6IV_4                                             (0x0004)

#define P6IV_6                                             (0x0006)

#define P6IV_8                                             (0x0008)

#define P6IV_10                                            (0x000a)

#define P6IV_12                                            (0x000c)

#define P6IV_14                                            (0x000e)

#define P6IV_16                                            (0x0010)

#define P6IV__NONE                                         (0x0000)

#define P6IV__P6IFG0                                       (0x0002)

#define P6IV__P6IFG1                                       (0x0004)

#define P6IV__P6IFG2                                       (0x0006)

#define P6IV__P6IFG3                                       (0x0008)

#define P6IV__P6IFG4                                       (0x000a)

#define P6IV__P6IFG5                                       (0x000c)

#define P6IV__P6IFG6                                       (0x000e)

#define P6IV__P6IFG7                                       (0x0010)

/* DIO_PDIN[P7IN] Bits */

#define P7IN_OFS                                           ( 0)

#define P7IN_M                                             (0x00ff)

/* DIO_PDIN[P8IN] Bits */

#define P8IN_OFS                                           ( 8)

#define P8IN_M                                             (0xff00)

/* DIO_PDOUT[P7OUT] Bits */

#define P7OUT_OFS                                          ( 0)

#define P7OUT_M                                            (0x00ff)

/* DIO_PDOUT[P8OUT] Bits */

#define P8OUT_OFS                                          ( 8)

#define P8OUT_M                                            (0xff00)

/* DIO_PDDIR[P7DIR] Bits */

#define P7DIR_OFS                                          ( 0)

#define P7DIR_M                                            (0x00ff)

/* DIO_PDDIR[P8DIR] Bits */

#define P8DIR_OFS                                          ( 8)

#define P8DIR_M                                            (0xff00)

/* DIO_PDREN[P7REN] Bits */

#define P7REN_OFS                                          ( 0)

#define P7REN_M                                            (0x00ff)

/* DIO_PDREN[P8REN] Bits */

#define P8REN_OFS                                          ( 8)

#define P8REN_M                                            (0xff00)

/* DIO_PDDS[P7DS] Bits */

#define P7DS_OFS                                           ( 0)

#define P7DS_M                                             (0x00ff)

/* DIO_PDDS[P8DS] Bits */

#define P8DS_OFS                                           ( 8)

#define P8DS_M                                             (0xff00)

/* DIO_PDSEL0[P7SEL0] Bits */

#define P7SEL0_OFS                                         ( 0)

#define P7SEL0_M                                           (0x00ff)

/* DIO_PDSEL0[P8SEL0] Bits */

#define P8SEL0_OFS                                         ( 8)

#define P8SEL0_M                                           (0xff00)

/* DIO_PDSEL1[P7SEL1] Bits */

#define P7SEL1_OFS                                         ( 0)

#define P7SEL1_M                                           (0x00ff)

/* DIO_PDSEL1[P8SEL1] Bits */

#define P8SEL1_OFS                                         ( 8)

#define P8SEL1_M                                           (0xff00)

/* DIO_P7IV[P7IV] Bits */

#define P7IV_OFS                                           ( 0)

#define P7IV_M                                             (0x001f)

#define P7IV0                                              (0x0001)

#define P7IV1                                              (0x0002)

#define P7IV2                                              (0x0004)

#define P7IV3                                              (0x0008)

#define P7IV4                                              (0x0010)

#define P7IV_0                                             (0x0000)

#define P7IV_2                                             (0x0002)

#define P7IV_4                                             (0x0004)

#define P7IV_6                                             (0x0006)

#define P7IV_8                                             (0x0008)

#define P7IV_10                                            (0x000a)

#define P7IV_12                                            (0x000c)

#define P7IV_14                                            (0x000e)

#define P7IV_16                                            (0x0010)

#define P7IV__NONE                                         (0x0000)

#define P7IV__P7IFG0                                       (0x0002)

#define P7IV__P7IFG1                                       (0x0004)

#define P7IV__P7IFG2                                       (0x0006)

#define P7IV__P7IFG3                                       (0x0008)

#define P7IV__P7IFG4                                       (0x000a)

#define P7IV__P7IFG5                                       (0x000c)

#define P7IV__P7IFG6                                       (0x000e)

#define P7IV__P7IFG7                                       (0x0010)

/* DIO_PDSELC[P7SELC] Bits */

#define P7SELC_OFS                                         ( 0)

#define P7SELC_M                                           (0x00ff)

/* DIO_PDSELC[P8SELC] Bits */

#define P8SELC_OFS                                         ( 8)

#define P8SELC_M                                           (0xff00)

/* DIO_PDIES[P7IES] Bits */

#define P7IES_OFS                                          ( 0)

#define P7IES_M                                            (0x00ff)

/* DIO_PDIES[P8IES] Bits */

#define P8IES_OFS                                          ( 8)

#define P8IES_M                                            (0xff00)

/* DIO_PDIE[P7IE] Bits */

#define P7IE_OFS                                           ( 0)

#define P7IE_M                                             (0x00ff)

/* DIO_PDIE[P8IE] Bits */

#define P8IE_OFS                                           ( 8)

#define P8IE_M                                             (0xff00)

/* DIO_PDIFG[P7IFG] Bits */

#define P7IFG_OFS                                          ( 0)

#define P7IFG_M                                            (0x00ff)

/* DIO_PDIFG[P8IFG] Bits */

#define P8IFG_OFS                                          ( 8)

#define P8IFG_M                                            (0xff00)

/* DIO_P8IV[P8IV] Bits */

#define P8IV_OFS                                           ( 0)

#define P8IV_M                                             (0x001f)

#define P8IV0                                              (0x0001)

#define P8IV1                                              (0x0002)

#define P8IV2                                              (0x0004)

#define P8IV3                                              (0x0008)

#define P8IV4                                              (0x0010)

#define P8IV_0                                             (0x0000)

#define P8IV_2                                             (0x0002)

#define P8IV_4                                             (0x0004)

#define P8IV_6                                             (0x0006)

#define P8IV_8                                             (0x0008)

#define P8IV_10                                            (0x000a)

#define P8IV_12                                            (0x000c)

#define P8IV_14                                            (0x000e)

#define P8IV_16                                            (0x0010)

#define P8IV__NONE                                         (0x0000)

#define P8IV__P8IFG0                                       (0x0002)

#define P8IV__P8IFG1                                       (0x0004)

#define P8IV__P8IFG2                                       (0x0006)

#define P8IV__P8IFG3                                       (0x0008)

#define P8IV__P8IFG4                                       (0x000a)

#define P8IV__P8IFG5                                       (0x000c)

#define P8IV__P8IFG6                                       (0x000e)

#define P8IV__P8IFG7                                       (0x0010)

/* DIO_PEIN[P9IN] Bits */

#define P9IN_OFS                                           ( 0)

#define P9IN_M                                             (0x00ff)

/* DIO_PEIN[P10IN] Bits */

#define P10IN_OFS                                          ( 8)

#define P10IN_M                                            (0xff00)

/* DIO_PEOUT[P9OUT] Bits */

#define P9OUT_OFS                                          ( 0)

#define P9OUT_M                                            (0x00ff)

/* DIO_PEOUT[P10OUT] Bits */

#define P10OUT_OFS                                         ( 8)

#define P10OUT_M                                           (0xff00)

/* DIO_PEDIR[P9DIR] Bits */

#define P9DIR_OFS                                          ( 0)

#define P9DIR_M                                            (0x00ff)

/* DIO_PEDIR[P10DIR] Bits */

#define P10DIR_OFS                                         ( 8)

#define P10DIR_M                                           (0xff00)

/* DIO_PEREN[P9REN] Bits */

#define P9REN_OFS                                          ( 0)

#define P9REN_M                                            (0x00ff)

/* DIO_PEREN[P10REN] Bits */

#define P10REN_OFS                                         ( 8)

#define P10REN_M                                           (0xff00)

/* DIO_PEDS[P9DS] Bits */

#define P9DS_OFS                                           ( 0)

#define P9DS_M                                             (0x00ff)

/* DIO_PEDS[P10DS] Bits */

#define P10DS_OFS                                          ( 8)

#define P10DS_M                                            (0xff00)

/* DIO_PESEL0[P9SEL0] Bits */

#define P9SEL0_OFS                                         ( 0)

#define P9SEL0_M                                           (0x00ff)

/* DIO_PESEL0[P10SEL0] Bits */

#define P10SEL0_OFS                                        ( 8)

#define P10SEL0_M                                          (0xff00)

/* DIO_PESEL1[P9SEL1] Bits */

#define P9SEL1_OFS                                         ( 0)

#define P9SEL1_M                                           (0x00ff)

/* DIO_PESEL1[P10SEL1] Bits */

#define P10SEL1_OFS                                        ( 8)

#define P10SEL1_M                                          (0xff00)

/* DIO_P9IV[P9IV] Bits */

#define P9IV_OFS                                           ( 0)

#define P9IV_M                                             (0x001f)

#define P9IV0                                              (0x0001)

#define P9IV1                                              (0x0002)

#define P9IV2                                              (0x0004)

#define P9IV3                                              (0x0008)

#define P9IV4                                              (0x0010)

#define P9IV_0                                             (0x0000)

#define P9IV_2                                             (0x0002)

#define P9IV_4                                             (0x0004)

#define P9IV_6                                             (0x0006)

#define P9IV_8                                             (0x0008)

#define P9IV_10                                            (0x000a)

#define P9IV_12                                            (0x000c)

#define P9IV_14                                            (0x000e)

#define P9IV_16                                            (0x0010)

#define P9IV__NONE                                         (0x0000)

#define P9IV__P9IFG0                                       (0x0002)

#define P9IV__P9IFG1                                       (0x0004)

#define P9IV__P9IFG2                                       (0x0006)

#define P9IV__P9IFG3                                       (0x0008)

#define P9IV__P9IFG4                                       (0x000a)

#define P9IV__P9IFG5                                       (0x000c)

#define P9IV__P9IFG6                                       (0x000e)

#define P9IV__P9IFG7                                       (0x0010)

/* DIO_PESELC[P9SELC] Bits */

#define P9SELC_OFS                                         ( 0)

#define P9SELC_M                                           (0x00ff)

/* DIO_PESELC[P10SELC] Bits */

#define P10SELC_OFS                                        ( 8)

#define P10SELC_M                                          (0xff00)

/* DIO_PEIES[P9IES] Bits */

#define P9IES_OFS                                          ( 0)

#define P9IES_M                                            (0x00ff)

/* DIO_PEIES[P10IES] Bits */

#define P10IES_OFS                                         ( 8)

#define P10IES_M                                           (0xff00)

/* DIO_PEIE[P9IE] Bits */

#define P9IE_OFS                                           ( 0)

#define P9IE_M                                             (0x00ff)

/* DIO_PEIE[P10IE] Bits */

#define P10IE_OFS                                          ( 8)

#define P10IE_M                                            (0xff00)

/* DIO_PEIFG[P9IFG] Bits */

#define P9IFG_OFS                                          ( 0)

#define P9IFG_M                                            (0x00ff)

/* DIO_PEIFG[P10IFG] Bits */

#define P10IFG_OFS                                         ( 8)

#define P10IFG_M                                           (0xff00)

/* DIO_P10IV[P10IV] Bits */

#define P10IV_OFS                                          ( 0)

#define P10IV_M                                            (0x001f)

#define P10IV0                                             (0x0001)

#define P10IV1                                             (0x0002)

#define P10IV2                                             (0x0004)

#define P10IV3                                             (0x0008)

#define P10IV4                                             (0x0010)

#define P10IV_0                                            (0x0000)

#define P10IV_2                                            (0x0002)

#define P10IV_4                                            (0x0004)

#define P10IV_6                                            (0x0006)

#define P10IV_8                                            (0x0008)

#define P10IV_10                                           (0x000a)

#define P10IV_12                                           (0x000c)

#define P10IV_14                                           (0x000e)

#define P10IV_16                                           (0x0010)

#define P10IV__NONE                                        (0x0000)

#define P10IV__P10IFG0                                     (0x0002)

#define P10IV__P10IFG1                                     (0x0004)

#define P10IV__P10IFG2                                     (0x0006)

#define P10IV__P10IFG3                                     (0x0008)

#define P10IV__P10IFG4                                     (0x000a)

#define P10IV__P10IFG5                                     (0x000c)

#define P10IV__P10IFG6                                     (0x000e)

#define P10IV__P10IFG7                                     (0x0010)

/******************************************************************************

* EUSCI_A Bits (legacy section)

******************************************************************************/

/* UCA0CTLW0[UCSWRST] Bits */

#define UCSWRST_OFS                              EUSCI_A_CTLW0_SWRST_OFS

#define UCSWRST                                  EUSCI_A_CTLW0_SWRST

/* UCA0CTLW0[UCTXBRK] Bits */

#define UCTXBRK_OFS                              EUSCI_A_CTLW0_TXBRK_OFS

#define UCTXBRK                                  EUSCI_A_CTLW0_TXBRK

/* UCA0CTLW0[UCTXADDR] Bits */

#define UCTXADDR_OFS                             EUSCI_A_CTLW0_TXADDR_OFS

#define UCTXADDR                                 EUSCI_A_CTLW0_TXADDR

/* UCA0CTLW0[UCDORM] Bits */

#define UCDORM_OFS                               EUSCI_A_CTLW0_DORM_OFS

#define UCDORM                                   EUSCI_A_CTLW0_DORM

/* UCA0CTLW0[UCBRKIE] Bits */

#define UCBRKIE_OFS                              EUSCI_A_CTLW0_BRKIE_OFS

#define UCBRKIE                                  EUSCI_A_CTLW0_BRKIE

/* UCA0CTLW0[UCRXEIE] Bits */

#define UCRXEIE_OFS                              EUSCI_A_CTLW0_RXEIE_OFS

#define UCRXEIE                                  EUSCI_A_CTLW0_RXEIE

/* UCA0CTLW0[UCSSEL] Bits */

#define UCSSEL_OFS                               EUSCI_A_CTLW0_SSEL_OFS

#define UCSSEL_M                                 EUSCI_A_CTLW0_SSEL_MASK

#define UCSSEL0                                  EUSCI_A_CTLW0_SSEL0

#define UCSSEL1                                  EUSCI_A_CTLW0_SSEL1

#define UCSSEL_0                                 EUSCI_A_CTLW0_UCSSEL_0

#define UCSSEL_1                                 EUSCI_A_CTLW0_UCSSEL_1

#define UCSSEL_2                                 EUSCI_A_CTLW0_UCSSEL_2

#define UCSSEL__UCLK                             EUSCI_A_CTLW0_SSEL__UCLK

#define UCSSEL__ACLK                             EUSCI_A_CTLW0_SSEL__ACLK

#define UCSSEL__SMCLK                            EUSCI_A_CTLW0_SSEL__SMCLK

/* UCA0CTLW0[UCSYNC] Bits */

#define UCSYNC_OFS                               EUSCI_A_CTLW0_SYNC_OFS

#define UCSYNC                                   EUSCI_A_CTLW0_SYNC

/* UCA0CTLW0[UCMODE] Bits */

#define UCMODE_OFS                               EUSCI_A_CTLW0_MODE_OFS

#define UCMODE_M                                 EUSCI_A_CTLW0_MODE_MASK

#define UCMODE0                                  EUSCI_A_CTLW0_MODE0

#define UCMODE1                                  EUSCI_A_CTLW0_MODE1

#define UCMODE_0                                 EUSCI_A_CTLW0_MODE_0

#define UCMODE_1                                 EUSCI_A_CTLW0_MODE_1

#define UCMODE_2                                 EUSCI_A_CTLW0_MODE_2

#define UCMODE_3                                 EUSCI_A_CTLW0_MODE_3

/* UCA0CTLW0[UCSPB] Bits */

#define UCSPB_OFS                                EUSCI_A_CTLW0_SPB_OFS

#define UCSPB                                    EUSCI_A_CTLW0_SPB

/* UCA0CTLW0[UC7BIT] Bits */

#define UC7BIT_OFS                               EUSCI_A_CTLW0_SEVENBIT_OFS

#define UC7BIT                                   EUSCI_A_CTLW0_SEVENBIT

/* UCA0CTLW0[UCMSB] Bits */

#define UCMSB_OFS                                EUSCI_A_CTLW0_MSB_OFS

#define UCMSB                                    EUSCI_A_CTLW0_MSB

/* UCA0CTLW0[UCPAR] Bits */

#define UCPAR_OFS                                EUSCI_A_CTLW0_PAR_OFS

#define UCPAR                                    EUSCI_A_CTLW0_PAR

/* UCA0CTLW0[UCPEN] Bits */

#define UCPEN_OFS                                EUSCI_A_CTLW0_PEN_OFS

#define UCPEN                                    EUSCI_A_CTLW0_PEN

/* UCA0CTLW0_SPI[UCSWRST] Bits */

//#define UCSWRST_OFS                              EUSCI_A_CTLW0_SWRST_OFS         /*!< UCSWRST Offset */

//#define UCSWRST                                  EUSCI_A_CTLW0_SWRST             /*!< Software reset enable */

/* UCA0CTLW0_SPI[UCSTEM] Bits */

#define UCSTEM_OFS                               EUSCI_A_CTLW0_STEM_OFS

#define UCSTEM                                   EUSCI_A_CTLW0_STEM

/* UCA0CTLW0_SPI[UCSSEL] Bits */

//#define UCSSEL_OFS                               EUSCI_A_CTLW0_SSEL_OFS          /*!< UCSSEL Offset */

//#define UCSSEL_M                                 EUSCI_A_CTLW0_SSEL_MASK         /*!< eUSCI_A clock source select */

//#define UCSSEL0                                  EUSCI_A_CTLW0_SSEL0             /*!< UCSSEL Bit 0 */

//#define UCSSEL1                                  EUSCI_A_CTLW0_SSEL1             /*!< UCSSEL Bit 1 */

//#define UCSSEL_0                                 EUSCI_A_CTLW0_UCSSEL_0          /*!< Reserved */

//#define UCSSEL_1                                 EUSCI_A_CTLW0_UCSSEL_1          /*!< ACLK */

//#define UCSSEL_2                                 EUSCI_A_CTLW0_UCSSEL_2          /*!< SMCLK */

//#define UCSSEL__ACLK                             EUSCI_A_CTLW0_SSEL__ACLK        /*!< ACLK */

//#define UCSSEL__SMCLK                            EUSCI_A_CTLW0_SSEL__SMCLK       /*!< SMCLK */

/* UCA0CTLW0_SPI[UCSYNC] Bits */

//#define UCSYNC_OFS                               EUSCI_A_CTLW0_SYNC_OFS          /*!< UCSYNC Offset */

//#define UCSYNC                                   EUSCI_A_CTLW0_SYNC              /*!< Synchronous mode enable */

/* UCA0CTLW0_SPI[UCMODE] Bits */

//#define UCMODE_OFS                               EUSCI_A_CTLW0_MODE_OFS          /*!< UCMODE Offset */

//#define UCMODE_M                                 EUSCI_A_CTLW0_MODE_MASK         /*!< eUSCI mode */

//#define UCMODE0                                  EUSCI_A_CTLW0_MODE0             /*!< UCMODE Bit 0 */

//#define UCMODE1                                  EUSCI_A_CTLW0_MODE1             /*!< UCMODE Bit 1 */

//#define UCMODE_0                                 EUSCI_A_CTLW0_MODE_0            /*!< 3-pin SPI */

//#define UCMODE_1                                 EUSCI_A_CTLW0_MODE_1            /*!< 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */

//#define UCMODE_2                                 EUSCI_A_CTLW0_MODE_2            /*!< 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */

/* UCA0CTLW0_SPI[UCMST] Bits */

#define UCMST_OFS                                EUSCI_A_CTLW0_MST_OFS

#define UCMST                                    EUSCI_A_CTLW0_MST

/* UCA0CTLW0_SPI[UC7BIT] Bits */

//#define UC7BIT_OFS                               EUSCI_A_CTLW0_SEVENBIT_OFS      /*!< UC7BIT Offset */

//#define UC7BIT                                   EUSCI_A_CTLW0_SEVENBIT          /*!< Character length */

/* UCA0CTLW0_SPI[UCMSB] Bits */

//#define UCMSB_OFS                                EUSCI_A_CTLW0_MSB_OFS           /*!< UCMSB Offset */

//#define UCMSB                                    EUSCI_A_CTLW0_MSB               /*!< MSB first select */

/* UCA0CTLW0_SPI[UCCKPL] Bits */

#define UCCKPL_OFS                               EUSCI_A_CTLW0_CKPL_OFS

#define UCCKPL                                   EUSCI_A_CTLW0_CKPL

/* UCA0CTLW0_SPI[UCCKPH] Bits */

#define UCCKPH_OFS                               EUSCI_A_CTLW0_CKPH_OFS

#define UCCKPH                                   EUSCI_A_CTLW0_CKPH

/* UCA0CTLW1[UCGLIT] Bits */

#define UCGLIT_OFS                               EUSCI_A_CTLW1_GLIT_OFS

#define UCGLIT_M                                 EUSCI_A_CTLW1_GLIT_MASK

#define UCGLIT0                                  EUSCI_A_CTLW1_GLIT0

#define UCGLIT1                                  EUSCI_A_CTLW1_GLIT1

#define UCGLIT_0                                 EUSCI_A_CTLW1_GLIT_0

#define UCGLIT_1                                 EUSCI_A_CTLW1_GLIT_1

#define UCGLIT_2                                 EUSCI_A_CTLW1_GLIT_2

#define UCGLIT_3                                 EUSCI_A_CTLW1_GLIT_3

/* UCA0MCTLW[UCOS16] Bits */

#define UCOS16_OFS                               EUSCI_A_MCTLW_OS16_OFS

#define UCOS16                                   EUSCI_A_MCTLW_OS16

/* UCA0MCTLW[UCBRF] Bits */

#define UCBRF_OFS                                EUSCI_A_MCTLW_BRF_OFS

#define UCBRF_M                                  EUSCI_A_MCTLW_BRF_MASK

/* UCA0MCTLW[UCBRS] Bits */

#define UCBRS_OFS                                EUSCI_A_MCTLW_BRS_OFS

#define UCBRS_M                                  EUSCI_A_MCTLW_BRS_MASK

/* UCA0STATW[UCBUSY] Bits */

#define UCBUSY_OFS                               EUSCI_A_STATW_BUSY_OFS

#define UCBUSY                                   EUSCI_A_STATW_BUSY

/* UCA0STATW[UCADDR_UCIDLE] Bits */

#define UCADDR_UCIDLE_OFS                        EUSCI_A_STATW_ADDR_IDLE_OFS

#define UCADDR_UCIDLE                            EUSCI_A_STATW_ADDR_IDLE

/* UCA0STATW[UCRXERR] Bits */

#define UCRXERR_OFS                              EUSCI_A_STATW_RXERR_OFS

#define UCRXERR                                  EUSCI_A_STATW_RXERR

/* UCA0STATW[UCBRK] Bits */

#define UCBRK_OFS                                EUSCI_A_STATW_BRK_OFS

#define UCBRK                                    EUSCI_A_STATW_BRK

/* UCA0STATW[UCPE] Bits */

#define UCPE_OFS                                 EUSCI_A_STATW_PE_OFS

#define UCPE                                     EUSCI_A_STATW_PE

/* UCA0STATW[UCOE] Bits */

#define UCOE_OFS                                 EUSCI_A_STATW_OE_OFS

#define UCOE                                     EUSCI_A_STATW_OE

/* UCA0STATW[UCFE] Bits */

#define UCFE_OFS                                 EUSCI_A_STATW_FE_OFS

#define UCFE                                     EUSCI_A_STATW_FE

/* UCA0STATW[UCLISTEN] Bits */

#define UCLISTEN_OFS                             EUSCI_A_STATW_LISTEN_OFS

#define UCLISTEN                                 EUSCI_A_STATW_LISTEN

/* UCA0STATW_SPI[UCBUSY] Bits */

//#define UCBUSY_OFS                               EUSCI_A_STATW_SPI_BUSY_OFS      /*!< UCBUSY Offset */

//#define UCBUSY                                   EUSCI_A_STATW_SPI_BUSY          /*!< eUSCI_A busy */

/* UCA0STATW_SPI[UCOE] Bits */

//#define UCOE_OFS                                 EUSCI_A_STATW_OE_OFS            /*!< UCOE Offset */

//#define UCOE                                     EUSCI_A_STATW_OE                /*!< Overrun error flag */

/* UCA0STATW_SPI[UCFE] Bits */

//#define UCFE_OFS                                 EUSCI_A_STATW_FE_OFS            /*!< UCFE Offset */

//#define UCFE                                     EUSCI_A_STATW_FE                /*!< Framing error flag */

/* UCA0STATW_SPI[UCLISTEN] Bits */

//#define UCLISTEN_OFS                             EUSCI_A_STATW_LISTEN_OFS        /*!< UCLISTEN Offset */

//#define UCLISTEN                                 EUSCI_A_STATW_LISTEN            /*!< Listen enable */

/* UCA0RXBUF[UCRXBUF] Bits */

#define UCRXBUF_OFS                              EUSCI_A_RXBUF_RXBUF_OFS

#define UCRXBUF_M                                EUSCI_A_RXBUF_RXBUF_MASK

/* UCA0RXBUF_SPI[UCRXBUF] Bits */

//#define UCRXBUF_OFS                              EUSCI_A_RXBUF_RXBUF_OFS         /*!< UCRXBUF Offset */

//#define UCRXBUF_M                                EUSCI_A_RXBUF_RXBUF_MASK        /*!< Receive data buffer */

/* UCA0TXBUF[UCTXBUF] Bits */

#define UCTXBUF_OFS                              EUSCI_A_TXBUF_TXBUF_OFS

#define UCTXBUF_M                                EUSCI_A_TXBUF_TXBUF_MASK

/* UCA0TXBUF_SPI[UCTXBUF] Bits */

//#define UCTXBUF_OFS                              EUSCI_A_TXBUF_TXBUF_OFS         /*!< UCTXBUF Offset */

//#define UCTXBUF_M                                EUSCI_A_TXBUF_TXBUF_MASK        /*!< Transmit data buffer */

/* UCA0ABCTL[UCABDEN] Bits */

#define UCABDEN_OFS                              EUSCI_A_ABCTL_ABDEN_OFS

#define UCABDEN                                  EUSCI_A_ABCTL_ABDEN

/* UCA0ABCTL[UCBTOE] Bits */

#define UCBTOE_OFS                               EUSCI_A_ABCTL_BTOE_OFS

#define UCBTOE                                   EUSCI_A_ABCTL_BTOE

/* UCA0ABCTL[UCSTOE] Bits */

#define UCSTOE_OFS                               EUSCI_A_ABCTL_STOE_OFS

#define UCSTOE                                   EUSCI_A_ABCTL_STOE

/* UCA0ABCTL[UCDELIM] Bits */

#define UCDELIM_OFS                              EUSCI_A_ABCTL_DELIM_OFS

#define UCDELIM_M                                EUSCI_A_ABCTL_DELIM_MASK

#define UCDELIM0                                 EUSCI_A_ABCTL_DELIM0

#define UCDELIM1                                 EUSCI_A_ABCTL_DELIM1

#define UCDELIM_0                                EUSCI_A_ABCTL_DELIM_0

#define UCDELIM_1                                EUSCI_A_ABCTL_DELIM_1

#define UCDELIM_2                                EUSCI_A_ABCTL_DELIM_2

#define UCDELIM_3                                EUSCI_A_ABCTL_DELIM_3

/* UCA0IRCTL[UCIREN] Bits */

#define UCIREN_OFS                               EUSCI_A_IRCTL_IREN_OFS

#define UCIREN                                   EUSCI_A_IRCTL_IREN

/* UCA0IRCTL[UCIRTXCLK] Bits */

#define UCIRTXCLK_OFS                            EUSCI_A_IRCTL_IRTXCLK_OFS

#define UCIRTXCLK                                EUSCI_A_IRCTL_IRTXCLK

/* UCA0IRCTL[UCIRTXPL] Bits */

#define UCIRTXPL_OFS                             EUSCI_A_IRCTL_IRTXPL_OFS

#define UCIRTXPL_M                               EUSCI_A_IRCTL_IRTXPL_MASK

/* UCA0IRCTL[UCIRRXFE] Bits */

#define UCIRRXFE_OFS                             EUSCI_A_IRCTL_IRRXFE_OFS

#define UCIRRXFE                                 EUSCI_A_IRCTL_IRRXFE

/* UCA0IRCTL[UCIRRXPL] Bits */

#define UCIRRXPL_OFS                             EUSCI_A_IRCTL_IRRXPL_OFS

#define UCIRRXPL                                 EUSCI_A_IRCTL_IRRXPL

/* UCA0IRCTL[UCIRRXFL] Bits */

#define UCIRRXFL_OFS                             EUSCI_A_IRCTL_IRRXFL_OFS

#define UCIRRXFL_M                               EUSCI_A_IRCTL_IRRXFL_MASK

/* UCA0IE[UCRXIE] Bits */

#define UCRXIE_OFS                               EUSCI_A_IE_RXIE_OFS

#define UCRXIE                                   EUSCI_A_IE_RXIE

/* UCA0IE[UCTXIE] Bits */

#define UCTXIE_OFS                               EUSCI_A_IE_TXIE_OFS

#define UCTXIE                                   EUSCI_A_IE_TXIE

/* UCA0IE[UCSTTIE] Bits */

#define UCSTTIE_OFS                              EUSCI_A_IE_STTIE_OFS

#define UCSTTIE                                  EUSCI_A_IE_STTIE

/* UCA0IE[UCTXCPTIE] Bits */

#define UCTXCPTIE_OFS                            EUSCI_A_IE_TXCPTIE_OFS

#define UCTXCPTIE                                EUSCI_A_IE_TXCPTIE

/* UCA0IE_SPI[UCRXIE] Bits */

//#define UCRXIE_OFS                               EUSCI_A_IE_RXIE_OFS             /*!< UCRXIE Offset */

//#define UCRXIE                                   EUSCI_A_IE_RXIE                 /*!< Receive interrupt enable */

/* UCA0IE_SPI[UCTXIE] Bits */

//#define UCTXIE_OFS                               EUSCI_A_IE_TXIE_OFS             /*!< UCTXIE Offset */

//#define UCTXIE                                   EUSCI_A_IE_TXIE                 /*!< Transmit interrupt enable */

/* UCA0IFG[UCRXIFG] Bits */

#define UCRXIFG_OFS                              EUSCI_A_IFG_RXIFG_OFS

#define UCRXIFG                                  EUSCI_A_IFG_RXIFG

/* UCA0IFG[UCTXIFG] Bits */

#define UCTXIFG_OFS                              EUSCI_A_IFG_TXIFG_OFS

#define UCTXIFG                                  EUSCI_A_IFG_TXIFG

/* UCA0IFG[UCSTTIFG] Bits */

#define UCSTTIFG_OFS                             EUSCI_A_IFG_STTIFG_OFS

#define UCSTTIFG                                 EUSCI_A_IFG_STTIFG

/* UCA0IFG[UCTXCPTIFG] Bits */

#define UCTXCPTIFG_OFS                           EUSCI_A_IFG_TXCPTIFG_OFS

#define UCTXCPTIFG                               EUSCI_A_IFG_TXCPTIFG

/* UCA0IFG_SPI[UCRXIFG] Bits */

//#define UCRXIFG_OFS                              EUSCI_A_IFG_RXIFG_OFS           /*!< UCRXIFG Offset */

//#define UCRXIFG                                  EUSCI_A_IFG_RXIFG               /*!< Receive interrupt flag */

/* UCA0IFG_SPI[UCTXIFG] Bits */

//#define UCTXIFG_OFS                              EUSCI_A_IFG_TXIFG_OFS           /*!< UCTXIFG Offset */

//#define UCTXIFG                                  EUSCI_A_IFG_TXIFG               /*!< Transmit interrupt flag */


/******************************************************************************

* EUSCI_B Bits (legacy section)

******************************************************************************/

/* UCB0CTLW0[UCSWRST] Bits */

//#define UCSWRST_OFS                              EUSCI_B_CTLW0_SWRST_OFS         /*!< UCSWRST Offset */

//#define UCSWRST                                  EUSCI_B_CTLW0_SWRST             /*!< Software reset enable */

/* UCB0CTLW0[UCTXSTT] Bits */

#define UCTXSTT_OFS                              EUSCI_B_CTLW0_TXSTT_OFS

#define UCTXSTT                                  EUSCI_B_CTLW0_TXSTT

/* UCB0CTLW0[UCTXSTP] Bits */

#define UCTXSTP_OFS                              EUSCI_B_CTLW0_TXSTP_OFS

#define UCTXSTP                                  EUSCI_B_CTLW0_TXSTP

/* UCB0CTLW0[UCTXNACK] Bits */

#define UCTXNACK_OFS                             EUSCI_B_CTLW0_TXNACK_OFS

#define UCTXNACK                                 EUSCI_B_CTLW0_TXNACK

/* UCB0CTLW0[UCTR] Bits */

#define UCTR_OFS                                 EUSCI_B_CTLW0_TR_OFS

#define UCTR                                     EUSCI_B_CTLW0_TR

/* UCB0CTLW0[UCTXACK] Bits */

#define UCTXACK_OFS                              EUSCI_B_CTLW0_TXACK_OFS

#define UCTXACK                                  EUSCI_B_CTLW0_TXACK

/* UCB0CTLW0[UCSSEL] Bits */

//#define UCSSEL_OFS                               EUSCI_B_CTLW0_SSEL_OFS          /*!< UCSSEL Offset */

//#define UCSSEL_M                                 EUSCI_B_CTLW0_SSEL_MASK         /*!< eUSCI_B clock source select */

//#define UCSSEL0                                  EUSCI_B_CTLW0_SSEL0             /*!< UCSSEL Bit 0 */

//#define UCSSEL1                                  EUSCI_B_CTLW0_SSEL1             /*!< UCSSEL Bit 1 */

//#define UCSSEL_0                                 EUSCI_B_CTLW0_UCSSEL_0          /*!< UCLKI */

//#define UCSSEL_1                                 EUSCI_B_CTLW0_UCSSEL_1          /*!< ACLK */

//#define UCSSEL_2                                 EUSCI_B_CTLW0_UCSSEL_2          /*!< SMCLK */

#define UCSSEL_3                                 EUSCI_B_CTLW0_UCSSEL_3

#define UCSSEL__UCLKI                            EUSCI_B_CTLW0_SSEL__UCLKI

//#define UCSSEL__ACLK                             EUSCI_B_CTLW0_SSEL__ACLK        /*!< ACLK */

//#define UCSSEL__SMCLK                            EUSCI_B_CTLW0_SSEL__SMCLK       /*!< SMCLK */

/* UCB0CTLW0[UCSYNC] Bits */

//#define UCSYNC_OFS                               EUSCI_B_CTLW0_SYNC_OFS          /*!< UCSYNC Offset */

//#define UCSYNC                                   EUSCI_B_CTLW0_SYNC              /*!< Synchronous mode enable */

/* UCB0CTLW0[UCMODE] Bits */

//#define UCMODE_OFS                               EUSCI_B_CTLW0_MODE_OFS          /*!< UCMODE Offset */

//#define UCMODE_M                                 EUSCI_B_CTLW0_MODE_MASK         /*!< eUSCI_B mode */

//#define UCMODE0                                  EUSCI_B_CTLW0_MODE0             /*!< UCMODE Bit 0 */

//#define UCMODE1                                  EUSCI_B_CTLW0_MODE1             /*!< UCMODE Bit 1 */

//#define UCMODE_0                                 EUSCI_B_CTLW0_MODE_0            /*!< 3-pin SPI */

//#define UCMODE_1                                 EUSCI_B_CTLW0_MODE_1            /*!< 4-pin SPI (master or slave enabled if STE = 1) */

//#define UCMODE_2                                 EUSCI_B_CTLW0_MODE_2            /*!< 4-pin SPI (master or slave enabled if STE = 0) */

//#define UCMODE_3                                 EUSCI_B_CTLW0_MODE_3            /*!< I2C mode */

/* UCB0CTLW0[UCMST] Bits */

//#define UCMST_OFS                                EUSCI_B_CTLW0_MST_OFS           /*!< UCMST Offset */

//#define UCMST                                    EUSCI_B_CTLW0_MST               /*!< Master mode select */

/* UCB0CTLW0[UCMM] Bits */

#define UCMM_OFS                                 EUSCI_B_CTLW0_MM_OFS

#define UCMM                                     EUSCI_B_CTLW0_MM

/* UCB0CTLW0[UCSLA10] Bits */

#define UCSLA10_OFS                              EUSCI_B_CTLW0_SLA10_OFS

#define UCSLA10                                  EUSCI_B_CTLW0_SLA10

/* UCB0CTLW0[UCA10] Bits */

#define UCA10_OFS                                EUSCI_B_CTLW0_A10_OFS

#define UCA10                                    EUSCI_B_CTLW0_A10

/* UCB0CTLW0_SPI[UCSWRST] Bits */

//#define UCSWRST_OFS                              EUSCI_B_CTLW0_SWRST_OFS         /*!< UCSWRST Offset */

//#define UCSWRST                                  EUSCI_B_CTLW0_SWRST             /*!< Software reset enable */

/* UCB0CTLW0_SPI[UCSTEM] Bits */

//#define UCSTEM_OFS                               EUSCI_B_CTLW0_STEM_OFS          /*!< UCSTEM Offset */

//#define UCSTEM                                   EUSCI_B_CTLW0_STEM              /*!< STE mode select in master mode. */

/* UCB0CTLW0_SPI[UCSSEL] Bits */

//#define UCSSEL_OFS                               EUSCI_B_CTLW0_SSEL_OFS          /*!< UCSSEL Offset */

//#define UCSSEL_M                                 EUSCI_B_CTLW0_SSEL_MASK         /*!< eUSCI_B clock source select */

//#define UCSSEL0                                  EUSCI_B_CTLW0_SSEL0             /*!< UCSSEL Bit 0 */

//#define UCSSEL1                                  EUSCI_B_CTLW0_SSEL1             /*!< UCSSEL Bit 1 */

//#define UCSSEL_0                                 EUSCI_B_CTLW0_UCSSEL_0          /*!< Reserved */

//#define UCSSEL_1                                 EUSCI_B_CTLW0_UCSSEL_1          /*!< ACLK */

//#define UCSSEL_2                                 EUSCI_B_CTLW0_UCSSEL_2          /*!< SMCLK */

//#define UCSSEL_3                                 EUSCI_B_CTLW0_UCSSEL_3          /*!< SMCLK */

//#define UCSSEL__ACLK                             EUSCI_B_CTLW0_SSEL__ACLK        /*!< ACLK */

//#define UCSSEL__SMCLK                            EUSCI_B_CTLW0_SSEL__SMCLK       /*!< SMCLK */

/* UCB0CTLW0_SPI[UCSYNC] Bits */

//#define UCSYNC_OFS                               EUSCI_B_CTLW0_SYNC_OFS          /*!< UCSYNC Offset */

//#define UCSYNC                                   EUSCI_B_CTLW0_SYNC              /*!< Synchronous mode enable */

/* UCB0CTLW0_SPI[UCMODE] Bits */

//#define UCMODE_OFS                               EUSCI_B_CTLW0_MODE_OFS          /*!< UCMODE Offset */

//#define UCMODE_M                                 EUSCI_B_CTLW0_MODE_MASK         /*!< eUSCI mode */

//#define UCMODE0                                  EUSCI_B_CTLW0_MODE0             /*!< UCMODE Bit 0 */

//#define UCMODE1                                  EUSCI_B_CTLW0_MODE1             /*!< UCMODE Bit 1 */

//#define UCMODE_0                                 EUSCI_B_CTLW0_MODE_0            /*!< 3-pin SPI */

//#define UCMODE_1                                 EUSCI_B_CTLW0_MODE_1            /*!< 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */

//#define UCMODE_2                                 EUSCI_B_CTLW0_MODE_2            /*!< 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */

//#define UCMODE_3                                 EUSCI_B_CTLW0_MODE_3            /*!< I2C mode */

/* UCB0CTLW0_SPI[UCMST] Bits */

//#define UCMST_OFS                                EUSCI_B_CTLW0_MST_OFS           /*!< UCMST Offset */

//#define UCMST                                    EUSCI_B_CTLW0_MST               /*!< Master mode select */

/* UCB0CTLW0_SPI[UC7BIT] Bits */

//#define UC7BIT_OFS                               EUSCI_B_CTLW0_SEVENBIT_OFS      /*!< UC7BIT Offset */

//#define UC7BIT                                   EUSCI_B_CTLW0_SEVENBIT          /*!< Character length */

/* UCB0CTLW0_SPI[UCMSB] Bits */

//#define UCMSB_OFS                                EUSCI_B_CTLW0_MSB_OFS           /*!< UCMSB Offset */

//#define UCMSB                                    EUSCI_B_CTLW0_MSB               /*!< MSB first select */

/* UCB0CTLW0_SPI[UCCKPL] Bits */

//#define UCCKPL_OFS                               EUSCI_B_CTLW0_CKPL_OFS          /*!< UCCKPL Offset */

//#define UCCKPL                                   EUSCI_B_CTLW0_CKPL              /*!< Clock polarity select */

/* UCB0CTLW0_SPI[UCCKPH] Bits */

//#define UCCKPH_OFS                               EUSCI_B_CTLW0_CKPH_OFS          /*!< UCCKPH Offset */

//#define UCCKPH                                   EUSCI_B_CTLW0_CKPH              /*!< Clock phase select */

/* UCB0CTLW1[UCGLIT] Bits */

//#define UCGLIT_OFS                               EUSCI_B_CTLW1_GLIT_OFS          /*!< UCGLIT Offset */

//#define UCGLIT_M                                 EUSCI_B_CTLW1_GLIT_MASK         /*!< Deglitch time */

//#define UCGLIT0                                  EUSCI_B_CTLW1_GLIT0             /*!< UCGLIT Bit 0 */

//#define UCGLIT1                                  EUSCI_B_CTLW1_GLIT1             /*!< UCGLIT Bit 1 */

//#define UCGLIT_0                                 EUSCI_B_CTLW1_GLIT_0            /*!< 50 ns */

//#define UCGLIT_1                                 EUSCI_B_CTLW1_GLIT_1            /*!< 25 ns */

//#define UCGLIT_2                                 EUSCI_B_CTLW1_GLIT_2            /*!< 12.5 ns */

//#define UCGLIT_3                                 EUSCI_B_CTLW1_GLIT_3            /*!< 6.25 ns */

/* UCB0CTLW1[UCASTP] Bits */

#define UCASTP_OFS                               EUSCI_B_CTLW1_ASTP_OFS

#define UCASTP_M                                 EUSCI_B_CTLW1_ASTP_MASK

#define UCASTP0                                  EUSCI_B_CTLW1_ASTP0

#define UCASTP1                                  EUSCI_B_CTLW1_ASTP1

#define UCASTP_0                                 EUSCI_B_CTLW1_ASTP_0

                                                                                 /* sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */

#define UCASTP_1                                 EUSCI_B_CTLW1_ASTP_1

                                                                                 /* UCBxTBCNT */

#define UCASTP_2                                 EUSCI_B_CTLW1_ASTP_2

                                                                                 /* reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the */

                                                                                 /* threshold */

/* UCB0CTLW1[UCSWACK] Bits */

#define UCSWACK_OFS                              EUSCI_B_CTLW1_SWACK_OFS

#define UCSWACK                                  EUSCI_B_CTLW1_SWACK

/* UCB0CTLW1[UCSTPNACK] Bits */

#define UCSTPNACK_OFS                            EUSCI_B_CTLW1_STPNACK_OFS

#define UCSTPNACK                                EUSCI_B_CTLW1_STPNACK

/* UCB0CTLW1[UCCLTO] Bits */

#define UCCLTO_OFS                               EUSCI_B_CTLW1_CLTO_OFS

#define UCCLTO_M                                 EUSCI_B_CTLW1_CLTO_MASK

#define UCCLTO0                                  EUSCI_B_CTLW1_CLTO0

#define UCCLTO1                                  EUSCI_B_CTLW1_CLTO1

#define UCCLTO_0                                 EUSCI_B_CTLW1_CLTO_0

#define UCCLTO_1                                 EUSCI_B_CTLW1_CLTO_1

#define UCCLTO_2                                 EUSCI_B_CTLW1_CLTO_2

#define UCCLTO_3                                 EUSCI_B_CTLW1_CLTO_3

/* UCB0CTLW1[UCETXINT] Bits */

#define UCETXINT_OFS                             EUSCI_B_CTLW1_ETXINT_OFS

#define UCETXINT                                 EUSCI_B_CTLW1_ETXINT

/* UCB0STATW[UCBBUSY] Bits */

#define UCBBUSY_OFS                              EUSCI_B_STATW_BBUSY_OFS

#define UCBBUSY                                  EUSCI_B_STATW_BBUSY

/* UCB0STATW[UCGC] Bits */

#define UCGC_OFS                                 EUSCI_B_STATW_GC_OFS

#define UCGC                                     EUSCI_B_STATW_GC

/* UCB0STATW[UCSCLLOW] Bits */

#define UCSCLLOW_OFS                             EUSCI_B_STATW_SCLLOW_OFS

#define UCSCLLOW                                 EUSCI_B_STATW_SCLLOW

/* UCB0STATW[UCBCNT] Bits */

#define UCBCNT_OFS                               EUSCI_B_STATW_BCNT_OFS

#define UCBCNT_M                                 EUSCI_B_STATW_BCNT_MASK

/* UCB0STATW_SPI[UCBUSY] Bits */

//#define UCBUSY_OFS                               EUSCI_B_STATW_SPI_BUSY_OFS      /*!< UCBUSY Offset */

//#define UCBUSY                                   EUSCI_B_STATW_SPI_BUSY          /*!< eUSCI_B busy */

/* UCB0STATW_SPI[UCOE] Bits */

//#define UCOE_OFS                                 EUSCI_B_STATW_OE_OFS            /*!< UCOE Offset */

//#define UCOE                                     EUSCI_B_STATW_OE                /*!< Overrun error flag */

/* UCB0STATW_SPI[UCFE] Bits */

//#define UCFE_OFS                                 EUSCI_B_STATW_FE_OFS            /*!< UCFE Offset */

//#define UCFE                                     EUSCI_B_STATW_FE                /*!< Framing error flag */

/* UCB0STATW_SPI[UCLISTEN] Bits */

//#define UCLISTEN_OFS                             EUSCI_B_STATW_LISTEN_OFS        /*!< UCLISTEN Offset */

//#define UCLISTEN                                 EUSCI_B_STATW_LISTEN            /*!< Listen enable */

/* UCB0TBCNT[UCTBCNT] Bits */

#define UCTBCNT_OFS                              EUSCI_B_TBCNT_TBCNT_OFS

#define UCTBCNT_M                                EUSCI_B_TBCNT_TBCNT_MASK

/* UCB0RXBUF[UCRXBUF] Bits */

//#define UCRXBUF_OFS                              EUSCI_B_RXBUF_RXBUF_OFS         /*!< UCRXBUF Offset */

//#define UCRXBUF_M                                EUSCI_B_RXBUF_RXBUF_MASK        /*!< Receive data buffer */

/* UCB0RXBUF_SPI[UCRXBUF] Bits */

//#define UCRXBUF_OFS                              EUSCI_B_RXBUF_RXBUF_OFS         /*!< UCRXBUF Offset */

//#define UCRXBUF_M                                EUSCI_B_RXBUF_RXBUF_MASK        /*!< Receive data buffer */

/* UCB0TXBUF[UCTXBUF] Bits */

//#define UCTXBUF_OFS                              EUSCI_B_TXBUF_TXBUF_OFS         /*!< UCTXBUF Offset */

//#define UCTXBUF_M                                EUSCI_B_TXBUF_TXBUF_MASK        /*!< Transmit data buffer */

/* UCB0TXBUF_SPI[UCTXBUF] Bits */

//#define UCTXBUF_OFS                              EUSCI_B_TXBUF_TXBUF_OFS         /*!< UCTXBUF Offset */

//#define UCTXBUF_M                                EUSCI_B_TXBUF_TXBUF_MASK        /*!< Transmit data buffer */

/* UCB0I2COA0[I2COA0] Bits */

#define I2COA0_OFS                               EUSCI_B_I2COA0_I2COA0_OFS

#define I2COA0_M                                 EUSCI_B_I2COA0_I2COA0_MASK

/* UCB0I2COA0[UCOAEN] Bits */

#define UCOAEN_OFS                               EUSCI_B_I2COA0_OAEN_OFS

#define UCOAEN                                   EUSCI_B_I2COA0_OAEN

/* UCB0I2COA0[UCGCEN] Bits */

#define UCGCEN_OFS                               EUSCI_B_I2COA0_GCEN_OFS

#define UCGCEN                                   EUSCI_B_I2COA0_GCEN

/* UCB0I2COA1[I2COA1] Bits */

#define I2COA1_OFS                               EUSCI_B_I2COA1_I2COA1_OFS

#define I2COA1_M                                 EUSCI_B_I2COA1_I2COA1_MASK

/* UCB0I2COA1[UCOAEN] Bits */

//#define UCOAEN_OFS                               EUSCI_B_I2COA1_OAEN_OFS         /*!< UCOAEN Offset */

//#define UCOAEN                                   EUSCI_B_I2COA1_OAEN             /*!< Own Address enable register */

/* UCB0I2COA2[I2COA2] Bits */

#define I2COA2_OFS                               EUSCI_B_I2COA2_I2COA2_OFS

#define I2COA2_M                                 EUSCI_B_I2COA2_I2COA2_MASK

/* UCB0I2COA2[UCOAEN] Bits */

//#define UCOAEN_OFS                               EUSCI_B_I2COA2_OAEN_OFS         /*!< UCOAEN Offset */

//#define UCOAEN                                   EUSCI_B_I2COA2_OAEN             /*!< Own Address enable register */

/* UCB0I2COA3[I2COA3] Bits */

#define I2COA3_OFS                               EUSCI_B_I2COA3_I2COA3_OFS

#define I2COA3_M                                 EUSCI_B_I2COA3_I2COA3_MASK

/* UCB0I2COA3[UCOAEN] Bits */

//#define UCOAEN_OFS                               EUSCI_B_I2COA3_OAEN_OFS         /*!< UCOAEN Offset */

//#define UCOAEN                                   EUSCI_B_I2COA3_OAEN             /*!< Own Address enable register */

/* UCB0ADDRX[ADDRX] Bits */

#define ADDRX_OFS                                EUSCI_B_ADDRX_ADDRX_OFS

#define ADDRX_M                                  EUSCI_B_ADDRX_ADDRX_MASK

#define ADDRX0                                   EUSCI_B_ADDRX_ADDRX0

#define ADDRX1                                   EUSCI_B_ADDRX_ADDRX1

#define ADDRX2                                   EUSCI_B_ADDRX_ADDRX2

#define ADDRX3                                   EUSCI_B_ADDRX_ADDRX3

#define ADDRX4                                   EUSCI_B_ADDRX_ADDRX4

#define ADDRX5                                   EUSCI_B_ADDRX_ADDRX5

#define ADDRX6                                   EUSCI_B_ADDRX_ADDRX6

#define ADDRX7                                   EUSCI_B_ADDRX_ADDRX7

#define ADDRX8                                   EUSCI_B_ADDRX_ADDRX8

#define ADDRX9                                   EUSCI_B_ADDRX_ADDRX9

/* UCB0ADDMASK[ADDMASK] Bits */

#define ADDMASK_OFS                              EUSCI_B_ADDMASK_ADDMASK_OFS

#define ADDMASK_M                                EUSCI_B_ADDMASK_ADDMASK_MASK

/* UCB0I2CSA[I2CSA] Bits */

#define I2CSA_OFS                                EUSCI_B_I2CSA_I2CSA_OFS

#define I2CSA_M                                  EUSCI_B_I2CSA_I2CSA_MASK

/* UCB0IE[UCRXIE0] Bits */

#define UCRXIE0_OFS                              EUSCI_B_IE_RXIE0_OFS

#define UCRXIE0                                  EUSCI_B_IE_RXIE0

/* UCB0IE[UCTXIE0] Bits */

#define UCTXIE0_OFS                              EUSCI_B_IE_TXIE0_OFS

#define UCTXIE0                                  EUSCI_B_IE_TXIE0

/* UCB0IE[UCSTTIE] Bits */

//#define UCSTTIE_OFS                              EUSCI_B_IE_STTIE_OFS            /*!< UCSTTIE Offset */

//#define UCSTTIE                                  EUSCI_B_IE_STTIE                /*!< START condition interrupt enable */

/* UCB0IE[UCSTPIE] Bits */

#define UCSTPIE_OFS                              EUSCI_B_IE_STPIE_OFS

#define UCSTPIE                                  EUSCI_B_IE_STPIE

/* UCB0IE[UCALIE] Bits */

#define UCALIE_OFS                               EUSCI_B_IE_ALIE_OFS

#define UCALIE                                   EUSCI_B_IE_ALIE

/* UCB0IE[UCNACKIE] Bits */

#define UCNACKIE_OFS                             EUSCI_B_IE_NACKIE_OFS

#define UCNACKIE                                 EUSCI_B_IE_NACKIE

/* UCB0IE[UCBCNTIE] Bits */

#define UCBCNTIE_OFS                             EUSCI_B_IE_BCNTIE_OFS

#define UCBCNTIE                                 EUSCI_B_IE_BCNTIE

/* UCB0IE[UCCLTOIE] Bits */

#define UCCLTOIE_OFS                             EUSCI_B_IE_CLTOIE_OFS

#define UCCLTOIE                                 EUSCI_B_IE_CLTOIE

/* UCB0IE[UCRXIE1] Bits */

#define UCRXIE1_OFS                              EUSCI_B_IE_RXIE1_OFS

#define UCRXIE1                                  EUSCI_B_IE_RXIE1

/* UCB0IE[UCTXIE1] Bits */

#define UCTXIE1_OFS                              EUSCI_B_IE_TXIE1_OFS

#define UCTXIE1                                  EUSCI_B_IE_TXIE1

/* UCB0IE[UCRXIE2] Bits */

#define UCRXIE2_OFS                              EUSCI_B_IE_RXIE2_OFS

#define UCRXIE2                                  EUSCI_B_IE_RXIE2

/* UCB0IE[UCTXIE2] Bits */

#define UCTXIE2_OFS                              EUSCI_B_IE_TXIE2_OFS

#define UCTXIE2                                  EUSCI_B_IE_TXIE2

/* UCB0IE[UCRXIE3] Bits */

#define UCRXIE3_OFS                              EUSCI_B_IE_RXIE3_OFS

#define UCRXIE3                                  EUSCI_B_IE_RXIE3

/* UCB0IE[UCTXIE3] Bits */

#define UCTXIE3_OFS                              EUSCI_B_IE_TXIE3_OFS

#define UCTXIE3                                  EUSCI_B_IE_TXIE3

/* UCB0IE[UCBIT9IE] Bits */

#define UCBIT9IE_OFS                             EUSCI_B_IE_BIT9IE_OFS

#define UCBIT9IE                                 EUSCI_B_IE_BIT9IE

/* UCB0IE_SPI[UCRXIE] Bits */

//#define UCRXIE_OFS                               EUSCI_B_IE_RXIE_OFS             /*!< UCRXIE Offset */

//#define UCRXIE                                   EUSCI_B_IE_RXIE                 /*!< Receive interrupt enable */

/* UCB0IE_SPI[UCTXIE] Bits */

//#define UCTXIE_OFS                               EUSCI_B_IE_TXIE_OFS             /*!< UCTXIE Offset */

//#define UCTXIE                                   EUSCI_B_IE_TXIE                 /*!< Transmit interrupt enable */

/* UCB0IFG[UCRXIFG0] Bits */

#define UCRXIFG0_OFS                             EUSCI_B_IFG_RXIFG0_OFS

#define UCRXIFG0                                 EUSCI_B_IFG_RXIFG0

/* UCB0IFG[UCTXIFG0] Bits */

#define UCTXIFG0_OFS                             EUSCI_B_IFG_TXIFG0_OFS

#define UCTXIFG0                                 EUSCI_B_IFG_TXIFG0

/* UCB0IFG[UCSTTIFG] Bits */

//#define UCSTTIFG_OFS                             EUSCI_B_IFG_STTIFG_OFS          /*!< UCSTTIFG Offset */

//#define UCSTTIFG                                 EUSCI_B_IFG_STTIFG              /*!< START condition interrupt flag */

/* UCB0IFG[UCSTPIFG] Bits */

#define UCSTPIFG_OFS                             EUSCI_B_IFG_STPIFG_OFS

#define UCSTPIFG                                 EUSCI_B_IFG_STPIFG

/* UCB0IFG[UCALIFG] Bits */

#define UCALIFG_OFS                              EUSCI_B_IFG_ALIFG_OFS

#define UCALIFG                                  EUSCI_B_IFG_ALIFG

/* UCB0IFG[UCNACKIFG] Bits */

#define UCNACKIFG_OFS                            EUSCI_B_IFG_NACKIFG_OFS

#define UCNACKIFG                                EUSCI_B_IFG_NACKIFG

/* UCB0IFG[UCBCNTIFG] Bits */

#define UCBCNTIFG_OFS                            EUSCI_B_IFG_BCNTIFG_OFS

#define UCBCNTIFG                                EUSCI_B_IFG_BCNTIFG

/* UCB0IFG[UCCLTOIFG] Bits */

#define UCCLTOIFG_OFS                            EUSCI_B_IFG_CLTOIFG_OFS

#define UCCLTOIFG                                EUSCI_B_IFG_CLTOIFG

/* UCB0IFG[UCRXIFG1] Bits */

#define UCRXIFG1_OFS                             EUSCI_B_IFG_RXIFG1_OFS

#define UCRXIFG1                                 EUSCI_B_IFG_RXIFG1

/* UCB0IFG[UCTXIFG1] Bits */

#define UCTXIFG1_OFS                             EUSCI_B_IFG_TXIFG1_OFS

#define UCTXIFG1                                 EUSCI_B_IFG_TXIFG1

/* UCB0IFG[UCRXIFG2] Bits */

#define UCRXIFG2_OFS                             EUSCI_B_IFG_RXIFG2_OFS

#define UCRXIFG2                                 EUSCI_B_IFG_RXIFG2

/* UCB0IFG[UCTXIFG2] Bits */

#define UCTXIFG2_OFS                             EUSCI_B_IFG_TXIFG2_OFS

#define UCTXIFG2                                 EUSCI_B_IFG_TXIFG2

/* UCB0IFG[UCRXIFG3] Bits */

#define UCRXIFG3_OFS                             EUSCI_B_IFG_RXIFG3_OFS

#define UCRXIFG3                                 EUSCI_B_IFG_RXIFG3

/* UCB0IFG[UCTXIFG3] Bits */

#define UCTXIFG3_OFS                             EUSCI_B_IFG_TXIFG3_OFS

#define UCTXIFG3                                 EUSCI_B_IFG_TXIFG3

/* UCB0IFG[UCBIT9IFG] Bits */

#define UCBIT9IFG_OFS                            EUSCI_B_IFG_BIT9IFG_OFS

#define UCBIT9IFG                                EUSCI_B_IFG_BIT9IFG

/* UCB0IFG_SPI[UCRXIFG] Bits */

//#define UCRXIFG_OFS                              EUSCI_B_IFG_RXIFG_OFS           /*!< UCRXIFG Offset */

//#define UCRXIFG                                  EUSCI_B_IFG_RXIFG               /*!< Receive interrupt flag */

/* UCB0IFG_SPI[UCTXIFG] Bits */

//#define UCTXIFG_OFS                              EUSCI_B_IFG_TXIFG_OFS           /*!< UCTXIFG Offset */

//#define UCTXIFG                                  EUSCI_B_IFG_TXIFG               /*!< Transmit interrupt flag */


/******************************************************************************

* PMAP Bits (legacy section)

******************************************************************************/

/* PMAPCTL[PMAPLOCKED] Bits */

#define PMAPLOCKED_OFS                           PMAP_CTL_LOCKED_OFS

#define PMAPLOCKED                               PMAP_CTL_LOCKED

/* PMAPCTL[PMAPRECFG] Bits */

#define PMAPRECFG_OFS                            PMAP_CTL_PRECFG_OFS

#define PMAPRECFG                                PMAP_CTL_PRECFG

/* Pre-defined bitfield values */

/* PMAP_PMAPCTL[PMAPLOCKED] Bits */

#define PMAPLOCKED_OFS                                     PMAP_CTL_LOCKED_OFS

#define PMAPLOCKED                                         PMAP_CTL_LOCKED

/* PMAP_PMAPCTL[PMAPRECFG] Bits */

#define PMAPRECFG_OFS                                      PMAP_CTL_PRECFG_OFS

#define PMAPRECFG                                          PMAP_CTL_PRECFG

#define PM_NONE                                            PMAP_NONE

#define PM_UCA0CLK                                         PMAP_UCA0CLK

#define PM_UCA0RXD                                         PMAP_UCA0RXD

#define PM_UCA0SOMI                                        PMAP_UCA0SOMI

#define PM_UCA0TXD                                         PMAP_UCA0TXD

#define PM_UCA0SIMO                                        PMAP_UCA0SIMO

#define PM_UCB0CLK                                         PMAP_UCB0CLK

#define PM_UCB0SDA                                         PMAP_UCB0SDA

#define PM_UCB0SIMO                                        PMAP_UCB0SIMO

#define PM_UCB0SCL                                         PMAP_UCB0SCL

#define PM_UCB0SOMI                                        PMAP_UCB0SOMI

#define PM_UCA1STE                                         PMAP_UCA1STE

#define PM_UCA1CLK                                         PMAP_UCA1CLK

#define PM_UCA1RXD                                         PMAP_UCA1RXD

#define PM_UCA1SOMI                                        PMAP_UCA1SOMI

#define PM_UCA1TXD                                         PMAP_UCA1TXD

#define PM_UCA1SIMO                                        PMAP_UCA1SIMO

#define PM_UCA2STE                                         PMAP_UCA2STE

#define PM_UCA2CLK                                         PMAP_UCA2CLK

#define PM_UCA2RXD                                         PMAP_UCA2RXD

#define PM_UCA2SOMI                                        PMAP_UCA2SOMI

#define PM_UCA2TXD                                         PMAP_UCA2TXD

#define PM_UCA2SIMO                                        PMAP_UCA2SIMO

#define PM_UCB2STE                                         PMAP_UCB2STE

#define PM_UCB2CLK                                         PMAP_UCB2CLK

#define PM_UCB2SDA                                         PMAP_UCB2SDA

#define PM_UCB2SIMO                                        PMAP_UCB2SIMO

#define PM_UCB2SCL                                         PMAP_UCB2SCL

#define PM_UCB2SOMI                                        PMAP_UCB2SOMI

#define PM_TA0CCR0A                                        PMAP_TA0CCR0A

#define PM_TA0CCR1A                                        PMAP_TA0CCR1A

#define PM_TA0CCR2A                                        PMAP_TA0CCR2A

#define PM_TA0CCR3A                                        PMAP_TA0CCR3A

#define PM_TA0CCR4A                                        PMAP_TA0CCR4A

#define PM_TA1CCR1A                                        PMAP_TA1CCR1A

#define PM_TA1CCR2A                                        PMAP_TA1CCR2A

#define PM_TA1CCR3A                                        PMAP_TA1CCR3A

#define PM_TA1CCR4A                                        PMAP_TA1CCR4A

#define PM_TA0CLK                                          PMAP_TA0CLK

#define PM_CE0OUT                                          PMAP_CE0OUT

#define PM_TA1CLK                                          PMAP_TA1CLK

#define PM_CE1OUT                                          PMAP_CE1OUT

#define PM_DMAE0                                           PMAP_DMAE0

#define PM_SMCLK                                           PMAP_SMCLK

#define PM_ANALOG                                          PMAP_ANALOG


#define PMAPKEY                                            PMAP_KEYID_VAL

#define PMAPPWD                                            PMAP_KEYID_VAL

#define PMAPPW                                             PMAP_KEYID_VAL

/******************************************************************************

* REF_A Bits (legacy section)

******************************************************************************/

/* REFCTL0[REFON] Bits */

#define REFON_OFS                                REF_A_CTL0_ON_OFS

#define REFON                                    REF_A_CTL0_ON

/* REFCTL0[REFOUT] Bits */

#define REFOUT_OFS                               REF_A_CTL0_OUT_OFS

#define REFOUT                                   REF_A_CTL0_OUT

/* REFCTL0[REFTCOFF] Bits */

#define REFTCOFF_OFS                             REF_A_CTL0_TCOFF_OFS

#define REFTCOFF                                 REF_A_CTL0_TCOFF

/* REFCTL0[REFVSEL] Bits */

#define REFVSEL_OFS                              REF_A_CTL0_VSEL_OFS

#define REFVSEL_M                                REF_A_CTL0_VSEL_MASK

#define REFVSEL0                                 REF_A_CTL0_VSEL0

#define REFVSEL1                                 REF_A_CTL0_VSEL1

#define REFVSEL_0                                REF_A_CTL0_VSEL_0

#define REFVSEL_1                                REF_A_CTL0_VSEL_1

#define REFVSEL_3                                REF_A_CTL0_VSEL_3

/* REFCTL0[REFGENOT] Bits */

#define REFGENOT_OFS                             REF_A_CTL0_GENOT_OFS

#define REFGENOT                                 REF_A_CTL0_GENOT

/* REFCTL0[REFBGOT] Bits */

#define REFBGOT_OFS                              REF_A_CTL0_BGOT_OFS

#define REFBGOT                                  REF_A_CTL0_BGOT

/* REFCTL0[REFGENACT] Bits */

#define REFGENACT_OFS                            REF_A_CTL0_GENACT_OFS

#define REFGENACT                                REF_A_CTL0_GENACT

/* REFCTL0[REFBGACT] Bits */

#define REFBGACT_OFS                             REF_A_CTL0_BGACT_OFS

#define REFBGACT                                 REF_A_CTL0_BGACT

/* REFCTL0[REFGENBUSY] Bits */

#define REFGENBUSY_OFS                           REF_A_CTL0_GENBUSY_OFS

#define REFGENBUSY                               REF_A_CTL0_GENBUSY

/* REFCTL0[BGMODE] Bits */

#define BGMODE_OFS                               REF_A_CTL0_BGMODE_OFS

#define BGMODE                                   REF_A_CTL0_BGMODE

/* REFCTL0[REFGENRDY] Bits */

#define REFGENRDY_OFS                            REF_A_CTL0_GENRDY_OFS

#define REFGENRDY                                REF_A_CTL0_GENRDY

/* REFCTL0[REFBGRDY] Bits */

#define REFBGRDY_OFS                             REF_A_CTL0_BGRDY_OFS

#define REFBGRDY                                 REF_A_CTL0_BGRDY

/******************************************************************************

* RTC_C Bits (legacy section)

******************************************************************************/

/* RTCCTL0[RTCRDYIFG] Bits */

#define RTCRDYIFG_OFS                            RTC_C_CTL0_RDYIFG_OFS

#define RTCRDYIFG                                RTC_C_CTL0_RDYIFG

/* RTCCTL0[RTCAIFG] Bits */

#define RTCAIFG_OFS                              RTC_C_CTL0_AIFG_OFS

#define RTCAIFG                                  RTC_C_CTL0_AIFG

/* RTCCTL0[RTCTEVIFG] Bits */

#define RTCTEVIFG_OFS                            RTC_C_CTL0_TEVIFG_OFS

#define RTCTEVIFG                                RTC_C_CTL0_TEVIFG

/* RTCCTL0[RTCOFIFG] Bits */

#define RTCOFIFG_OFS                             RTC_C_CTL0_OFIFG_OFS

#define RTCOFIFG                                 RTC_C_CTL0_OFIFG

/* RTCCTL0[RTCRDYIE] Bits */

#define RTCRDYIE_OFS                             RTC_C_CTL0_RDYIE_OFS

#define RTCRDYIE                                 RTC_C_CTL0_RDYIE

/* RTCCTL0[RTCAIE] Bits */

#define RTCAIE_OFS                               RTC_C_CTL0_AIE_OFS

#define RTCAIE                                   RTC_C_CTL0_AIE

/* RTCCTL0[RTCTEVIE] Bits */

#define RTCTEVIE_OFS                             RTC_C_CTL0_TEVIE_OFS

#define RTCTEVIE                                 RTC_C_CTL0_TEVIE

/* RTCCTL0[RTCOFIE] Bits */

#define RTCOFIE_OFS                              RTC_C_CTL0_OFIE_OFS

#define RTCOFIE                                  RTC_C_CTL0_OFIE

/* RTCCTL0[RTCKEY] Bits */

#define RTCKEY_OFS                               RTC_C_CTL0_KEY_OFS

#define RTCKEY_M                                 RTC_C_CTL0_KEY_MASK

/* RTCCTL13[RTCTEV] Bits */

#define RTCTEV_OFS                               RTC_C_CTL13_TEV_OFS

#define RTCTEV_M                                 RTC_C_CTL13_TEV_MASK

#define RTCTEV0                                  RTC_C_CTL13_TEV0

#define RTCTEV1                                  RTC_C_CTL13_TEV1

#define RTCTEV_0                                 RTC_C_CTL13_TEV_0

#define RTCTEV_1                                 RTC_C_CTL13_TEV_1

#define RTCTEV_2                                 RTC_C_CTL13_TEV_2

#define RTCTEV_3                                 RTC_C_CTL13_TEV_3

/* RTCCTL13[RTCSSEL] Bits */

#define RTCSSEL_OFS                              RTC_C_CTL13_SSEL_OFS

#define RTCSSEL_M                                RTC_C_CTL13_SSEL_MASK

#define RTCSSEL0                                 RTC_C_CTL13_SSEL0

#define RTCSSEL1                                 RTC_C_CTL13_SSEL1

#define RTCSSEL_0                                RTC_C_CTL13_SSEL_0

#define RTCSSEL__BCLK                            RTC_C_CTL13_SSEL__BCLK

/* RTCCTL13[RTCRDY] Bits */

#define RTCRDY_OFS                               RTC_C_CTL13_RDY_OFS

#define RTCRDY                                   RTC_C_CTL13_RDY

/* RTCCTL13[RTCMODE] Bits */

#define RTCMODE_OFS                              RTC_C_CTL13_MODE_OFS

#define RTCMODE                                  RTC_C_CTL13_MODE

/* RTCCTL13[RTCHOLD] Bits */

#define RTCHOLD_OFS                              RTC_C_CTL13_HOLD_OFS

#define RTCHOLD                                  RTC_C_CTL13_HOLD

/* RTCCTL13[RTCBCD] Bits */

#define RTCBCD_OFS                               RTC_C_CTL13_BCD_OFS

#define RTCBCD                                   RTC_C_CTL13_BCD

/* RTCCTL13[RTCCALF] Bits */

#define RTCCALF_OFS                              RTC_C_CTL13_CALF_OFS

#define RTCCALF_M                                RTC_C_CTL13_CALF_MASK

#define RTCCALF0                                 RTC_C_CTL13_CALF0

#define RTCCALF1                                 RTC_C_CTL13_CALF1

#define RTCCALF_0                                RTC_C_CTL13_CALF_0

#define RTCCALF_1                                RTC_C_CTL13_CALF_1

#define RTCCALF_2                                RTC_C_CTL13_CALF_2

#define RTCCALF_3                                RTC_C_CTL13_CALF_3

#define RTCCALF__NONE                            RTC_C_CTL13_CALF__NONE

#define RTCCALF__512                             RTC_C_CTL13_CALF__512

#define RTCCALF__256                             RTC_C_CTL13_CALF__256

#define RTCCALF__1                               RTC_C_CTL13_CALF__1

/* RTCOCAL[RTCOCAL] Bits */

#define RTCOCAL_OFS                              RTC_C_OCAL_OCAL_OFS

#define RTCOCAL_M                                RTC_C_OCAL_OCAL_MASK

/* RTCOCAL[RTCOCALS] Bits */

#define RTCOCALS_OFS                             RTC_C_OCAL_OCALS_OFS

#define RTCOCALS                                 RTC_C_OCAL_OCALS

/* RTCTCMP[RTCTCMP] Bits */

#define RTCTCMP_OFS                              RTC_C_TCMP_TCMPX_OFS

#define RTCTCMP_M                                RTC_C_TCMP_TCMPX_MASK

/* RTCTCMP[RTCTCOK] Bits */

#define RTCTCOK_OFS                              RTC_C_TCMP_TCOK_OFS

#define RTCTCOK                                  RTC_C_TCMP_TCOK

/* RTCTCMP[RTCTCRDY] Bits */

#define RTCTCRDY_OFS                             RTC_C_TCMP_TCRDY_OFS

#define RTCTCRDY                                 RTC_C_TCMP_TCRDY

/* RTCTCMP[RTCTCMPS] Bits */

#define RTCTCMPS_OFS                             RTC_C_TCMP_TCMPS_OFS

#define RTCTCMPS                                 RTC_C_TCMP_TCMPS

/* RTCPS0CTL[RT0PSIFG] Bits */

#define RT0PSIFG_OFS                             RTC_C_PS0CTL_RT0PSIFG_OFS

#define RT0PSIFG                                 RTC_C_PS0CTL_RT0PSIFG

/* RTCPS0CTL[RT0PSIE] Bits */

#define RT0PSIE_OFS                              RTC_C_PS0CTL_RT0PSIE_OFS

#define RT0PSIE                                  RTC_C_PS0CTL_RT0PSIE

/* RTCPS0CTL[RT0IP] Bits */

#define RT0IP_OFS                                RTC_C_PS0CTL_RT0IP_OFS

#define RT0IP_M                                  RTC_C_PS0CTL_RT0IP_MASK

#define RT0IP0                                   RTC_C_PS0CTL_RT0IP0

#define RT0IP1                                   RTC_C_PS0CTL_RT0IP1

#define RT0IP2                                   RTC_C_PS0CTL_RT0IP2

#define RT0IP_0                                  RTC_C_PS0CTL_RT0IP_0

#define RT0IP_1                                  RTC_C_PS0CTL_RT0IP_1

#define RT0IP_2                                  RTC_C_PS0CTL_RT0IP_2

#define RT0IP_3                                  RTC_C_PS0CTL_RT0IP_3

#define RT0IP_4                                  RTC_C_PS0CTL_RT0IP_4

#define RT0IP_5                                  RTC_C_PS0CTL_RT0IP_5

#define RT0IP_6                                  RTC_C_PS0CTL_RT0IP_6

#define RT0IP_7                                  RTC_C_PS0CTL_RT0IP_7

#define RT0IP__2                                 RTC_C_PS0CTL_RT0IP__2

#define RT0IP__4                                 RTC_C_PS0CTL_RT0IP__4

#define RT0IP__8                                 RTC_C_PS0CTL_RT0IP__8

#define RT0IP__16                                RTC_C_PS0CTL_RT0IP__16

#define RT0IP__32                                RTC_C_PS0CTL_RT0IP__32

#define RT0IP__64                                RTC_C_PS0CTL_RT0IP__64

#define RT0IP__128                               RTC_C_PS0CTL_RT0IP__128

#define RT0IP__256                               RTC_C_PS0CTL_RT0IP__256

/* RTCPS1CTL[RT1PSIFG] Bits */

#define RT1PSIFG_OFS                             RTC_C_PS1CTL_RT1PSIFG_OFS

#define RT1PSIFG                                 RTC_C_PS1CTL_RT1PSIFG

/* RTCPS1CTL[RT1PSIE] Bits */

#define RT1PSIE_OFS                              RTC_C_PS1CTL_RT1PSIE_OFS

#define RT1PSIE                                  RTC_C_PS1CTL_RT1PSIE

/* RTCPS1CTL[RT1IP] Bits */

#define RT1IP_OFS                                RTC_C_PS1CTL_RT1IP_OFS

#define RT1IP_M                                  RTC_C_PS1CTL_RT1IP_MASK

#define RT1IP0                                   RTC_C_PS1CTL_RT1IP0

#define RT1IP1                                   RTC_C_PS1CTL_RT1IP1

#define RT1IP2                                   RTC_C_PS1CTL_RT1IP2

#define RT1IP_0                                  RTC_C_PS1CTL_RT1IP_0

#define RT1IP_1                                  RTC_C_PS1CTL_RT1IP_1

#define RT1IP_2                                  RTC_C_PS1CTL_RT1IP_2

#define RT1IP_3                                  RTC_C_PS1CTL_RT1IP_3

#define RT1IP_4                                  RTC_C_PS1CTL_RT1IP_4

#define RT1IP_5                                  RTC_C_PS1CTL_RT1IP_5

#define RT1IP_6                                  RTC_C_PS1CTL_RT1IP_6

#define RT1IP_7                                  RTC_C_PS1CTL_RT1IP_7

#define RT1IP__2                                 RTC_C_PS1CTL_RT1IP__2

#define RT1IP__4                                 RTC_C_PS1CTL_RT1IP__4

#define RT1IP__8                                 RTC_C_PS1CTL_RT1IP__8

#define RT1IP__16                                RTC_C_PS1CTL_RT1IP__16

#define RT1IP__32                                RTC_C_PS1CTL_RT1IP__32

#define RT1IP__64                                RTC_C_PS1CTL_RT1IP__64

#define RT1IP__128                               RTC_C_PS1CTL_RT1IP__128

#define RT1IP__256                               RTC_C_PS1CTL_RT1IP__256

/* RTCPS[RT0PS] Bits */

#define RT0PS_OFS                                RTC_C_PS_RT0PS_OFS

#define RT0PS_M                                  RTC_C_PS_RT0PS_MASK

/* RTCPS[RT1PS] Bits */

#define RT1PS_OFS                                RTC_C_PS_RT1PS_OFS

#define RT1PS_M                                  RTC_C_PS_RT1PS_MASK

/* RTCTIM0[SECONDS] Bits */

#define SECONDS_OFS                              RTC_C_TIM0_SEC_OFS

#define SECONDS_M                                RTC_C_TIM0_SEC_MASK

/* RTCTIM0[MINUTES] Bits */

#define MINUTES_OFS                              RTC_C_TIM0_MIN_OFS

#define MINUTES_M                                RTC_C_TIM0_MIN_MASK

/* RTCTIM0_BCD[SECONDSLOWDIGIT] Bits */

#define SECONDSLOWDIGIT_OFS                      RTC_C_TIM0_SEC_LD_OFS

#define SECONDSLOWDIGIT_M                        RTC_C_TIM0_SEC_LD_MASK

/* RTCTIM0_BCD[SECONDSHIGHDIGIT] Bits */

#define SECONDSHIGHDIGIT_OFS                     RTC_C_TIM0_SEC_HD_OFS

#define SECONDSHIGHDIGIT_M                       RTC_C_TIM0_SEC_HD_MASK

/* RTCTIM0_BCD[MINUTESLOWDIGIT] Bits */

#define MINUTESLOWDIGIT_OFS                      RTC_C_TIM0_MIN_LD_OFS

#define MINUTESLOWDIGIT_M                        RTC_C_TIM0_MIN_LD_MASK

/* RTCTIM0_BCD[MINUTESHIGHDIGIT] Bits */

#define MINUTESHIGHDIGIT_OFS                     RTC_C_TIM0_MIN_HD_OFS

#define MINUTESHIGHDIGIT_M                       RTC_C_TIM0_MIN_HD_MASK

/* RTCTIM1[HOURS] Bits */

#define HOURS_OFS                                RTC_C_TIM1_HOUR_OFS

#define HOURS_M                                  RTC_C_TIM1_HOUR_MASK

/* RTCTIM1[DAYOFWEEK] Bits */

#define DAYOFWEEK_OFS                            RTC_C_TIM1_DOW_OFS

#define DAYOFWEEK_M                              RTC_C_TIM1_DOW_MASK

/* RTCTIM1_BCD[HOURSLOWDIGIT] Bits */

#define HOURSLOWDIGIT_OFS                        RTC_C_TIM1_HOUR_LD_OFS

#define HOURSLOWDIGIT_M                          RTC_C_TIM1_HOUR_LD_MASK

/* RTCTIM1_BCD[HOURSHIGHDIGIT] Bits */

#define HOURSHIGHDIGIT_OFS                       RTC_C_TIM1_HOUR_HD_OFS

#define HOURSHIGHDIGIT_M                         RTC_C_TIM1_HOUR_HD_MASK

/* RTCTIM1_BCD[DAYOFWEEK] Bits */

//#define DAYOFWEEK_OFS                            RTC_C_TIM1_DOW_OFS              /*!< DayofWeek Offset */

//#define DAYOFWEEK_M                              RTC_C_TIM1_DOW_MASK             /*!< Day of week (0 to 6) */

/* RTCDATE[DAY] Bits */

#define DAY_OFS                                  RTC_C_DATE_DAY_OFS

#define DAY_M                                    RTC_C_DATE_DAY_MASK

/* RTCDATE[MONTH] Bits */

#define MONTH_OFS                                RTC_C_DATE_MON_OFS

#define MONTH_M                                  RTC_C_DATE_MON_MASK

/* RTCDATE_BCD[DAYLOWDIGIT] Bits */

#define DAYLOWDIGIT_OFS                          RTC_C_DATE_DAY_LD_OFS

#define DAYLOWDIGIT_M                            RTC_C_DATE_DAY_LD_MASK

/* RTCDATE_BCD[DAYHIGHDIGIT] Bits */

#define DAYHIGHDIGIT_OFS                         RTC_C_DATE_DAY_HD_OFS

#define DAYHIGHDIGIT_M                           RTC_C_DATE_DAY_HD_MASK

/* RTCDATE_BCD[MONTHLOWDIGIT] Bits */

#define MONTHLOWDIGIT_OFS                        RTC_C_DATE_MON_LD_OFS

#define MONTHLOWDIGIT_M                          RTC_C_DATE_MON_LD_MASK

/* RTCDATE_BCD[MONTHHIGHDIGIT] Bits */

#define MONTHHIGHDIGIT_OFS                       RTC_C_DATE_MON_HD_OFS

#define MONTHHIGHDIGIT                           RTC_C_DATE_MON_HD

/* RTCYEAR[YEARLOWBYTE] Bits */

#define YEARLOWBYTE_OFS                          RTC_C_YEAR_YEAR_LB_OFS

#define YEARLOWBYTE_M                            RTC_C_YEAR_YEAR_LB_MASK

/* RTCYEAR[YEARHIGHBYTE] Bits */

#define YEARHIGHBYTE_OFS                         RTC_C_YEAR_YEAR_HB_OFS

#define YEARHIGHBYTE_M                           RTC_C_YEAR_YEAR_HB_MASK

/* RTCYEAR_BCD[YEAR] Bits */

#define YEAR_OFS                                 RTC_C_YEAR_YEAR_OFS

#define YEAR_M                                   RTC_C_YEAR_YEAR_MASK

/* RTCYEAR_BCD[DECADE] Bits */

#define DECADE_OFS                               RTC_C_YEAR_DEC_OFS

#define DECADE_M                                 RTC_C_YEAR_DEC_MASK

/* RTCYEAR_BCD[CENTURYLOWDIGIT] Bits */

#define CENTURYLOWDIGIT_OFS                      RTC_C_YEAR_CENT_LD_OFS

#define CENTURYLOWDIGIT_M                        RTC_C_YEAR_CENT_LD_MASK

/* RTCYEAR_BCD[CENTURYHIGHDIGIT] Bits */

#define CENTURYHIGHDIGIT_OFS                     RTC_C_YEAR_CENT_HD_OFS

#define CENTURYHIGHDIGIT_M                       RTC_C_YEAR_CENT_HD_MASK

/* RTCAMINHR[MINUTES] Bits */

//#define MINUTES_OFS                              RTC_C_AMINHR_MIN_OFS            /*!< Minutes Offset */

//#define MINUTES_M                                RTC_C_AMINHR_MIN_MASK           /*!< Minutes (0 to 59) */

/* RTCAMINHR[MINAE] Bits */

#define MINAE_OFS                                RTC_C_AMINHR_MINAE_OFS

#define MINAE                                    RTC_C_AMINHR_MINAE

/* RTCAMINHR[HOURS] Bits */

//#define HOURS_OFS                                RTC_C_AMINHR_HOUR_OFS           /*!< Hours Offset */

//#define HOURS_M                                  RTC_C_AMINHR_HOUR_MASK          /*!< Hours (0 to 23) */

/* RTCAMINHR[HOURAE] Bits */

#define HOURAE_OFS                               RTC_C_AMINHR_HOURAE_OFS

#define HOURAE                                   RTC_C_AMINHR_HOURAE

/* RTCAMINHR_BCD[MINUTESLOWDIGIT] Bits */

//#define MINUTESLOWDIGIT_OFS                      RTC_C_AMINHR_MIN_LD_OFS         /*!< MinutesLowDigit Offset */

//#define MINUTESLOWDIGIT_M                        RTC_C_AMINHR_MIN_LD_MASK        /*!< Minutes  low digit (0 to 9) */

/* RTCAMINHR_BCD[MINUTESHIGHDIGIT] Bits */

//#define MINUTESHIGHDIGIT_OFS                     RTC_C_AMINHR_MIN_HD_OFS         /*!< MinutesHighDigit Offset */

//#define MINUTESHIGHDIGIT_M                       RTC_C_AMINHR_MIN_HD_MASK        /*!< Minutes  high digit (0 to 5) */

/* RTCAMINHR_BCD[MINAE] Bits */

//#define MINAE_OFS                                RTC_C_AMINHR_MINAE_OFS          /*!< MINAE Offset */

//#define MINAE                                    RTC_C_AMINHR_MINAE              /*!< Alarm enable */

/* RTCAMINHR_BCD[HOURSLOWDIGIT] Bits */

//#define HOURSLOWDIGIT_OFS                        RTC_C_AMINHR_HOUR_LD_OFS        /*!< HoursLowDigit Offset */

//#define HOURSLOWDIGIT_M                          RTC_C_AMINHR_HOUR_LD_MASK       /*!< Hours  low digit (0 to 9) */

/* RTCAMINHR_BCD[HOURSHIGHDIGIT] Bits */

//#define HOURSHIGHDIGIT_OFS                       RTC_C_AMINHR_HOUR_HD_OFS        /*!< HoursHighDigit Offset */

//#define HOURSHIGHDIGIT_M                         RTC_C_AMINHR_HOUR_HD_MASK       /*!< Hours  high digit (0 to 2) */

/* RTCAMINHR_BCD[HOURAE] Bits */

//#define HOURAE_OFS                               RTC_C_AMINHR_HOURAE_OFS         /*!< HOURAE Offset */

//#define HOURAE                                   RTC_C_AMINHR_HOURAE             /*!< Alarm enable */

/* RTCADOWDAY[DAYOFWEEK] Bits */

//#define DAYOFWEEK_OFS                            RTC_C_ADOWDAY_DOW_OFS           /*!< DayofWeek Offset */

//#define DAYOFWEEK_M                              RTC_C_ADOWDAY_DOW_MASK          /*!< Day of week (0 to 6) */

/* RTCADOWDAY[DOWAE] Bits */

#define DOWAE_OFS                                RTC_C_ADOWDAY_DOWAE_OFS

#define DOWAE                                    RTC_C_ADOWDAY_DOWAE

/* RTCADOWDAY[DAYOFMONTH] Bits */

#define DAYOFMONTH_OFS                           RTC_C_ADOWDAY_DAY_OFS

#define DAYOFMONTH_M                             RTC_C_ADOWDAY_DAY_MASK

/* RTCADOWDAY[DAYAE] Bits */

#define DAYAE_OFS                                RTC_C_ADOWDAY_DAYAE_OFS

#define DAYAE                                    RTC_C_ADOWDAY_DAYAE

/* RTCADOWDAY_BCD[DAYOFWEEK] Bits */

//#define DAYOFWEEK_OFS                            RTC_C_ADOWDAY_DOW_OFS           /*!< DayofWeek Offset */

//#define DAYOFWEEK_M                              RTC_C_ADOWDAY_DOW_MASK          /*!< Day of week (0 to 6) */

/* RTCADOWDAY_BCD[DOWAE] Bits */

//#define DOWAE_OFS                                RTC_C_ADOWDAY_DOWAE_OFS         /*!< DOWAE Offset */

//#define DOWAE                                    RTC_C_ADOWDAY_DOWAE             /*!< Alarm enable */

/* RTCADOWDAY_BCD[DAYLOWDIGIT] Bits */

//#define DAYLOWDIGIT_OFS                          RTC_C_ADOWDAY_DAY_LD_OFS        /*!< DayLowDigit Offset */

//#define DAYLOWDIGIT_M                            RTC_C_ADOWDAY_DAY_LD_MASK       /*!< Day of month  low digit (0 to 9) */

/* RTCADOWDAY_BCD[DAYHIGHDIGIT] Bits */

//#define DAYHIGHDIGIT_OFS                         RTC_C_ADOWDAY_DAY_HD_OFS        /*!< DayHighDigit Offset */

//#define DAYHIGHDIGIT_M                           RTC_C_ADOWDAY_DAY_HD_MASK       /*!< Day of month  high digit (0 to 3) */

/* RTCADOWDAY_BCD[DAYAE] Bits */

//#define DAYAE_OFS                                RTC_C_ADOWDAY_DAYAE_OFS         /*!< DAYAE Offset */

//#define DAYAE                                    RTC_C_ADOWDAY_DAYAE             /*!< Alarm enable */

/* Pre-defined bitfield values */

#define RTCKEY                                             RTC_C_KEY

#define RTCKEY_H                                           RTC_C_KEY_H

#define RTCKEY_VAL                                         RTC_C_KEY_VAL

/******************************************************************************

* TIMER_A Bits (legacy section)

******************************************************************************/

/* TA0CTL[TAIFG] Bits */

#define TAIFG_OFS                                TIMER_A_CTL_IFG_OFS

#define TAIFG                                    TIMER_A_CTL_IFG

/* TA0CTL[TAIE] Bits */

#define TAIE_OFS                                 TIMER_A_CTL_IE_OFS

#define TAIE                                     TIMER_A_CTL_IE

/* TA0CTL[TACLR] Bits */

#define TACLR_OFS                                TIMER_A_CTL_CLR_OFS

#define TACLR                                    TIMER_A_CTL_CLR

/* TA0CTL[MC] Bits */

#define MC_OFS                                   TIMER_A_CTL_MC_OFS

#define MC_M                                     TIMER_A_CTL_MC_MASK

#define MC0                                      TIMER_A_CTL_MC0

#define MC1                                      TIMER_A_CTL_MC1

#define MC_0                                     TIMER_A_CTL_MC_0

#define MC_1                                     TIMER_A_CTL_MC_1

#define MC_2                                     TIMER_A_CTL_MC_2

#define MC_3                                     TIMER_A_CTL_MC_3

#define MC__STOP                                 TIMER_A_CTL_MC__STOP

#define MC__UP                                   TIMER_A_CTL_MC__UP

#define MC__CONTINUOUS                           TIMER_A_CTL_MC__CONTINUOUS

#define MC__UPDOWN                               TIMER_A_CTL_MC__UPDOWN

/* TA0CTL[ID] Bits */

#define ID_OFS                                   TIMER_A_CTL_ID_OFS

#define ID_M                                     TIMER_A_CTL_ID_MASK

#define ID0                                      TIMER_A_CTL_ID0

#define ID1                                      TIMER_A_CTL_ID1

#define ID_0                                     TIMER_A_CTL_ID_0

#define ID_1                                     TIMER_A_CTL_ID_1

#define ID_2                                     TIMER_A_CTL_ID_2

#define ID_3                                     TIMER_A_CTL_ID_3

#define ID__1                                    TIMER_A_CTL_ID__1

#define ID__2                                    TIMER_A_CTL_ID__2

#define ID__4                                    TIMER_A_CTL_ID__4

#define ID__8                                    TIMER_A_CTL_ID__8

/* TA0CTL[TASSEL] Bits */

#define TASSEL_OFS                               TIMER_A_CTL_SSEL_OFS

#define TASSEL_M                                 TIMER_A_CTL_SSEL_MASK

#define TASSEL0                                  TIMER_A_CTL_SSEL0

#define TASSEL1                                  TIMER_A_CTL_SSEL1

#define TASSEL_0                                 TIMER_A_CTL_TASSEL_0

#define TASSEL_1                                 TIMER_A_CTL_TASSEL_1

#define TASSEL_2                                 TIMER_A_CTL_TASSEL_2

#define TASSEL_3                                 TIMER_A_CTL_TASSEL_3

#define TASSEL__TACLK                            TIMER_A_CTL_SSEL__TACLK

#define TASSEL__ACLK                             TIMER_A_CTL_SSEL__ACLK

#define TASSEL__SMCLK                            TIMER_A_CTL_SSEL__SMCLK

#define TASSEL__INCLK                            TIMER_A_CTL_SSEL__INCLK

/* TA0CCTLn[CCIFG] Bits */

#define CCIFG_OFS                                TIMER_A_CCTLN_CCIFG_OFS

#define CCIFG                                    TIMER_A_CCTLN_CCIFG

/* TA0CCTLn[COV] Bits */

#define COV_OFS                                  TIMER_A_CCTLN_COV_OFS

#define COV                                      TIMER_A_CCTLN_COV

/* TA0CCTLn[OUT] Bits */

#define OUT_OFS                                  TIMER_A_CCTLN_OUT_OFS

//#define OUT                                      TIMER_A_CCTLN_OUT               /*!< Output */

/* TA0CCTLn[CCI] Bits */

#define CCI_OFS                                  TIMER_A_CCTLN_CCI_OFS

#define CCI                                      TIMER_A_CCTLN_CCI

/* TA0CCTLn[CCIE] Bits */

#define CCIE_OFS                                 TIMER_A_CCTLN_CCIE_OFS

#define CCIE                                     TIMER_A_CCTLN_CCIE

/* TA0CCTLn[OUTMOD] Bits */

#define OUTMOD_OFS                               TIMER_A_CCTLN_OUTMOD_OFS

#define OUTMOD_M                                 TIMER_A_CCTLN_OUTMOD_MASK

#define OUTMOD0                                  TIMER_A_CCTLN_OUTMOD0

#define OUTMOD1                                  TIMER_A_CCTLN_OUTMOD1

#define OUTMOD2                                  TIMER_A_CCTLN_OUTMOD2

#define OUTMOD_0                                 TIMER_A_CCTLN_OUTMOD_0

#define OUTMOD_1                                 TIMER_A_CCTLN_OUTMOD_1

#define OUTMOD_2                                 TIMER_A_CCTLN_OUTMOD_2

#define OUTMOD_3                                 TIMER_A_CCTLN_OUTMOD_3

#define OUTMOD_4                                 TIMER_A_CCTLN_OUTMOD_4

#define OUTMOD_5                                 TIMER_A_CCTLN_OUTMOD_5

#define OUTMOD_6                                 TIMER_A_CCTLN_OUTMOD_6

#define OUTMOD_7                                 TIMER_A_CCTLN_OUTMOD_7

/* TA0CCTLn[CAP] Bits */

#define CAP_OFS                                  TIMER_A_CCTLN_CAP_OFS

#define CAP                                      TIMER_A_CCTLN_CAP

/* TA0CCTLn[SCCI] Bits */

#define SCCI_OFS                                 TIMER_A_CCTLN_SCCI_OFS

#define SCCI                                     TIMER_A_CCTLN_SCCI

/* TA0CCTLn[SCS] Bits */

#define SCS_OFS                                  TIMER_A_CCTLN_SCS_OFS

#define SCS                                      TIMER_A_CCTLN_SCS

/* TA0CCTLn[CCIS] Bits */

#define CCIS_OFS                                 TIMER_A_CCTLN_CCIS_OFS

#define CCIS_M                                   TIMER_A_CCTLN_CCIS_MASK

#define CCIS0                                    TIMER_A_CCTLN_CCIS0

#define CCIS1                                    TIMER_A_CCTLN_CCIS1

#define CCIS_0                                   TIMER_A_CCTLN_CCIS_0

#define CCIS_1                                   TIMER_A_CCTLN_CCIS_1

#define CCIS_2                                   TIMER_A_CCTLN_CCIS_2

#define CCIS_3                                   TIMER_A_CCTLN_CCIS_3

#define CCIS__CCIA                               TIMER_A_CCTLN_CCIS__CCIA

#define CCIS__CCIB                               TIMER_A_CCTLN_CCIS__CCIB

#define CCIS__GND                                TIMER_A_CCTLN_CCIS__GND

#define CCIS__VCC                                TIMER_A_CCTLN_CCIS__VCC

/* TA0CCTLn[CM] Bits */

#define CM_OFS                                   TIMER_A_CCTLN_CM_OFS

#define CM_M                                     TIMER_A_CCTLN_CM_MASK

#define CM0                                      TIMER_A_CCTLN_CM0

#define CM1                                      TIMER_A_CCTLN_CM1

#define CM_0                                     TIMER_A_CCTLN_CM_0

#define CM_1                                     TIMER_A_CCTLN_CM_1

#define CM_2                                     TIMER_A_CCTLN_CM_2

#define CM_3                                     TIMER_A_CCTLN_CM_3

#define CM__NONE                                 TIMER_A_CCTLN_CM__NONE

#define CM__RISING                               TIMER_A_CCTLN_CM__RISING

#define CM__FALLING                              TIMER_A_CCTLN_CM__FALLING

#define CM__BOTH                                 TIMER_A_CCTLN_CM__BOTH

/* TA0EX0[TAIDEX] Bits */

#define TAIDEX_OFS                               TIMER_A_EX0_IDEX_OFS

#define TAIDEX_M                                 TIMER_A_EX0_IDEX_MASK

#define TAIDEX0                                  TIMER_A_EX0_IDEX0

#define TAIDEX1                                  TIMER_A_EX0_IDEX1

#define TAIDEX2                                  TIMER_A_EX0_IDEX2

#define TAIDEX_0                                 TIMER_A_EX0_TAIDEX_0

#define TAIDEX_1                                 TIMER_A_EX0_TAIDEX_1

#define TAIDEX_2                                 TIMER_A_EX0_TAIDEX_2

#define TAIDEX_3                                 TIMER_A_EX0_TAIDEX_3

#define TAIDEX_4                                 TIMER_A_EX0_TAIDEX_4

#define TAIDEX_5                                 TIMER_A_EX0_TAIDEX_5

#define TAIDEX_6                                 TIMER_A_EX0_TAIDEX_6

#define TAIDEX_7                                 TIMER_A_EX0_TAIDEX_7

#define TAIDEX__1                                TIMER_A_EX0_IDEX__1

#define TAIDEX__2                                TIMER_A_EX0_IDEX__2

#define TAIDEX__3                                TIMER_A_EX0_IDEX__3

#define TAIDEX__4                                TIMER_A_EX0_IDEX__4

#define TAIDEX__5                                TIMER_A_EX0_IDEX__5

#define TAIDEX__6                                TIMER_A_EX0_IDEX__6

#define TAIDEX__7                                TIMER_A_EX0_IDEX__7

#define TAIDEX__8                                TIMER_A_EX0_IDEX__8

/******************************************************************************

* WDT_A Bits (legacy section)

******************************************************************************/

/* WDTCTL[WDTIS] Bits */

#define WDTIS_OFS                                WDT_A_CTL_IS_OFS

#define WDTIS_M                                  WDT_A_CTL_IS_MASK

#define WDTIS0                                   WDT_A_CTL_IS0

#define WDTIS1                                   WDT_A_CTL_IS1

#define WDTIS2                                   WDT_A_CTL_IS2

#define WDTIS_0                                  WDT_A_CTL_IS_0

#define WDTIS_1                                  WDT_A_CTL_IS_1

#define WDTIS_2                                  WDT_A_CTL_IS_2

#define WDTIS_3                                  WDT_A_CTL_IS_3

#define WDTIS_4                                  WDT_A_CTL_IS_4

#define WDTIS_5                                  WDT_A_CTL_IS_5

#define WDTIS_6                                  WDT_A_CTL_IS_6

#define WDTIS_7                                  WDT_A_CTL_IS_7

/* WDTCTL[WDTCNTCL] Bits */

#define WDTCNTCL_OFS                             WDT_A_CTL_CNTCL_OFS

#define WDTCNTCL                                 WDT_A_CTL_CNTCL

/* WDTCTL[WDTTMSEL] Bits */

#define WDTTMSEL_OFS                             WDT_A_CTL_TMSEL_OFS

#define WDTTMSEL                                 WDT_A_CTL_TMSEL

/* WDTCTL[WDTSSEL] Bits */

#define WDTSSEL_OFS                              WDT_A_CTL_SSEL_OFS

#define WDTSSEL_M                                WDT_A_CTL_SSEL_MASK

#define WDTSSEL0                                 WDT_A_CTL_SSEL0

#define WDTSSEL1                                 WDT_A_CTL_SSEL1

#define WDTSSEL_0                                WDT_A_CTL_SSEL_0

#define WDTSSEL_1                                WDT_A_CTL_SSEL_1

#define WDTSSEL_2                                WDT_A_CTL_SSEL_2

#define WDTSSEL_3                                WDT_A_CTL_SSEL_3

#define WDTSSEL__SMCLK                           WDT_A_CTL_SSEL__SMCLK

#define WDTSSEL__ACLK                            WDT_A_CTL_SSEL__ACLK

#define WDTSSEL__VLOCLK                          WDT_A_CTL_SSEL__VLOCLK

#define WDTSSEL__BCLK                            WDT_A_CTL_SSEL__BCLK

/* WDTCTL[WDTHOLD] Bits */

#define WDTHOLD_OFS                              WDT_A_CTL_HOLD_OFS

#define WDTHOLD                                  WDT_A_CTL_HOLD

/* WDTCTL[WDTPW] Bits */

#define WDTPW_OFS                                WDT_A_CTL_PW_OFS

#define WDTPW_M                                  WDT_A_CTL_PW_MASK

/* Pre-defined bitfield values */

#define WDTPW                                          WDT_A_CTL_PW

#ifdef __cplusplus

}

#endif


#endif /* __MSP432P401R_CLASSIC_H__ */