YAHAL
Yet Another Hardware Abstraction Library
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esp8266ex.h
1/*
2 * esp8266ex_new.h
3 *
4 * Created on: 03.07.2016
5 * Author: aterstegge
6 */
7
8#ifndef ESP8266EX_H_
9#define ESP8266EX_H_
10
11#include <stdint.h>
12
13#define __RO const volatile
14#define __WO volatile
15#define __RW volatile
16
18// Memory layout
20#define DPORT0 ((uint32_t)0x3ff00000) // dport0 registers
21#define MM_IO ((uint32_t)0x60000000) // Memory Mapped IO
22
23// memory mapped peripherals base addresses
24#define UART0_BASE (MM_IO + 0x000) // Base address of UART0 module
25#define SPI1_BASE (MM_IO + 0x100) // Base address of SPI1 module
26#define SPI0_BASE (MM_IO + 0x200) // Base address of SPI0 module
27#define GPIO_BASE (MM_IO + 0x300) // Base address of GPIO module
28#define FRC_BASE (MM_IO + 0x600) // Base address of FRC module
29#define RTC_BASE (MM_IO + 0x700) // Base address of RTC module
30#define IOMUX_BASE (MM_IO + 0x800) // Base address of IOMUX module
31#define WDT_BASE (MM_IO + 0x900) // Base address of WDT module
32#define UART1_BASE (MM_IO + 0xf00) // Base address of UART1 module
33
35// Helper templates and macros
37template <typename T, int Offset, int Bits>
38struct BitFieldMember_RO
39{
40 private:
41 T value; // This is the value which is 'mirrored' by the union
42 static const T max = (T(1) << Bits) - T(1);
43
44 public:
45 inline operator T() const {
46 return (value >> Offset) & max;
47 }
48};
49
50template <typename T, int Offset, int Bits>
51struct BitFieldMember_WO
52{
53 private:
54 T value; // This is the value which is 'mirrored' by the union
55 static const T max = (T(1) << Bits) - T(1);
56 static const T mask = max << Offset;
57
58 public:
59 inline BitFieldMember_WO & operator=(T v) {
60 value = (value & ~mask) | ((v & max) << Offset);
61 return *this;
62 }
63};
64
65template <typename T, int Offset, int Bits>
66struct BitFieldMember_RW
67{
68 private:
69 T value; // This is the value which is 'mirrored' by the union
70 static const T max = (T(1) << Bits) - T(1);
71 static const T mask = max << Offset;
72
73 public:
74 inline operator T() const {
75 return (value >> Offset) & max;
76 }
77 inline BitFieldMember_RW & operator=(T v) {
78 value = (value & ~mask) | ((v & max) << Offset);
79 return *this;
80 }
81};
82
83#define BEGIN_BITFIELD_TYPE(typeName, T) \
84 union typeName \
85 { \
86 T value; \
87 typeName& operator=(T v) { value = v; return *this; } \
88 operator T&() { return value; } \
89 operator T() const { return value; } \
90 typedef T StorageType;
91
92#define ADD_BITFIELD_MEMBER_RO(memberName, offset, bits) \
93 BitFieldMember_RO<StorageType, offset, bits> memberName;
94
95#define ADD_BITFIELD_MEMBER_WO(memberName, offset, bits) \
96 BitFieldMember_WO<StorageType, offset, bits> memberName;
97
98#define ADD_BITFIELD_MEMBER_RW(memberName, offset, bits) \
99 BitFieldMember_RW<StorageType, offset, bits> memberName;
100
101#define END_BITFIELD_TYPE() \
102 };
103
105// SPI (SPI0, SPI1) definitions //
107
108namespace _SPI_ {
109
110 BEGIN_BITFIELD_TYPE(cmd_t, uint32_t)
111 ADD_BITFIELD_MEMBER_RW(USR, 18, 1)
112 ADD_BITFIELD_MEMBER_RW(HPM, 19, 1)
113 ADD_BITFIELD_MEMBER_RW(RES, 20, 1)
114 ADD_BITFIELD_MEMBER_RW(DP, 21, 1)
115 ADD_BITFIELD_MEMBER_RW(CE, 22, 1)
116 ADD_BITFIELD_MEMBER_RW(BE, 23, 1)
117 ADD_BITFIELD_MEMBER_RW(SE, 24, 1)
118 ADD_BITFIELD_MEMBER_RW(PP, 25, 1)
119 ADD_BITFIELD_MEMBER_RW(WRSR, 26, 1)
120 ADD_BITFIELD_MEMBER_RW(RDSR, 27, 1)
121 ADD_BITFIELD_MEMBER_RW(RDID, 28, 1)
122 ADD_BITFIELD_MEMBER_RW(WRDI, 29, 1)
123 ADD_BITFIELD_MEMBER_RW(WREN, 30, 1)
124 ADD_BITFIELD_MEMBER_RW(READ, 31, 1)
125 END_BITFIELD_TYPE()
126
127 BEGIN_BITFIELD_TYPE(ctrl_t, uint32_t)
128 ADD_BITFIELD_MEMBER_RW(FASTRD, 13, 1)
129 ADD_BITFIELD_MEMBER_RW(DOUT, 14, 1)
130 ADD_BITFIELD_MEMBER_RW(RESANDRES, 15, 1)
131 ADD_BITFIELD_MEMBER_RW(SSTAAI, 16, 1)
132 ADD_BITFIELD_MEMBER_RW(AHB, 17, 1)
133 ADD_BITFIELD_MEMBER_RW(HOLD, 18, 1)
134 ADD_BITFIELD_MEMBER_RW(SHARE, 19, 1)
135 ADD_BITFIELD_MEMBER_RW(QOUT, 20, 1)
136 ADD_BITFIELD_MEMBER_RW(WPR, 21, 1)
137 ADD_BITFIELD_MEMBER_RW(TWOBSE, 22, 1)
138 ADD_BITFIELD_MEMBER_RW(DIO, 23, 1)
139 ADD_BITFIELD_MEMBER_RW(QIO, 24, 1)
140 ADD_BITFIELD_MEMBER_RW(RD_BO, 25, 1)
141 ADD_BITFIELD_MEMBER_RW(WR_BO, 26, 1)
142 END_BITFIELD_TYPE()
143
144 BEGIN_BITFIELD_TYPE(ctrl1_t, uint32_t)
145 ADD_BITFIELD_MEMBER_RW(BTL, 0,16)
146 ADD_BITFIELD_MEMBER_RW(TRES, 16,12)
147 ADD_BITFIELD_MEMBER_RW(TCSH, 28, 4)
148 END_BITFIELD_TYPE()
149
150 BEGIN_BITFIELD_TYPE(status_t, uint32_t)
151 ADD_BITFIELD_MEMBER_RW(BUSY, 0, 1)
152 ADD_BITFIELD_MEMBER_RW(WRE, 1, 1)
153 ADD_BITFIELD_MEMBER_RW(BP0, 2, 1)
154 ADD_BITFIELD_MEMBER_RW(BP1, 3, 1)
155 ADD_BITFIELD_MEMBER_RW(BP2, 4, 1)
156 ADD_BITFIELD_MEMBER_RW(TBP, 5, 1)
157 ADD_BITFIELD_MEMBER_RW(SP, 7, 1)
158 ADD_BITFIELD_MEMBER_RW(WB, 16, 8)
159 ADD_BITFIELD_MEMBER_RW(EXT, 24, 8)
160 END_BITFIELD_TYPE()
161
162 BEGIN_BITFIELD_TYPE(ctrl2_t, uint32_t)
163 ADD_BITFIELD_MEMBER_RW(ST, 0, 4)
164 ADD_BITFIELD_MEMBER_RW(HT, 4, 4)
165 ADD_BITFIELD_MEMBER_RW(CKOLM, 8, 4)
166 ADD_BITFIELD_MEMBER_RW(CKOHM, 12, 4)
167 ADD_BITFIELD_MEMBER_RW(MISODM, 16, 2)
168 ADD_BITFIELD_MEMBER_RW(MISODN, 18, 3)
169 ADD_BITFIELD_MEMBER_RW(MOSIDM, 21, 2)
170 ADD_BITFIELD_MEMBER_RW(MOSIDN, 23, 3)
171 ADD_BITFIELD_MEMBER_RW(CSDM, 26, 2)
172 ADD_BITFIELD_MEMBER_RW(CSDN, 28, 4)
173 END_BITFIELD_TYPE()
174
175 BEGIN_BITFIELD_TYPE(clock_t, uint32_t)
176 ADD_BITFIELD_MEMBER_RW(CNT_L, 0, 6)
177 ADD_BITFIELD_MEMBER_RW(CNT_H, 6, 6)
178 ADD_BITFIELD_MEMBER_RW(CNT_N, 12, 6)
179 ADD_BITFIELD_MEMBER_RW(DIVPRE, 18,13)
180 ADD_BITFIELD_MEMBER_RW(EQU_SYSCLK, 31, 1)
181 END_BITFIELD_TYPE()
182
183 BEGIN_BITFIELD_TYPE(user_t, uint32_t)
184 ADD_BITFIELD_MEMBER_RW(DUPLEX, 0, 1)
185 ADD_BITFIELD_MEMBER_RW(AHBUCMD4B, 1, 1)
186 ADD_BITFIELD_MEMBER_RW(AHBUCMD, 3, 1)
187 ADD_BITFIELD_MEMBER_RW(CSHOLD, 4, 1)
188 ADD_BITFIELD_MEMBER_RW(CSSETUP, 5, 1)
189 ADD_BITFIELD_MEMBER_RW(SSE, 6, 1)
190 ADD_BITFIELD_MEMBER_RW(SME, 7, 1)
191 ADD_BITFIELD_MEMBER_RW(AHBEM, 8, 2)
192 ADD_BITFIELD_MEMBER_RW(RDBYO, 10, 1)
193 ADD_BITFIELD_MEMBER_RW(WRBYO, 11, 1)
194 ADD_BITFIELD_MEMBER_RW(FWDUAL, 12, 1)
195 ADD_BITFIELD_MEMBER_RW(FWQUAD, 13, 1)
196 ADD_BITFIELD_MEMBER_RW(FWDIO, 14, 1)
197 ADD_BITFIELD_MEMBER_RW(FWQIO, 15, 1)
198 ADD_BITFIELD_MEMBER_RW(SIO, 16, 1)
199 ADD_BITFIELD_MEMBER_RW(HOLDPOL, 17, 1)
200 ADD_BITFIELD_MEMBER_RW(MOSIHOLD, 18, 1)
201 ADD_BITFIELD_MEMBER_RW(MISOHOLD, 19, 1)
202 ADD_BITFIELD_MEMBER_RW(DUMMYHOLD, 20, 1)
203 ADD_BITFIELD_MEMBER_RW(ADDRHOLD, 21, 1)
204 ADD_BITFIELD_MEMBER_RW(CMDHOLD, 22, 1)
205 ADD_BITFIELD_MEMBER_RW(PREPHOLD, 23, 1)
206 ADD_BITFIELD_MEMBER_RW(MISOH, 24, 1)
207 ADD_BITFIELD_MEMBER_RW(MOSIH, 25, 1)
208 ADD_BITFIELD_MEMBER_RW(DUMMYIDLE, 26, 1)
209 ADD_BITFIELD_MEMBER_RW(MOSI, 27, 1)
210 ADD_BITFIELD_MEMBER_RW(MISO, 28, 1)
211 ADD_BITFIELD_MEMBER_RW(DUMMY, 29, 1)
212 ADD_BITFIELD_MEMBER_RW(ADDR, 30, 1)
213 ADD_BITFIELD_MEMBER_RW(COMMAND, 31, 1)
214 END_BITFIELD_TYPE()
215
216 BEGIN_BITFIELD_TYPE(user1_t, uint32_t)
217 ADD_BITFIELD_MEMBER_RW(DUMMY_CYC, 0, 8)
218 ADD_BITFIELD_MEMBER_RW(MISO_LEN, 8, 9)
219 ADD_BITFIELD_MEMBER_RW(MOSI_LEN, 17, 9)
220 ADD_BITFIELD_MEMBER_RW(ADDR_LEN, 26, 6)
221 END_BITFIELD_TYPE()
222
223 BEGIN_BITFIELD_TYPE(user2_t, uint32_t)
224 ADD_BITFIELD_MEMBER_RW(CMD_VAL, 0,16)
225 ADD_BITFIELD_MEMBER_RW(CMD_LEN, 28, 4)
226 END_BITFIELD_TYPE()
227
228 BEGIN_BITFIELD_TYPE(pin_t, uint32_t)
229 ADD_BITFIELD_MEMBER_RW(CS0_DIS, 0, 1)
230 ADD_BITFIELD_MEMBER_RW(CS1_DIS, 1, 1)
231 ADD_BITFIELD_MEMBER_RW(CS2_DIS, 2, 1)
232 END_BITFIELD_TYPE()
233
234 BEGIN_BITFIELD_TYPE(slave_t, uint32_t)
235 ADD_BITFIELD_MEMBER_RW(RD_BUF_DONE, 0, 1)
236 ADD_BITFIELD_MEMBER_RW(WR_BUF_DONE, 1, 1)
237 ADD_BITFIELD_MEMBER_RW(RD_STA_DONE, 2, 1)
238 ADD_BITFIELD_MEMBER_RW(WR_STA_DONE, 3, 1)
239 ADD_BITFIELD_MEMBER_RW(TRANS_DONE, 4, 1)
240 ADD_BITFIELD_MEMBER_RW(RD_BUF_IE, 5, 1)
241 ADD_BITFIELD_MEMBER_RW(WR_BUF_IE, 6, 1)
242 ADD_BITFIELD_MEMBER_RW(RD_STA_IE, 7, 1)
243 ADD_BITFIELD_MEMBER_RW(WR_STA_IE, 8, 1)
244 ADD_BITFIELD_MEMBER_RW(TRANS_IE, 9, 1)
245 ADD_BITFIELD_MEMBER_RW(CS_IM, 10, 2)
246 ADD_BITFIELD_MEMBER_RW(SLV_LST_CMD, 17, 3)
247 ADD_BITFIELD_MEMBER_RW(SLV_LST_ST, 20, 3)
248 ADD_BITFIELD_MEMBER_RO(TRANS_CNT, 23, 4)
249 ADD_BITFIELD_MEMBER_RW(CMD_DEFINE, 27, 1)
250 ADD_BITFIELD_MEMBER_RW(WRRD_STA_EN, 28, 1)
251 ADD_BITFIELD_MEMBER_RW(WRRD_BUF_EN, 29, 1)
252 ADD_BITFIELD_MEMBER_RW(SLV_MODE, 30, 1)
253 ADD_BITFIELD_MEMBER_RW(SYNC_RESET, 31, 1)
254 END_BITFIELD_TYPE()
255
256 BEGIN_BITFIELD_TYPE(slave1_t, uint32_t)
257 ADD_BITFIELD_MEMBER_RW(RDB_DUM_EN, 0, 1)
258 ADD_BITFIELD_MEMBER_RW(WRB_DUM_EN, 1, 1)
259 ADD_BITFIELD_MEMBER_RW(RDS_DUM_EN, 2, 1)
260 ADD_BITFIELD_MEMBER_RW(WRS_DUM_EN, 3, 1)
261 ADD_BITFIELD_MEMBER_RW(WR_ADR_LEN, 4, 6)
262 ADD_BITFIELD_MEMBER_RW(RD_ADR_LEN, 10, 6)
263 ADD_BITFIELD_MEMBER_RW(BUF_LEN, 16, 9)
264 ADD_BITFIELD_MEMBER_RW(SLV_STAT_RD, 25, 9)
265 ADD_BITFIELD_MEMBER_RW(SLV_STAT_FST,26, 9)
266 ADD_BITFIELD_MEMBER_RW(STATUS_LEN, 27, 5)
267 END_BITFIELD_TYPE()
268
269 BEGIN_BITFIELD_TYPE(slave2_t, uint32_t)
270 ADD_BITFIELD_MEMBER_RW(RDSTA_D_LEN, 0, 8)
271 ADD_BITFIELD_MEMBER_RW(WRSTA_D_LEN, 8, 8)
272 ADD_BITFIELD_MEMBER_RW(RDBUF_D_LEN, 18, 8)
273 ADD_BITFIELD_MEMBER_RW(WRBUF_D_LEN, 24, 8)
274 END_BITFIELD_TYPE()
275
276 BEGIN_BITFIELD_TYPE(slave3_t, uint32_t)
277 ADD_BITFIELD_MEMBER_RW(RDBUF_C_VAL, 0, 8)
278 ADD_BITFIELD_MEMBER_RW(WRBUF_C_VAL, 8, 8)
279 ADD_BITFIELD_MEMBER_RW(RDSTA_C_VAL, 18, 8)
280 ADD_BITFIELD_MEMBER_RW(WRSTA_C_VAL, 24, 8)
281 END_BITFIELD_TYPE()
282
283 BEGIN_BITFIELD_TYPE(ext0_t, uint32_t)
284 ADD_BITFIELD_MEMBER_RW(T_PP_TIME, 0,12)
285 ADD_BITFIELD_MEMBER_RW(T_PP_SHIFT, 16, 4)
286 ADD_BITFIELD_MEMBER_RW(T_PP_ENA, 31, 1)
287 END_BITFIELD_TYPE()
288
289 BEGIN_BITFIELD_TYPE(ext1_t, uint32_t)
290 ADD_BITFIELD_MEMBER_RW(T_ERA_TIME, 0,12)
291 ADD_BITFIELD_MEMBER_RW(T_ERA_SHIFT, 16, 4)
292 ADD_BITFIELD_MEMBER_RW(T_ERA_ENA, 31, 1)
293 END_BITFIELD_TYPE()
294
295 BEGIN_BITFIELD_TYPE(ext2_t, uint32_t)
296 ADD_BITFIELD_MEMBER_RW(SPI_ST, 0, 3)
297 END_BITFIELD_TYPE()
298
299 BEGIN_BITFIELD_TYPE(ext3_t, uint32_t)
300 ADD_BITFIELD_MEMBER_RW(INT_HOLD_ENA, 0, 2)
301 END_BITFIELD_TYPE()
302
303 struct Type {
304 cmd_t CMD;
305 __RW uint32_t ADDR;
306 ctrl_t CTRL;
307 ctrl1_t CTRL1;
308 status_t RD_STATUS;
309 ctrl2_t CTRL2;
310 clock_t CLOCK;
311 user_t USER;
312 user1_t USER1;
313 user2_t USER2;
314 __RW uint32_t WR_STATUS;
315 pin_t PIN;
316 slave_t SLAVE;
317 slave1_t SLAVE1;
318 slave2_t SLAVE2;
319 slave3_t SLAVE3;
320 __RW uint32_t W[16];
321 __RO uint32_t dummy[28];
322 ext0_t E0;
323 ext1_t E1;
324 ext2_t E2;
325 ext3_t E3;
326 };
327}
328
329//_SPI_::Type & ESP_SPI0 = (*(_SPI_::Type *) SPI0_BASE);
330//_SPI_::Type & ESP_SPI1 = (*(_SPI_::Type *) SPI1_BASE);
331
332#define SPI0 (*(ESP_SPI::Type *) SPI0_BASE)
333#define SPI1 (*(ESP_SPI::Type *) SPI1_BASE)
334
336// GPIO definitions //
338
339namespace _GPIO_ {
340
341 BEGIN_BITFIELD_TYPE(out_t, uint32_t)
342 ADD_BITFIELD_MEMBER_RW(DATA, 0, 16)
343 ADD_BITFIELD_MEMBER_RW(BT_SEL, 16, 16)
344 END_BITFIELD_TYPE()
345
346 BEGIN_BITFIELD_TYPE(enable_t, uint32_t)
347 ADD_BITFIELD_MEMBER_RW(DATA, 0, 16)
348 ADD_BITFIELD_MEMBER_RW(SDIO_SEL,16, 6)
349 END_BITFIELD_TYPE()
350
351 BEGIN_BITFIELD_TYPE(in_t, uint32_t)
352 ADD_BITFIELD_MEMBER_RO(DATA, 0, 16)
353 ADD_BITFIELD_MEMBER_RO(STRAPPING, 16, 16)
354 END_BITFIELD_TYPE()
355
356 BEGIN_BITFIELD_TYPE(pin_t, uint32_t)
357 ADD_BITFIELD_MEMBER_RW(SOURCE, 0, 1)
358 ADD_BITFIELD_MEMBER_RW(DRIVER, 2, 1)
359 ADD_BITFIELD_MEMBER_RW(INT_TYPE, 7, 3)
360 ADD_BITFIELD_MEMBER_RW(WAKEUP_ENABLE, 10, 1)
361 END_BITFIELD_TYPE()
362
363 // values for SOURCE
364 const uint32_t SOURCE_GPIO = 0;
365 const uint32_t SOURCE_SIGMA_DELTA = 1;
366 // values for DRIVER
367 const uint32_t DRIVER_PUSH_PULL = 0;
368 const uint32_t DRIVER_OPEN_DRAIN = 1;
369 // values for INT_TYPE
370 const uint32_t INT_DISABLE = 0;
371 const uint32_t INT_RAISING_EDGE = 1;
372 const uint32_t INT_FALLING_EDGE = 2;
373 const uint32_t INT_BOTH_EDGES = 3;
374 const uint32_t INT_LEVEL_LOW = 4;
375 const uint32_t INT_LEVEL_HIGH = 5;
376
377 BEGIN_BITFIELD_TYPE(sigmadelta_t, uint32_t)
378 ADD_BITFIELD_MEMBER_RW(TARGET, 0, 8)
379 ADD_BITFIELD_MEMBER_RW(PRESCALE, 8, 8)
380 ADD_BITFIELD_MEMBER_RW(ENABLE, 16, 1)
381 END_BITFIELD_TYPE()
382
383 BEGIN_BITFIELD_TYPE(rtc_sync_t, uint32_t)
384 ADD_BITFIELD_MEMBER_RW(PERIOD_NUM, 0, 10)
385 ADD_BITFIELD_MEMBER_RW(CALIB_START, 31, 1)
386 END_BITFIELD_TYPE()
387
388 BEGIN_BITFIELD_TYPE(rtc_value_t, uint32_t)
389 ADD_BITFIELD_MEMBER_RW(CALIB_VALUE, 0, 20)
390 ADD_BITFIELD_MEMBER_RW(CALIB_RDY_REAL, 30, 1)
391 ADD_BITFIELD_MEMBER_RW(CALIB_RDY, 31, 1)
392 END_BITFIELD_TYPE()
393
394 struct Type {
395 out_t OUT;
396 __WO uint32_t OUT_DATA_W1TS;
397 __WO uint32_t OUT_DATA_W1TC;
398 enable_t ENABLE;
399 __WO uint32_t ENABLE_W1TS;
400 __WO uint32_t ENABLE_W1TC;
401 in_t IN;
402 __RW uint32_t STATUS;
403 __WO uint32_t STATUS_W1TS;
404 __WO uint32_t STATUS_W1TC;
405 pin_t PIN[16];
406 sigmadelta_t SIGMA_DELTA;
407 rtc_sync_t RTC_CALIB_SYNC;
408 rtc_value_t RTC_CALIB_VALUE;
409 };
410}
411
412//_GPIO_::Type & ESP_GPIO = (*(_GPIO_::Type *) GPIO_BASE);
413#define ESP_GPIO (*(_GPIO_::Type *) GPIO_BASE)
414
415
417// Timer (FRC1, FRC2) definitions //
419
420namespace _FRC_ {
421
422 BEGIN_BITFIELD_TYPE(frctrl_t, uint32_t)
423 ADD_BITFIELD_MEMBER_RW(INT_TYPE, 0, 1)
424 ADD_BITFIELD_MEMBER_RW(DIVIDER, 2, 2)
425 ADD_BITFIELD_MEMBER_RW(RELOAD, 6, 1)
426 ADD_BITFIELD_MEMBER_RW(ENABLE, 7, 1)
427 ADD_BITFIELD_MEMBER_RO(INT_STATUS, 8, 1)
428 END_BITFIELD_TYPE()
429
430 // values for CTRL.INT_TYPE bitfield
431 const uint32_t INT_TYPE_EDGE = 0;
432 const uint32_t INT_TYPE_LEVEL = 1;
433 // values for CTRL.DIVIDER bitfield
434 const uint32_t DIVIDER_1 = 0;
435 const uint32_t DIVIDER_16 = 1;
436 const uint32_t DIVIDER_256 = 2;
437 // values for INT register
438 const uint32_t INT_CLR = 0;
439
440 struct Type1 {
441 __RW uint32_t LOAD; // 23 bit value !
442 __RO uint32_t COUNT; // 23 bit value, default 0x7fffff
443 frctrl_t CTRL;
444 __RW uint32_t INT; // only 1 bit
445 }; // __attribute__((packed));
446
447 struct Type2 : public Type1 {
448 __RW uint32_t ALARM;
449 }; // __attribute__((packed));
450}
451
452//_FRC_::Type1 & ESP_FRC1 = (*(_FRC_::Type1 *) (FRC_BASE + 0x0000));
453//_FRC_::Type2 & ESP_FRC2 = (*(_FRC_::Type2 *) (FRC_BASE + 0x0020));
454
455#define ESP_FRC1 (*(_FRC_::Type1 *) (FRC_BASE + 0x0000))
456#define ESP_FRC2 (*(_FRC_::Type2 *) (FRC_BASE + 0x0020))
457
458namespace _IOMUX_ {
459
460 BEGIN_BITFIELD_TYPE(conf_t, uint32_t)
461 ADD_BITFIELD_MEMBER_RW(SPI0CLK_EQU_SYSCLK, 8, 1)
462 ADD_BITFIELD_MEMBER_RW(SPI1CLK_EQU_SYSCLK, 9, 1)
463 END_BITFIELD_TYPE()
464
465 BEGIN_BITFIELD_TYPE(mux_t, uint32_t)
466 ADD_BITFIELD_MEMBER_RW(OE, 0, 1)
467 ADD_BITFIELD_MEMBER_RW(SLEEP_OE, 1, 1)
468 ADD_BITFIELD_MEMBER_RW(SLEEP_PULLDOWN, 2, 1)
469 ADD_BITFIELD_MEMBER_RW(SLEEP_PULLUP, 3, 1)
470 ADD_BITFIELD_MEMBER_RW(PULLDOWN, 6, 1)
471 ADD_BITFIELD_MEMBER_RW(PULLUP, 7, 1)
472 ADD_BITFIELD_MEMBER_RW(FUNC, 19, 4)
473 END_BITFIELD_TYPE()
474
475 const static uint32_t GPIO_TO_IOMUX[] = { 12,5,13,4,14,15,6,7,8,9,10,11,0,1,2,3 };
476
477 struct Type {
478 conf_t CONF;
479 mux_t ENTRY[16];
480
481 mux_t & operator() (int gpio) {
482 return ENTRY[ GPIO_TO_IOMUX[gpio] ];
483 }
484 };
485}
486
487//_IOMUX_::Type & ESP_IOMUX = (*(_IOMUX_::Type *) IOMUX_BASE);
488
489#define ESP_IOMUX (*(_IOMUX_::Type *) IOMUX_BASE)
490
491#endif /* ESP8266EX_H_ */
BitFieldMember_RO
Definition esp8266_old.h:39
BitFieldMember_RW
Definition esp8266_old.h:67
BitFieldMember_WO
Definition esp8266_old.h:52
_FRC_::Type1
Definition esp8266ex.h:440
_FRC_::Type2
Definition esp8266ex.h:447
_GPIO_::Type
Definition esp8266ex.h:394
_IOMUX_::Type
Definition esp8266ex.h:477
_SPI_::Type
Definition esp8266ex.h:303
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