YAHAL
Yet Another Hardware Abstraction Library
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esp32.h
1/*
2 * esp32.h
3 *
4 * Created on: 21.04.2018
5 * Author: aterstegge
6 */
7
8#ifndef ESP32_H_
9#define ESP32_H_
10
11#include <stdint.h>
12
13#define __RO const volatile
14#define __WO volatile
15#define __RW volatile
16
18// Memory layout
20#define PERI_BASE ((uint32_t)0x3ff00000) // Base of all memory mapped peripherals
21
22#define DPORT_BASE (PERI_BASE + 0x00000000) // Base address of DPort Registers
23#define AES_ACCEL_BASE (PERI_BASE + 0x00001000) // Base address of AES Accelerator
24#define RSA_ACCEL_BASE (PERI_BASE + 0x00002000) // Base address of RSA Accelerator
25#define SHA_ACCEL_BASE (PERI_BASE + 0x00003000) // Base address of SHA Accelerator
26#define SEC_BOOT_BASE (PERI_BASE + 0x00004000) // Base address of Secure Boot
27#define CACHE_MMU_BASE (PERI_BASE + 0x00010000) // Base address of Cache MMU Table
28#define PID_CTRL_BASE (PERI_BASE + 0x0001f000) // Base address of PID Controller
29#define UART0_BASE (PERI_BASE + 0x00040000) // Base address of UART0
30#define SPI1_BASE (PERI_BASE + 0x00042000) // Base address of SPI1
31#define SPI0_BASE (PERI_BASE + 0x00043000) // Base address of SPI0
32#define GPIO_BASE (PERI_BASE + 0x00044000) // Base address of GPIO
33#define RTC_BASE (PERI_BASE + 0x00048000) // Base address of RTC
34#define IO_MUX_BASE (PERI_BASE + 0x00049000) // Base address of IO MUX
35#define SDIO_SLV1_BASE (PERI_BASE + 0x0004b000) // Base address of SDIO Slave 1
36#define UDMA1_BASE (PERI_BASE + 0x0004c000) // Base address of UDMA1
37#define I2S0_BASE (PERI_BASE + 0x0004f000) // Base address of I2S0
38#define UART1_BASE (PERI_BASE + 0x00050000) // Base address of UART1
39#define I2C0_BASE (PERI_BASE + 0x00053000) // Base address of I2C0
40#define UDMA0_BASE (PERI_BASE + 0x00054000) // Base address of UDMA0
41#define SDIO_SLV2_BASE (PERI_BASE + 0x00055000) // Base address of SDIO Slave 2
42#define RMT_BASE (PERI_BASE + 0x00056000) // Base address of RMT
43#define PCNT_BASE (PERI_BASE + 0x00057000) // Base address of PCNT
44#define SDIO_SLV3_BASE (PERI_BASE + 0x00058000) // Base address of SDIO Slave 3
45#define LED_PWM_BASE (PERI_BASE + 0x00059000) // Base address of LED PWM
46#define EFUSE_BASE (PERI_BASE + 0x0005a000) // Base address of Efuse Controller
47#define FLASH_ENC_BASE (PERI_BASE + 0x0005b000) // Base address of Flash Encryption
48#define PWM0_BASE (PERI_BASE + 0x0005e000) // Base address of PWM0
49#define TIMG0_BASE (PERI_BASE + 0x0005f000) // Base address of TIMG0
50#define TIMG1_BASE (PERI_BASE + 0x00060000) // Base address of TIMG1
51#define SPI2_BASE (PERI_BASE + 0x00064000) // Base address of SPI2
52#define SPI3_BASE (PERI_BASE + 0x00065000) // Base address of SPI3
53#define SYSCON_BASE (PERI_BASE + 0x00066000) // Base address of SYSCON
54#define I2C1_BASE (PERI_BASE + 0x00067000) // Base address of I2C1
55#define SDMMC_BASE (PERI_BASE + 0x00068000) // Base address of SDMMC
56#define EMAC_BASE (PERI_BASE + 0x00069000) // Base address of EMAC
57#define PWM1_BASE (PERI_BASE + 0x0006c000) // Base address of PWM1
58#define I2S1_BASE (PERI_BASE + 0x0006d000) // Base address of I2S1
59#define UART2_BASE (PERI_BASE + 0x0006e000) // Base address of UART2
60#define PWM2_BASE (PERI_BASE + 0x0006f000) // Base address of PWM2
61#define PWM3_BASE (PERI_BASE + 0x00070000) // Base address of PWM3
62#define RNG_BASE (PERI_BASE + 0x00075000) // Base address of RNG
63
64
66// Helper templates and macros
68template <typename T, int Offset, int Bits>
69struct BitFieldMember_RO
70{
71 private:
72 T value; // This is the value which is 'mirrored' by the union
73 static const T max = (T(1) << Bits) - T(1);
74
75 public:
76 inline operator T() const {
77 return (value >> Offset) & max;
78 }
79};
80
81template <typename T, int Offset, int Bits>
82struct BitFieldMember_WO
83{
84 private:
85 T value; // This is the value which is 'mirrored' by the union
86 static const T max = (T(1) << Bits) - T(1);
87 static const T mask = max << Offset;
88
89 public:
90 inline BitFieldMember_WO & operator=(T v) {
91 value = (value & ~mask) | ((v & max) << Offset);
92 return *this;
93 }
94};
95
96template <typename T, int Offset, int Bits>
97struct BitFieldMember_RW
98{
99 private:
100 T value; // This is the value which is 'mirrored' by the union
101 static const T max = (T(1) << Bits) - T(1);
102 static const T mask = max << Offset;
103
104 public:
105 inline operator T() const {
106 return (value >> Offset) & max;
107 }
108 inline BitFieldMember_RW & operator=(T v) {
109 value = (value & ~mask) | ((v & max) << Offset);
110 return *this;
111 }
112};
113
114#define BEGIN_BITFIELD_TYPE(typeName, T) \
115 union typeName \
116 { \
117 T value; \
118 typeName& operator=(T v) { value = v; return *this; } \
119 operator T&() { return value; } \
120 operator T() const { return value; } \
121 typedef T StorageType;
122
123#define ADD_BITFIELD_MEMBER_RO(memberName, offset, bits) \
124 BitFieldMember_RO<StorageType, offset, bits> memberName;
125
126#define ADD_BITFIELD_MEMBER_WO(memberName, offset, bits) \
127 BitFieldMember_WO<StorageType, offset, bits> memberName;
128
129#define ADD_BITFIELD_MEMBER_RW(memberName, offset, bits) \
130 BitFieldMember_RW<StorageType, offset, bits> memberName;
131
132#define END_BITFIELD_TYPE() \
133 };
134
136// SPI (SPI0, SPI1) definitions //
138
139namespace _SPI_ {
140
141 BEGIN_BITFIELD_TYPE(cmd_t, uint32_t)
142 ADD_BITFIELD_MEMBER_RW(USR, 18, 1)
143 ADD_BITFIELD_MEMBER_RW(HPM, 19, 1)
144 ADD_BITFIELD_MEMBER_RW(RES, 20, 1)
145 ADD_BITFIELD_MEMBER_RW(DP, 21, 1)
146 ADD_BITFIELD_MEMBER_RW(CE, 22, 1)
147 ADD_BITFIELD_MEMBER_RW(BE, 23, 1)
148 ADD_BITFIELD_MEMBER_RW(SE, 24, 1)
149 ADD_BITFIELD_MEMBER_RW(PP, 25, 1)
150 ADD_BITFIELD_MEMBER_RW(WRSR, 26, 1)
151 ADD_BITFIELD_MEMBER_RW(RDSR, 27, 1)
152 ADD_BITFIELD_MEMBER_RW(RDID, 28, 1)
153 ADD_BITFIELD_MEMBER_RW(WRDI, 29, 1)
154 ADD_BITFIELD_MEMBER_RW(WREN, 30, 1)
155 ADD_BITFIELD_MEMBER_RW(READ, 31, 1)
156 END_BITFIELD_TYPE()
157
158 BEGIN_BITFIELD_TYPE(ctrl_t, uint32_t)
159 ADD_BITFIELD_MEMBER_RW(FASTRD, 13, 1)
160 ADD_BITFIELD_MEMBER_RW(DOUT, 14, 1)
161 ADD_BITFIELD_MEMBER_RW(RESANDRES, 15, 1)
162 ADD_BITFIELD_MEMBER_RW(SSTAAI, 16, 1)
163 ADD_BITFIELD_MEMBER_RW(AHB, 17, 1)
164 ADD_BITFIELD_MEMBER_RW(HOLD, 18, 1)
165 ADD_BITFIELD_MEMBER_RW(SHARE, 19, 1)
166 ADD_BITFIELD_MEMBER_RW(QOUT, 20, 1)
167 ADD_BITFIELD_MEMBER_RW(WPR, 21, 1)
168 ADD_BITFIELD_MEMBER_RW(TWOBSE, 22, 1)
169 ADD_BITFIELD_MEMBER_RW(DIO, 23, 1)
170 ADD_BITFIELD_MEMBER_RW(QIO, 24, 1)
171 ADD_BITFIELD_MEMBER_RW(RD_BO, 25, 1)
172 ADD_BITFIELD_MEMBER_RW(WR_BO, 26, 1)
173 END_BITFIELD_TYPE()
174
175 BEGIN_BITFIELD_TYPE(ctrl1_t, uint32_t)
176 ADD_BITFIELD_MEMBER_RW(BTL, 0,16)
177 ADD_BITFIELD_MEMBER_RW(TRES, 16,12)
178 ADD_BITFIELD_MEMBER_RW(TCSH, 28, 4)
179 END_BITFIELD_TYPE()
180
181 BEGIN_BITFIELD_TYPE(status_t, uint32_t)
182 ADD_BITFIELD_MEMBER_RW(BUSY, 0, 1)
183 ADD_BITFIELD_MEMBER_RW(WRE, 1, 1)
184 ADD_BITFIELD_MEMBER_RW(BP0, 2, 1)
185 ADD_BITFIELD_MEMBER_RW(BP1, 3, 1)
186 ADD_BITFIELD_MEMBER_RW(BP2, 4, 1)
187 ADD_BITFIELD_MEMBER_RW(TBP, 5, 1)
188 ADD_BITFIELD_MEMBER_RW(SP, 7, 1)
189 ADD_BITFIELD_MEMBER_RW(WB, 16, 8)
190 ADD_BITFIELD_MEMBER_RW(EXT, 24, 8)
191 END_BITFIELD_TYPE()
192
193 BEGIN_BITFIELD_TYPE(ctrl2_t, uint32_t)
194 ADD_BITFIELD_MEMBER_RW(ST, 0, 4)
195 ADD_BITFIELD_MEMBER_RW(HT, 4, 4)
196 ADD_BITFIELD_MEMBER_RW(CKOLM, 8, 4)
197 ADD_BITFIELD_MEMBER_RW(CKOHM, 12, 4)
198 ADD_BITFIELD_MEMBER_RW(MISODM, 16, 2)
199 ADD_BITFIELD_MEMBER_RW(MISODN, 18, 3)
200 ADD_BITFIELD_MEMBER_RW(MOSIDM, 21, 2)
201 ADD_BITFIELD_MEMBER_RW(MOSIDN, 23, 3)
202 ADD_BITFIELD_MEMBER_RW(CSDM, 26, 2)
203 ADD_BITFIELD_MEMBER_RW(CSDN, 28, 4)
204 END_BITFIELD_TYPE()
205
206 BEGIN_BITFIELD_TYPE(clock_t, uint32_t)
207 ADD_BITFIELD_MEMBER_RW(CNT_L, 0, 6)
208 ADD_BITFIELD_MEMBER_RW(CNT_H, 6, 6)
209 ADD_BITFIELD_MEMBER_RW(CNT_N, 12, 6)
210 ADD_BITFIELD_MEMBER_RW(DIVPRE, 18,13)
211 ADD_BITFIELD_MEMBER_RW(EQU_SYSCLK, 31, 1)
212 END_BITFIELD_TYPE()
213
214 BEGIN_BITFIELD_TYPE(user_t, uint32_t)
215 ADD_BITFIELD_MEMBER_RW(DUPLEX, 0, 1)
216 ADD_BITFIELD_MEMBER_RW(AHBUCMD4B, 1, 1)
217 ADD_BITFIELD_MEMBER_RW(AHBUCMD, 3, 1)
218 ADD_BITFIELD_MEMBER_RW(CSHOLD, 4, 1)
219 ADD_BITFIELD_MEMBER_RW(CSSETUP, 5, 1)
220 ADD_BITFIELD_MEMBER_RW(SSE, 6, 1)
221 ADD_BITFIELD_MEMBER_RW(SME, 7, 1)
222 ADD_BITFIELD_MEMBER_RW(AHBEM, 8, 2)
223 ADD_BITFIELD_MEMBER_RW(RDBYO, 10, 1)
224 ADD_BITFIELD_MEMBER_RW(WRBYO, 11, 1)
225 ADD_BITFIELD_MEMBER_RW(FWDUAL, 12, 1)
226 ADD_BITFIELD_MEMBER_RW(FWQUAD, 13, 1)
227 ADD_BITFIELD_MEMBER_RW(FWDIO, 14, 1)
228 ADD_BITFIELD_MEMBER_RW(FWQIO, 15, 1)
229 ADD_BITFIELD_MEMBER_RW(SIO, 16, 1)
230 ADD_BITFIELD_MEMBER_RW(HOLDPOL, 17, 1)
231 ADD_BITFIELD_MEMBER_RW(MOSIHOLD, 18, 1)
232 ADD_BITFIELD_MEMBER_RW(MISOHOLD, 19, 1)
233 ADD_BITFIELD_MEMBER_RW(DUMMYHOLD, 20, 1)
234 ADD_BITFIELD_MEMBER_RW(ADDRHOLD, 21, 1)
235 ADD_BITFIELD_MEMBER_RW(CMDHOLD, 22, 1)
236 ADD_BITFIELD_MEMBER_RW(PREPHOLD, 23, 1)
237 ADD_BITFIELD_MEMBER_RW(MISOH, 24, 1)
238 ADD_BITFIELD_MEMBER_RW(MOSIH, 25, 1)
239 ADD_BITFIELD_MEMBER_RW(DUMMYIDLE, 26, 1)
240 ADD_BITFIELD_MEMBER_RW(MOSI, 27, 1)
241 ADD_BITFIELD_MEMBER_RW(MISO, 28, 1)
242 ADD_BITFIELD_MEMBER_RW(DUMMY, 29, 1)
243 ADD_BITFIELD_MEMBER_RW(ADDR, 30, 1)
244 ADD_BITFIELD_MEMBER_RW(COMMAND, 31, 1)
245 END_BITFIELD_TYPE()
246
247 BEGIN_BITFIELD_TYPE(user1_t, uint32_t)
248 ADD_BITFIELD_MEMBER_RW(DUMMY_CYC, 0, 8)
249 ADD_BITFIELD_MEMBER_RW(MISO_LEN, 8, 9)
250 ADD_BITFIELD_MEMBER_RW(MOSI_LEN, 17, 9)
251 ADD_BITFIELD_MEMBER_RW(ADDR_LEN, 26, 6)
252 END_BITFIELD_TYPE()
253
254 BEGIN_BITFIELD_TYPE(user2_t, uint32_t)
255 ADD_BITFIELD_MEMBER_RW(CMD_VAL, 0,16)
256 ADD_BITFIELD_MEMBER_RW(CMD_LEN, 28, 4)
257 END_BITFIELD_TYPE()
258
259 BEGIN_BITFIELD_TYPE(pin_t, uint32_t)
260 ADD_BITFIELD_MEMBER_RW(CS0_DIS, 0, 1)
261 ADD_BITFIELD_MEMBER_RW(CS1_DIS, 1, 1)
262 ADD_BITFIELD_MEMBER_RW(CS2_DIS, 2, 1)
263 END_BITFIELD_TYPE()
264
265 BEGIN_BITFIELD_TYPE(slave_t, uint32_t)
266 ADD_BITFIELD_MEMBER_RW(RD_BUF_DONE, 0, 1)
267 ADD_BITFIELD_MEMBER_RW(WR_BUF_DONE, 1, 1)
268 ADD_BITFIELD_MEMBER_RW(RD_STA_DONE, 2, 1)
269 ADD_BITFIELD_MEMBER_RW(WR_STA_DONE, 3, 1)
270 ADD_BITFIELD_MEMBER_RW(TRANS_DONE, 4, 1)
271 ADD_BITFIELD_MEMBER_RW(RD_BUF_IE, 5, 1)
272 ADD_BITFIELD_MEMBER_RW(WR_BUF_IE, 6, 1)
273 ADD_BITFIELD_MEMBER_RW(RD_STA_IE, 7, 1)
274 ADD_BITFIELD_MEMBER_RW(WR_STA_IE, 8, 1)
275 ADD_BITFIELD_MEMBER_RW(TRANS_IE, 9, 1)
276 ADD_BITFIELD_MEMBER_RW(CS_IM, 10, 2)
277 ADD_BITFIELD_MEMBER_RW(SLV_LST_CMD, 17, 3)
278 ADD_BITFIELD_MEMBER_RW(SLV_LST_ST, 20, 3)
279 ADD_BITFIELD_MEMBER_RO(TRANS_CNT, 23, 4)
280 ADD_BITFIELD_MEMBER_RW(CMD_DEFINE, 27, 1)
281 ADD_BITFIELD_MEMBER_RW(WRRD_STA_EN, 28, 1)
282 ADD_BITFIELD_MEMBER_RW(WRRD_BUF_EN, 29, 1)
283 ADD_BITFIELD_MEMBER_RW(SLV_MODE, 30, 1)
284 ADD_BITFIELD_MEMBER_RW(SYNC_RESET, 31, 1)
285 END_BITFIELD_TYPE()
286
287 BEGIN_BITFIELD_TYPE(slave1_t, uint32_t)
288 ADD_BITFIELD_MEMBER_RW(RDB_DUM_EN, 0, 1)
289 ADD_BITFIELD_MEMBER_RW(WRB_DUM_EN, 1, 1)
290 ADD_BITFIELD_MEMBER_RW(RDS_DUM_EN, 2, 1)
291 ADD_BITFIELD_MEMBER_RW(WRS_DUM_EN, 3, 1)
292 ADD_BITFIELD_MEMBER_RW(WR_ADR_LEN, 4, 6)
293 ADD_BITFIELD_MEMBER_RW(RD_ADR_LEN, 10, 6)
294 ADD_BITFIELD_MEMBER_RW(BUF_LEN, 16, 9)
295 ADD_BITFIELD_MEMBER_RW(SLV_STAT_RD, 25, 9)
296 ADD_BITFIELD_MEMBER_RW(SLV_STAT_FST,26, 9)
297 ADD_BITFIELD_MEMBER_RW(STATUS_LEN, 27, 5)
298 END_BITFIELD_TYPE()
299
300 BEGIN_BITFIELD_TYPE(slave2_t, uint32_t)
301 ADD_BITFIELD_MEMBER_RW(RDSTA_D_LEN, 0, 8)
302 ADD_BITFIELD_MEMBER_RW(WRSTA_D_LEN, 8, 8)
303 ADD_BITFIELD_MEMBER_RW(RDBUF_D_LEN, 18, 8)
304 ADD_BITFIELD_MEMBER_RW(WRBUF_D_LEN, 24, 8)
305 END_BITFIELD_TYPE()
306
307 BEGIN_BITFIELD_TYPE(slave3_t, uint32_t)
308 ADD_BITFIELD_MEMBER_RW(RDBUF_C_VAL, 0, 8)
309 ADD_BITFIELD_MEMBER_RW(WRBUF_C_VAL, 8, 8)
310 ADD_BITFIELD_MEMBER_RW(RDSTA_C_VAL, 18, 8)
311 ADD_BITFIELD_MEMBER_RW(WRSTA_C_VAL, 24, 8)
312 END_BITFIELD_TYPE()
313
314 BEGIN_BITFIELD_TYPE(ext0_t, uint32_t)
315 ADD_BITFIELD_MEMBER_RW(T_PP_TIME, 0,12)
316 ADD_BITFIELD_MEMBER_RW(T_PP_SHIFT, 16, 4)
317 ADD_BITFIELD_MEMBER_RW(T_PP_ENA, 31, 1)
318 END_BITFIELD_TYPE()
319
320 BEGIN_BITFIELD_TYPE(ext1_t, uint32_t)
321 ADD_BITFIELD_MEMBER_RW(T_ERA_TIME, 0,12)
322 ADD_BITFIELD_MEMBER_RW(T_ERA_SHIFT, 16, 4)
323 ADD_BITFIELD_MEMBER_RW(T_ERA_ENA, 31, 1)
324 END_BITFIELD_TYPE()
325
326 BEGIN_BITFIELD_TYPE(ext2_t, uint32_t)
327 ADD_BITFIELD_MEMBER_RW(SPI_ST, 0, 3)
328 END_BITFIELD_TYPE()
329
330 BEGIN_BITFIELD_TYPE(ext3_t, uint32_t)
331 ADD_BITFIELD_MEMBER_RW(INT_HOLD_ENA, 0, 2)
332 END_BITFIELD_TYPE()
333
334 struct Type {
335 cmd_t CMD;
336 __RW uint32_t ADDR;
337 ctrl_t CTRL;
338 ctrl1_t CTRL1;
339 status_t RD_STATUS;
340 ctrl2_t CTRL2;
341 clock_t CLOCK;
342 user_t USER;
343 user1_t USER1;
344 user2_t USER2;
345 __RW uint32_t WR_STATUS;
346 pin_t PIN;
347 slave_t SLAVE;
348 slave1_t SLAVE1;
349 slave2_t SLAVE2;
350 slave3_t SLAVE3;
351 __RW uint32_t W[16];
352 __RO uint32_t dummy[28];
353 ext0_t E0;
354 ext1_t E1;
355 ext2_t E2;
356 ext3_t E3;
357 };
358}
359
360//_SPI_::Type & ESP_SPI0 = (*(_SPI_::Type *) SPI0_BASE);
361//_SPI_::Type & ESP_SPI1 = (*(_SPI_::Type *) SPI1_BASE);
362
363#define SPI0 (*(ESP_SPI::Type *) SPI0_BASE)
364#define SPI1 (*(ESP_SPI::Type *) SPI1_BASE)
365
367// GPIO definitions //
369
370namespace _GPIO_ {
371
372 BEGIN_BITFIELD_TYPE(out_t, uint32_t)
373 ADD_BITFIELD_MEMBER_RW(DATA, 0, 16)
374 ADD_BITFIELD_MEMBER_RW(BT_SEL, 16, 16)
375 END_BITFIELD_TYPE()
376
377 BEGIN_BITFIELD_TYPE(enable_t, uint32_t)
378 ADD_BITFIELD_MEMBER_RW(DATA, 0, 16)
379 ADD_BITFIELD_MEMBER_RW(SDIO_SEL,16, 6)
380 END_BITFIELD_TYPE()
381
382 BEGIN_BITFIELD_TYPE(in_t, uint32_t)
383 ADD_BITFIELD_MEMBER_RO(DATA, 0, 16)
384 ADD_BITFIELD_MEMBER_RO(STRAPPING, 16, 16)
385 END_BITFIELD_TYPE()
386
387 BEGIN_BITFIELD_TYPE(pin_t, uint32_t)
388 ADD_BITFIELD_MEMBER_RW(SOURCE, 0, 1)
389 ADD_BITFIELD_MEMBER_RW(DRIVER, 2, 1)
390 ADD_BITFIELD_MEMBER_RW(INT_TYPE, 7, 3)
391 ADD_BITFIELD_MEMBER_RW(WAKEUP_ENABLE, 10, 1)
392 END_BITFIELD_TYPE()
393
394 // values for SOURCE
395 const uint32_t SOURCE_GPIO = 0;
396 const uint32_t SOURCE_SIGMA_DELTA = 1;
397 // values for DRIVER
398 const uint32_t DRIVER_PUSH_PULL = 0;
399 const uint32_t DRIVER_OPEN_DRAIN = 1;
400 // values for INT_TYPE
401 const uint32_t INT_DISABLE = 0;
402 const uint32_t INT_RAISING_EDGE = 1;
403 const uint32_t INT_FALLING_EDGE = 2;
404 const uint32_t INT_BOTH_EDGES = 3;
405 const uint32_t INT_LEVEL_LOW = 4;
406 const uint32_t INT_LEVEL_HIGH = 5;
407
408 BEGIN_BITFIELD_TYPE(sigmadelta_t, uint32_t)
409 ADD_BITFIELD_MEMBER_RW(TARGET, 0, 8)
410 ADD_BITFIELD_MEMBER_RW(PRESCALE, 8, 8)
411 ADD_BITFIELD_MEMBER_RW(ENABLE, 16, 1)
412 END_BITFIELD_TYPE()
413
414 BEGIN_BITFIELD_TYPE(rtc_sync_t, uint32_t)
415 ADD_BITFIELD_MEMBER_RW(PERIOD_NUM, 0, 10)
416 ADD_BITFIELD_MEMBER_RW(CALIB_START, 31, 1)
417 END_BITFIELD_TYPE()
418
419 BEGIN_BITFIELD_TYPE(rtc_value_t, uint32_t)
420 ADD_BITFIELD_MEMBER_RW(CALIB_VALUE, 0, 20)
421 ADD_BITFIELD_MEMBER_RW(CALIB_RDY_REAL, 30, 1)
422 ADD_BITFIELD_MEMBER_RW(CALIB_RDY, 31, 1)
423 END_BITFIELD_TYPE()
424
425 struct Type {
426 out_t OUT;
427 __WO uint32_t OUT_DATA_W1TS;
428 __WO uint32_t OUT_DATA_W1TC;
429 enable_t ENABLE;
430 __WO uint32_t ENABLE_W1TS;
431 __WO uint32_t ENABLE_W1TC;
432 in_t IN;
433 __RW uint32_t STATUS;
434 __WO uint32_t STATUS_W1TS;
435 __WO uint32_t STATUS_W1TC;
436 pin_t PIN[16];
437 sigmadelta_t SIGMA_DELTA;
438 rtc_sync_t RTC_CALIB_SYNC;
439 rtc_value_t RTC_CALIB_VALUE;
440 };
441}
442
443//_GPIO_::Type & ESP_GPIO = (*(_GPIO_::Type *) GPIO_BASE);
444#define ESP_GPIO (*(_GPIO_::Type *) GPIO_BASE)
445
446
448// Timer (FRC1, FRC2) definitions //
450
451namespace _FRC_ {
452
453 BEGIN_BITFIELD_TYPE(frctrl_t, uint32_t)
454 ADD_BITFIELD_MEMBER_RW(INT_TYPE, 0, 1)
455 ADD_BITFIELD_MEMBER_RW(DIVIDER, 2, 2)
456 ADD_BITFIELD_MEMBER_RW(RELOAD, 6, 1)
457 ADD_BITFIELD_MEMBER_RW(ENABLE, 7, 1)
458 ADD_BITFIELD_MEMBER_RO(INT_STATUS, 8, 1)
459 END_BITFIELD_TYPE()
460
461 // values for CTRL.INT_TYPE bitfield
462 const uint32_t INT_TYPE_EDGE = 0;
463 const uint32_t INT_TYPE_LEVEL = 1;
464 // values for CTRL.DIVIDER bitfield
465 const uint32_t DIVIDER_1 = 0;
466 const uint32_t DIVIDER_16 = 1;
467 const uint32_t DIVIDER_256 = 2;
468 // values for INT register
469 const uint32_t INT_CLR = 0;
470
471 struct Type1 {
472 __RW uint32_t LOAD; // 23 bit value !
473 __RO uint32_t COUNT; // 23 bit value, default 0x7fffff
474 frctrl_t CTRL;
475 __RW uint32_t INT; // only 1 bit
476 }; // __attribute__((packed));
477
478 struct Type2 : public Type1 {
479 __RW uint32_t ALARM;
480 }; // __attribute__((packed));
481}
482
483//_FRC_::Type1 & ESP_FRC1 = (*(_FRC_::Type1 *) (FRC_BASE + 0x0000));
484//_FRC_::Type2 & ESP_FRC2 = (*(_FRC_::Type2 *) (FRC_BASE + 0x0020));
485
486#define ESP_FRC1 (*(_FRC_::Type1 *) (FRC_BASE + 0x0000))
487#define ESP_FRC2 (*(_FRC_::Type2 *) (FRC_BASE + 0x0020))
488
489namespace _IOMUX_ {
490
491 BEGIN_BITFIELD_TYPE(conf_t, uint32_t)
492 ADD_BITFIELD_MEMBER_RW(SPI0CLK_EQU_SYSCLK, 8, 1)
493 ADD_BITFIELD_MEMBER_RW(SPI1CLK_EQU_SYSCLK, 9, 1)
494 END_BITFIELD_TYPE()
495
496 BEGIN_BITFIELD_TYPE(mux_t, uint32_t)
497 ADD_BITFIELD_MEMBER_RW(OE, 0, 1)
498 ADD_BITFIELD_MEMBER_RW(SLEEP_OE, 1, 1)
499 ADD_BITFIELD_MEMBER_RW(SLEEP_PULLDOWN, 2, 1)
500 ADD_BITFIELD_MEMBER_RW(SLEEP_PULLUP, 3, 1)
501 ADD_BITFIELD_MEMBER_RW(PULLDOWN, 6, 1)
502 ADD_BITFIELD_MEMBER_RW(PULLUP, 7, 1)
503 ADD_BITFIELD_MEMBER_RW(FUNC, 19, 4)
504 END_BITFIELD_TYPE()
505
506 const static uint32_t GPIO_TO_IOMUX[] = { 12,5,13,4,14,15,6,7,8,9,10,11,0,1,2,3 };
507
508 struct Type {
509 conf_t CONF;
510 mux_t ENTRY[16];
511
512 mux_t & operator() (int gpio) {
513 return ENTRY[ GPIO_TO_IOMUX[gpio] ];
514 }
515 };
516}
517
518//_IOMUX_::Type & ESP_IOMUX = (*(_IOMUX_::Type *) IOMUX_BASE);
519
520#define ESP_IOMUX (*(_IOMUX_::Type *) IOMUX_BASE)
521
522#endif /* ESP8266EX_H_ */
BitFieldMember_RO
Definition esp8266_old.h:39
BitFieldMember_RW
Definition esp8266_old.h:67
BitFieldMember_WO
Definition esp8266_old.h:52
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