YAHAL
Yet Another Hardware Abstraction Library
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RP2040.h
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1/*************************************************************************/
8/*
9 * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
10 * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
11 *
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the License); you may
15 * not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 * www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 * SPDX-License-Identifier: BSD-3-Clause
27 */
28
29#ifndef _CMSIS_RP2040_H_
30#define _CMSIS_RP2040_H_
31
32// ==========================================================================
33// ===================== Interrupt Number Definition ======================
34// ==========================================================================
35typedef enum
36{
37 // ============ ARM Cortex-M0+ Specific Interrupt Numbers =============
38 Reset_IRQn = -15, // -15 Reset Vector
39 NonMaskableInt_IRQn = -14, // -14 Non-maskable Interrupt
40 HardFault_IRQn = -13, // -13 Hard Fault, all classes
41 SVCall_IRQn = -5, // -5 System Service Call (SVC)
42 PendSV_IRQn = -2, // -2 Pendable system service
43 SysTick_IRQn = -1, // -1 System Tick Timer
44 // ================ RP2040 Specific Interrupt Numbers =================
45 TIMER_IRQ_0_IRQn = 0, // 0 TIMER_IRQ_0
46 TIMER_IRQ_1_IRQn = 1, // 1 TIMER_IRQ_1
47 TIMER_IRQ_2_IRQn = 2, // 2 TIMER_IRQ_2
48 TIMER_IRQ_3_IRQn = 3, // 3 TIMER_IRQ_3
49 PWM_IRQ_WRAP_IRQn = 4, // 4 PWM_IRQ_WRAP
50 USBCTRL_IRQ_IRQn = 5, // 5 USBCTRL_IRQ
51 XIP_IRQ_IRQn = 6, // 6 XIP_IRQ
52 PIO0_IRQ_0_IRQn = 7, // 7 PIO0_IRQ_0
53 PIO0_IRQ_1_IRQn = 8, // 8 PIO0_IRQ_1
54 PIO1_IRQ_0_IRQn = 9, // 9 PIO1_IRQ_0
55 PIO1_IRQ_1_IRQn = 10, // 10 PIO1_IRQ_1
56 DMA_IRQ_0_IRQn = 11, // 11 DMA_IRQ_0
57 DMA_IRQ_1_IRQn = 12, // 12 DMA_IRQ_1
58 IO_IRQ_BANK0_IRQn = 13, // 13 IO_IRQ_BANK0
59 IO_IRQ_QSPI_IRQn = 14, // 14 IO_IRQ_QSPI
60 SIO_IRQ_PROC0_IRQn = 15, // 15 SIO_IRQ_PROC0
61 SIO_IRQ_PROC1_IRQn = 16, // 16 SIO_IRQ_PROC1
62 CLOCKS_IRQ_IRQn = 17, // 17 CLOCKS_IRQ
63 SPI0_IRQ_IRQn = 18, // 18 SPI0_IRQ
64 SPI1_IRQ_IRQn = 19, // 19 SPI1_IRQ
65 UART0_IRQ_IRQn = 20, // 20 UART0_IRQ
66 UART1_IRQ_IRQn = 21, // 21 UART1_IRQ
67 ADC_IRQ_FIFO_IRQn = 22, // 22 ADC_IRQ_FIFO
68 I2C0_IRQ_IRQn = 23, // 23 I2C0_IRQ
69 I2C1_IRQ_IRQn = 24, // 24 I2C1_IRQ
70 RTC_IRQ_IRQn = 25 // 25 RTC_IRQ
71} IRQn_Type;
72
73// ==========================================================================
74// ================ Processor and Core Peripheral Section =================
75// ==========================================================================
76
77//=== Configuration of the ARM Cortex-M0+ Processor and Core Peripherals ==
78#define __CM0PLUS_REV 0x0001U // CM0PLUS Core Revision
79#define __NVIC_PRIO_BITS 2 // Bits used for NVIC priorities
80#define __Vendor_SysTickConfig 0 // Nonstandard SysTick config
81#define __VTOR_PRESENT 1 // CPU supports VTOR Register
82#define __MPU_PRESENT 1 // MPU present
83
84#include "core_cm0plus.h" // ARM Cortex-M0+ processor and core peripherals
85
86// ==========================================================================
87// ======================= MCU Peripheral Section ==========================
88// ==========================================================================
89
90#include "RP2040_regs.h" // RP2040 peripherals and registers
91
92#endif // _CMSIS_RP2040_H
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