YAHAL
Yet Another Hardware Abstraction Library
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ESP8266.h
1
2// This file was generated with svd2cpp, source file was ESP8266.svd
3// DO NOT EDIT - CHANGES MIGHT BE OVERWRITTEN !!
5//
6#include "bitfield_defs.h"
7
8// name: esp8266
9// version: 1.0
10// addressUnitBits: 8
11// width: 32
12// cpu
13// name: Xtensa LX106
14// revision: 1
15// endian: little
16// mpuPresent: false
17// fpuPresent: true
18// nvicPrioBits: 3
19// vendorSystickConfig: false
20
21namespace _DPORT_ {
22
23 // EDGE_INT_ENABLE
24 // Reset value: 0x00000000
25 BEGIN_TYPE(EDGE_INT_ENABLE_t, uint32_t)
26 ADD_BITFIELD_RW(Register, 0, 32)
27 END_TYPE()
28
29 // DPORT_CTL
30 // Reset value: 0x00000000
31 BEGIN_TYPE(DPORT_CTL_t, uint32_t)
32 ADD_BITFIELD_RW(DPORT_CTL_DOUBLE_CLK, 0, 1)
33 END_TYPE()
34
35 struct DPORT_t {
36 uint32_t reserved0;
37 EDGE_INT_ENABLE_t EDGE_INT_ENABLE;
38 uint32_t reserved1[3];
39 DPORT_CTL_t DPORT_CTL;
40 };
41
42 static DPORT_t & DPORT = (*(DPORT_t *)0x3ff00000);
43
44} // _DPORT_
45
46namespace _EFUSE_ {
47
48 // EFUSE_DATA0
49 // Reset value: 0x00000000
50 BEGIN_TYPE(EFUSE_DATA0_t, uint32_t)
51 ADD_BITFIELD_RW(Register, 0, 32)
52 END_TYPE()
53
54 // EFUSE_DATA1
55 // Reset value: 0x00000000
56 BEGIN_TYPE(EFUSE_DATA1_t, uint32_t)
57 ADD_BITFIELD_RW(Register, 0, 32)
58 END_TYPE()
59
60 // EFUSE_DATA2
61 // Reset value: 0x00000000
62 BEGIN_TYPE(EFUSE_DATA2_t, uint32_t)
63 ADD_BITFIELD_RW(Register, 0, 32)
64 END_TYPE()
65
66 // EFUSE_DATA3
67 // Reset value: 0x00000000
68 BEGIN_TYPE(EFUSE_DATA3_t, uint32_t)
69 ADD_BITFIELD_RW(Register, 0, 32)
70 END_TYPE()
71
72 struct EFUSE_t {
73 EFUSE_DATA0_t EFUSE_DATA0;
74 EFUSE_DATA1_t EFUSE_DATA1;
75 EFUSE_DATA2_t EFUSE_DATA2;
76 EFUSE_DATA3_t EFUSE_DATA3;
77 };
78
79 static EFUSE_t & EFUSE = (*(EFUSE_t *)0x3ff00050);
80
81} // _EFUSE_
82
83namespace _GPIO_ {
84
85 // BT-Coexist Selection register
86 // Reset value: 0x00000000
87 BEGIN_TYPE(OUT_t, uint32_t)
88 // BT-Coexist Selection register
89 ADD_BITFIELD_RW(BT_SEL, 16, 16)
90 // The output value when the GPIO pin is set as output.
91 ADD_BITFIELD_RW(DATA, 0, 16)
92 END_TYPE()
93
94 // GPIO_OUT_W1TS
95 // Reset value: 0x00000000
96 BEGIN_TYPE(OUT_W1TS_t, uint32_t)
97 // Writing 1 into a bit in this register
98 // will set the related bit in GPIO_OUT_DATA
99 ADD_BITFIELD_WO(GPIO_OUT_DATA_W1TS, 0, 16)
100 END_TYPE()
101
102 // GPIO_OUT_W1TC
103 // Reset value: 0x00000000
104 BEGIN_TYPE(OUT_W1TC_t, uint32_t)
105 // Writing 1 into a bit in this register
106 // will clear the related bit in GPIO_OUT_DATA
107 ADD_BITFIELD_WO(GPIO_OUT_DATA_W1TC, 0, 16)
108 END_TYPE()
109
110 // GPIO_ENABLE
111 // Reset value: 0x00000000
112 BEGIN_TYPE(ENABLE_t, uint32_t)
113 // SDIO-dis selection register
114 ADD_BITFIELD_RW(SDIO_SEL, 16, 6)
115 // The output enable register.
116 ADD_BITFIELD_RW(DATA, 0, 16)
117 END_TYPE()
118
119 // GPIO_ENABLE_W1TS
120 // Reset value: 0x00000000
121 BEGIN_TYPE(ENABLE_W1TS_t, uint32_t)
122 // Writing 1 into a bit in this register
123 // will set the related bit in GPIO_ENABLE_DATA
124 ADD_BITFIELD_WO(GPIO_ENABLE_DATA_W1TS, 0, 16)
125 END_TYPE()
126
127 // GPIO_ENABLE_W1TC
128 // Reset value: 0x00000000
129 BEGIN_TYPE(ENABLE_W1TC_t, uint32_t)
130 // Writing 1 into a bit in this register
131 // will clear the related bit in GPIO_ENABLE_DATA
132 ADD_BITFIELD_WO(GPIO_ENABLE_DATA_W1TC, 0, 16)
133 END_TYPE()
134
135 // The values of the strapping pins.
136 // Reset value: 0x00000000
137 BEGIN_TYPE(IN_t, uint32_t)
138 // The values of the strapping pins.
139 ADD_BITFIELD_RW(STRAPPING, 16, 16)
140 // The values of the GPIO pins when the GPIO pin is set as input.
141 ADD_BITFIELD_RW(DATA, 0, 16)
142 END_TYPE()
143
144 // GPIO_STATUS
145 // Reset value: 0x00000000
146 BEGIN_TYPE(STATUS_t, uint32_t)
147 // Interrupt enable register.
148 ADD_BITFIELD_RW(GPIO_STATUS_INTERRUPT, 0, 16)
149 END_TYPE()
150
151 // GPIO_STATUS_W1TS
152 // Reset value: 0x00000000
153 BEGIN_TYPE(STATUS_W1TS_t, uint32_t)
154 // Writing 1 into a bit in this register will
155 // set the related bit in GPIO_STATUS_INTERRUPT
156 ADD_BITFIELD_WO(GPIO_STATUS_INTERRUPT_W1TS, 0, 16)
157 END_TYPE()
158
159 // GPIO_STATUS_W1TC
160 // Reset value: 0x00000000
161 BEGIN_TYPE(STATUS_W1TC_t, uint32_t)
162 // Writing 1 into a bit in this register will
163 // clear the related bit in GPIO_STATUS_INTERRUPT
164 ADD_BITFIELD_WO(GPIO_STATUS_INTERRUPT_W1TC, 0, 16)
165 END_TYPE()
166
167 // GPIO_PIN register
168 // Reset value: 0x00000000
169 BEGIN_TYPE(PIN_t, uint32_t)
170 // 1: sigma-delta; 0: GPIO_DATA
171 ADD_BITFIELD_RW(SOURCE, 0, 1)
172 // 1: open drain; 0: normal
173 ADD_BITFIELD_RW(DRIVER, 2, 1)
174 // Interrupt type
175 ADD_BITFIELD_RW(INT_TYPE, 7, 3)
176 // 0: disable; 1: enable GPIO wakeup CPU,
177 // only when GPIO INT_TYPE is 0x4 or 0x5
178 ADD_BITFIELD_RW(WAKEUP_ENABLE, 10, 1)
179 END_TYPE()
180
181 static const uint32_t PIN_SOURCE__GPIO = 0;
182 static const uint32_t PIN_SOURCE__SIGMA_DELTA = 1;
183 static const uint32_t PIN_DRIVER__PUSH_PULL = 0;
184 static const uint32_t PIN_DRIVER__OPEN_DRAIN = 1;
185 static const uint32_t PIN_INT_TYPE__DISABLE = 0;
186 static const uint32_t PIN_INT_TYPE__RAISING_EDGE = 1;
187 static const uint32_t PIN_INT_TYPE__FALLING_EDGE = 2;
188 static const uint32_t PIN_INT_TYPE__BOTH_EDGES = 3;
189 static const uint32_t PIN_INT_TYPE__LEVEL_LOW = 4;
190 static const uint32_t PIN_INT_TYPE__LEVEL_HIGH = 5;
191
192 // GPIO_SIGMA_DELTA
193 // Reset value: 0x00000000
194 BEGIN_TYPE(SIGMA_DELTA_t, uint32_t)
195 // 1: enable sigma-delta; 0: disable
196 ADD_BITFIELD_RW(ENABLE, 16, 1)
197 // Clock pre-divider for sigma-delta.
198 ADD_BITFIELD_RW(PRESCALE, 8, 8)
199 // target level of the sigma-delta. It is a signed byte.
200 ADD_BITFIELD_RW(TARGET, 0, 8)
201 END_TYPE()
202
203 // Positvie edge of this bit will trigger the RTC-clock-calibration process.
204 // Reset value: 0x00000000
205 BEGIN_TYPE(RTC_CALIB_SYNC_t, uint32_t)
206 // Positvie edge of this bit will trigger the RTC-clock-calibration process.
207 ADD_BITFIELD_RW(RTC_CALIB_START, 31, 1)
208 // The cycle number of RTC-clock during RTC-clock-calibration
209 ADD_BITFIELD_RW(RTC_PERIOD_NUM, 0, 10)
210 END_TYPE()
211
212 // 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done
213 // Reset value: 0x00000000
214 BEGIN_TYPE(RTC_CALIB_VALUE_t, uint32_t)
215 // 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done
216 ADD_BITFIELD_RW(RTC_CALIB_RDY, 31, 1)
217 // 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done
218 ADD_BITFIELD_RW(RTC_CALIB_RDY_REAL, 30, 1)
219 // The cycle number of clk_xtal (crystal clock)
220 // for the RTC_PERIOD_NUM cycles of RTC-clock
221 ADD_BITFIELD_RW(RTC_CALIB_VALUE, 0, 20)
222 END_TYPE()
223
224 struct GPIO_t {
225 OUT_t OUT;
226 OUT_W1TS_t OUT_W1TS;
227 OUT_W1TC_t OUT_W1TC;
228 ENABLE_t ENABLE;
229 ENABLE_W1TS_t ENABLE_W1TS;
230 ENABLE_W1TC_t ENABLE_W1TC;
231 IN_t IN;
232 STATUS_t STATUS;
233 STATUS_W1TS_t STATUS_W1TS;
234 STATUS_W1TC_t STATUS_W1TC;
235 PIN_t PIN[16];
236 SIGMA_DELTA_t SIGMA_DELTA;
237 RTC_CALIB_SYNC_t RTC_CALIB_SYNC;
238 RTC_CALIB_VALUE_t RTC_CALIB_VALUE;
239 };
240
241 static GPIO_t & GPIO = (*(GPIO_t *)0x60000300);
242
243} // _GPIO_
244
245namespace _I2S_ {
246
247 // I2STXFIFO
248 // Reset value: 0x00000000
249 BEGIN_TYPE(I2STXFIFO_t, uint32_t)
250 ADD_BITFIELD_RW(Register, 0, 32)
251 END_TYPE()
252
253 // I2SRXFIFO
254 // Reset value: 0x00000000
255 BEGIN_TYPE(I2SRXFIFO_t, uint32_t)
256 ADD_BITFIELD_RW(Register, 0, 32)
257 END_TYPE()
258
259 // I2SCONF
260 // Reset value: 0x00000000
261 BEGIN_TYPE(I2SCONF_t, uint32_t)
262 ADD_BITFIELD_RW(I2S_BCK_DIV_NUM, 22, 6)
263 ADD_BITFIELD_RW(I2S_CLKM_DIV_NUM, 16, 6)
264 ADD_BITFIELD_RW(I2S_BITS_MOD, 12, 4)
265 ADD_BITFIELD_RW(I2S_RECE_MSB_SHIFT, 11, 1)
266 ADD_BITFIELD_RW(I2S_TRANS_MSB_SHIFT, 10, 1)
267 ADD_BITFIELD_RW(I2S_I2S_RX_START, 9, 1)
268 ADD_BITFIELD_RW(I2S_I2S_TX_START, 8, 1)
269 ADD_BITFIELD_RW(I2S_MSB_RIGHT, 7, 1)
270 ADD_BITFIELD_RW(I2S_RIGHT_FIRST, 6, 1)
271 ADD_BITFIELD_RW(I2S_RECE_SLAVE_MOD, 5, 1)
272 ADD_BITFIELD_RW(I2S_TRANS_SLAVE_MOD, 4, 1)
273 ADD_BITFIELD_RW(I2S_I2S_RX_FIFO_RESET, 3, 1)
274 ADD_BITFIELD_RW(I2S_I2S_TX_FIFO_RESET, 2, 1)
275 ADD_BITFIELD_RW(I2S_I2S_RX_RESET, 1, 1)
276 ADD_BITFIELD_RW(I2S_I2S_TX_RESET, 0, 1)
277 END_TYPE()
278
279 // I2SINT_RAW
280 // Reset value: 0x00000000
281 BEGIN_TYPE(I2SINT_RAW_t, uint32_t)
282 ADD_BITFIELD_RW(I2S_I2S_TX_REMPTY_INT_RAW, 5, 1)
283 ADD_BITFIELD_RW(I2S_I2S_TX_WFULL_INT_RAW, 4, 1)
284 ADD_BITFIELD_RW(I2S_I2S_RX_REMPTY_INT_RAW, 3, 1)
285 ADD_BITFIELD_RW(I2S_I2S_RX_WFULL_INT_RAW, 2, 1)
286 ADD_BITFIELD_RW(I2S_I2S_TX_PUT_DATA_INT_RAW, 1, 1)
287 ADD_BITFIELD_RW(I2S_I2S_RX_TAKE_DATA_INT_RAW, 0, 1)
288 END_TYPE()
289
290 // I2SINT_ST
291 // Reset value: 0x00000000
292 BEGIN_TYPE(I2SINT_ST_t, uint32_t)
293 ADD_BITFIELD_RW(I2S_I2S_TX_REMPTY_INT_ST, 5, 1)
294 ADD_BITFIELD_RW(I2S_I2S_TX_WFULL_INT_ST, 4, 1)
295 ADD_BITFIELD_RW(I2S_I2S_RX_REMPTY_INT_ST, 3, 1)
296 ADD_BITFIELD_RW(I2S_I2S_RX_WFULL_INT_ST, 2, 1)
297 ADD_BITFIELD_RW(I2S_I2S_TX_PUT_DATA_INT_ST, 1, 1)
298 ADD_BITFIELD_RW(I2S_I2S_RX_TAKE_DATA_INT_ST, 0, 1)
299 END_TYPE()
300
301 // I2SINT_ENA
302 // Reset value: 0x00000000
303 BEGIN_TYPE(I2SINT_ENA_t, uint32_t)
304 ADD_BITFIELD_RW(I2S_I2S_TX_REMPTY_INT_ENA, 5, 1)
305 ADD_BITFIELD_RW(I2S_I2S_TX_WFULL_INT_ENA, 4, 1)
306 ADD_BITFIELD_RW(I2S_I2S_RX_REMPTY_INT_ENA, 3, 1)
307 ADD_BITFIELD_RW(I2S_I2S_RX_WFULL_INT_ENA, 2, 1)
308 ADD_BITFIELD_RW(I2S_I2S_TX_PUT_DATA_INT_ENA, 1, 1)
309 ADD_BITFIELD_RW(I2S_I2S_RX_TAKE_DATA_INT_ENA, 0, 1)
310 END_TYPE()
311
312 // I2SINT_CLR
313 // Reset value: 0x00000000
314 BEGIN_TYPE(I2SINT_CLR_t, uint32_t)
315 ADD_BITFIELD_RW(I2S_I2S_TX_REMPTY_INT_CLR, 5, 1)
316 ADD_BITFIELD_RW(I2S_I2S_TX_WFULL_INT_CLR, 4, 1)
317 ADD_BITFIELD_RW(I2S_I2S_RX_REMPTY_INT_CLR, 3, 1)
318 ADD_BITFIELD_RW(I2S_I2S_RX_WFULL_INT_CLR, 2, 1)
319 ADD_BITFIELD_RW(I2S_I2S_PUT_DATA_INT_CLR, 1, 1)
320 ADD_BITFIELD_RW(I2S_I2S_TAKE_DATA_INT_CLR, 0, 1)
321 END_TYPE()
322
323 // I2STIMING
324 // Reset value: 0x00000000
325 BEGIN_TYPE(I2STIMING_t, uint32_t)
326 ADD_BITFIELD_RW(I2S_TRANS_BCK_IN_INV, 22, 1)
327 ADD_BITFIELD_RW(I2S_RECE_DSYNC_SW, 21, 1)
328 ADD_BITFIELD_RW(I2S_TRANS_DSYNC_SW, 20, 1)
329 ADD_BITFIELD_RW(I2S_RECE_BCK_OUT_DELAY, 18, 2)
330 ADD_BITFIELD_RW(I2S_RECE_WS_OUT_DELAY, 16, 2)
331 ADD_BITFIELD_RW(I2S_TRANS_SD_OUT_DELAY, 14, 2)
332 ADD_BITFIELD_RW(I2S_TRANS_WS_OUT_DELAY, 12, 2)
333 ADD_BITFIELD_RW(I2S_TRANS_BCK_OUT_DELAY, 10, 2)
334 ADD_BITFIELD_RW(I2S_RECE_SD_IN_DELAY, 8, 2)
335 ADD_BITFIELD_RW(I2S_RECE_WS_IN_DELAY, 6, 2)
336 ADD_BITFIELD_RW(I2S_RECE_BCK_IN_DELAY, 4, 2)
337 ADD_BITFIELD_RW(I2S_TRANS_WS_IN_DELAY, 2, 2)
338 ADD_BITFIELD_RW(I2S_TRANS_BCK_IN_DELAY, 0, 2)
339 END_TYPE()
340
341 // I2S_FIFO_CONF
342 // Reset value: 0x00000000
343 BEGIN_TYPE(I2S_FIFO_CONF_t, uint32_t)
344 ADD_BITFIELD_RW(I2S_I2S_RX_FIFO_MOD, 16, 3)
345 ADD_BITFIELD_RW(I2S_I2S_TX_FIFO_MOD, 13, 3)
346 ADD_BITFIELD_RW(I2S_I2S_DSCR_EN, 12, 1)
347 ADD_BITFIELD_RW(I2S_I2S_TX_DATA_NUM, 6, 6)
348 ADD_BITFIELD_RW(I2S_I2S_RX_DATA_NUM, 0, 6)
349 END_TYPE()
350
351 // I2SRXEOF_NUM
352 // Reset value: 0x00000000
353 BEGIN_TYPE(I2SRXEOF_NUM_t, uint32_t)
354 ADD_BITFIELD_RW(I2S_I2S_RX_EOF_NUM, 0, 32)
355 END_TYPE()
356
357 // I2SCONF_SIGLE_DATA
358 // Reset value: 0x00000000
359 BEGIN_TYPE(I2SCONF_SIGLE_DATA_t, uint32_t)
360 ADD_BITFIELD_RW(I2S_I2S_SIGLE_DATA, 0, 32)
361 END_TYPE()
362
363 struct I2S_t {
364 I2STXFIFO_t I2STXFIFO;
365 I2SRXFIFO_t I2SRXFIFO;
366 I2SCONF_t I2SCONF;
367 I2SINT_RAW_t I2SINT_RAW;
368 I2SINT_ST_t I2SINT_ST;
369 I2SINT_ENA_t I2SINT_ENA;
370 I2SINT_CLR_t I2SINT_CLR;
371 I2STIMING_t I2STIMING;
372 I2S_FIFO_CONF_t I2S_FIFO_CONF;
373 I2SRXEOF_NUM_t I2SRXEOF_NUM;
374 I2SCONF_SIGLE_DATA_t I2SCONF_SIGLE_DATA;
375 };
376
377 static I2S_t & I2S = (*(I2S_t *)0x60000e00);
378
379} // _I2S_
380
381namespace _IO_MUX_ {
382
383 // IO_MUX_CONF
384 // Reset value: 0x00000000
385 BEGIN_TYPE(CONF_t, uint32_t)
386 ADD_BITFIELD_RW(SPI0_CLK_EQU_SYS_CLK, 8, 1)
387 ADD_BITFIELD_RW(SPI1_CLK_EQU_SYS_CLK, 9, 1)
388 END_TYPE()
389
390 // IO_MUX Entry
391 // Reset value: 0x00000000
392 BEGIN_TYPE(ENTRY_t, uint32_t)
393 ADD_BITFIELD_RW(OE, 0, 1)
394 ADD_BITFIELD_RW(OE_SLEEP, 1, 1)
395 ADD_BITFIELD_RW(PULLDOWN_SLEEP, 2, 1)
396 ADD_BITFIELD_RW(PULLUP_SLEEP, 3, 1)
397 ADD_BITFIELD_RW(PULLDOWN, 6, 1)
398 ADD_BITFIELD_RW(PULLUP, 7, 1)
399 ADD_BITFIELD_RW(FUNC, 19, 4)
400 END_TYPE()
401
402 struct IO_MUX_t {
403 CONF_t CONF;
404 ENTRY_t ENTRY[16];
405 };
406
407 static IO_MUX_t & IO_MUX = (*(IO_MUX_t *)0x60000800);
408
409} // _IO_MUX_
410
411namespace _RTC_ {
412
413 // RTC_STORE0
414 // Reset value: 0x00000000
415 BEGIN_TYPE(RTC_STORE0_t, uint32_t)
416 ADD_BITFIELD_RW(Register, 0, 32)
417 END_TYPE()
418
419 // RTC_STATE1
420 // Reset value: 0x00000000
421 BEGIN_TYPE(RTC_STATE1_t, uint32_t)
422 ADD_BITFIELD_RW(Register, 0, 32)
423 END_TYPE()
424
425 struct RTC_t {
426 uint32_t reserved0[5];
427 RTC_STATE1_t RTC_STATE1;
428 uint32_t reserved1[6];
429 RTC_STORE0_t RTC_STORE0;
430 };
431
432 static RTC_t & RTC = (*(RTC_t *)0x60000700);
433
434} // _RTC_
435
436namespace _SLC_ {
437
438 // SLC_CONF0
439 // Reset value: 0x00000000
440 BEGIN_TYPE(SLC_CONF0_t, uint32_t)
441 ADD_BITFIELD_RW(SLC_MODE, 12, 2)
442 ADD_BITFIELD_RW(SLC_DATA_BURST_EN, 9, 1)
443 ADD_BITFIELD_RW(SLC_DSCR_BURST_EN, 8, 1)
444 ADD_BITFIELD_RW(SLC_RX_NO_RESTART_CLR, 7, 1)
445 ADD_BITFIELD_RW(SLC_RX_AUTO_WRBACK, 6, 1)
446 ADD_BITFIELD_RW(SLC_RX_LOOP_TEST, 5, 1)
447 ADD_BITFIELD_RW(SLC_TX_LOOP_TEST, 4, 1)
448 ADD_BITFIELD_RW(SLC_AHBM_RST, 3, 1)
449 ADD_BITFIELD_RW(SLC_AHBM_FIFO_RST, 2, 1)
450 ADD_BITFIELD_RW(SLC_RXLINK_RST, 1, 1)
451 ADD_BITFIELD_RW(SLC_TXLINK_RST, 0, 1)
452 END_TYPE()
453
454 // SLC_INT_RAW
455 // Reset value: 0x00000000
456 BEGIN_TYPE(SLC_INT_RAW_t, uint32_t)
457 ADD_BITFIELD_RW(SLC_TX_DSCR_EMPTY_INT_RAW, 21, 1)
458 ADD_BITFIELD_RW(SLC_RX_DSCR_ERR_INT_RAW, 20, 1)
459 ADD_BITFIELD_RW(SLC_TX_DSCR_ERR_INT_RAW, 19, 1)
460 ADD_BITFIELD_RW(SLC_TOHOST_INT_RAW, 18, 1)
461 ADD_BITFIELD_RW(SLC_RX_EOF_INT_RAW, 17, 1)
462 ADD_BITFIELD_RW(SLC_RX_DONE_INT_RAW, 16, 1)
463 ADD_BITFIELD_RW(SLC_TX_EOF_INT_RAW, 15, 1)
464 ADD_BITFIELD_RW(SLC_TX_DONE_INT_RAW, 14, 1)
465 ADD_BITFIELD_RW(SLC_TOKEN1_1TO0_INT_RAW, 13, 1)
466 ADD_BITFIELD_RW(SLC_TOKEN0_1TO0_INT_RAW, 12, 1)
467 ADD_BITFIELD_RW(SLC_TX_OVF_INT_RAW, 11, 1)
468 ADD_BITFIELD_RW(SLC_RX_UDF_INT_RAW, 10, 1)
469 ADD_BITFIELD_RW(SLC_TX_START_INT_RAW, 9, 1)
470 ADD_BITFIELD_RW(SLC_RX_START_INT_RAW, 8, 1)
471 ADD_BITFIELD_RW(SLC_FRHOST_BIT7_INT_RAW, 7, 1)
472 ADD_BITFIELD_RW(SLC_FRHOST_BIT6_INT_RAW, 6, 1)
473 ADD_BITFIELD_RW(SLC_FRHOST_BIT5_INT_RAW, 5, 1)
474 ADD_BITFIELD_RW(SLC_FRHOST_BIT4_INT_RAW, 4, 1)
475 ADD_BITFIELD_RW(SLC_FRHOST_BIT3_INT_RAW, 3, 1)
476 ADD_BITFIELD_RW(SLC_FRHOST_BIT2_INT_RAW, 2, 1)
477 ADD_BITFIELD_RW(SLC_FRHOST_BIT1_INT_RAW, 1, 1)
478 ADD_BITFIELD_RW(SLC_FRHOST_BIT0_INT_RAW, 0, 1)
479 END_TYPE()
480
481 // SLC_INT_STATUS
482 // Reset value: 0x00000000
483 BEGIN_TYPE(SLC_INT_STATUS_t, uint32_t)
484 ADD_BITFIELD_RW(SLC_TX_DSCR_EMPTY_INT_ST, 21, 1)
485 ADD_BITFIELD_RW(SLC_RX_DSCR_ERR_INT_ST, 20, 1)
486 ADD_BITFIELD_RW(SLC_TX_DSCR_ERR_INT_ST, 19, 1)
487 ADD_BITFIELD_RW(SLC_TOHOST_INT_ST, 18, 1)
488 ADD_BITFIELD_RW(SLC_RX_EOF_INT_ST, 17, 1)
489 ADD_BITFIELD_RW(SLC_RX_DONE_INT_ST, 16, 1)
490 ADD_BITFIELD_RW(SLC_TX_EOF_INT_ST, 15, 1)
491 ADD_BITFIELD_RW(SLC_TX_DONE_INT_ST, 14, 1)
492 ADD_BITFIELD_RW(SLC_TOKEN1_1TO0_INT_ST, 13, 1)
493 ADD_BITFIELD_RW(SLC_TOKEN0_1TO0_INT_ST, 12, 1)
494 ADD_BITFIELD_RW(SLC_TX_OVF_INT_ST, 11, 1)
495 ADD_BITFIELD_RW(SLC_RX_UDF_INT_ST, 10, 1)
496 ADD_BITFIELD_RW(SLC_TX_START_INT_ST, 9, 1)
497 ADD_BITFIELD_RW(SLC_RX_START_INT_ST, 8, 1)
498 ADD_BITFIELD_RW(SLC_FRHOST_BIT7_INT_ST, 7, 1)
499 ADD_BITFIELD_RW(SLC_FRHOST_BIT6_INT_ST, 6, 1)
500 ADD_BITFIELD_RW(SLC_FRHOST_BIT5_INT_ST, 5, 1)
501 ADD_BITFIELD_RW(SLC_FRHOST_BIT4_INT_ST, 4, 1)
502 ADD_BITFIELD_RW(SLC_FRHOST_BIT3_INT_ST, 3, 1)
503 ADD_BITFIELD_RW(SLC_FRHOST_BIT2_INT_ST, 2, 1)
504 ADD_BITFIELD_RW(SLC_FRHOST_BIT1_INT_ST, 1, 1)
505 ADD_BITFIELD_RW(SLC_FRHOST_BIT0_INT_ST, 0, 1)
506 END_TYPE()
507
508 // SLC_INT_ENA
509 // Reset value: 0x00000000
510 BEGIN_TYPE(SLC_INT_ENA_t, uint32_t)
511 ADD_BITFIELD_RW(SLC_TX_DSCR_EMPTY_INT_ENA, 21, 1)
512 ADD_BITFIELD_RW(SLC_RX_DSCR_ERR_INT_ENA, 20, 1)
513 ADD_BITFIELD_RW(SLC_TX_DSCR_ERR_INT_ENA, 19, 1)
514 ADD_BITFIELD_RW(SLC_TOHOST_INT_ENA, 18, 1)
515 ADD_BITFIELD_RW(SLC_RX_EOF_INT_ENA, 17, 1)
516 ADD_BITFIELD_RW(SLC_RX_DONE_INT_ENA, 16, 1)
517 ADD_BITFIELD_RW(SLC_TX_EOF_INT_ENA, 15, 1)
518 ADD_BITFIELD_RW(SLC_TX_DONE_INT_ENA, 14, 1)
519 ADD_BITFIELD_RW(SLC_TOKEN1_1TO0_INT_ENA, 13, 1)
520 ADD_BITFIELD_RW(SLC_TOKEN0_1TO0_INT_ENA, 12, 1)
521 ADD_BITFIELD_RW(SLC_TX_OVF_INT_ENA, 11, 1)
522 ADD_BITFIELD_RW(SLC_RX_UDF_INT_ENA, 10, 1)
523 ADD_BITFIELD_RW(SLC_TX_START_INT_ENA, 9, 1)
524 ADD_BITFIELD_RW(SLC_RX_START_INT_ENA, 8, 1)
525 ADD_BITFIELD_RW(SLC_FRHOST_BIT7_INT_ENA, 7, 1)
526 ADD_BITFIELD_RW(SLC_FRHOST_BIT6_INT_ENA, 6, 1)
527 ADD_BITFIELD_RW(SLC_FRHOST_BIT5_INT_ENA, 5, 1)
528 ADD_BITFIELD_RW(SLC_FRHOST_BIT4_INT_ENA, 4, 1)
529 ADD_BITFIELD_RW(SLC_FRHOST_BIT3_INT_ENA, 3, 1)
530 ADD_BITFIELD_RW(SLC_FRHOST_BIT2_INT_ENA, 2, 1)
531 ADD_BITFIELD_RW(SLC_FRHOST_BIT1_INT_ENA, 1, 1)
532 ADD_BITFIELD_RW(SLC_FRHOST_BIT0_INT_ENA, 0, 1)
533 END_TYPE()
534
535 // SLC_INT_CLR
536 // Reset value: 0x00000000
537 BEGIN_TYPE(SLC_INT_CLR_t, uint32_t)
538 ADD_BITFIELD_RW(SLC_TX_DSCR_EMPTY_INT_CLR, 21, 1)
539 ADD_BITFIELD_RW(SLC_RX_DSCR_ERR_INT_CLR, 20, 1)
540 ADD_BITFIELD_RW(SLC_TX_DSCR_ERR_INT_CLR, 19, 1)
541 ADD_BITFIELD_RW(SLC_TOHOST_INT_CLR, 18, 1)
542 ADD_BITFIELD_RW(SLC_RX_EOF_INT_CLR, 17, 1)
543 ADD_BITFIELD_RW(SLC_RX_DONE_INT_CLR, 16, 1)
544 ADD_BITFIELD_RW(SLC_TX_EOF_INT_CLR, 15, 1)
545 ADD_BITFIELD_RW(SLC_TX_DONE_INT_CLR, 14, 1)
546 ADD_BITFIELD_RW(SLC_TOKEN1_1TO0_INT_CLR, 13, 1)
547 ADD_BITFIELD_RW(SLC_TOKEN0_1TO0_INT_CLR, 12, 1)
548 ADD_BITFIELD_RW(SLC_TX_OVF_INT_CLR, 11, 1)
549 ADD_BITFIELD_RW(SLC_RX_UDF_INT_CLR, 10, 1)
550 ADD_BITFIELD_RW(SLC_TX_START_INT_CLR, 9, 1)
551 ADD_BITFIELD_RW(SLC_RX_START_INT_CLR, 8, 1)
552 ADD_BITFIELD_RW(SLC_FRHOST_BIT7_INT_CLR, 7, 1)
553 ADD_BITFIELD_RW(SLC_FRHOST_BIT6_INT_CLR, 6, 1)
554 ADD_BITFIELD_RW(SLC_FRHOST_BIT5_INT_CLR, 5, 1)
555 ADD_BITFIELD_RW(SLC_FRHOST_BIT4_INT_CLR, 4, 1)
556 ADD_BITFIELD_RW(SLC_FRHOST_BIT3_INT_CLR, 3, 1)
557 ADD_BITFIELD_RW(SLC_FRHOST_BIT2_INT_CLR, 2, 1)
558 ADD_BITFIELD_RW(SLC_FRHOST_BIT1_INT_CLR, 1, 1)
559 ADD_BITFIELD_RW(SLC_FRHOST_BIT0_INT_CLR, 0, 1)
560 END_TYPE()
561
562 // SLC_RX_STATUS
563 // Reset value: 0x00000000
564 BEGIN_TYPE(SLC_RX_STATUS_t, uint32_t)
565 ADD_BITFIELD_RW(SLC_RX_EMPTY, 1, 1)
566 ADD_BITFIELD_RW(SLC_RX_FULL, 0, 1)
567 END_TYPE()
568
569 // SLC_RX_FIFO_PUSH
570 // Reset value: 0x00000000
571 BEGIN_TYPE(SLC_RX_FIFO_PUSH_t, uint32_t)
572 ADD_BITFIELD_RW(SLC_RXFIFO_PUSH, 16, 1)
573 ADD_BITFIELD_RW(SLC_RXFIFO_WDATA, 0, 9)
574 END_TYPE()
575
576 // SLC_TX_STATUS
577 // Reset value: 0x00000000
578 BEGIN_TYPE(SLC_TX_STATUS_t, uint32_t)
579 ADD_BITFIELD_RW(SLC_TX_EMPTY, 1, 1)
580 ADD_BITFIELD_RW(SLC_TX_FULL, 0, 1)
581 END_TYPE()
582
583 // SLC_TX_FIFO_POP
584 // Reset value: 0x00000000
585 BEGIN_TYPE(SLC_TX_FIFO_POP_t, uint32_t)
586 ADD_BITFIELD_RW(SLC_TXFIFO_POP, 16, 1)
587 ADD_BITFIELD_RW(SLC_TXFIFO_RDATA, 0, 11)
588 END_TYPE()
589
590 // SLC_RX_LINK
591 // Reset value: 0x00000000
592 BEGIN_TYPE(SLC_RX_LINK_t, uint32_t)
593 ADD_BITFIELD_RW(SLC_RXLINK_PARK, 31, 1)
594 ADD_BITFIELD_RW(SLC_RXLINK_RESTART, 30, 1)
595 ADD_BITFIELD_RW(SLC_RXLINK_START, 29, 1)
596 ADD_BITFIELD_RW(SLC_RXLINK_STOP, 28, 1)
597 ADD_BITFIELD_RW(SLC_RXLINK_ADDR, 0, 20)
598 END_TYPE()
599
600 // SLC_TX_LINK
601 // Reset value: 0x00000000
602 BEGIN_TYPE(SLC_TX_LINK_t, uint32_t)
603 ADD_BITFIELD_RW(SLC_TXLINK_PARK, 31, 1)
604 ADD_BITFIELD_RW(SLC_TXLINK_RESTART, 30, 1)
605 ADD_BITFIELD_RW(SLC_TXLINK_START, 29, 1)
606 ADD_BITFIELD_RW(SLC_TXLINK_STOP, 28, 1)
607 ADD_BITFIELD_RW(SLC_TXLINK_ADDR, 0, 20)
608 END_TYPE()
609
610 // SLC_INTVEC_TOHOST
611 // Reset value: 0x00000000
612 BEGIN_TYPE(SLC_INTVEC_TOHOST_t, uint32_t)
613 ADD_BITFIELD_RW(SLC_TOHOST_INTVEC, 0, 8)
614 END_TYPE()
615
616 // SLC_TOKEN0
617 // Reset value: 0x00000000
618 BEGIN_TYPE(SLC_TOKEN0_t, uint32_t)
619 ADD_BITFIELD_RW(SLC_TOKEN0, 16, 12)
620 ADD_BITFIELD_RW(SLC_TOKEN0_LOCAL_INC_MORE, 14, 1)
621 ADD_BITFIELD_RW(SLC_TOKEN0_LOCAL_INC, 13, 1)
622 ADD_BITFIELD_RW(SLC_TOKEN0_LOCAL_WR, 12, 1)
623 ADD_BITFIELD_RW(SLC_TOKEN0_LOCAL_WDATA, 0, 12)
624 END_TYPE()
625
626 // SLC_TOKEN1
627 // Reset value: 0x00000000
628 BEGIN_TYPE(SLC_TOKEN1_t, uint32_t)
629 ADD_BITFIELD_RW(SLC_TOKEN1, 16, 12)
630 ADD_BITFIELD_RW(SLC_TOKEN1_LOCAL_INC_MORE, 14, 1)
631 ADD_BITFIELD_RW(SLC_TOKEN1_LOCAL_INC, 13, 1)
632 ADD_BITFIELD_RW(SLC_TOKEN1_LOCAL_WR, 12, 1)
633 ADD_BITFIELD_RW(SLC_TOKEN1_LOCAL_WDATA, 0, 12)
634 END_TYPE()
635
636 // SLC_CONF1
637 // Reset value: 0x00000000
638 BEGIN_TYPE(SLC_CONF1_t, uint32_t)
639 ADD_BITFIELD_RW(Register, 0, 32)
640 END_TYPE()
641
642 // SLC_STATE0
643 // Reset value: 0x00000000
644 BEGIN_TYPE(SLC_STATE0_t, uint32_t)
645 ADD_BITFIELD_RW(Register, 0, 32)
646 END_TYPE()
647
648 // SLC_STATE1
649 // Reset value: 0x00000000
650 BEGIN_TYPE(SLC_STATE1_t, uint32_t)
651 ADD_BITFIELD_RW(Register, 0, 32)
652 END_TYPE()
653
654 // SLC_BRIDGE_CONF
655 // Reset value: 0x00000000
656 BEGIN_TYPE(SLC_BRIDGE_CONF_t, uint32_t)
657 ADD_BITFIELD_RW(SLC_TX_PUSH_IDLE_NUM, 16, 16)
658 ADD_BITFIELD_RW(SLC_TX_DUMMY_MODE, 12, 1)
659 ADD_BITFIELD_RW(SLC_FIFO_MAP_ENA, 8, 4)
660 ADD_BITFIELD_RW(SLC_TXEOF_ENA, 0, 6)
661 END_TYPE()
662
663 // SLC_RX_EOF_DES_ADDR
664 // Reset value: 0x00000000
665 BEGIN_TYPE(SLC_RX_EOF_DES_ADDR_t, uint32_t)
666 ADD_BITFIELD_RW(Register, 0, 32)
667 END_TYPE()
668
669 // SLC_TX_EOF_DES_ADDR
670 // Reset value: 0x00000000
671 BEGIN_TYPE(SLC_TX_EOF_DES_ADDR_t, uint32_t)
672 ADD_BITFIELD_RW(Register, 0, 32)
673 END_TYPE()
674
675 // SLC_RX_EOF_BFR_DES_ADDR
676 // Reset value: 0x00000000
677 BEGIN_TYPE(SLC_RX_EOF_BFR_DES_ADDR_t, uint32_t)
678 ADD_BITFIELD_RW(Register, 0, 32)
679 END_TYPE()
680
681 // SLC_AHB_TEST
682 // Reset value: 0x00000000
683 BEGIN_TYPE(SLC_AHB_TEST_t, uint32_t)
684 ADD_BITFIELD_RW(SLC_AHB_TESTADDR, 4, 2)
685 ADD_BITFIELD_RW(SLC_AHB_TESTMODE, 0, 3)
686 END_TYPE()
687
688 // SLC_SDIO_ST
689 // Reset value: 0x00000000
690 BEGIN_TYPE(SLC_SDIO_ST_t, uint32_t)
691 ADD_BITFIELD_RW(SLC_BUS_ST, 12, 3)
692 ADD_BITFIELD_RW(SLC_SDIO_WAKEUP, 8, 1)
693 ADD_BITFIELD_RW(SLC_FUNC_ST, 4, 4)
694 ADD_BITFIELD_RW(SLC_CMD_ST, 0, 3)
695 END_TYPE()
696
697 // SLC_RX_DSCR_CONF
698 // Reset value: 0x00000000
699 BEGIN_TYPE(SLC_RX_DSCR_CONF_t, uint32_t)
700 ADD_BITFIELD_RW(SLC_INFOR_NO_REPLACE, 9, 1)
701 ADD_BITFIELD_RW(SLC_TOKEN_NO_REPLACE, 8, 1)
702 END_TYPE()
703
704 // SLC_TXLINK_DSCR
705 // Reset value: 0x00000000
706 BEGIN_TYPE(SLC_TXLINK_DSCR_t, uint32_t)
707 ADD_BITFIELD_RW(Register, 0, 32)
708 END_TYPE()
709
710 // SLC_TXLINK_DSCR_BF0
711 // Reset value: 0x00000000
712 BEGIN_TYPE(SLC_TXLINK_DSCR_BF0_t, uint32_t)
713 ADD_BITFIELD_RW(Register, 0, 32)
714 END_TYPE()
715
716 // SLC_TXLINK_DSCR_BF1
717 // Reset value: 0x00000000
718 BEGIN_TYPE(SLC_TXLINK_DSCR_BF1_t, uint32_t)
719 ADD_BITFIELD_RW(Register, 0, 32)
720 END_TYPE()
721
722 // SLC_RXLINK_DSCR
723 // Reset value: 0x00000000
724 BEGIN_TYPE(SLC_RXLINK_DSCR_t, uint32_t)
725 ADD_BITFIELD_RW(Register, 0, 32)
726 END_TYPE()
727
728 // SLC_RXLINK_DSCR_BF0
729 // Reset value: 0x00000000
730 BEGIN_TYPE(SLC_RXLINK_DSCR_BF0_t, uint32_t)
731 ADD_BITFIELD_RW(Register, 0, 32)
732 END_TYPE()
733
734 // SLC_RXLINK_DSCR_BF1
735 // Reset value: 0x00000000
736 BEGIN_TYPE(SLC_RXLINK_DSCR_BF1_t, uint32_t)
737 ADD_BITFIELD_RW(Register, 0, 32)
738 END_TYPE()
739
740 // SLC_DATE
741 // Reset value: 0x00000000
742 BEGIN_TYPE(SLC_DATE_t, uint32_t)
743 ADD_BITFIELD_RW(Register, 0, 32)
744 END_TYPE()
745
746 // SLC_ID
747 // Reset value: 0x00000000
748 BEGIN_TYPE(SLC_ID_t, uint32_t)
749 ADD_BITFIELD_RW(Register, 0, 32)
750 END_TYPE()
751
752 struct SLC_t {
753 SLC_CONF0_t SLC_CONF0;
754 SLC_INT_RAW_t SLC_INT_RAW;
755 SLC_INT_STATUS_t SLC_INT_STATUS;
756 SLC_INT_ENA_t SLC_INT_ENA;
757 SLC_INT_CLR_t SLC_INT_CLR;
758 SLC_RX_STATUS_t SLC_RX_STATUS;
759 SLC_RX_FIFO_PUSH_t SLC_RX_FIFO_PUSH;
760 SLC_TX_STATUS_t SLC_TX_STATUS;
761 SLC_TX_FIFO_POP_t SLC_TX_FIFO_POP;
762 SLC_RX_LINK_t SLC_RX_LINK;
763 SLC_TX_LINK_t SLC_TX_LINK;
764 SLC_INTVEC_TOHOST_t SLC_INTVEC_TOHOST;
765 SLC_TOKEN0_t SLC_TOKEN0;
766 SLC_TOKEN1_t SLC_TOKEN1;
767 SLC_CONF1_t SLC_CONF1;
768 SLC_STATE0_t SLC_STATE0;
769 SLC_STATE1_t SLC_STATE1;
770 SLC_BRIDGE_CONF_t SLC_BRIDGE_CONF;
771 SLC_RX_EOF_DES_ADDR_t SLC_RX_EOF_DES_ADDR;
772 SLC_TX_EOF_DES_ADDR_t SLC_TX_EOF_DES_ADDR;
773 SLC_RX_EOF_BFR_DES_ADDR_t SLC_RX_EOF_BFR_DES_ADDR;
774 SLC_AHB_TEST_t SLC_AHB_TEST;
775 SLC_SDIO_ST_t SLC_SDIO_ST;
776 SLC_RX_DSCR_CONF_t SLC_RX_DSCR_CONF;
777 SLC_TXLINK_DSCR_t SLC_TXLINK_DSCR;
778 SLC_TXLINK_DSCR_BF0_t SLC_TXLINK_DSCR_BF0;
779 SLC_TXLINK_DSCR_BF1_t SLC_TXLINK_DSCR_BF1;
780 SLC_RXLINK_DSCR_t SLC_RXLINK_DSCR;
781 SLC_RXLINK_DSCR_BF0_t SLC_RXLINK_DSCR_BF0;
782 SLC_RXLINK_DSCR_BF1_t SLC_RXLINK_DSCR_BF1;
783 SLC_DATE_t SLC_DATE;
784 SLC_ID_t SLC_ID;
785 };
786
787 static SLC_t & SLC = (*(SLC_t *)0x60000b00);
788
789} // _SLC_
790
791namespace _SPI0_ {
792
793 // In the master mode, it is the start bit of a single operation.
794 // Self-clear by hardware
795 // Reset value: 0x00000000
796 BEGIN_TYPE(SPI_CMD_t, uint32_t)
797 // In the master mode, it is the start bit of a single operation.
798 // Self-clear by hardware
799 ADD_BITFIELD_RW(spi_usr, 18, 1)
800 END_TYPE()
801
802 // In the master mode, it is the value of address in "address" phase.
803 // Reset value: 0x00000000
804 BEGIN_TYPE(SPI_ADDR_t, uint32_t)
805 // In the master mode, it is the value of address in "address" phase.
806 ADD_BITFIELD_RW(iodata_start_addr, 0, 32)
807 END_TYPE()
808
809 // SPI_CTRL
810 // Reset value: 0x00000000
811 BEGIN_TYPE(SPI_CTRL_t, uint32_t)
812 // In "command", "address", "write-data" (MOSI) phases,
813 // 1: LSB first; 0: MSB first
814 ADD_BITFIELD_RW(spi_wr_bit_order, 26, 1)
815 // In "read-data" (MISO) phase,
816 // 1: LSB first; 0: MSB first
817 ADD_BITFIELD_RW(spi_rd_bit_order, 25, 1)
818 // In the read operations, "address" phase and "read-data" phase apply 4 signals
819 ADD_BITFIELD_RW(spi_qio_mode, 24, 1)
820 // In the read operations, "address" phase and "read-data" phase apply 2 signals
821 ADD_BITFIELD_RW(spi_dio_mode, 23, 1)
822 // In the read operations, "read-data" phase apply 4 signals
823 ADD_BITFIELD_RW(spi_qout_mode, 20, 1)
824 // In the read operations, "read-data" phase apply 2 signals
825 ADD_BITFIELD_RW(spi_dout_mode, 14, 1)
826 // this bit enable the bits: spi_qio_mode,
827 // spi_dio_mode, spi_qout_mode and spi_dout_mode
828 ADD_BITFIELD_RW(spi_fastrd_mode, 13, 1)
829 END_TYPE()
830
831 // In the slave mode, this register are the
832 // status register for the master to read out.
833 // Reset value: 0x00000000
834 BEGIN_TYPE(SPI_RD_STATUS_t, uint32_t)
835 // In the slave mode, this register are the
836 // status register for the master to read out.
837 ADD_BITFIELD_RW(slv_rd_status, 0, 32)
838 END_TYPE()
839
840 // spi_cs signal is delayed by 80MHz clock cycles
841 // Reset value: 0x00000000
842 BEGIN_TYPE(SPI_CTRL2_t, uint32_t)
843 // spi_cs signal is delayed by 80MHz clock cycles
844 ADD_BITFIELD_RW(spi_cs_delay_num, 28, 4)
845 // spi_cs signal is delayed by spi_clk.
846 // 0: zero; 1: half cycle; 2: one cycle
847 ADD_BITFIELD_RW(spi_cs_delay_mode, 26, 2)
848 // MOSI signals are delayed by 80MHz clock cycles
849 ADD_BITFIELD_RW(spi_mosi_delay_num, 23, 3)
850 // MOSI signals are delayed by spi_clk.
851 // 0: zero; 1: half cycle; 2: one cycle
852 ADD_BITFIELD_RW(spi_mosi_delay_mode, 21, 2)
853 // MISO signals are delayed by 80MHz clock cycles
854 ADD_BITFIELD_RW(spi_miso_delay_num, 18, 3)
855 // MISO signals are delayed by spi_clk.
856 // 0: zero; 1: half cycle; 2: one cycle
857 ADD_BITFIELD_RW(spi_miso_delay_mode, 16, 2)
858 END_TYPE()
859
860 // In the master mode,
861 // 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.
862 // Reset value: 0x00000000
863 BEGIN_TYPE(SPI_CLOCK_t, uint32_t)
864 // In the master mode,
865 // 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.
866 ADD_BITFIELD_RW(spi_clk_equ_sysclk, 31, 1)
867 // In the master mode, it is pre-divider of spi_clk.
868 ADD_BITFIELD_RW(spi_clkdiv_pre, 18, 13)
869 // In the master mode, it is the divider of spi_clk.
870 // So spi_clk frequency is 80MHz/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)
871 ADD_BITFIELD_RW(spi_clkcnt_N, 12, 6)
872 // In the master mode, it must be floor((spi_clkcnt_N+1)/2-1).
873 // In the slave mode, it must be 0.
874 ADD_BITFIELD_RW(spi_clkcnt_H, 6, 6)
875 // In the master mode, it must be eqaul to spi_clkcnt_N.
876 // In the slave mode, it must be 0.
877 ADD_BITFIELD_RW(spi_clkcnt_L, 0, 6)
878 END_TYPE()
879
880 // This bit enable the "command" phase of an operation.
881 // Reset value: 0x00000000
882 BEGIN_TYPE(SPI_USER_t, uint32_t)
883 // This bit enable the "command" phase of an operation.
884 ADD_BITFIELD_RW(spi_usr_command, 31, 1)
885 // This bit enable the "address" phase of an operation.
886 ADD_BITFIELD_RW(spi_usr_addr, 30, 1)
887 // This bit enable the "dummy" phase of an operation.
888 ADD_BITFIELD_RW(spi_usr_dummy, 29, 1)
889 // This bit enable the "read-data" phase of an operation.
890 ADD_BITFIELD_RW(spi_usr_miso, 28, 1)
891 // This bit enable the "write-data" phase of an operation.
892 ADD_BITFIELD_RW(spi_usr_mosi, 27, 1)
893 // 1: "write-data" phase only access to high-part of the buffer spi_w8~spi_w15
894 ADD_BITFIELD_RW(reg_usr_mosi_highpart, 25, 1)
895 // 1: "read-data" phase only access to high-part of the buffer spi_w8~spi_w15
896 ADD_BITFIELD_RW(reg_usr_miso_highpart, 24, 1)
897 // 1: mosi and miso signals share the same pin
898 ADD_BITFIELD_RW(spi_sio, 16, 1)
899 // In the write operations, "address" phase and
900 // "read-data" phase apply 4 signals
901 ADD_BITFIELD_RW(spi_fwrite_qio, 15, 1)
902 // In the write operations, "address" phase and
903 // "read-data" phase apply 2 signals
904 ADD_BITFIELD_RW(spi_fwrite_dio, 14, 1)
905 // In the write operations, "read-data" phase apply 4 signals
906 ADD_BITFIELD_RW(spi_fwrite_quad, 13, 1)
907 // In the write operations, "read-data" phase apply 2 signals
908 ADD_BITFIELD_RW(spi_fwrite_dual, 12, 1)
909 // In "command", "address", "write-data" (MOSI) phases,
910 // 1: little-endian; 0: big_endian
911 ADD_BITFIELD_RW(spi_wr_byte_order, 11, 1)
912 // In "read-data" (MISO) phase, 1: little-endian; 0: big_endian
913 ADD_BITFIELD_RW(spi_rd_byte_order, 10, 1)
914 // In the slave mode, 1: rising-edge; 0: falling-edge
915 ADD_BITFIELD_RW(spi_ck_i_edge, 6, 1)
916 END_TYPE()
917
918 // The length in bits of "address" phase.
919 // The register value shall be (bit_num-1)
920 // Reset value: 0x00000000
921 BEGIN_TYPE(SPI_USER1_t, uint32_t)
922 // The length in bits of "address" phase.
923 // The register value shall be (bit_num-1)
924 ADD_BITFIELD_RW(reg_usr_addr_bitlen, 26, 6)
925 // The length in bits of "write-data" phase.
926 // The register value shall be (bit_num-1)
927 ADD_BITFIELD_RW(reg_usr_mosi_bitlen, 17, 9)
928 // The length in bits of "read-data" phase.
929 // The register value shall be (bit_num-1)
930 ADD_BITFIELD_RW(reg_usr_miso_bitlen, 8, 9)
931 // The length in spi_clk cycles of "dummy" phase.
932 // The register value shall be (cycle_num-1)
933 ADD_BITFIELD_RW(reg_usr_dummy_cyclelen, 0, 8)
934 END_TYPE()
935
936 // The length in bits of "command" phase.
937 // The register value shall be (bit_num-1)
938 // Reset value: 0x00000000
939 BEGIN_TYPE(SPI_USER2_t, uint32_t)
940 // The length in bits of "command" phase.
941 // The register value shall be (bit_num-1)
942 ADD_BITFIELD_RW(reg_usr_command_bitlen, 28, 4)
943 // The value of "command" phase
944 ADD_BITFIELD_RW(reg_usr_command_value, 0, 16)
945 END_TYPE()
946
947 // In the slave mode, this register are the
948 // status register for the master to write into.
949 // Reset value: 0x00000000
950 BEGIN_TYPE(SPI_WR_STATUS_t, uint32_t)
951 // In the slave mode, this register are the
952 // status register for the master to write into.
953 ADD_BITFIELD_RW(slv_wr_status, 0, 32)
954 END_TYPE()
955
956 // 1: disable CS2; 0: spi_cs signal is from/to CS2 pin
957 // Reset value: 0x00000000
958 BEGIN_TYPE(SPI_PIN_t, uint32_t)
959 // 1: disable CS2; 0: spi_cs signal is from/to CS2 pin
960 ADD_BITFIELD_RW(spi_cs2_dis, 2, 1)
961 // 1: disable CS1; 0: spi_cs signal is from/to CS1 pin
962 ADD_BITFIELD_RW(spi_cs1_dis, 1, 1)
963 // 1: disable CS0; 0: spi_cs signal is from/to CS0 pin
964 ADD_BITFIELD_RW(spi_cs0_dis, 0, 1)
965 END_TYPE()
966
967 // It is the synchronous reset signal of the module.
968 // This bit is self-cleared by hardware.
969 // Reset value: 0x00000000
970 BEGIN_TYPE(SPI_SLAVE_t, uint32_t)
971 // It is the synchronous reset signal of the module.
972 // This bit is self-cleared by hardware.
973 ADD_BITFIELD_RW(spi_sync_reset, 31, 1)
974 // 1: slave mode, 0: master mode.
975 ADD_BITFIELD_RW(spi_slave_mode, 30, 1)
976 // 1: slave mode commands are defined in SPI_SLAVE3.
977 // 0: slave mode commands are fixed as
978 // 1: "write-status"; 4: "read-status"; 2: "write-buffer" and 3: "read-buffer".
979 ADD_BITFIELD_RW(slv_cmd_define, 27, 1)
980 // The operations counter in both the master mode and the slave mode.
981 ADD_BITFIELD_RO(spi_trans_cnt, 23, 4)
982 // Interrupt enable bits for the below 5 sources
983 ADD_BITFIELD_RW(spi_int_en, 5, 5)
984 // The interrupt raw bit for the completement of any
985 // operation in both the master mode and the slave mode.
986 ADD_BITFIELD_RW(spi_trans_done, 4, 1)
987 // The interrupt raw bit for the completement of
988 // "write-status" operation in the slave mode.
989 ADD_BITFIELD_RW(slv_wr_sta_done, 3, 1)
990 // The interrupt raw bit for the completement of
991 // "read-status" operation in the slave mode.
992 ADD_BITFIELD_RW(slv_rd_sta_done, 2, 1)
993 // The interrupt raw bit for the completement of
994 // "write-buffer" operation in the slave mode.
995 ADD_BITFIELD_RW(slv_wr_buf_done, 1, 1)
996 // The interrupt raw bit for the completement of
997 // "read-buffer" operation in the slave mode.
998 ADD_BITFIELD_RW(slv_rd_buf_done, 0, 1)
999 END_TYPE()
1000
1001 // In the slave mode, it is the length in bits for "write-status"
1002 // and "read-status" operations. The register valueshall be (bit_num-1)
1003 // Reset value: 0x00000000
1004 BEGIN_TYPE(SPI_SLAVE1_t, uint32_t)
1005 // In the slave mode, it is the length in bits for "write-status"
1006 // and "read-status" operations. The register valueshall be (bit_num-1)
1007 ADD_BITFIELD_RW(slv_status_bitlen, 27, 5)
1008 // In the slave mode, it is the length in bits for "write-buffer"
1009 // and "read-buffer" operations. The register value shallbe (bit_num-1)
1010 ADD_BITFIELD_RW(slv_buf_bitlen, 16, 9)
1011 // In the slave mode, it is the address length in bits for "read-buffer"
1012 // operation. The register value shall be(bit_num-1)
1013 ADD_BITFIELD_RW(slv_rd_addr_bitlen, 10, 6)
1014 // In the slave mode, it is the address length in bits for "write-buffer"
1015 // operation. The register value shall be(bit_num-1)
1016 ADD_BITFIELD_RW(slv_wr_addr_bitlen, 4, 6)
1017 // In the slave mode, it is the enable bit of
1018 // "dummy" phase for "write-status" operations.
1019 ADD_BITFIELD_RW(slv_wrsta_dummy_en, 3, 1)
1020 // In the slave mode, it is the enable bit of
1021 // "dummy" phase for "read-status" operations.
1022 ADD_BITFIELD_RW(slv_rdsta_dummy_en, 2, 1)
1023 // In the slave mode, it is the enable bit of
1024 // "dummy" phase for "write-buffer" operations.
1025 ADD_BITFIELD_RW(slv_wrbuf_dummy_en, 1, 1)
1026 // In the slave mode, it is the enable bit of
1027 // "dummy" phase for "read-buffer" operations.
1028 ADD_BITFIELD_RW(slv_rdbuf_dummy_en, 0, 1)
1029 END_TYPE()
1030
1031 // In the slave mode, it is the length in spi_clk cycles "dummy" phase
1032 // for "write-buffer" operations. The registervalue shall be (cycle_num-1)
1033 // Reset value: 0x00000000
1034 BEGIN_TYPE(SPI_SLAVE2_t, uint32_t)
1035 // In the slave mode, it is the length in spi_clk cycles "dummy" phase
1036 // for "write-buffer" operations. The registervalue shall be (cycle_num-1)
1037 ADD_BITFIELD_RW(slv_wrbuf_dummy_cyclelen, 24, 8)
1038 // In the slave mode, it is the length in spi_clk cycles of "dummy" phase
1039 // for "read-buffer" operations. The registervalue shall be (cycle_num-1)
1040 ADD_BITFIELD_RW(slv_rdbuf_dummy_cyclelen, 16, 8)
1041 // In the slave mode, it is the length in spi_clk cycles of "dummy" phase
1042 // for "write-status" operations. Theregister value shall be (cycle_num-1)
1043 ADD_BITFIELD_RW(slv_wrsta_dummy_cyclelen, 8, 8)
1044 // In the slave mode, it is the length in spi_clk cycles of "dummy" phase
1045 // for "read-status" operations. Theregister value shall be (cycle_num-1)
1046 ADD_BITFIELD_RW(slv_rdsta_dummy_cyclelen, 0, 8)
1047 END_TYPE()
1048
1049 // In slave mode, it is the value of "write-status" command
1050 // Reset value: 0x00000000
1051 BEGIN_TYPE(SPI_SLAVE3_t, uint32_t)
1052 // In slave mode, it is the value of "write-status" command
1053 ADD_BITFIELD_RW(slv_wrsta_cmd_value, 24, 8)
1054 // In slave mode, it is the value of "read-status" command
1055 ADD_BITFIELD_RW(slv_rdsta_cmd_value, 16, 8)
1056 // In slave mode, it is the value of "write-buffer" command
1057 ADD_BITFIELD_RW(slv_wrbuf_cmd_value, 8, 8)
1058 // In slave mode, it is the value of "read-buffer" command
1059 ADD_BITFIELD_RW(slv_rdbuf_cmd_value, 0, 8)
1060 END_TYPE()
1061
1062 // This register is for two SPI masters to share the same cs,
1063 // clock and data signals.
1064 // Reset value: 0x00000000
1065 BEGIN_TYPE(SPI_EXT3_t, uint32_t)
1066 // This register is for two SPI masters to share the same cs,
1067 // clock and data signals.
1068 ADD_BITFIELD_RW(reg_int_hold_ena, 0, 2)
1069 END_TYPE()
1070
1071 // The data inside the buffer of the SPI module, word 0
1072 // Reset value: 0x00000000
1073 BEGIN_TYPE(SPI_W0_t, uint32_t)
1074 // The data inside the buffer of the SPI module, word 0
1075 ADD_BITFIELD_RW(spi_w0, 0, 32)
1076 END_TYPE()
1077
1078 // The data inside the buffer of the SPI module, word 1
1079 // Reset value: 0x00000000
1080 BEGIN_TYPE(SPI_W1_t, uint32_t)
1081 // The data inside the buffer of the SPI module, word 1
1082 ADD_BITFIELD_RW(spi_w1, 0, 32)
1083 END_TYPE()
1084
1085 // The data inside the buffer of the SPI module, word 2
1086 // Reset value: 0x00000000
1087 BEGIN_TYPE(SPI_W2_t, uint32_t)
1088 // The data inside the buffer of the SPI module, word 2
1089 ADD_BITFIELD_RW(spi_w2, 0, 32)
1090 END_TYPE()
1091
1092 // The data inside the buffer of the SPI module, word 3
1093 // Reset value: 0x00000000
1094 BEGIN_TYPE(SPI_W3_t, uint32_t)
1095 // The data inside the buffer of the SPI module, word 3
1096 ADD_BITFIELD_RW(spi_w3, 0, 32)
1097 END_TYPE()
1098
1099 // The data inside the buffer of the SPI module, word 4
1100 // Reset value: 0x00000000
1101 BEGIN_TYPE(SPI_W4_t, uint32_t)
1102 // The data inside the buffer of the SPI module, word 4
1103 ADD_BITFIELD_RW(spi_w4, 0, 32)
1104 END_TYPE()
1105
1106 // The data inside the buffer of the SPI module, word 5
1107 // Reset value: 0x00000000
1108 BEGIN_TYPE(SPI_W5_t, uint32_t)
1109 // The data inside the buffer of the SPI module, word 5
1110 ADD_BITFIELD_RW(spi_w5, 0, 32)
1111 END_TYPE()
1112
1113 // The data inside the buffer of the SPI module, word 6
1114 // Reset value: 0x00000000
1115 BEGIN_TYPE(SPI_W6_t, uint32_t)
1116 // The data inside the buffer of the SPI module, word 6
1117 ADD_BITFIELD_RW(spi_w6, 0, 32)
1118 END_TYPE()
1119
1120 // The data inside the buffer of the SPI module, word 7
1121 // Reset value: 0x00000000
1122 BEGIN_TYPE(SPI_W7_t, uint32_t)
1123 // The data inside the buffer of the SPI module, word 7
1124 ADD_BITFIELD_RW(spi_w7, 0, 32)
1125 END_TYPE()
1126
1127 // The data inside the buffer of the SPI module, word 8
1128 // Reset value: 0x00000000
1129 BEGIN_TYPE(SPI_W8_t, uint32_t)
1130 // The data inside the buffer of the SPI module, word 8
1131 ADD_BITFIELD_RW(spi_w8, 0, 32)
1132 END_TYPE()
1133
1134 // The data inside the buffer of the SPI module, word 9
1135 // Reset value: 0x00000000
1136 BEGIN_TYPE(SPI_W9_t, uint32_t)
1137 // The data inside the buffer of the SPI module, word 9
1138 ADD_BITFIELD_RW(spi_w9, 0, 32)
1139 END_TYPE()
1140
1141 // The data inside the buffer of the SPI module, word 10
1142 // Reset value: 0x00000000
1143 BEGIN_TYPE(SPI_W10_t, uint32_t)
1144 // The data inside the buffer of the SPI module, word 10
1145 ADD_BITFIELD_RW(spi_w10, 0, 32)
1146 END_TYPE()
1147
1148 // The data inside the buffer of the SPI module, word 11
1149 // Reset value: 0x00000000
1150 BEGIN_TYPE(SPI_W11_t, uint32_t)
1151 // The data inside the buffer of the SPI module, word 11
1152 ADD_BITFIELD_RW(spi_w11, 0, 32)
1153 END_TYPE()
1154
1155 // The data inside the buffer of the SPI module, word 12
1156 // Reset value: 0x00000000
1157 BEGIN_TYPE(SPI_W12_t, uint32_t)
1158 // The data inside the buffer of the SPI module, word 12
1159 ADD_BITFIELD_RW(spi_w12, 0, 32)
1160 END_TYPE()
1161
1162 // The data inside the buffer of the SPI module, word 13
1163 // Reset value: 0x00000000
1164 BEGIN_TYPE(SPI_W13_t, uint32_t)
1165 // The data inside the buffer of the SPI module, word 13
1166 ADD_BITFIELD_RW(spi_w13, 0, 32)
1167 END_TYPE()
1168
1169 // The data inside the buffer of the SPI module, word 14
1170 // Reset value: 0x00000000
1171 BEGIN_TYPE(SPI_W14_t, uint32_t)
1172 // The data inside the buffer of the SPI module, word 14
1173 ADD_BITFIELD_RW(spi_w14, 0, 32)
1174 END_TYPE()
1175
1176 // The data inside the buffer of the SPI module, word 15
1177 // Reset value: 0x00000000
1178 BEGIN_TYPE(SPI_W15_t, uint32_t)
1179 // The data inside the buffer of the SPI module, word 15
1180 ADD_BITFIELD_RW(spi_w15, 0, 32)
1181 END_TYPE()
1182
1183 struct SPI0_t {
1184 SPI_CMD_t SPI_CMD;
1185 SPI_ADDR_t SPI_ADDR;
1186 SPI_CTRL_t SPI_CTRL;
1187 uint32_t reserved0;
1188 SPI_RD_STATUS_t SPI_RD_STATUS;
1189 SPI_CTRL2_t SPI_CTRL2;
1190 SPI_CLOCK_t SPI_CLOCK;
1191 SPI_USER_t SPI_USER;
1192 SPI_USER1_t SPI_USER1;
1193 SPI_USER2_t SPI_USER2;
1194 SPI_WR_STATUS_t SPI_WR_STATUS;
1195 SPI_PIN_t SPI_PIN;
1196 SPI_SLAVE_t SPI_SLAVE;
1197 SPI_SLAVE1_t SPI_SLAVE1;
1198 SPI_SLAVE2_t SPI_SLAVE2;
1199 SPI_SLAVE3_t SPI_SLAVE3;
1200 SPI_W0_t SPI_W0;
1201 SPI_W1_t SPI_W1;
1202 SPI_W2_t SPI_W2;
1203 SPI_W3_t SPI_W3;
1204 SPI_W4_t SPI_W4;
1205 SPI_W5_t SPI_W5;
1206 SPI_W6_t SPI_W6;
1207 SPI_W7_t SPI_W7;
1208 SPI_W8_t SPI_W8;
1209 SPI_W9_t SPI_W9;
1210 SPI_W10_t SPI_W10;
1211 SPI_W11_t SPI_W11;
1212 SPI_W12_t SPI_W12;
1213 SPI_W13_t SPI_W13;
1214 SPI_W14_t SPI_W14;
1215 SPI_W15_t SPI_W15;
1216 uint32_t reserved1[31];
1217 SPI_EXT3_t SPI_EXT3;
1218 };
1219
1220 static SPI0_t & SPI0 = (*(SPI0_t *)0x60000200);
1221
1222} // _SPI0_
1223
1224namespace _SPI1_ {
1225
1226 // In the master mode, it is the start bit of a single operation.
1227 // Self-clear by hardware
1228 // Reset value: 0x00000000
1229 BEGIN_TYPE(SPI_CMD_t, uint32_t)
1230 // In the master mode, it is the start bit of a single operation.
1231 // Self-clear by hardware
1232 ADD_BITFIELD_RW(spi_usr, 18, 1)
1233 END_TYPE()
1234
1235 // In the master mode, it is the value of address in "address" phase.
1236 // Reset value: 0x00000000
1237 BEGIN_TYPE(SPI_ADDR_t, uint32_t)
1238 // In the master mode, it is the value of address in "address" phase.
1239 ADD_BITFIELD_RW(iodata_start_addr, 0, 32)
1240 END_TYPE()
1241
1242 // SPI_CTRL
1243 // Reset value: 0x00000000
1244 BEGIN_TYPE(SPI_CTRL_t, uint32_t)
1245 // In "command", "address", "write-data" (MOSI) phases,
1246 // 1: LSB first; 0: MSB first
1247 ADD_BITFIELD_RW(spi_wr_bit_order, 26, 1)
1248 // In "read-data" (MISO) phase,
1249 // 1: LSB first; 0: MSB first
1250 ADD_BITFIELD_RW(spi_rd_bit_order, 25, 1)
1251 // In the read operations, "address" phase and "read-data" phase apply 4 signals
1252 ADD_BITFIELD_RW(spi_qio_mode, 24, 1)
1253 // In the read operations, "address" phase and "read-data" phase apply 2 signals
1254 ADD_BITFIELD_RW(spi_dio_mode, 23, 1)
1255 // In the read operations, "read-data" phase apply 4 signals
1256 ADD_BITFIELD_RW(spi_qout_mode, 20, 1)
1257 // In the read operations, "read-data" phase apply 2 signals
1258 ADD_BITFIELD_RW(spi_dout_mode, 14, 1)
1259 // this bit enable the bits: spi_qio_mode,
1260 // spi_dio_mode, spi_qout_mode and spi_dout_mode
1261 ADD_BITFIELD_RW(spi_fastrd_mode, 13, 1)
1262 END_TYPE()
1263
1264 // In the slave mode, this register are the status register for the master to read out.
1265 // Reset value: 0x00000000
1266 BEGIN_TYPE(SPI_RD_STATUS_t, uint32_t)
1267 // In the slave mode, this register are the
1268 // status register for the master to read out.
1269 ADD_BITFIELD_RW(slv_rd_status, 0, 32)
1270 END_TYPE()
1271
1272 // spi_cs signal is delayed by 80MHz clock cycles
1273 // Reset value: 0x00000000
1274 BEGIN_TYPE(SPI_CTRL2_t, uint32_t)
1275 // spi_cs signal is delayed by 80MHz clock cycles
1276 ADD_BITFIELD_RW(spi_cs_delay_num, 28, 4)
1277 // spi_cs signal is delayed by spi_clk.
1278 // 0: zero; 1: half cycle; 2: one cycle
1279 ADD_BITFIELD_RW(spi_cs_delay_mode, 26, 2)
1280 // MOSI signals are delayed by 80MHz clock cycles
1281 ADD_BITFIELD_RW(spi_mosi_delay_num, 23, 3)
1282 // MOSI signals are delayed by spi_clk.
1283 // 0: zero; 1: half cycle; 2: one cycle
1284 ADD_BITFIELD_RW(spi_mosi_delay_mode, 21, 2)
1285 // MISO signals are delayed by 80MHz clock cycles
1286 ADD_BITFIELD_RW(spi_miso_delay_num, 18, 3)
1287 // MISO signals are delayed by spi_clk.
1288 // 0: zero; 1: half cycle; 2: one cycle
1289 ADD_BITFIELD_RW(spi_miso_delay_mode, 16, 2)
1290 END_TYPE()
1291
1292 // In the master mode,
1293 // 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.
1294 // Reset value: 0x00000000
1295 BEGIN_TYPE(SPI_CLOCK_t, uint32_t)
1296 // In the master mode,
1297 // 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.
1298 ADD_BITFIELD_RW(spi_clk_equ_sysclk, 31, 1)
1299 // In the master mode, it is pre-divider of spi_clk.
1300 ADD_BITFIELD_RW(spi_clkdiv_pre, 18, 13)
1301 // In the master mode, it is the divider of spi_clk.
1302 // So spi_clk frequency is 80MHz/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)
1303 ADD_BITFIELD_RW(spi_clkcnt_N, 12, 6)
1304 // In the master mode, it must be floor((spi_clkcnt_N+1)/2-1).
1305 // In the slave mode, it must be 0.
1306 ADD_BITFIELD_RW(spi_clkcnt_H, 6, 6)
1307 // In the master mode, it must be eqaul to spi_clkcnt_N.
1308 // In the slave mode, it must be 0.
1309 ADD_BITFIELD_RW(spi_clkcnt_L, 0, 6)
1310 END_TYPE()
1311
1312 // This bit enable the "command" phase of an operation.
1313 // Reset value: 0x00000000
1314 BEGIN_TYPE(SPI_USER_t, uint32_t)
1315 // This bit enable the "command" phase of an operation.
1316 ADD_BITFIELD_RW(spi_usr_command, 31, 1)
1317 // This bit enable the "address" phase of an operation.
1318 ADD_BITFIELD_RW(spi_usr_addr, 30, 1)
1319 // This bit enable the "dummy" phase of an operation.
1320 ADD_BITFIELD_RW(spi_usr_dummy, 29, 1)
1321 // This bit enable the "read-data" phase of an operation.
1322 ADD_BITFIELD_RW(spi_usr_miso, 28, 1)
1323 // This bit enable the "write-data" phase of an operation.
1324 ADD_BITFIELD_RW(spi_usr_mosi, 27, 1)
1325 // 1: "write-data" phase only access to high-part of the buffer spi_w8~spi_w15
1326 ADD_BITFIELD_RW(reg_usr_mosi_highpart, 25, 1)
1327 // 1: "read-data" phase only access to high-part of the buffer spi_w8~spi_w15
1328 ADD_BITFIELD_RW(reg_usr_miso_highpart, 24, 1)
1329 // 1: mosi and miso signals share the same pin
1330 ADD_BITFIELD_RW(spi_sio, 16, 1)
1331 // In the write operations, "address" phase and
1332 // "read-data" phase apply 4 signals
1333 ADD_BITFIELD_RW(spi_fwrite_qio, 15, 1)
1334 // In the write operations, "address" phase
1335 // and "read-data" phase apply 2 signals
1336 ADD_BITFIELD_RW(spi_fwrite_dio, 14, 1)
1337 // In the write operations, "read-data" phase apply 4 signals
1338 ADD_BITFIELD_RW(spi_fwrite_quad, 13, 1)
1339 // In the write operations, "read-data" phase apply 2 signals
1340 ADD_BITFIELD_RW(spi_fwrite_dual, 12, 1)
1341 // In "command", "address", "write-data" (MOSI) phases,
1342 // 1: little-endian; 0: big_endian
1343 ADD_BITFIELD_RW(spi_wr_byte_order, 11, 1)
1344 // In "read-data" (MISO) phase,
1345 // 1: little-endian; 0: big_endian
1346 ADD_BITFIELD_RW(spi_rd_byte_order, 10, 1)
1347 // In the slave mode,
1348 // 1: rising-edge; 0: falling-edge
1349 ADD_BITFIELD_RW(spi_ck_i_edge, 6, 1)
1350 END_TYPE()
1351
1352 // The length in bits of "address" phase.
1353 // The register value shall be (bit_num-1)
1354 // Reset value: 0x00000000
1355 BEGIN_TYPE(SPI_USER1_t, uint32_t)
1356 // The length in bits of "address" phase.
1357 // The register value shall be (bit_num-1)
1358 ADD_BITFIELD_RW(reg_usr_addr_bitlen, 26, 6)
1359 // The length in bits of "write-data" phase.
1360 // The register value shall be (bit_num-1)
1361 ADD_BITFIELD_RW(reg_usr_mosi_bitlen, 17, 9)
1362 // The length in bits of "read-data" phase.
1363 // The register value shall be (bit_num-1)
1364 ADD_BITFIELD_RW(reg_usr_miso_bitlen, 8, 9)
1365 // The length in spi_clk cycles of "dummy" phase.
1366 // The register value shall be (cycle_num-1)
1367 ADD_BITFIELD_RW(reg_usr_dummy_cyclelen, 0, 8)
1368 END_TYPE()
1369
1370 // The length in bits of "command" phase.
1371 // The register value shall be (bit_num-1)
1372 // Reset value: 0x00000000
1373 BEGIN_TYPE(SPI_USER2_t, uint32_t)
1374 // The length in bits of "command" phase.
1375 // The register value shall be (bit_num-1)
1376 ADD_BITFIELD_RW(reg_usr_command_bitlen, 28, 4)
1377 // The value of "command" phase
1378 ADD_BITFIELD_RW(reg_usr_command_value, 0, 16)
1379 END_TYPE()
1380
1381 // In the slave mode, this register are the
1382 // status register for the master to write into.
1383 // Reset value: 0x00000000
1384 BEGIN_TYPE(SPI_WR_STATUS_t, uint32_t)
1385 // In the slave mode, this register are the
1386 // status register for the master to write into.
1387 ADD_BITFIELD_RW(slv_wr_status, 0, 32)
1388 END_TYPE()
1389
1390 // 1: disable CS2; 0: spi_cs signal is from/to CS2 pin
1391 // Reset value: 0x00000000
1392 BEGIN_TYPE(SPI_PIN_t, uint32_t)
1393 // 1: disable CS2; 0: spi_cs signal is from/to CS2 pin
1394 ADD_BITFIELD_RW(spi_cs2_dis, 2, 1)
1395 // 1: disable CS1; 0: spi_cs signal is from/to CS1 pin
1396 ADD_BITFIELD_RW(spi_cs1_dis, 1, 1)
1397 // 1: disable CS0; 0: spi_cs signal is from/to CS0 pin
1398 ADD_BITFIELD_RW(spi_cs0_dis, 0, 1)
1399 END_TYPE()
1400
1401 // It is the synchronous reset signal of the module.
1402 // This bit is self-cleared by hardware.
1403 // Reset value: 0x00000000
1404 BEGIN_TYPE(SPI_SLAVE_t, uint32_t)
1405 // It is the synchronous reset signal of the module.
1406 // This bit is self-cleared by hardware.
1407 ADD_BITFIELD_RW(spi_sync_reset, 31, 1)
1408 // 1: slave mode, 0: master mode.
1409 ADD_BITFIELD_RW(spi_slave_mode, 30, 1)
1410 // 1: slave mode commands are defined in SPI_SLAVE3.
1411 // 0: slave mode commands are fixed as 1: "write-status";
1412 // 4: "read-status"; 2: "write-buffer" and 3: "read-buffer".
1413 ADD_BITFIELD_RW(slv_cmd_define, 27, 1)
1414 // The operations counter in both the master mode and the slave mode.
1415 ADD_BITFIELD_RO(spi_trans_cnt, 23, 4)
1416 // Interrupt enable bits for the below 5 sources
1417 ADD_BITFIELD_RW(spi_int_en, 5, 5)
1418 // The interrupt raw bit for the completement of any
1419 // operation in both the master mode and the slave mode.
1420 ADD_BITFIELD_RW(spi_trans_done, 4, 1)
1421 // The interrupt raw bit for the completement
1422 // of "write-status" operation in the slave mode.
1423 ADD_BITFIELD_RW(slv_wr_sta_done, 3, 1)
1424 // The interrupt raw bit for the completement
1425 // of "read-status" operation in the slave mode.
1426 ADD_BITFIELD_RW(slv_rd_sta_done, 2, 1)
1427 // The interrupt raw bit for the completement
1428 // of "write-buffer" operation in the slave mode.
1429 ADD_BITFIELD_RW(slv_wr_buf_done, 1, 1)
1430 // The interrupt raw bit for the completement
1431 // of "read-buffer" operation in the slave mode.
1432 ADD_BITFIELD_RW(slv_rd_buf_done, 0, 1)
1433 END_TYPE()
1434
1435 // In the slave mode, it is the length in bits for "write-status"
1436 // and "read-status" operations. The register valueshall be (bit_num-1)
1437 // Reset value: 0x00000000
1438 BEGIN_TYPE(SPI_SLAVE1_t, uint32_t)
1439 // In the slave mode, it is the length in bits for "write-status"
1440 // and "read-status" operations. The register valueshall be (bit_num-1)
1441 ADD_BITFIELD_RW(slv_status_bitlen, 27, 5)
1442 // In the slave mode, it is the length in bits for "write-buffer"
1443 // and "read-buffer" operations. The register value shallbe (bit_num-1)
1444 ADD_BITFIELD_RW(slv_buf_bitlen, 16, 9)
1445 // In the slave mode, it is the address length in bits for "read-buffer"
1446 // operation. The register value shall be(bit_num-1)
1447 ADD_BITFIELD_RW(slv_rd_addr_bitlen, 10, 6)
1448 // In the slave mode, it is the address length in bits for "write-buffer"
1449 // operation. The register value shall be(bit_num-1)
1450 ADD_BITFIELD_RW(slv_wr_addr_bitlen, 4, 6)
1451 // In the slave mode, it is the enable bit
1452 // of "dummy" phase for "write-status" operations.
1453 ADD_BITFIELD_RW(slv_wrsta_dummy_en, 3, 1)
1454 // In the slave mode, it is the enable bit of "dummy" phase
1455 // for "read-status" operations.
1456 ADD_BITFIELD_RW(slv_rdsta_dummy_en, 2, 1)
1457 // In the slave mode, it is the enable bit of "dummy" phase
1458 // for "write-buffer" operations.
1459 ADD_BITFIELD_RW(slv_wrbuf_dummy_en, 1, 1)
1460 // In the slave mode, it is the enable bit of "dummy" phase
1461 // for "read-buffer" operations.
1462 ADD_BITFIELD_RW(slv_rdbuf_dummy_en, 0, 1)
1463 END_TYPE()
1464
1465 // In the slave mode, it is the length in spi_clk cycles "dummy" phase
1466 // for "write-buffer" operations. The registervalue shall be (cycle_num-1)
1467 // Reset value: 0x00000000
1468 BEGIN_TYPE(SPI_SLAVE2_t, uint32_t)
1469 // In the slave mode, it is the length in spi_clk cycles "dummy" phase
1470 // for "write-buffer" operations. The registervalue shall be (cycle_num-1)
1471 ADD_BITFIELD_RW(slv_wrbuf_dummy_cyclelen, 24, 8)
1472 // In the slave mode, it is the length in spi_clk cycles of "dummy" phase
1473 // for "read-buffer" operations. The registervalue shall be (cycle_num-1)
1474 ADD_BITFIELD_RW(slv_rdbuf_dummy_cyclelen, 16, 8)
1475 // In the slave mode, it is the length in spi_clk cycles of "dummy" phase
1476 // for "write-status" operations. Theregister value shall be (cycle_num-1)
1477 ADD_BITFIELD_RW(slv_wrsta_dummy_cyclelen, 8, 8)
1478 // In the slave mode, it is the length in spi_clk cycles of "dummy" phase
1479 // for "read-status" operations. Theregister value shall be (cycle_num-1)
1480 ADD_BITFIELD_RW(slv_rdsta_dummy_cyclelen, 0, 8)
1481 END_TYPE()
1482
1483 // In slave mode, it is the value of "write-status" command
1484 // Reset value: 0x00000000
1485 BEGIN_TYPE(SPI_SLAVE3_t, uint32_t)
1486 // In slave mode, it is the value of "write-status" command
1487 ADD_BITFIELD_RW(slv_wrsta_cmd_value, 24, 8)
1488 // In slave mode, it is the value of "read-status" command
1489 ADD_BITFIELD_RW(slv_rdsta_cmd_value, 16, 8)
1490 // In slave mode, it is the value of "write-buffer" command
1491 ADD_BITFIELD_RW(slv_wrbuf_cmd_value, 8, 8)
1492 // In slave mode, it is the value of "read-buffer" command
1493 ADD_BITFIELD_RW(slv_rdbuf_cmd_value, 0, 8)
1494 END_TYPE()
1495
1496 // This register is for two SPI masters to share the same cs,
1497 // clock and data signals.
1498 // Reset value: 0x00000000
1499 BEGIN_TYPE(SPI_EXT3_t, uint32_t)
1500 // This register is for two SPI masters to share the same cs,
1501 // clock and data signals.
1502 ADD_BITFIELD_RW(reg_int_hold_ena, 0, 2)
1503 END_TYPE()
1504
1505 // the data inside the buffer of the SPI module, word 0
1506 // Reset value: 0x00000000
1507 BEGIN_TYPE(SPI_W0_t, uint32_t)
1508 // the data inside the buffer of the SPI module, word 0
1509 ADD_BITFIELD_RW(spi_w0, 0, 32)
1510 END_TYPE()
1511
1512 // the data inside the buffer of the SPI module, word 1
1513 // Reset value: 0x00000000
1514 BEGIN_TYPE(SPI_W1_t, uint32_t)
1515 // the data inside the buffer of the SPI module, word 1
1516 ADD_BITFIELD_RW(spi_w1, 0, 32)
1517 END_TYPE()
1518
1519 // the data inside the buffer of the SPI module, word 2
1520 // Reset value: 0x00000000
1521 BEGIN_TYPE(SPI_W2_t, uint32_t)
1522 // the data inside the buffer of the SPI module, word 2
1523 ADD_BITFIELD_RW(spi_w2, 0, 32)
1524 END_TYPE()
1525
1526 // the data inside the buffer of the SPI module, word 3
1527 // Reset value: 0x00000000
1528 BEGIN_TYPE(SPI_W3_t, uint32_t)
1529 // the data inside the buffer of the SPI module, word 3
1530 ADD_BITFIELD_RW(spi_w3, 0, 32)
1531 END_TYPE()
1532
1533 // the data inside the buffer of the SPI module, word 4
1534 // Reset value: 0x00000000
1535 BEGIN_TYPE(SPI_W4_t, uint32_t)
1536 // the data inside the buffer of the SPI module, word 4
1537 ADD_BITFIELD_RW(spi_w4, 0, 32)
1538 END_TYPE()
1539
1540 // the data inside the buffer of the SPI module, word 5
1541 // Reset value: 0x00000000
1542 BEGIN_TYPE(SPI_W5_t, uint32_t)
1543 // the data inside the buffer of the SPI module, word 5
1544 ADD_BITFIELD_RW(spi_w5, 0, 32)
1545 END_TYPE()
1546
1547 // the data inside the buffer of the SPI module, word 6
1548 // Reset value: 0x00000000
1549 BEGIN_TYPE(SPI_W6_t, uint32_t)
1550 // the data inside the buffer of the SPI module, word 6
1551 ADD_BITFIELD_RW(spi_w6, 0, 32)
1552 END_TYPE()
1553
1554 // the data inside the buffer of the SPI module, word 7
1555 // Reset value: 0x00000000
1556 BEGIN_TYPE(SPI_W7_t, uint32_t)
1557 // the data inside the buffer of the SPI module, word 7
1558 ADD_BITFIELD_RW(spi_w7, 0, 32)
1559 END_TYPE()
1560
1561 // the data inside the buffer of the SPI module, word 8
1562 // Reset value: 0x00000000
1563 BEGIN_TYPE(SPI_W8_t, uint32_t)
1564 // the data inside the buffer of the SPI module, word 8
1565 ADD_BITFIELD_RW(spi_w8, 0, 32)
1566 END_TYPE()
1567
1568 // the data inside the buffer of the SPI module, word 9
1569 // Reset value: 0x00000000
1570 BEGIN_TYPE(SPI_W9_t, uint32_t)
1571 // the data inside the buffer of the SPI module, word 9
1572 ADD_BITFIELD_RW(spi_w9, 0, 32)
1573 END_TYPE()
1574
1575 // the data inside the buffer of the SPI module, word 10
1576 // Reset value: 0x00000000
1577 BEGIN_TYPE(SPI_W10_t, uint32_t)
1578 // the data inside the buffer of the SPI module, word 10
1579 ADD_BITFIELD_RW(spi_w10, 0, 32)
1580 END_TYPE()
1581
1582 // the data inside the buffer of the SPI module, word 11
1583 // Reset value: 0x00000000
1584 BEGIN_TYPE(SPI_W11_t, uint32_t)
1585 // the data inside the buffer of the SPI module, word 11
1586 ADD_BITFIELD_RW(spi_w11, 0, 32)
1587 END_TYPE()
1588
1589 // the data inside the buffer of the SPI module, word 12
1590 // Reset value: 0x00000000
1591 BEGIN_TYPE(SPI_W12_t, uint32_t)
1592 // the data inside the buffer of the SPI module, word 12
1593 ADD_BITFIELD_RW(spi_w12, 0, 32)
1594 END_TYPE()
1595
1596 // the data inside the buffer of the SPI module, word 13
1597 // Reset value: 0x00000000
1598 BEGIN_TYPE(SPI_W13_t, uint32_t)
1599 // the data inside the buffer of the SPI module, word 13
1600 ADD_BITFIELD_RW(spi_w13, 0, 32)
1601 END_TYPE()
1602
1603 // the data inside the buffer of the SPI module, word 14
1604 // Reset value: 0x00000000
1605 BEGIN_TYPE(SPI_W14_t, uint32_t)
1606 // the data inside the buffer of the SPI module, word 14
1607 ADD_BITFIELD_RW(spi_w14, 0, 32)
1608 END_TYPE()
1609
1610 // the data inside the buffer of the SPI module, word 15
1611 // Reset value: 0x00000000
1612 BEGIN_TYPE(SPI_W15_t, uint32_t)
1613 // the data inside the buffer of the SPI module, word 15
1614 ADD_BITFIELD_RW(spi_w15, 0, 32)
1615 END_TYPE()
1616
1617 struct SPI1_t {
1618 SPI_CMD_t SPI_CMD;
1619 SPI_ADDR_t SPI_ADDR;
1620 SPI_CTRL_t SPI_CTRL;
1621 uint32_t reserved0;
1622 SPI_RD_STATUS_t SPI_RD_STATUS;
1623 SPI_CTRL2_t SPI_CTRL2;
1624 SPI_CLOCK_t SPI_CLOCK;
1625 SPI_USER_t SPI_USER;
1626 SPI_USER1_t SPI_USER1;
1627 SPI_USER2_t SPI_USER2;
1628 SPI_WR_STATUS_t SPI_WR_STATUS;
1629 SPI_PIN_t SPI_PIN;
1630 SPI_SLAVE_t SPI_SLAVE;
1631 SPI_SLAVE1_t SPI_SLAVE1;
1632 SPI_SLAVE2_t SPI_SLAVE2;
1633 SPI_SLAVE3_t SPI_SLAVE3;
1634 SPI_W0_t SPI_W0;
1635 SPI_W1_t SPI_W1;
1636 SPI_W2_t SPI_W2;
1637 SPI_W3_t SPI_W3;
1638 SPI_W4_t SPI_W4;
1639 SPI_W5_t SPI_W5;
1640 SPI_W6_t SPI_W6;
1641 SPI_W7_t SPI_W7;
1642 SPI_W8_t SPI_W8;
1643 SPI_W9_t SPI_W9;
1644 SPI_W10_t SPI_W10;
1645 SPI_W11_t SPI_W11;
1646 SPI_W12_t SPI_W12;
1647 SPI_W13_t SPI_W13;
1648 SPI_W14_t SPI_W14;
1649 SPI_W15_t SPI_W15;
1650 uint32_t reserved1[31];
1651 SPI_EXT3_t SPI_EXT3;
1652 };
1653
1654 static SPI1_t & SPI1 = (*(SPI1_t *)0x60000100);
1655
1656} // _SPI1_
1657
1658namespace _TIMER_ {
1659
1660 // the load value into the counter
1661 // Reset value: 0x00000000
1662 BEGIN_TYPE(FRC1_LOAD_t, uint32_t)
1663 // the load value into the counter
1664 ADD_BITFIELD_RW(LOAD, 0, 23)
1665 END_TYPE()
1666
1667 // the current value of the counter. It is a decreasingcounter.
1668 // Reset value: 0x00000000
1669 BEGIN_TYPE(FRC1_COUNT_t, uint32_t)
1670 // The current value of the counter. It is a decreasingcounter.
1671 ADD_BITFIELD_RO(COUNT, 0, 23)
1672 END_TYPE()
1673
1674 // FRC1_CTRL
1675 // Reset value: 0x00000000
1676 BEGIN_TYPE(FRC1_CTRL_t, uint32_t)
1677 // Interrupt type, 0:edge, 1:level
1678 ADD_BITFIELD_RW(INT_TYPE, 0, 1)
1679 // Timer prescaler divider
1680 ADD_BITFIELD_RW(DIVIDER, 2, 2)
1681 // Automatically reload, when the counter is equal to zero
1682 ADD_BITFIELD_RW(RELOAD, 6, 1)
1683 // Timer enable
1684 ADD_BITFIELD_RW(ENABLE, 7, 1)
1685 // The status of the interrupt, when the count is deceased to zero
1686 ADD_BITFIELD_RO(INT_STATUS, 8, 1)
1687 END_TYPE()
1688
1689 static const uint32_t FRC1_CTRL_INT_TYPE__EDGE = 0;
1690 static const uint32_t FRC1_CTRL_INT_TYPE__LEVEL = 1;
1691 static const uint32_t FRC1_CTRL_DIVIDER__1 = 0;
1692 static const uint32_t FRC1_CTRL_DIVIDER__16 = 1;
1693 static const uint32_t FRC1_CTRL_DIVIDER__256 = 2;
1694
1695 // FRC1_INT
1696 // Reset value: 0x00000000
1697 BEGIN_TYPE(FRC1_INT_t, uint32_t)
1698 // write to clear the status of the interrupt, if theinterrupt type is "level"
1699 ADD_BITFIELD_RW(mask, 0, 1)
1700 END_TYPE()
1701
1702 // the load value into the counter
1703 // Reset value: 0x00000000
1704 BEGIN_TYPE(FRC2_LOAD_t, uint32_t)
1705 // the load value into the counter
1706 ADD_BITFIELD_RW(LOAD, 0, 32)
1707 END_TYPE()
1708
1709 // the current value of the counter. It is a increasingcounter.
1710 // Reset value: 0x00000000
1711 BEGIN_TYPE(FRC2_COUNT_t, uint32_t)
1712 // The current value of the counter. It is a increasingcounter.
1713 ADD_BITFIELD_RO(COUNT, 0, 32)
1714 END_TYPE()
1715
1716 // FRC2_CTRL
1717 // Reset value: 0x00000000
1718 BEGIN_TYPE(FRC2_CTRL_t, uint32_t)
1719 // Interrupt type, 0:edge, 1:level
1720 ADD_BITFIELD_RW(INT_TYPE, 0, 1)
1721 // Timer prescaler divider
1722 ADD_BITFIELD_RW(DIVIDER, 2, 2)
1723 // Automatically reload, when the counter is equal to zero
1724 ADD_BITFIELD_RW(RELOAD, 6, 1)
1725 // Timer enable
1726 ADD_BITFIELD_RW(ENABLE, 7, 1)
1727 // The status of the interrupt, when the count is deceased to zero
1728 ADD_BITFIELD_RO(INT_STATUS, 8, 1)
1729 END_TYPE()
1730
1731 static const uint32_t FRC2_CTRL_INT_TYPE__EDGE = 0;
1732 static const uint32_t FRC2_CTRL_INT_TYPE__LEVEL = 1;
1733 static const uint32_t FRC2_CTRL_DIVIDER__1 = 0;
1734 static const uint32_t FRC2_CTRL_DIVIDER__16 = 1;
1735 static const uint32_t FRC2_CTRL_DIVIDER__256 = 2;
1736
1737 // FRC2_INT
1738 // Reset value: 0x00000000
1739 BEGIN_TYPE(FRC2_INT_t, uint32_t)
1740 // write to clear the status of the interrupt, if theinterrupt type is "level"
1741 ADD_BITFIELD_RW(mask, 0, 1)
1742 END_TYPE()
1743
1744 // the alarm value for the counter
1745 // Reset value: 0x00000000
1746 BEGIN_TYPE(FRC2_ALARM_t, uint32_t)
1747 // the alarm value for the counter
1748 ADD_BITFIELD_RW(frc2_alarm, 0, 32)
1749 END_TYPE()
1750
1751 struct TIMER_t {
1752 FRC1_LOAD_t FRC1_LOAD;
1753 FRC1_COUNT_t FRC1_COUNT;
1754 FRC1_CTRL_t FRC1_CTRL;
1755 FRC1_INT_t FRC1_INT;
1756 uint32_t reserved0[4];
1757 FRC2_LOAD_t FRC2_LOAD;
1758 FRC2_COUNT_t FRC2_COUNT;
1759 FRC2_CTRL_t FRC2_CTRL;
1760 FRC2_INT_t FRC2_INT;
1761 FRC2_ALARM_t FRC2_ALARM;
1762 };
1763
1764 static TIMER_t & TIMER = (*(TIMER_t *)0x60000600);
1765
1766} // _TIMER_
1767
1768namespace _UART0_ {
1769
1770 // UART FIFO,length 128
1771 // Reset value: 0x00000000
1772 BEGIN_TYPE(UART_FIFO_t, uint32_t)
1773 // R/W share the same address
1774 ADD_BITFIELD_RO(rxfifo_rd_byte, 0, 8)
1775 END_TYPE()
1776
1777 // UART INTERRUPT RAW STATE
1778 // Reset value: 0x00000000
1779 BEGIN_TYPE(UART_INT_RAW_t, uint32_t)
1780 // The interrupt raw bit for Rx time-out interrupt
1781 // (depends on the UART_RX_TOUT_THRHD)
1782 ADD_BITFIELD_RO(rxfifo_tout_int_raw, 8, 1)
1783 // The interrupt raw bit for Rx byte start error
1784 ADD_BITFIELD_RO(brk_det_int_raw, 7, 1)
1785 // The interrupt raw bit for CTS changing level
1786 ADD_BITFIELD_RO(cts_chg_int_raw, 6, 1)
1787 // The interrupt raw bit for DSR changing level
1788 ADD_BITFIELD_RO(dsr_chg_int_raw, 5, 1)
1789 // The interrupt raw bit for rx fifo overflow
1790 ADD_BITFIELD_RO(rxfifo_ovf_int_raw, 4, 1)
1791 // The interrupt raw bit for other rx error
1792 ADD_BITFIELD_RO(frm_err_int_raw, 3, 1)
1793 // The interrupt raw bit for parity check error
1794 ADD_BITFIELD_RO(parity_err_int_raw, 2, 1)
1795 // The interrupt raw bit for tx fifo empty interrupt
1796 // (depends on UART_TXFIFO_EMPTY_THRHD bits)
1797 ADD_BITFIELD_RO(txfifo_empty_int_raw, 1, 1)
1798 // The interrupt raw bit for rx fifo full interrupt
1799 // (depends on UART_RXFIFO_FULL_THRHD bits)
1800 ADD_BITFIELD_RO(rxfifo_full_int_raw, 0, 1)
1801 END_TYPE()
1802
1803 // UART INTERRUPT STATEREGISTER UART_INT_RAW and UART_INT_ENA
1804 // Reset value: 0x00000000
1805 BEGIN_TYPE(UART_INT_ST_t, uint32_t)
1806 // The interrupt state bit for Rx time-out event
1807 ADD_BITFIELD_RO(rxfifo_tout_int_st, 8, 1)
1808 // The interrupt state bit for rx byte start error
1809 ADD_BITFIELD_RO(brk_det_int_st, 7, 1)
1810 // The interrupt state bit for CTS changing level
1811 ADD_BITFIELD_RO(cts_chg_int_st, 6, 1)
1812 // The interrupt state bit for DSR changing level
1813 ADD_BITFIELD_RO(dsr_chg_int_st, 5, 1)
1814 // The interrupt state bit for RX fifo overflow
1815 ADD_BITFIELD_RO(rxfifo_ovf_int_st, 4, 1)
1816 // The interrupt state for other rx error
1817 ADD_BITFIELD_RO(frm_err_int_st, 3, 1)
1818 // The interrupt state bit for rx parity error
1819 ADD_BITFIELD_RO(parity_err_int_st, 2, 1)
1820 // The interrupt state bit for TX fifo empty
1821 ADD_BITFIELD_RO(txfifo_empty_int_st, 1, 1)
1822 // The interrupt state bit for RX fifo full event
1823 ADD_BITFIELD_RO(rxfifo_full_int_st, 0, 1)
1824 END_TYPE()
1825
1826 // UART INTERRUPT ENABLE REGISTER
1827 // Reset value: 0x00000000
1828 BEGIN_TYPE(UART_INT_ENA_t, uint32_t)
1829 // The interrupt enable bit for rx time-out interrupt
1830 ADD_BITFIELD_RW(rxfifo_tout_int_ena, 8, 1)
1831 // The interrupt enable bit for rx byte start error
1832 ADD_BITFIELD_RW(brk_det_int_ena, 7, 1)
1833 // The interrupt enable bit for CTS changing level
1834 ADD_BITFIELD_RW(cts_chg_int_ena, 6, 1)
1835 // The interrupt enable bit for DSR changing level
1836 ADD_BITFIELD_RW(dsr_chg_int_ena, 5, 1)
1837 // The interrupt enable bit for rx fifo overflow
1838 ADD_BITFIELD_RW(rxfifo_ovf_int_ena, 4, 1)
1839 // The interrupt enable bit for other rx error
1840 ADD_BITFIELD_RW(frm_err_int_ena, 3, 1)
1841 // The interrupt enable bit for parity error
1842 ADD_BITFIELD_RW(parity_err_int_ena, 2, 1)
1843 // The interrupt enable bit for tx fifo empty event
1844 ADD_BITFIELD_RW(txfifo_empty_int_ena, 1, 1)
1845 // The interrupt enable bit for rx fifo full event
1846 ADD_BITFIELD_RW(rxfifo_full_int_ena, 0, 1)
1847 END_TYPE()
1848
1849 // UART INTERRUPT CLEAR REGISTER
1850 // Reset value: 0x00000000
1851 BEGIN_TYPE(UART_INT_CLR_t, uint32_t)
1852 // Set this bit to clear the rx time-out interrupt
1853 ADD_BITFIELD_WO(rxfifo_tout_int_clr, 8, 1)
1854 // Set this bit to clear the rx byte start interrupt
1855 ADD_BITFIELD_WO(brk_det_int_clr, 7, 1)
1856 // Set this bit to clear the CTS changing interrupt
1857 ADD_BITFIELD_WO(cts_chg_int_clr, 6, 1)
1858 // Set this bit to clear the DSR changing interrupt
1859 ADD_BITFIELD_WO(dsr_chg_int_clr, 5, 1)
1860 // Set this bit to clear the rx fifo over-flow interrupt
1861 ADD_BITFIELD_WO(rxfifo_ovf_int_clr, 4, 1)
1862 // Set this bit to clear other rx error interrupt
1863 ADD_BITFIELD_WO(frm_err_int_clr, 3, 1)
1864 // Set this bit to clear the parity error interrupt
1865 ADD_BITFIELD_WO(parity_err_int_clr, 2, 1)
1866 // Set this bit to clear the tx fifo empty interrupt
1867 ADD_BITFIELD_WO(txfifo_empty_int_clr, 1, 1)
1868 // Set this bit to clear the rx fifo full interrupt
1869 ADD_BITFIELD_WO(rxfifo_full_int_clr, 0, 1)
1870 END_TYPE()
1871
1872 // UART CLK DIV REGISTER
1873 // Reset value: 0x00000000
1874 BEGIN_TYPE(UART_CLKDIV_t, uint32_t)
1875 // BAUDRATE = UART_CLK_FREQ / UART_CLKDIV
1876 ADD_BITFIELD_RW(uart_clkdiv, 0, 20)
1877 END_TYPE()
1878
1879 // UART BAUDRATE DETECT REGISTER
1880 // Reset value: 0x00000000
1881 BEGIN_TYPE(UART_AUTOBAUD_t, uint32_t)
1882 ADD_BITFIELD_RW(glitch_filt, 8, 8)
1883 // Set this bit to enable baudrate detect
1884 ADD_BITFIELD_RW(autobaud_en, 0, 1)
1885 END_TYPE()
1886
1887 // UART STATUS REGISTER
1888 // Reset value: 0x00000000
1889 BEGIN_TYPE(UART_STATUS_t, uint32_t)
1890 // The level of the uart txd pin
1891 ADD_BITFIELD_RO(txd, 31, 1)
1892 // The level of uart rts pin
1893 ADD_BITFIELD_RO(rtsn, 30, 1)
1894 // The level of uart dtr pin
1895 ADD_BITFIELD_RO(dtrn, 29, 1)
1896 // Number of data in UART TX fifo
1897 ADD_BITFIELD_RO(txfifo_cnt, 16, 8)
1898 // The level of uart rxd pin
1899 ADD_BITFIELD_RO(rxd, 15, 1)
1900 // The level of uart cts pin
1901 ADD_BITFIELD_RO(ctsn, 14, 1)
1902 // The level of uart dsr pin
1903 ADD_BITFIELD_RO(dsrn, 13, 1)
1904 // Number of data in uart rx fifo
1905 ADD_BITFIELD_RO(rxfifo_cnt, 0, 8)
1906 END_TYPE()
1907
1908 // UART CONFIG0(UART0 and UART1)
1909 // Reset value: 0x00000000
1910 BEGIN_TYPE(UART_CONF0_t, uint32_t)
1911 // Set this bit to inverse uart dtr level
1912 ADD_BITFIELD_RW(uart_dtr_inv, 24, 1)
1913 // Set this bit to inverse uart rts level
1914 ADD_BITFIELD_RW(uart_rts_inv, 23, 1)
1915 // Set this bit to inverse uart txd level
1916 ADD_BITFIELD_RW(uart_txd_inv, 22, 1)
1917 // Set this bit to inverse uart dsr level
1918 ADD_BITFIELD_RW(uart_dsr_inv, 21, 1)
1919 // Set this bit to inverse uart cts level
1920 ADD_BITFIELD_RW(uart_cts_inv, 20, 1)
1921 // Set this bit to inverse uart rxd level
1922 ADD_BITFIELD_RW(uart_rxd_inv, 19, 1)
1923 // Set this bit to reset uart tx fifo
1924 ADD_BITFIELD_RW(txfifo_rst, 18, 1)
1925 // Set this bit to reset uart rx fifo
1926 ADD_BITFIELD_RW(rxfifo_rst, 17, 1)
1927 // Set this bit to enable uart tx hardware flow control
1928 ADD_BITFIELD_RW(tx_flow_en, 15, 1)
1929 // Set this bit to enable uart loopback test mode
1930 ADD_BITFIELD_RW(uart_loopback, 14, 1)
1931 // RESERVED, DO NOT CHANGE THIS BIT
1932 ADD_BITFIELD_RW(txd_brk, 8, 1)
1933 // sw dtr
1934 ADD_BITFIELD_RW(sw_dtr, 7, 1)
1935 // sw rts
1936 ADD_BITFIELD_RW(sw_rts, 6, 1)
1937 // Set stop bit: 1:1bit 2:1.5bits 3:2bits
1938 ADD_BITFIELD_RW(stop_bit_num, 4, 2)
1939 // Set bit num: 0:5bits 1:6bits 2:7bits 3:8bits
1940 ADD_BITFIELD_RW(bit_num, 2, 2)
1941 // Set this bit to enable uart parity check
1942 ADD_BITFIELD_RW(parity_en, 1, 1)
1943 // Set parity check: 0:even 1:odd, UART CONFIG1
1944 ADD_BITFIELD_RW(parity, 0, 1)
1945 END_TYPE()
1946
1947 // Set this bit to enable rx time-out function
1948 // Reset value: 0x00000000
1949 BEGIN_TYPE(UART_CONF1_t, uint32_t)
1950 // Set this bit to enable rx time-out function
1951 ADD_BITFIELD_RW(rx_tout_en, 31, 1)
1952 // Config bits for rx time-out threshold,uint: byte,0-127
1953 ADD_BITFIELD_RW(rx_tout_thrhd, 24, 7)
1954 // Set this bit to enable rx hardware flow control
1955 ADD_BITFIELD_RW(rx_flow_en, 23, 1)
1956 // The config bits for rx flow control threshold,0-127
1957 ADD_BITFIELD_RW(rx_flow_thrhd, 16, 7)
1958 // The config bits for tx fifo empty threshold,0-127
1959 ADD_BITFIELD_RW(txfifo_empty_thrhd, 8, 7)
1960 // The config bits for rx fifo full threshold,0-127
1961 ADD_BITFIELD_RW(rxfifo_full_thrhd, 0, 7)
1962 END_TYPE()
1963
1964 // UART_LOWPULSE
1965 // Reset value: 0x00000000
1966 BEGIN_TYPE(UART_LOWPULSE_t, uint32_t)
1967 // used in baudrate detect
1968 ADD_BITFIELD_RO(lowpulse_min_cnt, 0, 20)
1969 END_TYPE()
1970
1971 // UART_HIGHPULSE
1972 // Reset value: 0x00000000
1973 BEGIN_TYPE(UART_HIGHPULSE_t, uint32_t)
1974 // used in baudrate detect
1975 ADD_BITFIELD_RO(highpulse_min_cnt, 0, 20)
1976 END_TYPE()
1977
1978 // UART_RXD_CNT
1979 // Reset value: 0x00000000
1980 BEGIN_TYPE(UART_RXD_CNT_t, uint32_t)
1981 // used in baudrate detect
1982 ADD_BITFIELD_RO(rxd_edge_cnt, 0, 10)
1983 END_TYPE()
1984
1985 // UART HW INFO
1986 // Reset value: 0x00000000
1987 BEGIN_TYPE(UART_DATE_t, uint32_t)
1988 // UART HW INFO
1989 ADD_BITFIELD_RW(uart_date, 0, 32)
1990 END_TYPE()
1991
1992 // UART_ID
1993 // Reset value: 0x00000000
1994 BEGIN_TYPE(UART_ID_t, uint32_t)
1995 ADD_BITFIELD_RW(uart_id, 0, 32)
1996 END_TYPE()
1997
1998 struct UART0_t {
1999 UART_FIFO_t UART_FIFO;
2000 UART_INT_RAW_t UART_INT_RAW;
2001 UART_INT_ST_t UART_INT_ST;
2002 UART_INT_ENA_t UART_INT_ENA;
2003 UART_INT_CLR_t UART_INT_CLR;
2004 UART_CLKDIV_t UART_CLKDIV;
2005 UART_AUTOBAUD_t UART_AUTOBAUD;
2006 UART_STATUS_t UART_STATUS;
2007 UART_CONF0_t UART_CONF0;
2008 UART_CONF1_t UART_CONF1;
2009 UART_LOWPULSE_t UART_LOWPULSE;
2010 UART_HIGHPULSE_t UART_HIGHPULSE;
2011 UART_RXD_CNT_t UART_RXD_CNT;
2012 uint32_t reserved0[17];
2013 UART_DATE_t UART_DATE;
2014 UART_ID_t UART_ID;
2015 };
2016
2017 static UART0_t & UART0 = (*(UART0_t *)0x60000000);
2018
2019} // _UART0_
2020
2021namespace _UART1_ {
2022
2023 // UART FIFO,length 128
2024 // Reset value: 0x00000000
2025 BEGIN_TYPE(UART_FIFO_t, uint32_t)
2026 // R/W share the same address
2027 ADD_BITFIELD_RO(rxfifo_rd_byte, 0, 8)
2028 END_TYPE()
2029
2030 // UART INTERRUPT RAW STATE
2031 // Reset value: 0x00000000
2032 BEGIN_TYPE(UART_INT_RAW_t, uint32_t)
2033 // The interrupt raw bit for Rx time-out interrupt
2034 // (depends on the UART_RX_TOUT_THRHD)
2035 ADD_BITFIELD_RO(rxfifo_tout_int_raw, 8, 1)
2036 // The interrupt raw bit for Rx byte start error
2037 ADD_BITFIELD_RO(brk_det_int_raw, 7, 1)
2038 // The interrupt raw bit for CTS changing level
2039 ADD_BITFIELD_RO(cts_chg_int_raw, 6, 1)
2040 // The interrupt raw bit for DSR changing level
2041 ADD_BITFIELD_RO(dsr_chg_int_raw, 5, 1)
2042 // The interrupt raw bit for rx fifo overflow
2043 ADD_BITFIELD_RO(rxfifo_ovf_int_raw, 4, 1)
2044 // The interrupt raw bit for other rx error
2045 ADD_BITFIELD_RO(frm_err_int_raw, 3, 1)
2046 // The interrupt raw bit for parity check error
2047 ADD_BITFIELD_RO(parity_err_int_raw, 2, 1)
2048 // The interrupt raw bit for tx fifo empty interrupt(depands onUART_TXFIFO_EMPTY_THRHD bits)
2049 ADD_BITFIELD_RO(txfifo_empty_int_raw, 1, 1)
2050 // The interrupt raw bit for rx fifo full interrupt
2051 // (depends on UART_RXFIFO_FULL_THRHD bits)
2052 ADD_BITFIELD_RO(rxfifo_full_int_raw, 0, 1)
2053 END_TYPE()
2054
2055 // UART INTERRUPT STATEREGISTERUART_INT_RAW and UART_INT_ENA
2056 // Reset value: 0x00000000
2057 BEGIN_TYPE(UART_INT_ST_t, uint32_t)
2058 // The interrupt state bit for Rx time-out event
2059 ADD_BITFIELD_RO(rxfifo_tout_int_st, 8, 1)
2060 // The interrupt state bit for rx byte start error
2061 ADD_BITFIELD_RO(brk_det_int_st, 7, 1)
2062 // The interrupt state bit for CTS changing level
2063 ADD_BITFIELD_RO(cts_chg_int_st, 6, 1)
2064 // The interrupt state bit for DSR changing level
2065 ADD_BITFIELD_RO(dsr_chg_int_st, 5, 1)
2066 // The interrupt state bit for RX fifo overflow
2067 ADD_BITFIELD_RO(rxfifo_ovf_int_st, 4, 1)
2068 // The interrupt state for other rx error
2069 ADD_BITFIELD_RO(frm_err_int_st, 3, 1)
2070 // The interrupt state bit for rx parity error
2071 ADD_BITFIELD_RO(parity_err_int_st, 2, 1)
2072 // The interrupt state bit for TX fifo empty
2073 ADD_BITFIELD_RO(txfifo_empty_int_st, 1, 1)
2074 // The interrupt state bit for RX fifo full event
2075 ADD_BITFIELD_RO(rxfifo_full_int_st, 0, 1)
2076 END_TYPE()
2077
2078 // UART INTERRUPT ENABLE REGISTER
2079 // Reset value: 0x00000000
2080 BEGIN_TYPE(UART_INT_ENA_t, uint32_t)
2081 // The interrupt enable bit for rx time-out interrupt
2082 ADD_BITFIELD_RW(rxfifo_tout_int_ena, 8, 1)
2083 // The interrupt enable bit for rx byte start error
2084 ADD_BITFIELD_RW(brk_det_int_ena, 7, 1)
2085 // The interrupt enable bit for CTS changing level
2086 ADD_BITFIELD_RW(cts_chg_int_ena, 6, 1)
2087 // The interrupt enable bit for DSR changing level
2088 ADD_BITFIELD_RW(dsr_chg_int_ena, 5, 1)
2089 // The interrupt enable bit for rx fifo overflow
2090 ADD_BITFIELD_RW(rxfifo_ovf_int_ena, 4, 1)
2091 // The interrupt enable bit for other rx error
2092 ADD_BITFIELD_RW(frm_err_int_ena, 3, 1)
2093 // The interrupt enable bit for parity error
2094 ADD_BITFIELD_RW(parity_err_int_ena, 2, 1)
2095 // The interrupt enable bit for tx fifo empty event
2096 ADD_BITFIELD_RW(txfifo_empty_int_ena, 1, 1)
2097 // The interrupt enable bit for rx fifo full event
2098 ADD_BITFIELD_RW(rxfifo_full_int_ena, 0, 1)
2099 END_TYPE()
2100
2101 // UART INTERRUPT CLEAR REGISTER
2102 // Reset value: 0x00000000
2103 BEGIN_TYPE(UART_INT_CLR_t, uint32_t)
2104 // Set this bit to clear the rx time-out interrupt
2105 ADD_BITFIELD_WO(rxfifo_tout_int_clr, 8, 1)
2106 // Set this bit to clear the rx byte start interrupt
2107 ADD_BITFIELD_WO(brk_det_int_clr, 7, 1)
2108 // Set this bit to clear the CTS changing interrupt
2109 ADD_BITFIELD_WO(cts_chg_int_clr, 6, 1)
2110 // Set this bit to clear the DSR changing interrupt
2111 ADD_BITFIELD_WO(dsr_chg_int_clr, 5, 1)
2112 // Set this bit to clear the rx fifo over-flow interrupt
2113 ADD_BITFIELD_WO(rxfifo_ovf_int_clr, 4, 1)
2114 // Set this bit to clear other rx error interrupt
2115 ADD_BITFIELD_WO(frm_err_int_clr, 3, 1)
2116 // Set this bit to clear the parity error interrupt
2117 ADD_BITFIELD_WO(parity_err_int_clr, 2, 1)
2118 // Set this bit to clear the tx fifo empty interrupt
2119 ADD_BITFIELD_WO(txfifo_empty_int_clr, 1, 1)
2120 // Set this bit to clear the rx fifo full interrupt
2121 ADD_BITFIELD_WO(rxfifo_full_int_clr, 0, 1)
2122 END_TYPE()
2123
2124 // UART CLK DIV REGISTER
2125 // Reset value: 0x00000000
2126 BEGIN_TYPE(UART_CLKDIV_t, uint32_t)
2127 // BAUDRATE = UART_CLK_FREQ / UART_CLKDIV
2128 ADD_BITFIELD_RW(uart_clkdiv, 0, 20)
2129 END_TYPE()
2130
2131 // UART BAUDRATE DETECT REGISTER
2132 // Reset value: 0x00000000
2133 BEGIN_TYPE(UART_AUTOBAUD_t, uint32_t)
2134 ADD_BITFIELD_RW(glitch_filt, 8, 8)
2135 // Set this bit to enable baudrate detect
2136 ADD_BITFIELD_RW(autobaud_en, 0, 1)
2137 END_TYPE()
2138
2139 // UART STATUS REGISTER
2140 // Reset value: 0x00000000
2141 BEGIN_TYPE(UART_STATUS_t, uint32_t)
2142 // The level of the uart txd pin
2143 ADD_BITFIELD_RO(txd, 31, 1)
2144 // The level of uart rts pin
2145 ADD_BITFIELD_RO(rtsn, 30, 1)
2146 // The level of uart dtr pin
2147 ADD_BITFIELD_RO(dtrn, 29, 1)
2148 // Number of data in UART TX fifo
2149 ADD_BITFIELD_RO(txfifo_cnt, 16, 8)
2150 // The level of uart rxd pin
2151 ADD_BITFIELD_RO(rxd, 15, 1)
2152 // The level of uart cts pin
2153 ADD_BITFIELD_RO(ctsn, 14, 1)
2154 // The level of uart dsr pin
2155 ADD_BITFIELD_RO(dsrn, 13, 1)
2156 // Number of data in uart rx fifo
2157 ADD_BITFIELD_RO(rxfifo_cnt, 0, 8)
2158 END_TYPE()
2159
2160 // UART CONFIG0(UART0 and UART1)
2161 // Reset value: 0x00000000
2162 BEGIN_TYPE(UART_CONF0_t, uint32_t)
2163 // Set this bit to inverse uart dtr level
2164 ADD_BITFIELD_RW(uart_dtr_inv, 24, 1)
2165 // Set this bit to inverse uart rts level
2166 ADD_BITFIELD_RW(uart_rts_inv, 23, 1)
2167 // Set this bit to inverse uart txd level
2168 ADD_BITFIELD_RW(uart_txd_inv, 22, 1)
2169 // Set this bit to inverse uart dsr level
2170 ADD_BITFIELD_RW(uart_dsr_inv, 21, 1)
2171 // Set this bit to inverse uart cts level
2172 ADD_BITFIELD_RW(uart_cts_inv, 20, 1)
2173 // Set this bit to inverse uart rxd level
2174 ADD_BITFIELD_RW(uart_rxd_inv, 19, 1)
2175 // Set this bit to reset uart tx fifo
2176 ADD_BITFIELD_RW(txfifo_rst, 18, 1)
2177 // Set this bit to reset uart rx fifo
2178 ADD_BITFIELD_RW(rxfifo_rst, 17, 1)
2179 // Set this bit to enable uart tx hardware flow control
2180 ADD_BITFIELD_RW(tx_flow_en, 15, 1)
2181 // Set this bit to enable uart loopback test mode
2182 ADD_BITFIELD_RW(uart_loopback, 14, 1)
2183 // RESERVED, DO NOT CHANGE THIS BIT
2184 ADD_BITFIELD_RW(txd_brk, 8, 1)
2185 // sw dtr
2186 ADD_BITFIELD_RW(sw_dtr, 7, 1)
2187 // sw rts
2188 ADD_BITFIELD_RW(sw_rts, 6, 1)
2189 // Set stop bit: 1:1bit 2:1.5bits 3:2bits
2190 ADD_BITFIELD_RW(stop_bit_num, 4, 2)
2191 // Set bit num: 0:5bits 1:6bits 2:7bits 3:8bits
2192 ADD_BITFIELD_RW(bit_num, 2, 2)
2193 // Set this bit to enable uart parity check
2194 ADD_BITFIELD_RW(parity_en, 1, 1)
2195 // Set parity check: 0:even 1:odd, UART CONFIG1
2196 ADD_BITFIELD_RW(parity, 0, 1)
2197 END_TYPE()
2198
2199 // Set this bit to enable rx time-out function
2200 // Reset value: 0x00000000
2201 BEGIN_TYPE(UART_CONF1_t, uint32_t)
2202 // Set this bit to enable rx time-out function
2203 ADD_BITFIELD_RW(rx_tout_en, 31, 1)
2204 // Config bits for rx time-out threshold,uint: byte,0-127
2205 ADD_BITFIELD_RW(rx_tout_thrhd, 24, 7)
2206 // Set this bit to enable rx hardware flow control
2207 ADD_BITFIELD_RW(rx_flow_en, 23, 1)
2208 // The config bits for rx flow control threshold,0-127
2209 ADD_BITFIELD_RW(rx_flow_thrhd, 16, 7)
2210 // The config bits for tx fifo empty threshold,0-127
2211 ADD_BITFIELD_RW(txfifo_empty_thrhd, 8, 7)
2212 // The config bits for rx fifo full threshold,0-127
2213 ADD_BITFIELD_RW(rxfifo_full_thrhd, 0, 7)
2214 END_TYPE()
2215
2216 // UART_LOWPULSE
2217 // Reset value: 0x00000000
2218 BEGIN_TYPE(UART_LOWPULSE_t, uint32_t)
2219 // used in baudrate detect
2220 ADD_BITFIELD_RO(lowpulse_min_cnt, 0, 20)
2221 END_TYPE()
2222
2223 // UART_HIGHPULSE
2224 // Reset value: 0x00000000
2225 BEGIN_TYPE(UART_HIGHPULSE_t, uint32_t)
2226 // used in baudrate detect
2227 ADD_BITFIELD_RO(highpulse_min_cnt, 0, 20)
2228 END_TYPE()
2229
2230 // UART_RXD_CNT
2231 // Reset value: 0x00000000
2232 BEGIN_TYPE(UART_RXD_CNT_t, uint32_t)
2233 // used in baudrate detect
2234 ADD_BITFIELD_RO(rxd_edge_cnt, 0, 10)
2235 END_TYPE()
2236
2237 // UART HW INFO
2238 // Reset value: 0x00000000
2239 BEGIN_TYPE(UART_DATE_t, uint32_t)
2240 // UART HW INFO
2241 ADD_BITFIELD_RW(uart_date, 0, 32)
2242 END_TYPE()
2243
2244 // UART_ID
2245 // Reset value: 0x00000000
2246 BEGIN_TYPE(UART_ID_t, uint32_t)
2247 ADD_BITFIELD_RW(uart_id, 0, 32)
2248 END_TYPE()
2249
2250 struct UART1_t {
2251 UART_FIFO_t UART_FIFO;
2252 UART_INT_RAW_t UART_INT_RAW;
2253 UART_INT_ST_t UART_INT_ST;
2254 UART_INT_ENA_t UART_INT_ENA;
2255 UART_INT_CLR_t UART_INT_CLR;
2256 UART_CLKDIV_t UART_CLKDIV;
2257 UART_AUTOBAUD_t UART_AUTOBAUD;
2258 UART_STATUS_t UART_STATUS;
2259 UART_CONF0_t UART_CONF0;
2260 UART_CONF1_t UART_CONF1;
2261 UART_LOWPULSE_t UART_LOWPULSE;
2262 UART_HIGHPULSE_t UART_HIGHPULSE;
2263 UART_RXD_CNT_t UART_RXD_CNT;
2264 uint32_t reserved0[17];
2265 UART_DATE_t UART_DATE;
2266 UART_ID_t UART_ID;
2267 };
2268
2269 static UART1_t & UART1 = (*(UART1_t *)0x60000f00);
2270
2271} // _UART1_
2272
2273namespace _WDT_ {
2274
2275 // WDT_CTL
2276 // Reset value: 0x00000000
2277 BEGIN_TYPE(WDT_CTL_t, uint32_t)
2278 ADD_BITFIELD_RW(Register, 0, 32)
2279 END_TYPE()
2280
2281 // WDT_OP
2282 // Reset value: 0x00000000
2283 BEGIN_TYPE(WDT_OP_t, uint32_t)
2284 ADD_BITFIELD_RW(Register, 0, 32)
2285 END_TYPE()
2286
2287 // WDT_OP_ND
2288 // Reset value: 0x00000000
2289 BEGIN_TYPE(WDT_OP_ND_t, uint32_t)
2290 ADD_BITFIELD_RW(Register, 0, 32)
2291 END_TYPE()
2292
2293 // WDT_RST
2294 // Reset value: 0x00000000
2295 BEGIN_TYPE(WDT_RST_t, uint32_t)
2296 ADD_BITFIELD_RW(Register, 0, 32)
2297 END_TYPE()
2298
2299 struct WDT_t {
2300 WDT_CTL_t WDT_CTL;
2301 WDT_OP_t WDT_OP;
2302 WDT_OP_ND_t WDT_OP_ND;
2303 uint32_t reserved0[2];
2304 WDT_RST_t WDT_RST;
2305 };
2306
2307 static WDT_t & WDT = (*(WDT_t *)0x60000900);
2308
2309} // _WDT_
2310
2311// Interrupt numbers
_DPORT_::DPORT_t
Definition ESP8266.h:35
_EFUSE_::EFUSE_t
Definition ESP8266.h:72
_GPIO_::GPIO_t
Definition ESP8266.h:224
_I2S_::I2S_t
Definition ESP8266.h:363
_IO_MUX_::IO_MUX_t
Definition ESP8266.h:402
_SLC_::SLC_t
Definition ESP8266.h:752
_SPI1_::SPI1_t
Definition ESP8266.h:1617
_UART1_::UART1_t
Definition ESP8266.h:2250
_WDT_::WDT_t
Definition ESP8266.h:2299
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